1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 // For all FMA opcodes declared in fma3p_rm and fma3s_rm milticlasses defined
19 // below, both the register and memory variants are commutable.
20 // For the register form the commutable operands are 1, 2 and 3.
21 // For the memory variant the folded operand must be in 3. Thus,
22 // in that case, only the operands 1 and 2 can be swapped.
23 // Commuting some of operands may require the opcode change.
25 // operands 1 and 2 (memory & register forms): *213* --> *213*(no changes);
26 // operands 1 and 3 (register forms only): *213* --> *231*;
27 // operands 2 and 3 (register forms only): *213* --> *132*.
29 // operands 1 and 2 (memory & register forms): *132* --> *231*;
30 // operands 1 and 3 (register forms only): *132* --> *132*(no changes);
31 // operands 2 and 3 (register forms only): *132* --> *213*.
33 // operands 1 and 2 (memory & register forms): *231* --> *132*;
34 // operands 1 and 3 (register forms only): *231* --> *213*;
35 // operands 2 and 3 (register forms only): *231* --> *231*(no changes).
37 let Constraints = "$src1 = $dst", hasSideEffects = 0, isCommutable = 1 in
38 multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
39 PatFrag MemFrag128, PatFrag MemFrag256,
40 ValueType OpVT128, ValueType OpVT256,
41 SDPatternOperator Op = null_frag> {
42 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
43 (ins VR128:$src1, VR128:$src2, VR128:$src3),
45 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
46 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
47 VR128:$src1, VR128:$src3)))]>;
50 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
51 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
53 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
54 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
55 (MemFrag128 addr:$src3))))]>;
57 def Yr : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
58 (ins VR256:$src1, VR256:$src2, VR256:$src3),
60 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
61 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
62 VR256:$src3)))]>, VEX_L;
65 def Ym : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
66 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
68 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
70 (OpVT256 (Op VR256:$src2, VR256:$src1,
71 (MemFrag256 addr:$src3))))]>, VEX_L;
74 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
75 string OpcodeStr, string PackTy, string Suff,
76 PatFrag MemFrag128, PatFrag MemFrag256,
77 SDNode Op, ValueType OpTy128, ValueType OpTy256> {
78 defm NAME#213#Suff : fma3p_rm<opc213,
79 !strconcat(OpcodeStr, "213", PackTy),
80 MemFrag128, MemFrag256, OpTy128, OpTy256, Op>;
81 defm NAME#132#Suff : fma3p_rm<opc132,
82 !strconcat(OpcodeStr, "132", PackTy),
83 MemFrag128, MemFrag256, OpTy128, OpTy256>;
84 defm NAME#231#Suff : fma3p_rm<opc231,
85 !strconcat(OpcodeStr, "231", PackTy),
86 MemFrag128, MemFrag256, OpTy128, OpTy256>;
90 let ExeDomain = SSEPackedSingle in {
91 defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", "PS",
92 loadv4f32, loadv8f32, X86Fmadd, v4f32, v8f32>;
93 defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", "PS",
94 loadv4f32, loadv8f32, X86Fmsub, v4f32, v8f32>;
95 defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps", "PS",
96 loadv4f32, loadv8f32, X86Fmaddsub,
98 defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps", "PS",
99 loadv4f32, loadv8f32, X86Fmsubadd,
103 let ExeDomain = SSEPackedDouble in {
104 defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", "PD",
105 loadv2f64, loadv4f64, X86Fmadd, v2f64,
107 defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", "PD",
108 loadv2f64, loadv4f64, X86Fmsub, v2f64,
110 defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", "PD",
111 loadv2f64, loadv4f64, X86Fmaddsub,
112 v2f64, v4f64>, VEX_W;
113 defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", "PD",
114 loadv2f64, loadv4f64, X86Fmsubadd,
115 v2f64, v4f64>, VEX_W;
118 // Fused Negative Multiply-Add
119 let ExeDomain = SSEPackedSingle in {
120 defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", "PS", loadv4f32,
121 loadv8f32, X86Fnmadd, v4f32, v8f32>;
122 defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", "PS", loadv4f32,
123 loadv8f32, X86Fnmsub, v4f32, v8f32>;
125 let ExeDomain = SSEPackedDouble in {
126 defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", "PD", loadv2f64,
127 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
128 defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", "PD", loadv2f64,
129 loadv4f64, X86Fnmsub, v2f64, v4f64>, VEX_W;
132 // All source register operands of FMA opcodes defined in fma3s_rm multiclass
133 // can be commuted. In many cases such commute transformation requres an opcode
134 // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form
135 // would require an opcode change to FMA*231:
136 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2;
138 // FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2;
139 // Please see more detailed comment at the very beginning of the section
140 // defining FMA3 opcodes above.
141 let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0 in
142 multiclass fma3s_rm<bits<8> opc, string OpcodeStr,
143 X86MemOperand x86memop, RegisterClass RC,
144 SDPatternOperator OpNode = null_frag> {
145 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
146 (ins RC:$src1, RC:$src2, RC:$src3),
147 !strconcat(OpcodeStr,
148 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
149 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>;
152 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
153 (ins RC:$src1, RC:$src2, x86memop:$src3),
154 !strconcat(OpcodeStr,
155 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
157 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>;
160 // These FMA*_Int instructions are defined specially for being used when
161 // the scalar FMA intrinsics are lowered to machine instructions, and in that
162 // sense, they are similar to existing ADD*_Int, SUB*_Int, MUL*_Int, etc.
165 // All of the FMA*_Int opcodes are defined as commutable here.
166 // Commuting the 2nd and 3rd source register operands of FMAs is quite trivial
167 // and the corresponding optimizations have been developed.
168 // Commuting the 1st operand of FMA*_Int requires some additional analysis,
169 // the commute optimization is legal only if all users of FMA*_Int use only
170 // the lowest element of the FMA*_Int instruction. Even though such analysis
171 // may be not implemented yet we allow the routines doing the actual commute
172 // transformation to decide if one or another instruction is commutable or not.
173 let Constraints = "$src1 = $dst", isCommutable = 1, isCodeGenOnly = 1,
174 hasSideEffects = 0 in
175 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr,
176 Operand memopr, RegisterClass RC> {
177 def r_Int : FMA3<opc, MRMSrcReg, (outs RC:$dst),
178 (ins RC:$src1, RC:$src2, RC:$src3),
179 !strconcat(OpcodeStr,
180 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
184 def m_Int : FMA3<opc, MRMSrcMem, (outs RC:$dst),
185 (ins RC:$src1, RC:$src2, memopr:$src3),
186 !strconcat(OpcodeStr,
187 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
191 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
192 string OpStr, string PackTy, string Suff,
193 SDNode OpNode, RegisterClass RC,
194 X86MemOperand x86memop> {
195 let Predicates = [HasFMA, NoAVX512] in {
196 defm NAME#132#Suff : fma3s_rm<opc132, !strconcat(OpStr, "132", PackTy),
198 defm NAME#213#Suff : fma3s_rm<opc213, !strconcat(OpStr, "213", PackTy),
199 x86memop, RC, OpNode>;
200 defm NAME#231#Suff : fma3s_rm<opc231, !strconcat(OpStr, "231", PackTy),
205 // The FMA 213 form is created for lowering of scalar FMA intrinscis
206 // to machine instructions.
207 // The FMA 132 form can trivially be get by commuting the 2nd and 3rd operands
209 // The FMA 231 form can be get only by commuting the 1st operand of 213 or 132
210 // forms and is possible only after special analysis of all uses of the initial
211 // instruction. Such analysis do not exist yet and thus introducing the 231
212 // form of FMA*_Int instructions is done using an optimistic assumption that
213 // such analysis will be implemented eventually.
214 multiclass fma3s_int_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
215 string OpStr, string PackTy, string Suff,
216 RegisterClass RC, Operand memop> {
217 defm NAME#132#Suff : fma3s_rm_int<opc132, !strconcat(OpStr, "132", PackTy),
219 defm NAME#213#Suff : fma3s_rm_int<opc213, !strconcat(OpStr, "213", PackTy),
221 defm NAME#231#Suff : fma3s_rm_int<opc231, !strconcat(OpStr, "231", PackTy),
225 multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
226 string OpStr, Intrinsic IntF32, Intrinsic IntF64,
228 let ExeDomain = SSEPackedSingle in
229 defm NAME : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", "SS", OpNode,
231 fma3s_int_forms<opc132, opc213, opc231, OpStr, "ss", "SS",
234 let ExeDomain = SSEPackedDouble in
235 defm NAME : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "SD", OpNode,
237 fma3s_int_forms<opc132, opc213, opc231, OpStr, "sd", "SD",
238 VR128, sdmem>, VEX_W;
240 // These patterns use the 123 ordering, instead of 213, even though
241 // they match the intrinsic to the 213 version of the instruction.
242 // This is because src1 is tied to dest, and the scalar intrinsics
243 // require the pass-through values to come from the first source
244 // operand, not the second.
245 let Predicates = [HasFMA] in {
246 def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3),
247 (COPY_TO_REGCLASS(!cast<Instruction>(NAME#"213SSr_Int")
248 $src1, $src2, $src3), VR128)>;
250 def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3),
251 (COPY_TO_REGCLASS(!cast<Instruction>(NAME#"213SDr_Int")
252 $src1, $src2, $src3), VR128)>;
256 defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
257 int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
258 defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
259 int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
261 defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
262 int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
263 defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
264 int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
267 //===----------------------------------------------------------------------===//
268 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
269 //===----------------------------------------------------------------------===//
272 multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC,
273 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
275 let isCommutable = 1 in
276 def rr : FMA4<opc, MRMSrcRegOp4, (outs RC:$dst),
277 (ins RC:$src1, RC:$src2, RC:$src3),
278 !strconcat(OpcodeStr,
279 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
281 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG;
282 def rm : FMA4<opc, MRMSrcMemOp4, (outs RC:$dst),
283 (ins RC:$src1, RC:$src2, x86memop:$src3),
284 !strconcat(OpcodeStr,
285 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
286 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
287 (mem_frag addr:$src3)))]>, VEX_W, VEX_LIG;
288 def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
289 (ins RC:$src1, x86memop:$src2, RC:$src3),
290 !strconcat(OpcodeStr,
291 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
293 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG;
295 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
296 def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
297 (ins RC:$src1, RC:$src2, RC:$src3),
298 !strconcat(OpcodeStr,
299 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
300 VEX_LIG, FoldGenData<NAME#rr>;
303 multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
304 ComplexPattern mem_cpat, Intrinsic Int> {
305 let isCodeGenOnly = 1 in {
306 def rr_Int : FMA4<opc, MRMSrcRegOp4, (outs VR128:$dst),
307 (ins VR128:$src1, VR128:$src2, VR128:$src3),
308 !strconcat(OpcodeStr,
309 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
311 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, VEX_LIG;
312 def rm_Int : FMA4<opc, MRMSrcMemOp4, (outs VR128:$dst),
313 (ins VR128:$src1, VR128:$src2, memop:$src3),
314 !strconcat(OpcodeStr,
315 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
316 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2,
317 mem_cpat:$src3))]>, VEX_W, VEX_LIG;
318 def mr_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
319 (ins VR128:$src1, memop:$src2, VR128:$src3),
320 !strconcat(OpcodeStr,
321 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
323 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>, VEX_LIG;
324 let hasSideEffects = 0 in
325 def rr_Int_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
326 (ins VR128:$src1, VR128:$src2, VR128:$src3),
327 !strconcat(OpcodeStr,
328 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
329 []>, VEX_LIG, FoldGenData<NAME#rr_Int>;
330 } // isCodeGenOnly = 1
333 multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode,
334 ValueType OpVT128, ValueType OpVT256,
335 PatFrag ld_frag128, PatFrag ld_frag256> {
336 let isCommutable = 1 in
337 def rr : FMA4<opc, MRMSrcRegOp4, (outs VR128:$dst),
338 (ins VR128:$src1, VR128:$src2, VR128:$src3),
339 !strconcat(OpcodeStr,
340 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
342 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>,
344 def rm : FMA4<opc, MRMSrcMemOp4, (outs VR128:$dst),
345 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
346 !strconcat(OpcodeStr,
347 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
348 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
349 (ld_frag128 addr:$src3)))]>, VEX_W;
350 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
351 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
352 !strconcat(OpcodeStr,
353 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
355 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
356 let isCommutable = 1 in
357 def Yrr : FMA4<opc, MRMSrcRegOp4, (outs VR256:$dst),
358 (ins VR256:$src1, VR256:$src2, VR256:$src3),
359 !strconcat(OpcodeStr,
360 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
362 (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>,
364 def Yrm : FMA4<opc, MRMSrcMemOp4, (outs VR256:$dst),
365 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
366 !strconcat(OpcodeStr,
367 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
368 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
369 (ld_frag256 addr:$src3)))]>, VEX_W, VEX_L;
370 def Ymr : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
371 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
372 !strconcat(OpcodeStr,
373 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
374 [(set VR256:$dst, (OpNode VR256:$src1,
375 (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L;
377 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
378 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
379 (ins VR128:$src1, VR128:$src2, VR128:$src3),
380 !strconcat(OpcodeStr,
381 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
382 FoldGenData<NAME#rr>;
383 def Yrr_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
384 (ins VR256:$src1, VR256:$src2, VR256:$src3),
385 !strconcat(OpcodeStr,
386 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
387 VEX_L, FoldGenData<NAME#Yrr>;
388 } // isCodeGenOnly = 1
391 let ExeDomain = SSEPackedSingle in {
392 // Scalar Instructions
393 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32>,
394 fma4s_int<0x6A, "vfmaddss", ssmem, sse_load_f32,
395 int_x86_fma_vfmadd_ss>;
396 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32>,
397 fma4s_int<0x6E, "vfmsubss", ssmem, sse_load_f32,
398 int_x86_fma_vfmsub_ss>;
399 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32,
401 fma4s_int<0x7A, "vfnmaddss", ssmem, sse_load_f32,
402 int_x86_fma_vfnmadd_ss>;
403 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32,
405 fma4s_int<0x7E, "vfnmsubss", ssmem, sse_load_f32,
406 int_x86_fma_vfnmsub_ss>;
407 // Packed Instructions
408 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
409 loadv4f32, loadv8f32>;
410 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
411 loadv4f32, loadv8f32>;
412 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
413 loadv4f32, loadv8f32>;
414 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
415 loadv4f32, loadv8f32>;
416 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32,
417 loadv4f32, loadv8f32>;
418 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32,
419 loadv4f32, loadv8f32>;
422 let ExeDomain = SSEPackedDouble in {
423 // Scalar Instructions
424 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64>,
425 fma4s_int<0x6B, "vfmaddsd", sdmem, sse_load_f64,
426 int_x86_fma_vfmadd_sd>;
427 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64>,
428 fma4s_int<0x6F, "vfmsubsd", sdmem, sse_load_f64,
429 int_x86_fma_vfmsub_sd>;
430 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64,
432 fma4s_int<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
433 int_x86_fma_vfnmadd_sd>;
434 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64,
436 fma4s_int<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
437 int_x86_fma_vfnmsub_sd>;
438 // Packed Instructions
439 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
440 loadv2f64, loadv4f64>;
441 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
442 loadv2f64, loadv4f64>;
443 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
444 loadv2f64, loadv4f64>;
445 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
446 loadv2f64, loadv4f64>;
447 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64,
448 loadv2f64, loadv4f64>;
449 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64,
450 loadv2f64, loadv4f64>;