1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_CA : Format<39>;
39 def MRM_CB : Format<40>;
40 def MRM_E8 : Format<41>;
41 def MRM_F0 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_F8 : Format<45>;
45 def MRM_F9 : Format<46>;
46 def MRM_D0 : Format<47>;
47 def MRM_D1 : Format<48>;
48 def MRM_D4 : Format<49>;
49 def MRM_D5 : Format<50>;
50 def MRM_D6 : Format<51>;
51 def MRM_D8 : Format<52>;
52 def MRM_D9 : Format<53>;
53 def MRM_DA : Format<54>;
54 def MRM_DB : Format<55>;
55 def MRM_DC : Format<56>;
56 def MRM_DD : Format<57>;
57 def MRM_DE : Format<58>;
58 def MRM_DF : Format<59>;
60 // ImmType - This specifies the immediate type used by an instruction. This is
61 // part of the ad-hoc solution used to emit machine instruction encodings by our
62 // machine code emitter.
63 class ImmType<bits<3> val> {
66 def NoImm : ImmType<0>;
67 def Imm8 : ImmType<1>;
68 def Imm8PCRel : ImmType<2>;
69 def Imm16 : ImmType<3>;
70 def Imm16PCRel : ImmType<4>;
71 def Imm32 : ImmType<5>;
72 def Imm32PCRel : ImmType<6>;
73 def Imm64 : ImmType<7>;
75 // FPFormat - This specifies what form this FP instruction has. This is used by
76 // the Floating-Point stackifier pass.
77 class FPFormat<bits<3> val> {
80 def NotFP : FPFormat<0>;
81 def ZeroArgFP : FPFormat<1>;
82 def OneArgFP : FPFormat<2>;
83 def OneArgFPRW : FPFormat<3>;
84 def TwoArgFP : FPFormat<4>;
85 def CompareFP : FPFormat<5>;
86 def CondMovFP : FPFormat<6>;
87 def SpecialFP : FPFormat<7>;
89 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
90 // Keep in sync with tables in X86InstrInfo.cpp.
91 class Domain<bits<2> val> {
94 def GenericDomain : Domain<0>;
95 def SSEPackedSingle : Domain<1>;
96 def SSEPackedDouble : Domain<2>;
97 def SSEPackedInt : Domain<3>;
99 // Class specifying the vector form of the decompressed
100 // displacement of 8-bit.
101 class CD8VForm<bits<3> val> {
104 def CD8VF : CD8VForm<0>; // v := VL
105 def CD8VH : CD8VForm<1>; // v := VL/2
106 def CD8VQ : CD8VForm<2>; // v := VL/4
107 def CD8VO : CD8VForm<3>; // v := VL/8
108 def CD8VT1 : CD8VForm<4>; // v := 1
109 def CD8VT2 : CD8VForm<5>; // v := 2
110 def CD8VT4 : CD8VForm<6>; // v := 4
111 def CD8VT8 : CD8VForm<7>; // v := 8
113 // Prefix byte classes which are used to indicate to the ad-hoc machine code
114 // emitter that various prefix bytes are required.
115 class OpSize { bit hasOpSizePrefix = 1; }
116 class AdSize { bit hasAdSizePrefix = 1; }
117 class REX_W { bit hasREX_WPrefix = 1; }
118 class LOCK { bit hasLockPrefix = 1; }
119 class SegFS { bits<2> SegOvrBits = 1; }
120 class SegGS { bits<2> SegOvrBits = 2; }
121 class TB { bits<5> Prefix = 1; }
122 class REP { bits<5> Prefix = 2; }
123 class D8 { bits<5> Prefix = 3; }
124 class D9 { bits<5> Prefix = 4; }
125 class DA { bits<5> Prefix = 5; }
126 class DB { bits<5> Prefix = 6; }
127 class DC { bits<5> Prefix = 7; }
128 class DD { bits<5> Prefix = 8; }
129 class DE { bits<5> Prefix = 9; }
130 class DF { bits<5> Prefix = 10; }
131 class XD { bits<5> Prefix = 11; }
132 class XS { bits<5> Prefix = 12; }
133 class T8 { bits<5> Prefix = 13; }
134 class TA { bits<5> Prefix = 14; }
135 class A6 { bits<5> Prefix = 15; }
136 class A7 { bits<5> Prefix = 16; }
137 class T8XD { bits<5> Prefix = 17; }
138 class T8XS { bits<5> Prefix = 18; }
139 class TAXD { bits<5> Prefix = 19; }
140 class XOP8 { bits<5> Prefix = 20; }
141 class XOP9 { bits<5> Prefix = 21; }
142 class XOPA { bits<5> Prefix = 22; }
143 class VEX { bit hasVEXPrefix = 1; }
144 class VEX_W { bit hasVEX_WPrefix = 1; }
145 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
146 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
147 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
148 class VEX_L { bit hasVEX_L = 1; }
149 class VEX_LIG { bit ignoresVEX_L = 1; }
150 class EVEX : VEX { bit hasEVEXPrefix = 1; }
151 class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; }
152 class EVEX_K { bit hasEVEX_K = 1; }
153 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
154 class EVEX_B { bit hasEVEX_B = 1; }
155 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
156 class EVEX_CD8<int esize, CD8VForm form> {
157 bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00,
158 !if(!eq(esize, 16), 0b01,
159 !if(!eq(esize, 32), 0b10,
160 !if(!eq(esize, 64), 0b11, ?))));
161 bits<3> EVEX_CD8V = form.Value;
163 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
164 class MemOp4 { bit hasMemOp4Prefix = 1; }
165 class XOP { bit hasXOP_Prefix = 1; }
166 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
169 Domain d = GenericDomain>
171 let Namespace = "X86";
173 bits<8> Opcode = opcod;
175 bits<6> FormBits = Form.Value;
178 dag OutOperandList = outs;
179 dag InOperandList = ins;
180 string AsmString = AsmStr;
182 // If this is a pseudo instruction, mark it isCodeGenOnly.
183 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
185 let Itinerary = itin;
188 // Attributes specific to X86 instructions...
190 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
191 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
193 bits<5> Prefix = 0; // Which prefix byte does this inst have?
194 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
195 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
196 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
197 bits<2> SegOvrBits = 0; // Segment override prefix.
198 Domain ExeDomain = d;
199 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
200 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
201 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
202 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
203 // encode the third operand?
204 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
205 // to be encoded in a immediate field?
206 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
207 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
208 bit hasEVEXPrefix = 0; // Does this inst require EVEX form?
209 bit hasEVEX_K = 0; // Does this inst require masking?
210 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
211 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
212 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
213 bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size.
214 bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width.
215 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
216 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
217 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
219 // TSFlags layout should be kept in sync with X86InstrInfo.h.
220 let TSFlags{5-0} = FormBits;
221 let TSFlags{6} = hasOpSizePrefix;
222 let TSFlags{7} = hasAdSizePrefix;
223 let TSFlags{12-8} = Prefix;
224 let TSFlags{13} = hasREX_WPrefix;
225 let TSFlags{16-14} = ImmT.Value;
226 let TSFlags{19-17} = FPForm.Value;
227 let TSFlags{20} = hasLockPrefix;
228 let TSFlags{22-21} = SegOvrBits;
229 let TSFlags{24-23} = ExeDomain.Value;
230 let TSFlags{32-25} = Opcode;
231 let TSFlags{33} = hasVEXPrefix;
232 let TSFlags{34} = hasVEX_WPrefix;
233 let TSFlags{35} = hasVEX_4VPrefix;
234 let TSFlags{36} = hasVEX_4VOp3Prefix;
235 let TSFlags{37} = hasVEX_i8ImmReg;
236 let TSFlags{38} = hasVEX_L;
237 let TSFlags{39} = ignoresVEX_L;
238 let TSFlags{40} = hasEVEXPrefix;
239 let TSFlags{41} = hasEVEX_K;
240 let TSFlags{42} = hasEVEX_Z;
241 let TSFlags{43} = hasEVEX_L2;
242 let TSFlags{44} = hasEVEX_B;
243 let TSFlags{46-45} = EVEX_CD8E;
244 let TSFlags{49-47} = EVEX_CD8V;
245 let TSFlags{50} = has3DNow0F0FOpcode;
246 let TSFlags{51} = hasMemOp4Prefix;
247 let TSFlags{52} = hasXOP_Prefix;
250 class PseudoI<dag oops, dag iops, list<dag> pattern>
251 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
252 let Pattern = pattern;
255 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
256 list<dag> pattern, InstrItinClass itin = NoItinerary,
257 Domain d = GenericDomain>
258 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
259 let Pattern = pattern;
262 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
263 list<dag> pattern, InstrItinClass itin = NoItinerary,
264 Domain d = GenericDomain>
265 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
266 let Pattern = pattern;
269 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
270 list<dag> pattern, InstrItinClass itin = NoItinerary>
271 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
272 let Pattern = pattern;
275 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
276 list<dag> pattern, InstrItinClass itin = NoItinerary>
277 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
278 let Pattern = pattern;
281 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
282 list<dag> pattern, InstrItinClass itin = NoItinerary>
283 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
284 let Pattern = pattern;
288 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
289 list<dag> pattern, InstrItinClass itin = NoItinerary>
290 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
291 let Pattern = pattern;
295 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
296 list<dag> pattern, InstrItinClass itin = NoItinerary>
297 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
298 let Pattern = pattern;
302 // FPStack Instruction Templates:
303 // FPI - Floating Point Instruction template.
304 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
305 InstrItinClass itin = NoItinerary>
306 : I<o, F, outs, ins, asm, [], itin> {}
308 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
309 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
310 InstrItinClass itin = NoItinerary>
311 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
313 let Pattern = pattern;
316 // Templates for instructions that use a 16- or 32-bit segmented address as
317 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
319 // Iseg16 - 16-bit segment selector, 16-bit offset
320 // Iseg32 - 16-bit segment selector, 32-bit offset
322 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
323 list<dag> pattern, InstrItinClass itin = NoItinerary>
324 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
325 let Pattern = pattern;
329 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
330 list<dag> pattern, InstrItinClass itin = NoItinerary>
331 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
332 let Pattern = pattern;
339 // SI - SSE 1 & 2 scalar instructions
340 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
341 list<dag> pattern, InstrItinClass itin = NoItinerary>
342 : I<o, F, outs, ins, asm, pattern, itin> {
343 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
344 !if(hasVEXPrefix /* VEX */, [UseAVX],
345 !if(!eq(Prefix, __xs.Prefix), [UseSSE1],
346 !if(!eq(Prefix, __xd.Prefix), [UseSSE2],
347 !if(hasOpSizePrefix, [UseSSE2], [UseSSE1])))));
349 // AVX instructions have a 'v' prefix in the mnemonic
350 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
353 // SIi8 - SSE 1 & 2 scalar instructions
354 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
355 list<dag> pattern, InstrItinClass itin = NoItinerary>
356 : Ii8<o, F, outs, ins, asm, pattern, itin> {
357 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
358 !if(hasVEXPrefix /* VEX */, [UseAVX],
359 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2])));
361 // AVX instructions have a 'v' prefix in the mnemonic
362 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
365 // PI - SSE 1 & 2 packed instructions
366 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
367 InstrItinClass itin, Domain d>
368 : I<o, F, outs, ins, asm, pattern, itin, d> {
369 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
370 !if(hasVEXPrefix /* VEX */, [HasAVX],
371 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
373 // AVX instructions have a 'v' prefix in the mnemonic
374 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
377 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
378 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
379 InstrItinClass itin, Domain d>
380 : I<o, F, outs, ins, asm, pattern, itin, d> {
381 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
384 // PIi8 - SSE 1 & 2 packed instructions with immediate
385 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
386 list<dag> pattern, InstrItinClass itin, Domain d>
387 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
388 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
389 !if(hasVEXPrefix /* VEX */, [HasAVX],
390 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
392 // AVX instructions have a 'v' prefix in the mnemonic
393 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
396 // SSE1 Instruction Templates:
398 // SSI - SSE1 instructions with XS prefix.
399 // PSI - SSE1 instructions with TB prefix.
400 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
401 // VSSI - SSE1 instructions with XS prefix in AVX form.
402 // VPSI - SSE1 instructions with TB prefix in AVX form, packed single.
404 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
405 list<dag> pattern, InstrItinClass itin = NoItinerary>
406 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
407 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
408 list<dag> pattern, InstrItinClass itin = NoItinerary>
409 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
410 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
411 list<dag> pattern, InstrItinClass itin = NoItinerary>
412 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
414 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
415 list<dag> pattern, InstrItinClass itin = NoItinerary>
416 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
418 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
419 list<dag> pattern, InstrItinClass itin = NoItinerary>
420 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
422 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
423 list<dag> pattern, InstrItinClass itin = NoItinerary>
424 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
427 // SSE2 Instruction Templates:
429 // SDI - SSE2 instructions with XD prefix.
430 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
431 // S2SI - SSE2 instructions with XS prefix.
432 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
433 // PDI - SSE2 instructions with TB and OpSize prefixes, packed double domain.
434 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
435 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
436 // VPDI - SSE2 vector instructions with TB and OpSize prefixes in AVX form,
437 // packed double domain.
438 // VS2I - SSE2 scalar instructions with TB and OpSize prefixes in AVX form.
439 // S2I - SSE2 scalar instructions with TB and OpSize prefixes.
440 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
442 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
445 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
446 list<dag> pattern, InstrItinClass itin = NoItinerary>
447 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
448 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
449 list<dag> pattern, InstrItinClass itin = NoItinerary>
450 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
451 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
452 list<dag> pattern, InstrItinClass itin = NoItinerary>
453 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
454 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
455 list<dag> pattern, InstrItinClass itin = NoItinerary>
456 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
457 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
458 list<dag> pattern, InstrItinClass itin = NoItinerary>
459 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
461 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
462 list<dag> pattern, InstrItinClass itin = NoItinerary>
463 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
465 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
466 list<dag> pattern, InstrItinClass itin = NoItinerary>
467 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
469 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
470 list<dag> pattern, InstrItinClass itin = NoItinerary>
471 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
473 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
474 list<dag> pattern, InstrItinClass itin = NoItinerary>
475 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
476 OpSize, Requires<[HasAVX]>;
477 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
478 list<dag> pattern, InstrItinClass itin = NoItinerary>
479 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, TB,
480 OpSize, Requires<[UseAVX]>;
481 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
482 list<dag> pattern, InstrItinClass itin = NoItinerary>
483 : I<o, F, outs, ins, asm, pattern, itin>, TB,
484 OpSize, Requires<[UseSSE2]>;
485 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
486 list<dag> pattern, InstrItinClass itin = NoItinerary>
487 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
488 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
489 list<dag> pattern, InstrItinClass itin = NoItinerary>
490 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
492 // SSE3 Instruction Templates:
494 // S3I - SSE3 instructions with TB and OpSize prefixes.
495 // S3SI - SSE3 instructions with XS prefix.
496 // S3DI - SSE3 instructions with XD prefix.
498 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
499 list<dag> pattern, InstrItinClass itin = NoItinerary>
500 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
502 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
503 list<dag> pattern, InstrItinClass itin = NoItinerary>
504 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
506 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
507 list<dag> pattern, InstrItinClass itin = NoItinerary>
508 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
512 // SSSE3 Instruction Templates:
514 // SS38I - SSSE3 instructions with T8 prefix.
515 // SS3AI - SSSE3 instructions with TA prefix.
516 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
517 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
519 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
520 // uses the MMX registers. The 64-bit versions are grouped with the MMX
521 // classes. They need to be enabled even if AVX is enabled.
523 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
524 list<dag> pattern, InstrItinClass itin = NoItinerary>
525 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
526 Requires<[UseSSSE3]>;
527 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
528 list<dag> pattern, InstrItinClass itin = NoItinerary>
529 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
530 Requires<[UseSSSE3]>;
531 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
532 list<dag> pattern, InstrItinClass itin = NoItinerary>
533 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
534 Requires<[HasSSSE3]>;
535 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
536 list<dag> pattern, InstrItinClass itin = NoItinerary>
537 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
538 Requires<[HasSSSE3]>;
540 // SSE4.1 Instruction Templates:
542 // SS48I - SSE 4.1 instructions with T8 prefix.
543 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
545 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
546 list<dag> pattern, InstrItinClass itin = NoItinerary>
547 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
548 Requires<[UseSSE41]>;
549 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
550 list<dag> pattern, InstrItinClass itin = NoItinerary>
551 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
552 Requires<[UseSSE41]>;
554 // SSE4.2 Instruction Templates:
556 // SS428I - SSE 4.2 instructions with T8 prefix.
557 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
558 list<dag> pattern, InstrItinClass itin = NoItinerary>
559 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
560 Requires<[UseSSE42]>;
562 // SS42FI - SSE 4.2 instructions with T8XD prefix.
563 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
564 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
565 list<dag> pattern, InstrItinClass itin = NoItinerary>
566 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
568 // SS42AI = SSE 4.2 instructions with TA prefix
569 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
570 list<dag> pattern, InstrItinClass itin = NoItinerary>
571 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
572 Requires<[UseSSE42]>;
574 // AVX Instruction Templates:
575 // Instructions introduced in AVX (no SSE equivalent forms)
577 // AVX8I - AVX instructions with T8 and OpSize prefix.
578 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
579 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
580 list<dag> pattern, InstrItinClass itin = NoItinerary>
581 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
583 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
584 list<dag> pattern, InstrItinClass itin = NoItinerary>
585 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
588 // AVX2 Instruction Templates:
589 // Instructions introduced in AVX2 (no SSE equivalent forms)
591 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
592 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
593 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
594 list<dag> pattern, InstrItinClass itin = NoItinerary>
595 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
597 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
598 list<dag> pattern, InstrItinClass itin = NoItinerary>
599 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
603 // AVX-512 Instruction Templates:
604 // Instructions introduced in AVX-512 (no SSE equivalent forms)
606 // AVX5128I - AVX-512 instructions with T8 and OpSize prefix.
607 // AVX512AIi8 - AVX-512 instructions with TA, OpSize prefix and ImmT = Imm8.
608 // AVX512PDI - AVX-512 instructions with TB, OpSize, double packed.
609 // AVX512PSI - AVX-512 instructions with TB, single packed.
610 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
611 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
612 // AVX512BI - AVX-512 instructions with TB, OpSize, int packed domain.
613 // AVX512SI - AVX-512 scalar instructions with TB and OpSize prefixes.
615 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
616 list<dag> pattern, InstrItinClass itin = NoItinerary>
617 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
618 Requires<[HasAVX512]>;
619 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
620 list<dag> pattern, InstrItinClass itin = NoItinerary>
621 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
622 Requires<[HasAVX512]>;
623 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
624 list<dag> pattern, InstrItinClass itin = NoItinerary>
625 : I<o, F, outs, ins, asm, pattern, itin>, XS,
626 Requires<[HasAVX512]>;
627 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
628 list<dag> pattern, InstrItinClass itin = NoItinerary>
629 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
630 Requires<[HasAVX512]>;
631 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
632 list<dag> pattern, InstrItinClass itin = NoItinerary>
633 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
634 Requires<[HasAVX512]>;
635 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
636 list<dag> pattern, InstrItinClass itin = NoItinerary>
637 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
638 Requires<[HasAVX512]>;
639 class AVX512SI<bits<8> o, Format F, dag outs, dag ins, string asm,
640 list<dag> pattern, InstrItinClass itin = NoItinerary>
641 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
642 Requires<[HasAVX512]>;
643 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
644 list<dag> pattern, InstrItinClass itin = NoItinerary>
645 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
646 Requires<[HasAVX512]>;
647 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
648 list<dag> pattern, InstrItinClass itin = NoItinerary>
649 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB,
650 Requires<[HasAVX512]>;
651 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
652 list<dag> pattern, InstrItinClass itin = NoItinerary>
653 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB,
654 OpSize, Requires<[HasAVX512]>;
655 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
656 list<dag> pattern, InstrItinClass itin = NoItinerary>
657 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
658 Requires<[HasAVX512]>;
659 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
660 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
661 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
662 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
663 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
664 : I<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
665 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
666 list<dag>pattern, InstrItinClass itin = NoItinerary>
667 : I<o, F, outs, ins, asm, pattern, itin>, T8,
668 OpSize, EVEX_4V, Requires<[HasAVX512]>;
670 // AES Instruction Templates:
673 // These use the same encoding as the SSE4.2 T8 and TA encodings.
674 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
675 list<dag>pattern, InstrItinClass itin = IIC_AES>
676 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
679 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
680 list<dag> pattern, InstrItinClass itin = NoItinerary>
681 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
684 // PCLMUL Instruction Templates
685 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
686 list<dag>pattern, InstrItinClass itin = NoItinerary>
687 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
688 OpSize, Requires<[HasPCLMUL]>;
690 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
691 list<dag>pattern, InstrItinClass itin = NoItinerary>
692 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
693 OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
695 // FMA3 Instruction Templates
696 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
697 list<dag>pattern, InstrItinClass itin = NoItinerary>
698 : I<o, F, outs, ins, asm, pattern, itin>, T8,
699 OpSize, VEX_4V, FMASC, Requires<[HasFMA]>;
701 // FMA4 Instruction Templates
702 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
703 list<dag>pattern, InstrItinClass itin = NoItinerary>
704 : Ii8<o, F, outs, ins, asm, pattern, itin>, TA,
705 OpSize, VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
707 // XOP 2, 3 and 4 Operand Instruction Template
708 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
709 list<dag> pattern, InstrItinClass itin = NoItinerary>
710 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
711 XOP, XOP9, Requires<[HasXOP]>;
713 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
714 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
715 list<dag> pattern, InstrItinClass itin = NoItinerary>
716 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
717 XOP, XOP8, Requires<[HasXOP]>;
719 // XOP 5 operand instruction (VEX encoding!)
720 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
721 list<dag>pattern, InstrItinClass itin = NoItinerary>
722 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
723 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
725 // X86-64 Instruction templates...
728 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
729 list<dag> pattern, InstrItinClass itin = NoItinerary>
730 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
731 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
732 list<dag> pattern, InstrItinClass itin = NoItinerary>
733 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
734 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
735 list<dag> pattern, InstrItinClass itin = NoItinerary>
736 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
738 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
739 list<dag> pattern, InstrItinClass itin = NoItinerary>
740 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
741 let Pattern = pattern;
745 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
746 list<dag> pattern, InstrItinClass itin = NoItinerary>
747 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
748 let Pattern = pattern;
752 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
753 list<dag> pattern, InstrItinClass itin = NoItinerary>
754 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
755 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
756 list<dag> pattern, InstrItinClass itin = NoItinerary>
757 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
758 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
759 list<dag> pattern, InstrItinClass itin = NoItinerary>
760 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
761 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
762 list<dag> pattern, InstrItinClass itin = NoItinerary>
763 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
764 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
765 list<dag> pattern, InstrItinClass itin = NoItinerary>
766 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
767 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
768 list<dag> pattern, InstrItinClass itin = NoItinerary>
769 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
771 // MMX Instruction templates
774 // MMXI - MMX instructions with TB prefix.
775 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
776 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
777 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
778 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
779 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
780 // MMXID - MMX instructions with XD prefix.
781 // MMXIS - MMX instructions with XS prefix.
782 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
783 list<dag> pattern, InstrItinClass itin = NoItinerary>
784 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
785 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
786 list<dag> pattern, InstrItinClass itin = NoItinerary>
787 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In32BitMode]>;
788 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
789 list<dag> pattern, InstrItinClass itin = NoItinerary>
790 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
791 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
792 list<dag> pattern, InstrItinClass itin = NoItinerary>
793 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
794 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
795 list<dag> pattern, InstrItinClass itin = NoItinerary>
796 : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
797 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
798 list<dag> pattern, InstrItinClass itin = NoItinerary>
799 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
800 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
801 list<dag> pattern, InstrItinClass itin = NoItinerary>
802 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
803 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
804 list<dag> pattern, InstrItinClass itin = NoItinerary>
805 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;