1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<7> val> {
21 def Pseudo : Format<0>;
22 def RawFrm : Format<1>;
23 def AddRegFrm : Format<2>;
24 def RawFrmMemOffs : Format<3>;
25 def RawFrmSrc : Format<4>;
26 def RawFrmDst : Format<5>;
27 def RawFrmDstSrc : Format<6>;
28 def RawFrmImm8 : Format<7>;
29 def RawFrmImm16 : Format<8>;
30 def MRMDestMem : Format<32>;
31 def MRMSrcMem : Format<33>;
32 def MRMSrcMem4VOp3 : Format<34>;
33 def MRMSrcMemOp4 : Format<35>;
34 def MRMXm : Format<39>;
35 def MRM0m : Format<40>; def MRM1m : Format<41>; def MRM2m : Format<42>;
36 def MRM3m : Format<43>; def MRM4m : Format<44>; def MRM5m : Format<45>;
37 def MRM6m : Format<46>; def MRM7m : Format<47>;
38 def MRMDestReg : Format<48>;
39 def MRMSrcReg : Format<49>;
40 def MRMSrcReg4VOp3 : Format<50>;
41 def MRMSrcRegOp4 : Format<51>;
42 def MRMXr : Format<55>;
43 def MRM0r : Format<56>; def MRM1r : Format<57>; def MRM2r : Format<58>;
44 def MRM3r : Format<59>; def MRM4r : Format<60>; def MRM5r : Format<61>;
45 def MRM6r : Format<62>; def MRM7r : Format<63>;
46 def MRM_C0 : Format<64>; def MRM_C1 : Format<65>; def MRM_C2 : Format<66>;
47 def MRM_C3 : Format<67>; def MRM_C4 : Format<68>; def MRM_C5 : Format<69>;
48 def MRM_C6 : Format<70>; def MRM_C7 : Format<71>; def MRM_C8 : Format<72>;
49 def MRM_C9 : Format<73>; def MRM_CA : Format<74>; def MRM_CB : Format<75>;
50 def MRM_CC : Format<76>; def MRM_CD : Format<77>; def MRM_CE : Format<78>;
51 def MRM_CF : Format<79>; def MRM_D0 : Format<80>; def MRM_D1 : Format<81>;
52 def MRM_D2 : Format<82>; def MRM_D3 : Format<83>; def MRM_D4 : Format<84>;
53 def MRM_D5 : Format<85>; def MRM_D6 : Format<86>; def MRM_D7 : Format<87>;
54 def MRM_D8 : Format<88>; def MRM_D9 : Format<89>; def MRM_DA : Format<90>;
55 def MRM_DB : Format<91>; def MRM_DC : Format<92>; def MRM_DD : Format<93>;
56 def MRM_DE : Format<94>; def MRM_DF : Format<95>; def MRM_E0 : Format<96>;
57 def MRM_E1 : Format<97>; def MRM_E2 : Format<98>; def MRM_E3 : Format<99>;
58 def MRM_E4 : Format<100>; def MRM_E5 : Format<101>; def MRM_E6 : Format<102>;
59 def MRM_E7 : Format<103>; def MRM_E8 : Format<104>; def MRM_E9 : Format<105>;
60 def MRM_EA : Format<106>; def MRM_EB : Format<107>; def MRM_EC : Format<108>;
61 def MRM_ED : Format<109>; def MRM_EE : Format<110>; def MRM_EF : Format<111>;
62 def MRM_F0 : Format<112>; def MRM_F1 : Format<113>; def MRM_F2 : Format<114>;
63 def MRM_F3 : Format<115>; def MRM_F4 : Format<116>; def MRM_F5 : Format<117>;
64 def MRM_F6 : Format<118>; def MRM_F7 : Format<119>; def MRM_F8 : Format<120>;
65 def MRM_F9 : Format<121>; def MRM_FA : Format<122>; def MRM_FB : Format<123>;
66 def MRM_FC : Format<124>; def MRM_FD : Format<125>; def MRM_FE : Format<126>;
67 def MRM_FF : Format<127>;
69 // ImmType - This specifies the immediate type used by an instruction. This is
70 // part of the ad-hoc solution used to emit machine instruction encodings by our
71 // machine code emitter.
72 class ImmType<bits<4> val> {
75 def NoImm : ImmType<0>;
76 def Imm8 : ImmType<1>;
77 def Imm8PCRel : ImmType<2>;
78 def Imm8Reg : ImmType<3>; // Register encoded in [7:4].
79 def Imm16 : ImmType<4>;
80 def Imm16PCRel : ImmType<5>;
81 def Imm32 : ImmType<6>;
82 def Imm32PCRel : ImmType<7>;
83 def Imm32S : ImmType<8>;
84 def Imm64 : ImmType<9>;
86 // FPFormat - This specifies what form this FP instruction has. This is used by
87 // the Floating-Point stackifier pass.
88 class FPFormat<bits<3> val> {
91 def NotFP : FPFormat<0>;
92 def ZeroArgFP : FPFormat<1>;
93 def OneArgFP : FPFormat<2>;
94 def OneArgFPRW : FPFormat<3>;
95 def TwoArgFP : FPFormat<4>;
96 def CompareFP : FPFormat<5>;
97 def CondMovFP : FPFormat<6>;
98 def SpecialFP : FPFormat<7>;
100 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
101 // Keep in sync with tables in X86InstrInfo.cpp.
102 class Domain<bits<2> val> {
105 def GenericDomain : Domain<0>;
106 def SSEPackedSingle : Domain<1>;
107 def SSEPackedDouble : Domain<2>;
108 def SSEPackedInt : Domain<3>;
110 // Class specifying the vector form of the decompressed
111 // displacement of 8-bit.
112 class CD8VForm<bits<3> val> {
115 def CD8VF : CD8VForm<0>; // v := VL
116 def CD8VH : CD8VForm<1>; // v := VL/2
117 def CD8VQ : CD8VForm<2>; // v := VL/4
118 def CD8VO : CD8VForm<3>; // v := VL/8
119 // The tuple (subvector) forms.
120 def CD8VT1 : CD8VForm<4>; // v := 1
121 def CD8VT2 : CD8VForm<5>; // v := 2
122 def CD8VT4 : CD8VForm<6>; // v := 4
123 def CD8VT8 : CD8VForm<7>; // v := 8
125 // Class specifying the prefix used an opcode extension.
126 class Prefix<bits<3> val> {
129 def NoPrfx : Prefix<0>;
135 // Class specifying the opcode map.
136 class Map<bits<3> val> {
147 // Class specifying the encoding
148 class Encoding<bits<2> val> {
151 def EncNormal : Encoding<0>;
152 def EncVEX : Encoding<1>;
153 def EncXOP : Encoding<2>;
154 def EncEVEX : Encoding<3>;
156 // Operand size for encodings that change based on mode.
157 class OperandSize<bits<2> val> {
160 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
161 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
162 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
164 // Address size for encodings that change based on mode.
165 class AddressSize<bits<2> val> {
168 def AdSizeX : AddressSize<0>; // Address size determined using addr operand.
169 def AdSize16 : AddressSize<1>; // Encodes a 16-bit address.
170 def AdSize32 : AddressSize<2>; // Encodes a 32-bit address.
171 def AdSize64 : AddressSize<3>; // Encodes a 64-bit address.
173 // Prefix byte classes which are used to indicate to the ad-hoc machine code
174 // emitter that various prefix bytes are required.
175 class OpSize16 { OperandSize OpSize = OpSize16; }
176 class OpSize32 { OperandSize OpSize = OpSize32; }
177 class AdSize16 { AddressSize AdSize = AdSize16; }
178 class AdSize32 { AddressSize AdSize = AdSize32; }
179 class AdSize64 { AddressSize AdSize = AdSize64; }
180 class REX_W { bit hasREX_WPrefix = 1; }
181 class LOCK { bit hasLockPrefix = 1; }
182 class REP { bit hasREPPrefix = 1; }
183 class TB { Map OpMap = TB; }
184 class T8 { Map OpMap = T8; }
185 class TA { Map OpMap = TA; }
186 class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
187 class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
188 class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }
189 class OBXS { Prefix OpPrefix = XS; }
190 class PS : TB { Prefix OpPrefix = PS; }
191 class PD : TB { Prefix OpPrefix = PD; }
192 class XD : TB { Prefix OpPrefix = XD; }
193 class XS : TB { Prefix OpPrefix = XS; }
194 class T8PS : T8 { Prefix OpPrefix = PS; }
195 class T8PD : T8 { Prefix OpPrefix = PD; }
196 class T8XD : T8 { Prefix OpPrefix = XD; }
197 class T8XS : T8 { Prefix OpPrefix = XS; }
198 class TAPS : TA { Prefix OpPrefix = PS; }
199 class TAPD : TA { Prefix OpPrefix = PD; }
200 class TAXD : TA { Prefix OpPrefix = XD; }
201 class VEX { Encoding OpEnc = EncVEX; }
202 class VEX_W { bit hasVEX_WPrefix = 1; }
203 class VEX_4V : VEX { bit hasVEX_4V = 1; }
204 class VEX_L { bit hasVEX_L = 1; }
205 class VEX_LIG { bit ignoresVEX_L = 1; }
206 class EVEX : VEX { Encoding OpEnc = EncEVEX; }
207 class EVEX_4V : VEX_4V { Encoding OpEnc = EncEVEX; }
208 class EVEX_K { bit hasEVEX_K = 1; }
209 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
210 class EVEX_B { bit hasEVEX_B = 1; }
211 class EVEX_RC { bit hasEVEX_RC = 1; }
212 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
213 class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; }
214 class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; }
216 // Specify AVX512 8-bit compressed displacement encoding based on the vector
217 // element size in bits (8, 16, 32, 64) and the CDisp8 form.
218 class EVEX_CD8<int esize, CD8VForm form> {
219 int CD8_EltSize = !srl(esize, 3);
220 bits<3> CD8_Form = form.Value;
223 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
224 class XOP { Encoding OpEnc = EncXOP; }
225 class XOP_4V : XOP { bit hasVEX_4V = 1; }
227 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
230 Domain d = GenericDomain>
232 let Namespace = "X86";
234 bits<8> Opcode = opcod;
236 bits<7> FormBits = Form.Value;
239 dag OutOperandList = outs;
240 dag InOperandList = ins;
241 string AsmString = AsmStr;
243 // If this is a pseudo instruction, mark it isCodeGenOnly.
244 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
246 let Itinerary = itin;
249 // Attributes specific to X86 instructions...
251 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
252 // isCodeGenonly. Needed to hide an ambiguous
253 // AsmString from the parser, but still disassemble.
255 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
256 // based on operand size of the mode?
257 bits<2> OpSizeBits = OpSize.Value;
258 AddressSize AdSize = AdSizeX; // Does this instruction's encoding change
259 // based on address size of the mode?
260 bits<2> AdSizeBits = AdSize.Value;
262 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
263 bits<3> OpPrefixBits = OpPrefix.Value;
264 Map OpMap = OB; // Which opcode map does this inst have?
265 bits<3> OpMapBits = OpMap.Value;
266 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
267 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
268 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
269 Domain ExeDomain = d;
270 bit hasREPPrefix = 0; // Does this inst have a REP prefix?
271 Encoding OpEnc = EncNormal; // Encoding used by this instruction
272 bits<2> OpEncBits = OpEnc.Value;
273 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
274 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
275 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
276 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
277 bit hasEVEX_K = 0; // Does this inst require masking?
278 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
279 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
280 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
281 bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width.
282 // Declare it int rather than bits<4> so that all bits are defined when
283 // assigning to bits<7>.
284 int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes.
285 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
286 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
289 let EVEX_LL{0} = hasVEX_L;
290 let EVEX_LL{1} = hasEVEX_L2;
291 // Vector size in bytes.
292 bits<7> VectSize = !shl(16, EVEX_LL);
294 // The scaling factor for AVX512's compressed displacement is either
295 // - the size of a power-of-two number of elements or
296 // - the size of a single element for broadcasts or
297 // - the total vector size divided by a power-of-two number.
298 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64.
299 bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value),
301 !shl(CD8_EltSize, CD8_Form{1-0}),
304 !srl(VectSize, CD8_Form{1-0}))), 0);
306 // TSFlags layout should be kept in sync with X86BaseInfo.h.
307 let TSFlags{6-0} = FormBits;
308 let TSFlags{8-7} = OpSizeBits;
309 let TSFlags{10-9} = AdSizeBits;
310 let TSFlags{13-11} = OpPrefixBits;
311 let TSFlags{16-14} = OpMapBits;
312 let TSFlags{17} = hasREX_WPrefix;
313 let TSFlags{21-18} = ImmT.Value;
314 let TSFlags{24-22} = FPForm.Value;
315 let TSFlags{25} = hasLockPrefix;
316 let TSFlags{26} = hasREPPrefix;
317 let TSFlags{28-27} = ExeDomain.Value;
318 let TSFlags{30-29} = OpEncBits;
319 let TSFlags{38-31} = Opcode;
320 let TSFlags{39} = hasVEX_WPrefix;
321 let TSFlags{40} = hasVEX_4V;
322 let TSFlags{41} = hasVEX_L;
323 let TSFlags{42} = hasEVEX_K;
324 let TSFlags{43} = hasEVEX_Z;
325 let TSFlags{44} = hasEVEX_L2;
326 let TSFlags{45} = hasEVEX_B;
327 // If we run out of TSFlags bits, it's possible to encode this in 3 bits.
328 let TSFlags{52-46} = CD8_Scale;
329 let TSFlags{53} = has3DNow0F0FOpcode;
330 let TSFlags{54} = hasEVEX_RC;
333 class PseudoI<dag oops, dag iops, list<dag> pattern>
334 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
335 let Pattern = pattern;
338 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
339 list<dag> pattern, InstrItinClass itin = NoItinerary,
340 Domain d = GenericDomain>
341 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
342 let Pattern = pattern;
345 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
346 list<dag> pattern, InstrItinClass itin = NoItinerary,
347 Domain d = GenericDomain>
348 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
349 let Pattern = pattern;
352 class Ii8Reg<bits<8> o, Format f, dag outs, dag ins, string asm,
353 list<dag> pattern, InstrItinClass itin = NoItinerary,
354 Domain d = GenericDomain>
355 : X86Inst<o, f, Imm8Reg, outs, ins, asm, itin, d> {
356 let Pattern = pattern;
359 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
360 list<dag> pattern, InstrItinClass itin = NoItinerary>
361 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
362 let Pattern = pattern;
365 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
366 list<dag> pattern, InstrItinClass itin = NoItinerary>
367 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
368 let Pattern = pattern;
371 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
372 list<dag> pattern, InstrItinClass itin = NoItinerary>
373 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
374 let Pattern = pattern;
377 class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,
378 list<dag> pattern, InstrItinClass itin = NoItinerary>
379 : X86Inst<o, f, Imm32S, outs, ins, asm, itin> {
380 let Pattern = pattern;
384 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
385 list<dag> pattern, InstrItinClass itin = NoItinerary>
386 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
387 let Pattern = pattern;
391 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
392 list<dag> pattern, InstrItinClass itin = NoItinerary>
393 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
394 let Pattern = pattern;
398 // FPStack Instruction Templates:
399 // FPI - Floating Point Instruction template.
400 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
401 InstrItinClass itin = NoItinerary>
402 : I<o, F, outs, ins, asm, [], itin> {}
404 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
405 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
406 InstrItinClass itin = NoItinerary>
407 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
409 let Pattern = pattern;
412 // Templates for instructions that use a 16- or 32-bit segmented address as
413 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
415 // Iseg16 - 16-bit segment selector, 16-bit offset
416 // Iseg32 - 16-bit segment selector, 32-bit offset
418 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
419 list<dag> pattern, InstrItinClass itin = NoItinerary>
420 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
421 let Pattern = pattern;
425 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
426 list<dag> pattern, InstrItinClass itin = NoItinerary>
427 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
428 let Pattern = pattern;
432 // SI - SSE 1 & 2 scalar instructions
433 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
434 list<dag> pattern, InstrItinClass itin = NoItinerary,
435 Domain d = GenericDomain>
436 : I<o, F, outs, ins, asm, pattern, itin, d> {
437 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
438 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
439 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
440 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
441 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
444 // AVX instructions have a 'v' prefix in the mnemonic
445 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
446 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
450 // SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512
451 class SI_Int<bits<8> o, Format F, dag outs, dag ins, string asm,
452 list<dag> pattern, InstrItinClass itin = NoItinerary,
453 Domain d = GenericDomain>
454 : I<o, F, outs, ins, asm, pattern, itin, d> {
455 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
456 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
457 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
458 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
459 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
462 // AVX instructions have a 'v' prefix in the mnemonic
463 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
464 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
467 // SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512
468 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
469 list<dag> pattern, InstrItinClass itin = NoItinerary>
470 : Ii8<o, F, outs, ins, asm, pattern, itin> {
471 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
472 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
473 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
476 // AVX instructions have a 'v' prefix in the mnemonic
477 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
478 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
482 // PI - SSE 1 & 2 packed instructions
483 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
484 InstrItinClass itin, Domain d>
485 : I<o, F, outs, ins, asm, pattern, itin, d> {
486 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
487 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
488 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
491 // AVX instructions have a 'v' prefix in the mnemonic
492 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
493 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
497 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
498 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
499 InstrItinClass itin, Domain d>
500 : I<o, F, outs, ins, asm, pattern, itin, d> {
501 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2],
505 // PIi8 - SSE 1 & 2 packed instructions with immediate
506 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
507 list<dag> pattern, InstrItinClass itin, Domain d>
508 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
509 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
510 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
511 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
514 // AVX instructions have a 'v' prefix in the mnemonic
515 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
516 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
520 // SSE1 Instruction Templates:
522 // SSI - SSE1 instructions with XS prefix.
523 // PSI - SSE1 instructions with PS prefix.
524 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
525 // VSSI - SSE1 instructions with XS prefix in AVX form.
526 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
528 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
529 list<dag> pattern, InstrItinClass itin = NoItinerary>
530 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
531 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
532 list<dag> pattern, InstrItinClass itin = NoItinerary>
533 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
534 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
535 list<dag> pattern, InstrItinClass itin = NoItinerary>
536 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
538 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
539 list<dag> pattern, InstrItinClass itin = NoItinerary>
540 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
542 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
543 list<dag> pattern, InstrItinClass itin = NoItinerary>
544 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
546 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
547 list<dag> pattern, InstrItinClass itin = NoItinerary>
548 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, PS,
551 // SSE2 Instruction Templates:
553 // SDI - SSE2 instructions with XD prefix.
554 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
555 // S2SI - SSE2 instructions with XS prefix.
556 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
557 // PDI - SSE2 instructions with PD prefix, packed double domain.
558 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
559 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
560 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
561 // packed double domain.
562 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
563 // S2I - SSE2 scalar instructions with PD prefix.
564 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
566 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
569 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
570 list<dag> pattern, InstrItinClass itin = NoItinerary>
571 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
572 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
573 list<dag> pattern, InstrItinClass itin = NoItinerary>
574 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
575 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
576 list<dag> pattern, InstrItinClass itin = NoItinerary>
577 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
578 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
579 list<dag> pattern, InstrItinClass itin = NoItinerary>
580 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
581 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
582 list<dag> pattern, InstrItinClass itin = NoItinerary>
583 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
585 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
586 list<dag> pattern, InstrItinClass itin = NoItinerary>
587 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
589 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
590 list<dag> pattern, InstrItinClass itin = NoItinerary>
591 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
593 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
594 list<dag> pattern, InstrItinClass itin = NoItinerary>
595 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
597 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
598 list<dag> pattern, InstrItinClass itin = NoItinerary>
599 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
600 PD, Requires<[HasAVX]>;
601 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
602 list<dag> pattern, InstrItinClass itin = NoItinerary>
603 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
605 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
606 list<dag> pattern, InstrItinClass itin = NoItinerary>
607 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
608 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
609 list<dag> pattern, InstrItinClass itin = NoItinerary>
610 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
611 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
612 list<dag> pattern, InstrItinClass itin = NoItinerary>
613 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
615 // SSE3 Instruction Templates:
617 // S3I - SSE3 instructions with PD prefixes.
618 // S3SI - SSE3 instructions with XS prefix.
619 // S3DI - SSE3 instructions with XD prefix.
621 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
622 list<dag> pattern, InstrItinClass itin = NoItinerary>
623 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
625 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
626 list<dag> pattern, InstrItinClass itin = NoItinerary>
627 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
629 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
630 list<dag> pattern, InstrItinClass itin = NoItinerary>
631 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
635 // SSSE3 Instruction Templates:
637 // SS38I - SSSE3 instructions with T8 prefix.
638 // SS3AI - SSSE3 instructions with TA prefix.
639 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
640 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
642 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
643 // uses the MMX registers. The 64-bit versions are grouped with the MMX
644 // classes. They need to be enabled even if AVX is enabled.
646 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
647 list<dag> pattern, InstrItinClass itin = NoItinerary>
648 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
649 Requires<[UseSSSE3]>;
650 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
651 list<dag> pattern, InstrItinClass itin = NoItinerary>
652 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
653 Requires<[UseSSSE3]>;
654 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
655 list<dag> pattern, InstrItinClass itin = NoItinerary>
656 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PS,
657 Requires<[HasSSSE3]>;
658 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
659 list<dag> pattern, InstrItinClass itin = NoItinerary>
660 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPS,
661 Requires<[HasSSSE3]>;
663 // SSE4.1 Instruction Templates:
665 // SS48I - SSE 4.1 instructions with T8 prefix.
666 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
668 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
669 list<dag> pattern, InstrItinClass itin = NoItinerary>
670 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
671 Requires<[UseSSE41]>;
672 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
673 list<dag> pattern, InstrItinClass itin = NoItinerary>
674 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
675 Requires<[UseSSE41]>;
677 // SSE4.2 Instruction Templates:
679 // SS428I - SSE 4.2 instructions with T8 prefix.
680 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
681 list<dag> pattern, InstrItinClass itin = NoItinerary>
682 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
683 Requires<[UseSSE42]>;
685 // SS42FI - SSE 4.2 instructions with T8XD prefix.
686 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
687 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
688 list<dag> pattern, InstrItinClass itin = NoItinerary>
689 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
691 // SS42AI = SSE 4.2 instructions with TA prefix
692 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
693 list<dag> pattern, InstrItinClass itin = NoItinerary>
694 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
695 Requires<[UseSSE42]>;
697 // AVX Instruction Templates:
698 // Instructions introduced in AVX (no SSE equivalent forms)
700 // AVX8I - AVX instructions with T8PD prefix.
701 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
702 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
703 list<dag> pattern, InstrItinClass itin = NoItinerary>
704 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
706 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
707 list<dag> pattern, InstrItinClass itin = NoItinerary>
708 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
711 // AVX2 Instruction Templates:
712 // Instructions introduced in AVX2 (no SSE equivalent forms)
714 // AVX28I - AVX2 instructions with T8PD prefix.
715 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
716 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
717 list<dag> pattern, InstrItinClass itin = NoItinerary>
718 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
720 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
721 list<dag> pattern, InstrItinClass itin = NoItinerary>
722 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
726 // AVX-512 Instruction Templates:
727 // Instructions introduced in AVX-512 (no SSE equivalent forms)
729 // AVX5128I - AVX-512 instructions with T8PD prefix.
730 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
731 // AVX512PDI - AVX-512 instructions with PD, double packed.
732 // AVX512PSI - AVX-512 instructions with PS, single packed.
733 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
734 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
735 // AVX512BI - AVX-512 instructions with PD, int packed domain.
736 // AVX512SI - AVX-512 scalar instructions with PD prefix.
738 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
739 list<dag> pattern, InstrItinClass itin = NoItinerary>
740 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
741 Requires<[HasAVX512]>;
742 class AVX5128IBase : T8PD {
743 Domain ExeDomain = SSEPackedInt;
745 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
746 list<dag> pattern, InstrItinClass itin = NoItinerary>
747 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
748 Requires<[HasAVX512]>;
749 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
750 list<dag> pattern, InstrItinClass itin = NoItinerary>
751 : I<o, F, outs, ins, asm, pattern, itin>, XS,
752 Requires<[HasAVX512]>;
753 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
754 list<dag> pattern, InstrItinClass itin = NoItinerary>
755 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
756 Requires<[HasAVX512]>;
757 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
758 list<dag> pattern, InstrItinClass itin = NoItinerary>
759 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
760 Requires<[HasAVX512]>;
761 class AVX512BIBase : PD {
762 Domain ExeDomain = SSEPackedInt;
764 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
765 list<dag> pattern, InstrItinClass itin = NoItinerary>
766 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
767 Requires<[HasAVX512]>;
768 class AVX512BIi8Base : PD {
769 Domain ExeDomain = SSEPackedInt;
772 class AVX512XSIi8Base : XS {
773 Domain ExeDomain = SSEPackedInt;
776 class AVX512XDIi8Base : XD {
777 Domain ExeDomain = SSEPackedInt;
780 class AVX512PSIi8Base : PS {
781 Domain ExeDomain = SSEPackedSingle;
784 class AVX512PDIi8Base : PD {
785 Domain ExeDomain = SSEPackedDouble;
788 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
789 list<dag> pattern, InstrItinClass itin = NoItinerary>
790 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
791 Requires<[HasAVX512]>;
792 class AVX512AIi8Base : TAPD {
795 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
796 list<dag> pattern, InstrItinClass itin = NoItinerary>
797 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>,
798 Requires<[HasAVX512]>;
799 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
800 list<dag> pattern, InstrItinClass itin = NoItinerary>
801 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
802 Requires<[HasAVX512]>;
803 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
804 list<dag> pattern, InstrItinClass itin = NoItinerary>
805 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
806 Requires<[HasAVX512]>;
807 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
808 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
809 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
810 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
811 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
812 : I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
813 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
814 list<dag>pattern, InstrItinClass itin = NoItinerary>
815 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
816 EVEX_4V, Requires<[HasAVX512]>;
817 class AVX512FMA3Base : T8PD, EVEX_4V;
819 class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
820 list<dag>pattern, InstrItinClass itin = NoItinerary>
821 : I<o, F, outs, ins, asm, pattern, itin>, Requires<[HasAVX512]>;
823 // AES Instruction Templates:
826 // These use the same encoding as the SSE4.2 T8 and TA encodings.
827 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
828 list<dag>pattern, InstrItinClass itin = IIC_AES>
829 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
832 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
833 list<dag> pattern, InstrItinClass itin = NoItinerary>
834 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
837 // PCLMUL Instruction Templates
838 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
839 list<dag>pattern, InstrItinClass itin = NoItinerary>
840 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
841 Requires<[HasPCLMUL]>;
843 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
844 list<dag>pattern, InstrItinClass itin = NoItinerary>
845 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
846 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
848 // FMA3 Instruction Templates
849 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
850 list<dag>pattern, InstrItinClass itin = NoItinerary>
851 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
852 VEX_4V, FMASC, Requires<[HasFMA, NoVLX]>;
854 // FMA4 Instruction Templates
855 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
856 list<dag>pattern, InstrItinClass itin = NoItinerary>
857 : Ii8Reg<o, F, outs, ins, asm, pattern, itin>, TAPD,
858 VEX_4V, FMASC, Requires<[HasFMA4]>;
860 // XOP 2, 3 and 4 Operand Instruction Template
861 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
862 list<dag> pattern, InstrItinClass itin = NoItinerary>
863 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
864 XOP9, Requires<[HasXOP]>;
866 // XOP 2 and 3 Operand Instruction Templates with imm byte
867 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
868 list<dag> pattern, InstrItinClass itin = NoItinerary>
869 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
870 XOP8, Requires<[HasXOP]>;
871 // XOP 4 Operand Instruction Templates with imm byte
872 class IXOPi8Reg<bits<8> o, Format F, dag outs, dag ins, string asm,
873 list<dag> pattern, InstrItinClass itin = NoItinerary>
874 : Ii8Reg<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
875 XOP8, Requires<[HasXOP]>;
877 // XOP 5 operand instruction (VEX encoding!)
878 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
879 list<dag>pattern, InstrItinClass itin = NoItinerary>
880 : Ii8Reg<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
881 VEX_4V, Requires<[HasXOP]>;
883 // X86-64 Instruction templates...
886 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
887 list<dag> pattern, InstrItinClass itin = NoItinerary>
888 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
889 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
890 list<dag> pattern, InstrItinClass itin = NoItinerary>
891 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
892 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
893 list<dag> pattern, InstrItinClass itin = NoItinerary>
894 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W;
895 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
896 list<dag> pattern, InstrItinClass itin = NoItinerary>
897 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
898 class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm,
899 list<dag> pattern, InstrItinClass itin = NoItinerary>
900 : Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W;
902 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
903 list<dag> pattern, InstrItinClass itin = NoItinerary>
904 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
905 let Pattern = pattern;
909 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
910 list<dag> pattern, InstrItinClass itin = NoItinerary>
911 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
912 let Pattern = pattern;
916 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
917 list<dag> pattern, InstrItinClass itin = NoItinerary>
918 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
919 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
920 list<dag> pattern, InstrItinClass itin = NoItinerary>
921 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
923 // MMX Instruction templates
926 // MMXI - MMX instructions with TB prefix.
927 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
928 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
929 // MMX2I - MMX / SSE2 instructions with PD prefix.
930 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
931 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
932 // MMXID - MMX instructions with XD prefix.
933 // MMXIS - MMX instructions with XS prefix.
934 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
935 list<dag> pattern, InstrItinClass itin = NoItinerary>
936 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
937 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
938 list<dag> pattern, InstrItinClass itin = NoItinerary>
939 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,Not64BitMode]>;
940 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
941 list<dag> pattern, InstrItinClass itin = NoItinerary>
942 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,In64BitMode]>;
943 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
944 list<dag> pattern, InstrItinClass itin = NoItinerary>
945 : I<o, F, outs, ins, asm, pattern, itin>, PS, REX_W, Requires<[HasMMX]>;
946 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
947 list<dag> pattern, InstrItinClass itin = NoItinerary>
948 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
949 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
950 list<dag> pattern, InstrItinClass itin = NoItinerary>
951 : Ii8<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
952 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
953 list<dag> pattern, InstrItinClass itin = NoItinerary>
954 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
955 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
956 list<dag> pattern, InstrItinClass itin = NoItinerary>
957 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;