1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<7> val> {
21 def Pseudo : Format<0>;
22 def RawFrm : Format<1>;
23 def AddRegFrm : Format<2>;
24 def RawFrmMemOffs : Format<3>;
25 def RawFrmSrc : Format<4>;
26 def RawFrmDst : Format<5>;
27 def RawFrmDstSrc : Format<6>;
28 def RawFrmImm8 : Format<7>;
29 def RawFrmImm16 : Format<8>;
30 def MRMDestMem : Format<32>;
31 def MRMSrcMem : Format<33>;
32 def MRMSrcMem4VOp3 : Format<34>;
33 def MRMSrcMemOp4 : Format<35>;
34 def MRMXm : Format<39>;
35 def MRM0m : Format<40>; def MRM1m : Format<41>; def MRM2m : Format<42>;
36 def MRM3m : Format<43>; def MRM4m : Format<44>; def MRM5m : Format<45>;
37 def MRM6m : Format<46>; def MRM7m : Format<47>;
38 def MRMDestReg : Format<48>;
39 def MRMSrcReg : Format<49>;
40 def MRMSrcReg4VOp3 : Format<50>;
41 def MRMSrcRegOp4 : Format<51>;
42 def MRMXr : Format<55>;
43 def MRM0r : Format<56>; def MRM1r : Format<57>; def MRM2r : Format<58>;
44 def MRM3r : Format<59>; def MRM4r : Format<60>; def MRM5r : Format<61>;
45 def MRM6r : Format<62>; def MRM7r : Format<63>;
46 def MRM_C0 : Format<64>; def MRM_C1 : Format<65>; def MRM_C2 : Format<66>;
47 def MRM_C3 : Format<67>; def MRM_C4 : Format<68>; def MRM_C5 : Format<69>;
48 def MRM_C6 : Format<70>; def MRM_C7 : Format<71>; def MRM_C8 : Format<72>;
49 def MRM_C9 : Format<73>; def MRM_CA : Format<74>; def MRM_CB : Format<75>;
50 def MRM_CC : Format<76>; def MRM_CD : Format<77>; def MRM_CE : Format<78>;
51 def MRM_CF : Format<79>; def MRM_D0 : Format<80>; def MRM_D1 : Format<81>;
52 def MRM_D2 : Format<82>; def MRM_D3 : Format<83>; def MRM_D4 : Format<84>;
53 def MRM_D5 : Format<85>; def MRM_D6 : Format<86>; def MRM_D7 : Format<87>;
54 def MRM_D8 : Format<88>; def MRM_D9 : Format<89>; def MRM_DA : Format<90>;
55 def MRM_DB : Format<91>; def MRM_DC : Format<92>; def MRM_DD : Format<93>;
56 def MRM_DE : Format<94>; def MRM_DF : Format<95>; def MRM_E0 : Format<96>;
57 def MRM_E1 : Format<97>; def MRM_E2 : Format<98>; def MRM_E3 : Format<99>;
58 def MRM_E4 : Format<100>; def MRM_E5 : Format<101>; def MRM_E6 : Format<102>;
59 def MRM_E7 : Format<103>; def MRM_E8 : Format<104>; def MRM_E9 : Format<105>;
60 def MRM_EA : Format<106>; def MRM_EB : Format<107>; def MRM_EC : Format<108>;
61 def MRM_ED : Format<109>; def MRM_EE : Format<110>; def MRM_EF : Format<111>;
62 def MRM_F0 : Format<112>; def MRM_F1 : Format<113>; def MRM_F2 : Format<114>;
63 def MRM_F3 : Format<115>; def MRM_F4 : Format<116>; def MRM_F5 : Format<117>;
64 def MRM_F6 : Format<118>; def MRM_F7 : Format<119>; def MRM_F8 : Format<120>;
65 def MRM_F9 : Format<121>; def MRM_FA : Format<122>; def MRM_FB : Format<123>;
66 def MRM_FC : Format<124>; def MRM_FD : Format<125>; def MRM_FE : Format<126>;
67 def MRM_FF : Format<127>;
69 // ImmType - This specifies the immediate type used by an instruction. This is
70 // part of the ad-hoc solution used to emit machine instruction encodings by our
71 // machine code emitter.
72 class ImmType<bits<4> val> {
75 def NoImm : ImmType<0>;
76 def Imm8 : ImmType<1>;
77 def Imm8PCRel : ImmType<2>;
78 def Imm8Reg : ImmType<3>; // Register encoded in [7:4].
79 def Imm16 : ImmType<4>;
80 def Imm16PCRel : ImmType<5>;
81 def Imm32 : ImmType<6>;
82 def Imm32PCRel : ImmType<7>;
83 def Imm32S : ImmType<8>;
84 def Imm64 : ImmType<9>;
86 // FPFormat - This specifies what form this FP instruction has. This is used by
87 // the Floating-Point stackifier pass.
88 class FPFormat<bits<3> val> {
91 def NotFP : FPFormat<0>;
92 def ZeroArgFP : FPFormat<1>;
93 def OneArgFP : FPFormat<2>;
94 def OneArgFPRW : FPFormat<3>;
95 def TwoArgFP : FPFormat<4>;
96 def CompareFP : FPFormat<5>;
97 def CondMovFP : FPFormat<6>;
98 def SpecialFP : FPFormat<7>;
100 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
101 // Keep in sync with tables in X86InstrInfo.cpp.
102 class Domain<bits<2> val> {
105 def GenericDomain : Domain<0>;
106 def SSEPackedSingle : Domain<1>;
107 def SSEPackedDouble : Domain<2>;
108 def SSEPackedInt : Domain<3>;
110 // Class specifying the vector form of the decompressed
111 // displacement of 8-bit.
112 class CD8VForm<bits<3> val> {
115 def CD8VF : CD8VForm<0>; // v := VL
116 def CD8VH : CD8VForm<1>; // v := VL/2
117 def CD8VQ : CD8VForm<2>; // v := VL/4
118 def CD8VO : CD8VForm<3>; // v := VL/8
119 // The tuple (subvector) forms.
120 def CD8VT1 : CD8VForm<4>; // v := 1
121 def CD8VT2 : CD8VForm<5>; // v := 2
122 def CD8VT4 : CD8VForm<6>; // v := 4
123 def CD8VT8 : CD8VForm<7>; // v := 8
125 // Class specifying the prefix used an opcode extension.
126 class Prefix<bits<3> val> {
129 def NoPrfx : Prefix<0>;
135 // Class specifying the opcode map.
136 class Map<bits<3> val> {
147 // Class specifying the encoding
148 class Encoding<bits<2> val> {
151 def EncNormal : Encoding<0>;
152 def EncVEX : Encoding<1>;
153 def EncXOP : Encoding<2>;
154 def EncEVEX : Encoding<3>;
156 // Operand size for encodings that change based on mode.
157 class OperandSize<bits<2> val> {
160 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
161 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
162 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
164 // Address size for encodings that change based on mode.
165 class AddressSize<bits<2> val> {
168 def AdSizeX : AddressSize<0>; // Address size determined using addr operand.
169 def AdSize16 : AddressSize<1>; // Encodes a 16-bit address.
170 def AdSize32 : AddressSize<2>; // Encodes a 32-bit address.
171 def AdSize64 : AddressSize<3>; // Encodes a 64-bit address.
173 // Prefix byte classes which are used to indicate to the ad-hoc machine code
174 // emitter that various prefix bytes are required.
175 class OpSize16 { OperandSize OpSize = OpSize16; }
176 class OpSize32 { OperandSize OpSize = OpSize32; }
177 class AdSize16 { AddressSize AdSize = AdSize16; }
178 class AdSize32 { AddressSize AdSize = AdSize32; }
179 class AdSize64 { AddressSize AdSize = AdSize64; }
180 class REX_W { bit hasREX_WPrefix = 1; }
181 class LOCK { bit hasLockPrefix = 1; }
182 class REP { bit hasREPPrefix = 1; }
183 class TB { Map OpMap = TB; }
184 class T8 { Map OpMap = T8; }
185 class TA { Map OpMap = TA; }
186 class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
187 class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
188 class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }
189 class OBXS { Prefix OpPrefix = XS; }
190 class PS : TB { Prefix OpPrefix = PS; }
191 class PD : TB { Prefix OpPrefix = PD; }
192 class XD : TB { Prefix OpPrefix = XD; }
193 class XS : TB { Prefix OpPrefix = XS; }
194 class T8PS : T8 { Prefix OpPrefix = PS; }
195 class T8PD : T8 { Prefix OpPrefix = PD; }
196 class T8XD : T8 { Prefix OpPrefix = XD; }
197 class T8XS : T8 { Prefix OpPrefix = XS; }
198 class TAPS : TA { Prefix OpPrefix = PS; }
199 class TAPD : TA { Prefix OpPrefix = PD; }
200 class TAXD : TA { Prefix OpPrefix = XD; }
201 class VEX { Encoding OpEnc = EncVEX; }
202 class VEX_W { bits<2> VEX_WPrefix = 1; }
203 class VEX_WIG { bits<2> VEX_WPrefix = 2; }
204 class VEX_4V : VEX { bit hasVEX_4V = 1; }
205 class VEX_L { bit hasVEX_L = 1; }
206 class VEX_LIG { bit ignoresVEX_L = 1; }
207 class EVEX : VEX { Encoding OpEnc = EncEVEX; }
208 class EVEX_4V : VEX_4V { Encoding OpEnc = EncEVEX; }
209 class EVEX_K { bit hasEVEX_K = 1; }
210 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
211 class EVEX_B { bit hasEVEX_B = 1; }
212 class EVEX_RC { bit hasEVEX_RC = 1; }
213 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
214 class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; }
215 class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; }
217 // Specify AVX512 8-bit compressed displacement encoding based on the vector
218 // element size in bits (8, 16, 32, 64) and the CDisp8 form.
219 class EVEX_CD8<int esize, CD8VForm form> {
220 int CD8_EltSize = !srl(esize, 3);
221 bits<3> CD8_Form = form.Value;
224 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
225 class XOP { Encoding OpEnc = EncXOP; }
226 class XOP_4V : XOP { bit hasVEX_4V = 1; }
228 // Specify the alternative register form instruction to replace the current
229 // instruction in case it was picked during generation of memory folding tables
230 class FoldGenData<string _RegisterForm> {
231 string FoldGenRegForm = _RegisterForm;
234 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
237 Domain d = GenericDomain>
239 let Namespace = "X86";
241 bits<8> Opcode = opcod;
243 bits<7> FormBits = Form.Value;
246 dag OutOperandList = outs;
247 dag InOperandList = ins;
248 string AsmString = AsmStr;
250 // If this is a pseudo instruction, mark it isCodeGenOnly.
251 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
253 let Itinerary = itin;
256 // Attributes specific to X86 instructions...
258 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
259 // isCodeGenonly. Needed to hide an ambiguous
260 // AsmString from the parser, but still disassemble.
262 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
263 // based on operand size of the mode?
264 bits<2> OpSizeBits = OpSize.Value;
265 AddressSize AdSize = AdSizeX; // Does this instruction's encoding change
266 // based on address size of the mode?
267 bits<2> AdSizeBits = AdSize.Value;
269 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
270 bits<3> OpPrefixBits = OpPrefix.Value;
271 Map OpMap = OB; // Which opcode map does this inst have?
272 bits<3> OpMapBits = OpMap.Value;
273 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
274 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
275 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
276 Domain ExeDomain = d;
277 bit hasREPPrefix = 0; // Does this inst have a REP prefix?
278 Encoding OpEnc = EncNormal; // Encoding used by this instruction
279 bits<2> OpEncBits = OpEnc.Value;
280 bits<2> VEX_WPrefix = 0; // Does this inst set the VEX_W field?
281 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
282 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
283 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
284 bit hasEVEX_K = 0; // Does this inst require masking?
285 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
286 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
287 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
288 bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width.
289 // Declare it int rather than bits<4> so that all bits are defined when
290 // assigning to bits<7>.
291 int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes.
292 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
293 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
296 let EVEX_LL{0} = hasVEX_L;
297 let EVEX_LL{1} = hasEVEX_L2;
298 // Vector size in bytes.
299 bits<7> VectSize = !shl(16, EVEX_LL);
301 // The scaling factor for AVX512's compressed displacement is either
302 // - the size of a power-of-two number of elements or
303 // - the size of a single element for broadcasts or
304 // - the total vector size divided by a power-of-two number.
305 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64.
306 bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value),
308 !shl(CD8_EltSize, CD8_Form{1-0}),
311 !srl(VectSize, CD8_Form{1-0}))), 0);
313 // Used in the memory folding generation (TableGen backend) to point to an alternative
314 // instruction to replace the current one in case it got picked during generation.
315 string FoldGenRegForm = ?;
317 // TSFlags layout should be kept in sync with X86BaseInfo.h.
318 let TSFlags{6-0} = FormBits;
319 let TSFlags{8-7} = OpSizeBits;
320 let TSFlags{10-9} = AdSizeBits;
321 let TSFlags{13-11} = OpPrefixBits;
322 let TSFlags{16-14} = OpMapBits;
323 let TSFlags{17} = hasREX_WPrefix;
324 let TSFlags{21-18} = ImmT.Value;
325 let TSFlags{24-22} = FPForm.Value;
326 let TSFlags{25} = hasLockPrefix;
327 let TSFlags{26} = hasREPPrefix;
328 let TSFlags{28-27} = ExeDomain.Value;
329 let TSFlags{30-29} = OpEncBits;
330 let TSFlags{38-31} = Opcode;
331 // Currently no need for second bit in TSFlags - W Ignore is equivalent to 0.
332 let TSFlags{39} = VEX_WPrefix{0};
333 let TSFlags{40} = hasVEX_4V;
334 let TSFlags{41} = hasVEX_L;
335 let TSFlags{42} = hasEVEX_K;
336 let TSFlags{43} = hasEVEX_Z;
337 let TSFlags{44} = hasEVEX_L2;
338 let TSFlags{45} = hasEVEX_B;
339 // If we run out of TSFlags bits, it's possible to encode this in 3 bits.
340 let TSFlags{52-46} = CD8_Scale;
341 let TSFlags{53} = has3DNow0F0FOpcode;
342 let TSFlags{54} = hasEVEX_RC;
345 class PseudoI<dag oops, dag iops, list<dag> pattern>
346 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
347 let Pattern = pattern;
350 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
351 list<dag> pattern, InstrItinClass itin = NoItinerary,
352 Domain d = GenericDomain>
353 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
354 let Pattern = pattern;
357 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
358 list<dag> pattern, InstrItinClass itin = NoItinerary,
359 Domain d = GenericDomain>
360 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
361 let Pattern = pattern;
364 class Ii8Reg<bits<8> o, Format f, dag outs, dag ins, string asm,
365 list<dag> pattern, InstrItinClass itin = NoItinerary,
366 Domain d = GenericDomain>
367 : X86Inst<o, f, Imm8Reg, outs, ins, asm, itin, d> {
368 let Pattern = pattern;
371 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
372 list<dag> pattern, InstrItinClass itin = NoItinerary>
373 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
374 let Pattern = pattern;
377 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
378 list<dag> pattern, InstrItinClass itin = NoItinerary>
379 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
380 let Pattern = pattern;
383 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
384 list<dag> pattern, InstrItinClass itin = NoItinerary>
385 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
386 let Pattern = pattern;
389 class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,
390 list<dag> pattern, InstrItinClass itin = NoItinerary>
391 : X86Inst<o, f, Imm32S, outs, ins, asm, itin> {
392 let Pattern = pattern;
396 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
397 list<dag> pattern, InstrItinClass itin = NoItinerary>
398 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
399 let Pattern = pattern;
403 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
404 list<dag> pattern, InstrItinClass itin = NoItinerary>
405 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
406 let Pattern = pattern;
410 // FPStack Instruction Templates:
411 // FPI - Floating Point Instruction template.
412 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
413 InstrItinClass itin = NoItinerary>
414 : I<o, F, outs, ins, asm, [], itin> {}
416 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
417 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
418 InstrItinClass itin = NoItinerary>
419 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
421 let Pattern = pattern;
424 // Templates for instructions that use a 16- or 32-bit segmented address as
425 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
427 // Iseg16 - 16-bit segment selector, 16-bit offset
428 // Iseg32 - 16-bit segment selector, 32-bit offset
430 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
431 list<dag> pattern, InstrItinClass itin = NoItinerary>
432 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
433 let Pattern = pattern;
437 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
438 list<dag> pattern, InstrItinClass itin = NoItinerary>
439 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
440 let Pattern = pattern;
444 // SI - SSE 1 & 2 scalar instructions
445 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
446 list<dag> pattern, InstrItinClass itin = NoItinerary,
447 Domain d = GenericDomain>
448 : I<o, F, outs, ins, asm, pattern, itin, d> {
449 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
450 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
451 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
452 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
453 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
456 // AVX instructions have a 'v' prefix in the mnemonic
457 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
458 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
462 // SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512
463 class SI_Int<bits<8> o, Format F, dag outs, dag ins, string asm,
464 list<dag> pattern, InstrItinClass itin = NoItinerary,
465 Domain d = GenericDomain>
466 : I<o, F, outs, ins, asm, pattern, itin, d> {
467 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
468 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
469 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
470 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
471 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
474 // AVX instructions have a 'v' prefix in the mnemonic
475 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
476 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
479 // SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512
480 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
481 list<dag> pattern, InstrItinClass itin = NoItinerary>
482 : Ii8<o, F, outs, ins, asm, pattern, itin> {
483 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
484 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
485 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
488 // AVX instructions have a 'v' prefix in the mnemonic
489 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
490 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
494 // PI - SSE 1 & 2 packed instructions
495 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
496 InstrItinClass itin, Domain d>
497 : I<o, F, outs, ins, asm, pattern, itin, d> {
498 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
499 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
500 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
503 // AVX instructions have a 'v' prefix in the mnemonic
504 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
505 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
509 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
510 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
511 InstrItinClass itin, Domain d>
512 : I<o, F, outs, ins, asm, pattern, itin, d> {
513 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2],
517 // PIi8 - SSE 1 & 2 packed instructions with immediate
518 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
519 list<dag> pattern, InstrItinClass itin, Domain d>
520 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
521 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
522 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
523 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
526 // AVX instructions have a 'v' prefix in the mnemonic
527 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
528 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
532 // SSE1 Instruction Templates:
534 // SSI - SSE1 instructions with XS prefix.
535 // PSI - SSE1 instructions with PS prefix.
536 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
537 // VSSI - SSE1 instructions with XS prefix in AVX form.
538 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
540 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
541 list<dag> pattern, InstrItinClass itin = NoItinerary>
542 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
543 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
544 list<dag> pattern, InstrItinClass itin = NoItinerary>
545 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
546 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
547 list<dag> pattern, InstrItinClass itin = NoItinerary>
548 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
550 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
551 list<dag> pattern, InstrItinClass itin = NoItinerary>
552 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
554 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
555 list<dag> pattern, InstrItinClass itin = NoItinerary>
556 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
558 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
559 list<dag> pattern, InstrItinClass itin = NoItinerary>
560 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, PS,
563 // SSE2 Instruction Templates:
565 // SDI - SSE2 instructions with XD prefix.
566 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
567 // S2SI - SSE2 instructions with XS prefix.
568 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
569 // PDI - SSE2 instructions with PD prefix, packed double domain.
570 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
571 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
572 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
573 // packed double domain.
574 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
575 // S2I - SSE2 scalar instructions with PD prefix.
576 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
578 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
581 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
582 list<dag> pattern, InstrItinClass itin = NoItinerary>
583 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
584 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
585 list<dag> pattern, InstrItinClass itin = NoItinerary>
586 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
587 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
588 list<dag> pattern, InstrItinClass itin = NoItinerary>
589 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
590 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
591 list<dag> pattern, InstrItinClass itin = NoItinerary>
592 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
593 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
594 list<dag> pattern, InstrItinClass itin = NoItinerary>
595 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
597 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
598 list<dag> pattern, InstrItinClass itin = NoItinerary>
599 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
601 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
602 list<dag> pattern, InstrItinClass itin = NoItinerary>
603 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
605 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
606 list<dag> pattern, InstrItinClass itin = NoItinerary>
607 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
609 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
610 list<dag> pattern, InstrItinClass itin = NoItinerary>
611 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
612 PD, Requires<[HasAVX]>;
613 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
614 list<dag> pattern, InstrItinClass itin = NoItinerary>
615 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
617 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
618 list<dag> pattern, InstrItinClass itin = NoItinerary>
619 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
620 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
621 list<dag> pattern, InstrItinClass itin = NoItinerary>
622 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
623 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
624 list<dag> pattern, InstrItinClass itin = NoItinerary>
625 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
627 // SSE3 Instruction Templates:
629 // S3I - SSE3 instructions with PD prefixes.
630 // S3SI - SSE3 instructions with XS prefix.
631 // S3DI - SSE3 instructions with XD prefix.
633 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
634 list<dag> pattern, InstrItinClass itin = NoItinerary>
635 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
637 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
638 list<dag> pattern, InstrItinClass itin = NoItinerary>
639 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
641 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
642 list<dag> pattern, InstrItinClass itin = NoItinerary>
643 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
647 // SSSE3 Instruction Templates:
649 // SS38I - SSSE3 instructions with T8 prefix.
650 // SS3AI - SSSE3 instructions with TA prefix.
651 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
652 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
654 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
655 // uses the MMX registers. The 64-bit versions are grouped with the MMX
656 // classes. They need to be enabled even if AVX is enabled.
658 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
659 list<dag> pattern, InstrItinClass itin = NoItinerary>
660 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
661 Requires<[UseSSSE3]>;
662 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
663 list<dag> pattern, InstrItinClass itin = NoItinerary>
664 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
665 Requires<[UseSSSE3]>;
666 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
667 list<dag> pattern, InstrItinClass itin = NoItinerary>
668 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PS,
669 Requires<[HasSSSE3]>;
670 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
671 list<dag> pattern, InstrItinClass itin = NoItinerary>
672 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPS,
673 Requires<[HasSSSE3]>;
675 // SSE4.1 Instruction Templates:
677 // SS48I - SSE 4.1 instructions with T8 prefix.
678 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
680 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
681 list<dag> pattern, InstrItinClass itin = NoItinerary>
682 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
683 Requires<[UseSSE41]>;
684 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
685 list<dag> pattern, InstrItinClass itin = NoItinerary>
686 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
687 Requires<[UseSSE41]>;
689 // SSE4.2 Instruction Templates:
691 // SS428I - SSE 4.2 instructions with T8 prefix.
692 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
693 list<dag> pattern, InstrItinClass itin = NoItinerary>
694 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
695 Requires<[UseSSE42]>;
697 // SS42FI - SSE 4.2 instructions with T8XD prefix.
698 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
699 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
700 list<dag> pattern, InstrItinClass itin = NoItinerary>
701 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
703 // SS42AI = SSE 4.2 instructions with TA prefix
704 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
705 list<dag> pattern, InstrItinClass itin = NoItinerary>
706 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
707 Requires<[UseSSE42]>;
709 // AVX Instruction Templates:
710 // Instructions introduced in AVX (no SSE equivalent forms)
712 // AVX8I - AVX instructions with T8PD prefix.
713 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
714 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
715 list<dag> pattern, InstrItinClass itin = NoItinerary>
716 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
718 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
719 list<dag> pattern, InstrItinClass itin = NoItinerary>
720 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
723 // AVX2 Instruction Templates:
724 // Instructions introduced in AVX2 (no SSE equivalent forms)
726 // AVX28I - AVX2 instructions with T8PD prefix.
727 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
728 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
729 list<dag> pattern, InstrItinClass itin = NoItinerary>
730 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
732 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
733 list<dag> pattern, InstrItinClass itin = NoItinerary>
734 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
738 // AVX-512 Instruction Templates:
739 // Instructions introduced in AVX-512 (no SSE equivalent forms)
741 // AVX5128I - AVX-512 instructions with T8PD prefix.
742 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
743 // AVX512PDI - AVX-512 instructions with PD, double packed.
744 // AVX512PSI - AVX-512 instructions with PS, single packed.
745 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
746 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
747 // AVX512BI - AVX-512 instructions with PD, int packed domain.
748 // AVX512SI - AVX-512 scalar instructions with PD prefix.
750 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
751 list<dag> pattern, InstrItinClass itin = NoItinerary>
752 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
753 Requires<[HasAVX512]>;
754 class AVX5128IBase : T8PD {
755 Domain ExeDomain = SSEPackedInt;
757 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
758 list<dag> pattern, InstrItinClass itin = NoItinerary>
759 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
760 Requires<[HasAVX512]>;
761 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
762 list<dag> pattern, InstrItinClass itin = NoItinerary>
763 : I<o, F, outs, ins, asm, pattern, itin>, XS,
764 Requires<[HasAVX512]>;
765 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
766 list<dag> pattern, InstrItinClass itin = NoItinerary>
767 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
768 Requires<[HasAVX512]>;
769 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
770 list<dag> pattern, InstrItinClass itin = NoItinerary>
771 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
772 Requires<[HasAVX512]>;
773 class AVX512BIBase : PD {
774 Domain ExeDomain = SSEPackedInt;
776 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
777 list<dag> pattern, InstrItinClass itin = NoItinerary>
778 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
779 Requires<[HasAVX512]>;
780 class AVX512BIi8Base : PD {
781 Domain ExeDomain = SSEPackedInt;
784 class AVX512XSIi8Base : XS {
785 Domain ExeDomain = SSEPackedInt;
788 class AVX512XDIi8Base : XD {
789 Domain ExeDomain = SSEPackedInt;
792 class AVX512PSIi8Base : PS {
793 Domain ExeDomain = SSEPackedSingle;
796 class AVX512PDIi8Base : PD {
797 Domain ExeDomain = SSEPackedDouble;
800 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
801 list<dag> pattern, InstrItinClass itin = NoItinerary>
802 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
803 Requires<[HasAVX512]>;
804 class AVX512AIi8Base : TAPD {
807 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
808 list<dag> pattern, InstrItinClass itin = NoItinerary>
809 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>,
810 Requires<[HasAVX512]>;
811 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
812 list<dag> pattern, InstrItinClass itin = NoItinerary>
813 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
814 Requires<[HasAVX512]>;
815 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
816 list<dag> pattern, InstrItinClass itin = NoItinerary>
817 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
818 Requires<[HasAVX512]>;
819 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
820 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
821 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
822 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
823 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
824 : I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
825 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
826 list<dag>pattern, InstrItinClass itin = NoItinerary>
827 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
828 EVEX_4V, Requires<[HasAVX512]>;
829 class AVX512FMA3Base : T8PD, EVEX_4V;
831 class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
832 list<dag>pattern, InstrItinClass itin = NoItinerary>
833 : I<o, F, outs, ins, asm, pattern, itin>, Requires<[HasAVX512]>;
835 // AES Instruction Templates:
838 // These use the same encoding as the SSE4.2 T8 and TA encodings.
839 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
840 list<dag>pattern, InstrItinClass itin = IIC_AES>
841 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
844 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
845 list<dag> pattern, InstrItinClass itin = NoItinerary>
846 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
849 // PCLMUL Instruction Templates
850 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
851 list<dag>pattern, InstrItinClass itin = NoItinerary>
852 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
853 Requires<[HasPCLMUL]>;
855 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
856 list<dag>pattern, InstrItinClass itin = NoItinerary>
857 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
858 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
860 // FMA3 Instruction Templates
861 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
862 list<dag>pattern, InstrItinClass itin = NoItinerary>
863 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
864 VEX_4V, FMASC, Requires<[HasFMA, NoVLX]>;
866 // FMA4 Instruction Templates
867 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
868 list<dag>pattern, InstrItinClass itin = NoItinerary>
869 : Ii8Reg<o, F, outs, ins, asm, pattern, itin>, TAPD,
870 VEX_4V, FMASC, Requires<[HasFMA4]>;
872 // XOP 2, 3 and 4 Operand Instruction Template
873 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
874 list<dag> pattern, InstrItinClass itin = NoItinerary>
875 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
876 XOP9, Requires<[HasXOP]>;
878 // XOP 2 and 3 Operand Instruction Templates with imm byte
879 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
880 list<dag> pattern, InstrItinClass itin = NoItinerary>
881 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
882 XOP8, Requires<[HasXOP]>;
883 // XOP 4 Operand Instruction Templates with imm byte
884 class IXOPi8Reg<bits<8> o, Format F, dag outs, dag ins, string asm,
885 list<dag> pattern, InstrItinClass itin = NoItinerary>
886 : Ii8Reg<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
887 XOP8, Requires<[HasXOP]>;
889 // XOP 5 operand instruction (VEX encoding!)
890 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
891 list<dag>pattern, InstrItinClass itin = NoItinerary>
892 : Ii8Reg<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
893 VEX_4V, Requires<[HasXOP]>;
895 // X86-64 Instruction templates...
898 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
899 list<dag> pattern, InstrItinClass itin = NoItinerary>
900 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
901 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
902 list<dag> pattern, InstrItinClass itin = NoItinerary>
903 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
904 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
905 list<dag> pattern, InstrItinClass itin = NoItinerary>
906 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W;
907 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
908 list<dag> pattern, InstrItinClass itin = NoItinerary>
909 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
910 class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm,
911 list<dag> pattern, InstrItinClass itin = NoItinerary>
912 : Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W;
914 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
915 list<dag> pattern, InstrItinClass itin = NoItinerary>
916 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
917 let Pattern = pattern;
921 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
922 list<dag> pattern, InstrItinClass itin = NoItinerary>
923 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
924 let Pattern = pattern;
928 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
929 list<dag> pattern, InstrItinClass itin = NoItinerary>
930 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
931 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
932 list<dag> pattern, InstrItinClass itin = NoItinerary>
933 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
935 // MMX Instruction templates
938 // MMXI - MMX instructions with TB prefix.
939 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
940 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
941 // MMX2I - MMX / SSE2 instructions with PD prefix.
942 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
943 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
944 // MMXID - MMX instructions with XD prefix.
945 // MMXIS - MMX instructions with XS prefix.
946 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
947 list<dag> pattern, InstrItinClass itin = NoItinerary>
948 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
949 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
950 list<dag> pattern, InstrItinClass itin = NoItinerary>
951 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,Not64BitMode]>;
952 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
953 list<dag> pattern, InstrItinClass itin = NoItinerary>
954 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,In64BitMode]>;
955 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
956 list<dag> pattern, InstrItinClass itin = NoItinerary>
957 : I<o, F, outs, ins, asm, pattern, itin>, PS, REX_W, Requires<[HasMMX]>;
958 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
959 list<dag> pattern, InstrItinClass itin = NoItinerary>
960 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
961 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
962 list<dag> pattern, InstrItinClass itin = NoItinerary>
963 : Ii8<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
964 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
965 list<dag> pattern, InstrItinClass itin = NoItinerary>
966 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
967 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
968 list<dag> pattern, InstrItinClass itin = NoItinerary>
969 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;