contrib/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

   1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides pattern fragments useful for SIMD instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // MMX specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // Low word of MMX to GPR.
  19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
  20                             [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
  21 // GPR to low word of MMX.
  22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
  23                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
  24
  25 //===----------------------------------------------------------------------===//
  26 // MMX Pattern Fragments
  27 //===----------------------------------------------------------------------===//
  28
  29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
  30
  31 //===----------------------------------------------------------------------===//
  32 // SSE specific DAG Nodes.
  33 //===----------------------------------------------------------------------===//
  34
  35 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
  36                                        SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  37                                        SDTCisVT<3, i8>]>;
  38
  39 def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
  40 def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
  41 def X86fmins   : SDNode<"X86ISD::FMINS",     SDTFPBinOp>;
  42 def X86fmaxs   : SDNode<"X86ISD::FMAXS",     SDTFPBinOp>;
  43
  44 // Commutative and Associative FMIN and FMAX.
  45 def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
  46     [SDNPCommutative, SDNPAssociative]>;
  47 def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
  48     [SDNPCommutative, SDNPAssociative]>;
  49
  50 def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
  51                         [SDNPCommutative, SDNPAssociative]>;
  52 def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
  53                         [SDNPCommutative, SDNPAssociative]>;
  54 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
  55                         [SDNPCommutative, SDNPAssociative]>;
  56 def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp>;
  57 def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
  58 def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
  59 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
  60 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
  61 def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
  62 def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
  63 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
  64 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
  65 def X86cmps    : SDNode<"X86ISD::FSETCC",     SDTX86Cmps>;
  66 def X86pshufb  : SDNode<"X86ISD::PSHUFB",
  67                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
  68                                       SDTCisSameAs<0,2>]>>;
  69 def X86psadbw  : SDNode<"X86ISD::PSADBW",
  70                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
  71                                       SDTCVecEltisVT<1, i8>,
  72                                       SDTCisSameSizeAs<0,1>,
  73                                       SDTCisSameAs<1,2>]>, [SDNPCommutative]>;
  74 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
  75                   SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
  76                                        SDTCVecEltisVT<1, i8>,
  77                                        SDTCisSameSizeAs<0,1>,
  78                                        SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>>;
  79 def X86andnp   : SDNode<"X86ISD::ANDNP",
  80                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  81                                       SDTCisSameAs<0,2>]>>;
  82 def X86multishift   : SDNode<"X86ISD::MULTISHIFT",
  83                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
  84                                       SDTCisSameAs<1,2>]>>;
  85 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
  86                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
  87                                       SDTCisPtrTy<2>]>>;
  88 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
  89                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
  90                                       SDTCisPtrTy<2>]>>;
  91 def X86pinsrb  : SDNode<"X86ISD::PINSRB",
  92                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
  93                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
  94 def X86pinsrw  : SDNode<"X86ISD::PINSRW",
  95                  SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
  96                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
  97 def X86insertps : SDNode<"X86ISD::INSERTPS",
  98                  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
  99                                       SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
 100 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
 101                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 102
 103 def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
 104                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 105
 106 def SDTVtrunc    : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 107                                         SDTCisInt<0>, SDTCisInt<1>,
 108                                         SDTCisOpSmallerThanOp<0, 1>]>;
 109 def SDTVmtrunc   : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 110                                         SDTCisInt<0>, SDTCisInt<1>,
 111                                         SDTCisOpSmallerThanOp<0, 1>,
 112                                         SDTCisSameAs<0, 2>,
 113                                         SDTCVecEltisVT<3, i1>,
 114                                         SDTCisSameNumEltsAs<1, 3>]>;
 115
 116 def X86vtrunc    : SDNode<"X86ISD::VTRUNC",   SDTVtrunc>;
 117 def X86vtruncs   : SDNode<"X86ISD::VTRUNCS",  SDTVtrunc>;
 118 def X86vtruncus  : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
 119 def X86vmtrunc   : SDNode<"X86ISD::VMTRUNC",   SDTVmtrunc>;
 120 def X86vmtruncs  : SDNode<"X86ISD::VMTRUNCS",  SDTVmtrunc>;
 121 def X86vmtruncus : SDNode<"X86ISD::VMTRUNCUS", SDTVmtrunc>;
 122
 123 def X86vfpext  : SDNode<"X86ISD::VFPEXT",
 124                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>,
 125                                              SDTCVecEltisVT<1, f32>,
 126                                              SDTCisSameSizeAs<0, 1>]>>;
 127 def X86vfpround: SDNode<"X86ISD::VFPROUND",
 128                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
 129                                              SDTCVecEltisVT<1, f64>,
 130                                              SDTCisSameSizeAs<0, 1>]>>;
 131
 132 def X86froundRnd: SDNode<"X86ISD::VFPROUNDS_RND",
 133                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
 134                                              SDTCisSameAs<0, 1>,
 135                                              SDTCVecEltisVT<2, f64>,
 136                                              SDTCisSameSizeAs<0, 2>,
 137                                              SDTCisVT<3, i32>]>>;
 138
 139 def X86fpextRnd  : SDNode<"X86ISD::VFPEXTS_RND",
 140                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f64>,
 141                                              SDTCisSameAs<0, 1>,
 142                                              SDTCVecEltisVT<2, f32>,
 143                                              SDTCisSameSizeAs<0, 2>,
 144                                              SDTCisVT<3, i32>]>>;
 145
 146 def X86vmfpround: SDNode<"X86ISD::VMFPROUND",
 147                          SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
 148                                               SDTCVecEltisVT<1, f64>,
 149                                               SDTCisSameSizeAs<0, 1>,
 150                                               SDTCisSameAs<0, 2>,
 151                                               SDTCVecEltisVT<3, i1>,
 152                                               SDTCisSameNumEltsAs<1, 3>]>>;
 153
 154 def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 155                                         SDTCisVT<2, i8>, SDTCisInt<0>]>;
 156
 157 def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    X86vshiftimm>;
 158 def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    X86vshiftimm>;
 159 def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
 160 def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
 161 def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
 162
 163 def X86CmpMaskCC :
 164       SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 165                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 166                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
 167 def X86CmpMaskCCRound :
 168       SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
 169                        SDTCisVec<1>, SDTCisFP<1>, SDTCisSameAs<2, 1>,
 170                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
 171                        SDTCisVT<4, i32>]>;
 172 def X86CmpMaskCCScalar :
 173       SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
 174                            SDTCisVT<3, i8>]>;
 175
 176 def X86CmpMaskCCScalarRound :
 177       SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
 178                            SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
 179
 180 def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;
 181 // Hack to make CMPM commutable in tablegen patterns for load folding.
 182 def X86cmpm_c   : SDNode<"X86ISD::CMPM",     X86CmpMaskCC, [SDNPCommutative]>;
 183 def X86cmpmRnd  : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
 184 def X86cmpms    : SDNode<"X86ISD::FSETCCM",   X86CmpMaskCCScalar>;
 185 def X86cmpmsRnd : SDNode<"X86ISD::FSETCCM_RND",   X86CmpMaskCCScalarRound>;
 186
 187 def X86phminpos: SDNode<"X86ISD::PHMINPOS",
 188                  SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>;
 189
 190 def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 191                                             SDTCisVec<2>, SDTCisInt<0>,
 192                                             SDTCisInt<2>]>;
 193
 194 def X86vshl    : SDNode<"X86ISD::VSHL", X86vshiftuniform>;
 195 def X86vsrl    : SDNode<"X86ISD::VSRL", X86vshiftuniform>;
 196 def X86vsra    : SDNode<"X86ISD::VSRA", X86vshiftuniform>;
 197
 198 def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 199                                              SDTCisSameAs<0,2>, SDTCisInt<0>]>;
 200
 201 def X86vshlv   : SDNode<"X86ISD::VSHLV", X86vshiftvariable>;
 202 def X86vsrlv   : SDNode<"X86ISD::VSRLV", X86vshiftvariable>;
 203 def X86vsrav   : SDNode<"X86ISD::VSRAV", X86vshiftvariable>;
 204
 205 def X86vshli   : SDNode<"X86ISD::VSHLI", X86vshiftimm>;
 206 def X86vsrli   : SDNode<"X86ISD::VSRLI", X86vshiftimm>;
 207 def X86vsrai   : SDNode<"X86ISD::VSRAI", X86vshiftimm>;
 208
 209 def X86kshiftl : SDNode<"X86ISD::KSHIFTL",
 210                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 211                                              SDTCisSameAs<0, 1>,
 212                                              SDTCisVT<2, i8>]>>;
 213 def X86kshiftr : SDNode<"X86ISD::KSHIFTR",
 214                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 215                                              SDTCisSameAs<0, 1>,
 216                                              SDTCisVT<2, i8>]>>;
 217
 218 def X86kadd : SDNode<"X86ISD::KADD", SDTIntBinOp, [SDNPCommutative]>;
 219
 220 def X86vrotli  : SDNode<"X86ISD::VROTLI", X86vshiftimm>;
 221 def X86vrotri  : SDNode<"X86ISD::VROTRI", X86vshiftimm>;
 222
 223 def X86vpshl   : SDNode<"X86ISD::VPSHL", X86vshiftvariable>;
 224 def X86vpsha   : SDNode<"X86ISD::VPSHA", X86vshiftvariable>;
 225
 226 def X86vpcom   : SDNode<"X86ISD::VPCOM",
 227                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 228                                              SDTCisSameAs<0,2>,
 229                                              SDTCisVT<3, i8>, SDTCisInt<0>]>>;
 230 def X86vpcomu  : SDNode<"X86ISD::VPCOMU",
 231                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 232                                              SDTCisSameAs<0,2>,
 233                                              SDTCisVT<3, i8>, SDTCisInt<0>]>>;
 234 def X86vpermil2 : SDNode<"X86ISD::VPERMIL2",
 235                         SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 236                                              SDTCisSameAs<0,2>,
 237                                              SDTCisFP<0>, SDTCisInt<3>,
 238                                              SDTCisSameNumEltsAs<0, 3>,
 239                                              SDTCisSameSizeAs<0,3>,
 240                                              SDTCisVT<4, i8>]>>;
 241 def X86vpperm : SDNode<"X86ISD::VPPERM",
 242                         SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
 243                                              SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>;
 244
 245 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 246                                           SDTCisVec<1>,
 247                                           SDTCisSameAs<2, 1>]>;
 248
 249 def X86mulhrs  : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>;
 250 def X86avg     : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>;
 251 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
 252 def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
 253 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
 254 def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
 255
 256 def X86movmsk : SDNode<"X86ISD::MOVMSK",
 257                         SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>;
 258
 259 def X86selects : SDNode<"X86ISD::SELECTS",
 260                         SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>,
 261                                              SDTCisSameAs<0, 2>,
 262                                              SDTCisSameAs<2, 3>]>>;
 263
 264 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
 265                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 266                                              SDTCisSameAs<0,1>,
 267                                              SDTCisSameAs<1,2>]>,
 268                                              [SDNPCommutative]>;
 269 def X86pmuldq  : SDNode<"X86ISD::PMULDQ",
 270                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 271                                              SDTCisSameAs<0,1>,
 272                                              SDTCisSameAs<1,2>]>,
 273                                              [SDNPCommutative]>;
 274
 275 def X86extrqi : SDNode<"X86ISD::EXTRQI",
 276                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 277                                        SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
 278 def X86insertqi : SDNode<"X86ISD::INSERTQI",
 279                     SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 280                                          SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
 281                                          SDTCisVT<4, i8>]>>;
 282
 283 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
 284 // translated into one of the target nodes below during lowering.
 285 // Note: this is a work in progress...
 286 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 287 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 288                                 SDTCisSameAs<0,2>]>;
 289 def SDTShuff2OpFP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>,
 290                                          SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>;
 291
 292 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 293                                         SDTCisFP<0>, SDTCisInt<2>,
 294                                         SDTCisSameNumEltsAs<0,2>,
 295                                         SDTCisSameSizeAs<0,2>]>;
 296 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
 297                                  SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
 298 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 299                                  SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
 300 def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
 301                                         SDTCisSameAs<0,1>,
 302                                         SDTCisSameAs<0,2>,
 303                                         SDTCisVT<3, i32>]>;
 304 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisVec<0>,
 305                                              SDTCisSameAs<0,1>,
 306                                              SDTCisSameAs<0,2>,
 307                                              SDTCisVT<3, i32>,
 308                                              SDTCisVT<4, i32>]>;
 309 def SDTFPTernaryOpImmRound: SDTypeProfile<1, 5, [SDTCisFP<0>, SDTCisSameAs<0,1>,
 310                                                  SDTCisSameAs<0,2>,
 311                                                  SDTCisInt<3>,
 312                                                  SDTCisSameSizeAs<0, 3>,
 313                                                  SDTCisSameNumEltsAs<0, 3>,
 314                                                  SDTCisVT<4, i32>,
 315                                                  SDTCisVT<5, i32>]>;
 316 def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisVec<0>,
 317                                           SDTCisSameAs<0,1>,
 318                                           SDTCisVT<2, i32>]>;
 319 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
 320                                                SDTCisSameAs<0,1>,
 321                                                SDTCisVT<2, i32>,
 322                                                SDTCisVT<3, i32>]>;
 323
 324 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 325 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
 326                                           SDTCisInt<0>, SDTCisInt<1>]>;
 327
 328 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 329                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
 330
 331 def SDTTernlog  : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>,
 332                                        SDTCisSameAs<0,1>, SDTCisSameAs<0,2>,
 333                                        SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>;
 334
 335 def SDTFPBinOpRound : SDTypeProfile<1, 3, [      // fadd_round, fmul_round, etc.
 336   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>;
 337
 338 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [      // fsqrt_round, fgetexp_round, etc.
 339   SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>;
 340
 341 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 342                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>,
 343                            SDTCisFP<0>, SDTCisVT<4, i32>]>;
 344
 345 def X86PAlignr : SDNode<"X86ISD::PALIGNR",
 346                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>,
 347                                              SDTCisSameAs<0,1>,
 348                                              SDTCisSameAs<0,2>,
 349                                              SDTCisVT<3, i8>]>>;
 350 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
 351
 352 def X86VShld   : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>;
 353 def X86VShrd   : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>;
 354 def X86VShldv  : SDNode<"X86ISD::VSHLDV",
 355                         SDTypeProfile<1, 3, [SDTCisVec<0>,
 356                                              SDTCisSameAs<0,1>,
 357                                              SDTCisSameAs<0,2>,
 358                                              SDTCisSameAs<0,3>]>>;
 359 def X86VShrdv  : SDNode<"X86ISD::VSHRDV",
 360                         SDTypeProfile<1, 3, [SDTCisVec<0>,
 361                                              SDTCisSameAs<0,1>,
 362                                              SDTCisSameAs<0,2>,
 363                                              SDTCisSameAs<0,3>]>>;
 364
 365 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
 366
 367 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
 368 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
 369 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
 370
 371 def X86Shufp   : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
 372 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
 373
 374 def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
 375 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
 376 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
 377
 378 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2OpFP>;
 379 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2OpFP>;
 380
 381 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2OpFP>;
 382 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2OpFP>;
 383
 384 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>,
 385                                    SDTCisVec<1>, SDTCisInt<1>,
 386                                    SDTCisSameSizeAs<0,1>,
 387                                    SDTCisSameAs<1,2>,
 388                                    SDTCisOpSmallerThanOp<0, 1>]>;
 389 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
 390 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
 391
 392 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
 393 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
 394
 395 def X86vpmaddubsw  : SDNode<"X86ISD::VPMADDUBSW",
 396                             SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
 397                                                  SDTCVecEltisVT<1, i8>,
 398                                                  SDTCisSameSizeAs<0,1>,
 399                                                  SDTCisSameAs<1,2>]>>;
 400 def X86vpmaddwd    : SDNode<"X86ISD::VPMADDWD",
 401                             SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>,
 402                                                  SDTCVecEltisVT<1, i16>,
 403                                                  SDTCisSameSizeAs<0,1>,
 404                                                  SDTCisSameAs<1,2>]>,
 405                             [SDNPCommutative]>;
 406
 407 def X86VPermilpv  : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
 408 def X86VPermilpi  : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
 409 def X86VPermv     : SDNode<"X86ISD::VPERMV",
 410                            SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>,
 411                                                 SDTCisSameNumEltsAs<0,1>,
 412                                                 SDTCisSameSizeAs<0,1>,
 413                                                 SDTCisSameAs<0,2>]>>;
 414 def X86VPermi     : SDNode<"X86ISD::VPERMI",    SDTShuff2OpI>;
 415 def X86VPermt2     : SDNode<"X86ISD::VPERMV3",
 416                     SDTypeProfile<1, 3, [SDTCisVec<0>,
 417                                          SDTCisSameAs<0,1>, SDTCisInt<2>,
 418                                          SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
 419                                          SDTCisSameSizeAs<0,2>,
 420                                          SDTCisSameAs<0,3>]>, []>;
 421
 422 def X86vpternlog  : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
 423
 424 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 425
 426 def X86VFixupimm   : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImmRound>;
 427 def X86VFixupimmScalar   : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImmRound>;
 428 def X86VRange      : SDNode<"X86ISD::VRANGE",        SDTFPBinOpImm>;
 429 def X86VRangeRnd   : SDNode<"X86ISD::VRANGE_RND",    SDTFPBinOpImmRound>;
 430 def X86VReduce     : SDNode<"X86ISD::VREDUCE",       SDTFPUnaryOpImm>;
 431 def X86VReduceRnd  : SDNode<"X86ISD::VREDUCE_RND",   SDTFPUnaryOpImmRound>;
 432 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE",     SDTFPUnaryOpImm>;
 433 def X86VRndScaleRnd: SDNode<"X86ISD::VRNDSCALE_RND", SDTFPUnaryOpImmRound>;
 434 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",      SDTFPUnaryOpImm>;
 435 def X86VGetMantRnd : SDNode<"X86ISD::VGETMANT_RND",  SDTFPUnaryOpImmRound>;
 436 def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS",
 437                        SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 438                                             SDTCisFP<1>,
 439                                             SDTCisSameNumEltsAs<0,1>,
 440                                             SDTCisVT<2, i32>]>, []>;
 441 def X86Vfpclasss   : SDNode<"X86ISD::VFPCLASSS",
 442                        SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>,
 443                                             SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;
 444
 445 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 446                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 447                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 448
 449 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 450 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
 451
 452 def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
 453
 454 def X86Addsub    : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
 455
 456 def X86faddRnd   : SDNode<"X86ISD::FADD_RND",  SDTFPBinOpRound>;
 457 def X86faddRnds  : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>;
 458 def X86fsubRnd   : SDNode<"X86ISD::FSUB_RND",  SDTFPBinOpRound>;
 459 def X86fsubRnds  : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>;
 460 def X86fmulRnd   : SDNode<"X86ISD::FMUL_RND",  SDTFPBinOpRound>;
 461 def X86fmulRnds  : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>;
 462 def X86fdivRnd   : SDNode<"X86ISD::FDIV_RND",  SDTFPBinOpRound>;
 463 def X86fdivRnds  : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>;
 464 def X86fmaxRnd   : SDNode<"X86ISD::FMAX_RND",  SDTFPBinOpRound>;
 465 def X86fmaxRnds  : SDNode<"X86ISD::FMAXS_RND", SDTFPBinOpRound>;
 466 def X86fminRnd   : SDNode<"X86ISD::FMIN_RND",  SDTFPBinOpRound>;
 467 def X86fminRnds  : SDNode<"X86ISD::FMINS_RND", SDTFPBinOpRound>;
 468 def X86scalef    : SDNode<"X86ISD::SCALEF",         SDTFPBinOpRound>;
 469 def X86scalefs   : SDNode<"X86ISD::SCALEFS",        SDTFPBinOpRound>;
 470 def X86fsqrtRnd     : SDNode<"X86ISD::FSQRT_RND",   SDTFPUnaryOpRound>;
 471 def X86fsqrtRnds    : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>;
 472 def X86fgetexpRnd   : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
 473 def X86fgetexpRnds  : SDNode<"X86ISD::FGETEXPS_RND", SDTFPBinOpRound>;
 474
 475 def X86Fmadd     : SDNode<"ISD::FMA",          SDTFPTernaryOp, [SDNPCommutative]>;
 476 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFPTernaryOp, [SDNPCommutative]>;
 477 def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFPTernaryOp, [SDNPCommutative]>;
 478 def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFPTernaryOp, [SDNPCommutative]>;
 479 def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFPTernaryOp, [SDNPCommutative]>;
 480 def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFPTernaryOp, [SDNPCommutative]>;
 481
 482 def X86FmaddRnd     : SDNode<"X86ISD::FMADD_RND",     SDTFmaRound, [SDNPCommutative]>;
 483 def X86FnmaddRnd    : SDNode<"X86ISD::FNMADD_RND",    SDTFmaRound, [SDNPCommutative]>;
 484 def X86FmsubRnd     : SDNode<"X86ISD::FMSUB_RND",     SDTFmaRound, [SDNPCommutative]>;
 485 def X86FnmsubRnd    : SDNode<"X86ISD::FNMSUB_RND",    SDTFmaRound, [SDNPCommutative]>;
 486 def X86FmaddsubRnd  : SDNode<"X86ISD::FMADDSUB_RND",  SDTFmaRound, [SDNPCommutative]>;
 487 def X86FmsubaddRnd  : SDNode<"X86ISD::FMSUBADD_RND",  SDTFmaRound, [SDNPCommutative]>;
 488
 489 def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>,
 490                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 491 def x86vpmadd52l     : SDNode<"X86ISD::VPMADD52L",     SDTIFma, [SDNPCommutative]>;
 492 def x86vpmadd52h     : SDNode<"X86ISD::VPMADD52H",     SDTIFma, [SDNPCommutative]>;
 493
 494 def X86rsqrt14   : SDNode<"X86ISD::RSQRT14",  SDTFPUnaryOp>;
 495 def X86rcp14     : SDNode<"X86ISD::RCP14",    SDTFPUnaryOp>;
 496
 497 // VNNI
 498 def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 499                                    SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 500 def X86Vpdpbusd  : SDNode<"X86ISD::VPDPBUSD", SDTVnni>;
 501 def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>;
 502 def X86Vpdpwssd  : SDNode<"X86ISD::VPDPWSSD", SDTVnni>;
 503 def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>;
 504
 505 def X86rsqrt28   : SDNode<"X86ISD::RSQRT28",  SDTFPUnaryOpRound>;
 506 def X86rcp28     : SDNode<"X86ISD::RCP28",    SDTFPUnaryOpRound>;
 507 def X86exp2      : SDNode<"X86ISD::EXP2",     SDTFPUnaryOpRound>;
 508
 509 def X86rsqrt14s  : SDNode<"X86ISD::RSQRT14S",   SDTFPBinOp>;
 510 def X86rcp14s    : SDNode<"X86ISD::RCP14S",     SDTFPBinOp>;
 511 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28S",   SDTFPBinOpRound>;
 512 def X86rcp28s    : SDNode<"X86ISD::RCP28S",     SDTFPBinOpRound>;
 513 def X86Ranges    : SDNode<"X86ISD::VRANGES",    SDTFPBinOpImm>;
 514 def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>;
 515 def X86Reduces   : SDNode<"X86ISD::VREDUCES",   SDTFPBinOpImm>;
 516 def X86GetMants  : SDNode<"X86ISD::VGETMANTS",  SDTFPBinOpImm>;
 517 def X86RangesRnd    : SDNode<"X86ISD::VRANGES_RND",    SDTFPBinOpImmRound>;
 518 def X86RndScalesRnd : SDNode<"X86ISD::VRNDSCALES_RND", SDTFPBinOpImmRound>;
 519 def X86ReducesRnd   : SDNode<"X86ISD::VREDUCES_RND",   SDTFPBinOpImmRound>;
 520 def X86GetMantsRnd  : SDNode<"X86ISD::VGETMANTS_RND",  SDTFPBinOpImmRound>;
 521
 522 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
 523                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 524 def X86expand  : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
 525                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 526
 527 // vpshufbitqmb
 528 def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB",
 529                              SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 530                                                   SDTCisSameAs<1,2>,
 531                                                   SDTCVecEltisVT<0,i1>,
 532                                                   SDTCisSameNumEltsAs<0,1>]>>;
 533
 534 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 535                                           SDTCisSameAs<0,1>, SDTCisInt<2>,
 536                                           SDTCisVT<3, i32>]>;
 537
 538 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 539                                         SDTCisInt<0>, SDTCisFP<1>]>;
 540 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 541                                            SDTCisInt<0>, SDTCisFP<1>,
 542                                            SDTCisVT<2, i32>]>;
 543 def SDTSFloatToInt: SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisFP<1>,
 544                                          SDTCisVec<1>]>;
 545 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
 546                                             SDTCisVec<1>, SDTCisVT<2, i32>]>;
 547
 548 def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 549                                       SDTCisFP<0>, SDTCisInt<1>]>;
 550 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 551                                            SDTCisFP<0>, SDTCisInt<1>,
 552                                            SDTCisVT<2, i32>]>;
 553
 554 // Scalar
 555 def X86SintToFpRnd  : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND",  SDTintToFPRound>;
 556 def X86UintToFpRnd  : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND",  SDTintToFPRound>;
 557
 558 def X86cvtts2Int  : SDNode<"X86ISD::CVTTS2SI",  SDTSFloatToInt>;
 559 def X86cvtts2UInt : SDNode<"X86ISD::CVTTS2UI",  SDTSFloatToInt>;
 560 def X86cvtts2IntRnd  : SDNode<"X86ISD::CVTTS2SI_RND",  SDTSFloatToIntRnd>;
 561 def X86cvtts2UIntRnd : SDNode<"X86ISD::CVTTS2UI_RND",  SDTSFloatToIntRnd>;
 562
 563 def X86cvts2si  : SDNode<"X86ISD::CVTS2SI", SDTSFloatToInt>;
 564 def X86cvts2usi : SDNode<"X86ISD::CVTS2UI", SDTSFloatToInt>;
 565 def X86cvts2siRnd  : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>;
 566 def X86cvts2usiRnd : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>;
 567
 568 // Vector with rounding mode
 569
 570 // cvtt fp-to-int staff
 571 def X86cvttp2siRnd    : SDNode<"X86ISD::CVTTP2SI_RND", SDTFloatToIntRnd>;
 572 def X86cvttp2uiRnd    : SDNode<"X86ISD::CVTTP2UI_RND", SDTFloatToIntRnd>;
 573
 574 def X86VSintToFpRnd   : SDNode<"X86ISD::SINT_TO_FP_RND",  SDTVintToFPRound>;
 575 def X86VUintToFpRnd   : SDNode<"X86ISD::UINT_TO_FP_RND",  SDTVintToFPRound>;
 576
 577 // cvt fp-to-int staff
 578 def X86cvtp2IntRnd      : SDNode<"X86ISD::CVTP2SI_RND",  SDTFloatToIntRnd>;
 579 def X86cvtp2UIntRnd     : SDNode<"X86ISD::CVTP2UI_RND",  SDTFloatToIntRnd>;
 580
 581 // Vector without rounding mode
 582
 583 // cvtt fp-to-int staff
 584 def X86cvttp2si      : SDNode<"X86ISD::CVTTP2SI",  SDTFloatToInt>;
 585 def X86cvttp2ui      : SDNode<"X86ISD::CVTTP2UI",  SDTFloatToInt>;
 586
 587 def X86VSintToFP      : SDNode<"X86ISD::CVTSI2P",  SDTVintToFP>;
 588 def X86VUintToFP      : SDNode<"X86ISD::CVTUI2P",  SDTVintToFP>;
 589
 590 // cvt int-to-fp staff
 591 def X86cvtp2Int      : SDNode<"X86ISD::CVTP2SI",  SDTFloatToInt>;
 592 def X86cvtp2UInt     : SDNode<"X86ISD::CVTP2UI",  SDTFloatToInt>;
 593
 594
 595 def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 596                                          SDTCisInt<0>, SDTCisFP<1>,
 597                                          SDTCisSameSizeAs<0, 1>,
 598                                          SDTCisSameAs<0, 2>,
 599                                          SDTCVecEltisVT<3, i1>,
 600                                          SDTCisSameNumEltsAs<1, 3>]>;
 601
 602 def X86mcvtp2Int     : SDNode<"X86ISD::MCVTP2SI",  SDTMFloatToInt>;
 603 def X86mcvtp2UInt    : SDNode<"X86ISD::MCVTP2UI",  SDTMFloatToInt>;
 604 def X86mcvttp2si     : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>;
 605 def X86mcvttp2ui     : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>;
 606
 607
 608 def X86cvtph2ps     : SDNode<"X86ISD::CVTPH2PS",
 609                               SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
 610                                                    SDTCVecEltisVT<1, i16>]> >;
 611
 612 def X86cvtph2psRnd  : SDNode<"X86ISD::CVTPH2PS_RND",
 613                               SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
 614                                                    SDTCVecEltisVT<1, i16>,
 615                                                    SDTCisVT<2, i32>]> >;
 616
 617 def X86cvtps2ph   : SDNode<"X86ISD::CVTPS2PH",
 618                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
 619                                              SDTCVecEltisVT<1, f32>,
 620                                              SDTCisVT<2, i32>]> >;
 621 def X86mcvtps2ph   : SDNode<"X86ISD::MCVTPS2PH",
 622                         SDTypeProfile<1, 4, [SDTCVecEltisVT<0, i16>,
 623                                              SDTCVecEltisVT<1, f32>,
 624                                              SDTCisVT<2, i32>,
 625                                              SDTCisSameAs<0, 3>,
 626                                              SDTCVecEltisVT<4, i1>,
 627                                              SDTCisSameNumEltsAs<1, 4>]> >;
 628 def X86vfpextRnd  : SDNode<"X86ISD::VFPEXT_RND",
 629                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>,
 630                                              SDTCVecEltisVT<1, f32>,
 631                                              SDTCisOpSmallerThanOp<1, 0>,
 632                                              SDTCisVT<2, i32>]>>;
 633 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND",
 634                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
 635                                              SDTCVecEltisVT<1, f64>,
 636                                              SDTCisOpSmallerThanOp<0, 1>,
 637                                              SDTCisVT<2, i32>]>>;
 638
 639 // galois field arithmetic
 640 def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>;
 641 def X86GF2P8affineqb    : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>;
 642 def X86GF2P8mulb        : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>;
 643
 644 //===----------------------------------------------------------------------===//
 645 // SSE Complex Patterns
 646 //===----------------------------------------------------------------------===//
 647
 648 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 649 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 650 // forms.
 651 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
 652                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 653                                    SDNPWantRoot, SDNPWantParent]>;
 654 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
 655                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 656                                    SDNPWantRoot, SDNPWantParent]>;
 657
 658 def ssmem : Operand<v4f32> {
 659   let PrintMethod = "printf32mem";
 660   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
 661   let ParserMatchClass = X86Mem32AsmOperand;
 662   let OperandType = "OPERAND_MEMORY";
 663 }
 664 def sdmem : Operand<v2f64> {
 665   let PrintMethod = "printf64mem";
 666   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
 667   let ParserMatchClass = X86Mem64AsmOperand;
 668   let OperandType = "OPERAND_MEMORY";
 669 }
 670
 671 //===----------------------------------------------------------------------===//
 672 // SSE pattern fragments
 673 //===----------------------------------------------------------------------===//
 674
 675 // 128-bit load pattern fragments
 676 def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
 677 def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
 678 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 679 def loadv4i32    : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
 680 def loadv8i16    : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
 681 def loadv16i8    : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
 682
 683 // 256-bit load pattern fragments
 684 def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32  (load node:$ptr))>;
 685 def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64  (load node:$ptr))>;
 686 def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64  (load node:$ptr))>;
 687 def loadv8i32    : PatFrag<(ops node:$ptr), (v8i32  (load node:$ptr))>;
 688 def loadv16i16   : PatFrag<(ops node:$ptr), (v16i16 (load node:$ptr))>;
 689 def loadv32i8    : PatFrag<(ops node:$ptr), (v32i8  (load node:$ptr))>;
 690
 691 // 512-bit load pattern fragments
 692 def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
 693 def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64  (load node:$ptr))>;
 694 def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64  (load node:$ptr))>;
 695 def loadv16i32   : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
 696 def loadv32i16   : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
 697 def loadv64i8    : PatFrag<(ops node:$ptr), (v64i8  (load node:$ptr))>;
 698
 699 // 128-/256-/512-bit extload pattern fragments
 700 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
 701 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
 702 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
 703
 704 // Like 'store', but always requires vector size alignment.
 705 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
 706                            (store node:$val, node:$ptr), [{
 707   auto *St = cast<StoreSDNode>(N);
 708   return St->getAlignment() >= St->getMemoryVT().getStoreSize();
 709 }]>;
 710
 711 // Like 'load', but always requires vector size alignment.
 712 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 713   auto *Ld = cast<LoadSDNode>(N);
 714   return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
 715 }]>;
 716
 717 // 128-bit aligned load pattern fragments
 718 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 719 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
 720                                (v4f32 (alignedload node:$ptr))>;
 721 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
 722                                (v2f64 (alignedload node:$ptr))>;
 723 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
 724                                (v2i64 (alignedload node:$ptr))>;
 725 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
 726                                (v4i32 (alignedload node:$ptr))>;
 727 def alignedloadv8i16 : PatFrag<(ops node:$ptr),
 728                                (v8i16 (alignedload node:$ptr))>;
 729 def alignedloadv16i8 : PatFrag<(ops node:$ptr),
 730                                (v16i8 (alignedload node:$ptr))>;
 731
 732 // 256-bit aligned load pattern fragments
 733 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 734 def alignedloadv8f32  : PatFrag<(ops node:$ptr),
 735                                 (v8f32  (alignedload node:$ptr))>;
 736 def alignedloadv4f64  : PatFrag<(ops node:$ptr),
 737                                 (v4f64  (alignedload node:$ptr))>;
 738 def alignedloadv4i64  : PatFrag<(ops node:$ptr),
 739                                 (v4i64  (alignedload node:$ptr))>;
 740 def alignedloadv8i32  : PatFrag<(ops node:$ptr),
 741                                 (v8i32  (alignedload node:$ptr))>;
 742 def alignedloadv16i16 : PatFrag<(ops node:$ptr),
 743                                 (v16i16 (alignedload node:$ptr))>;
 744 def alignedloadv32i8  : PatFrag<(ops node:$ptr),
 745                                 (v32i8  (alignedload node:$ptr))>;
 746
 747 // 512-bit aligned load pattern fragments
 748 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
 749                                 (v16f32 (alignedload node:$ptr))>;
 750 def alignedloadv8f64  : PatFrag<(ops node:$ptr),
 751                                 (v8f64  (alignedload node:$ptr))>;
 752 def alignedloadv8i64  : PatFrag<(ops node:$ptr),
 753                                 (v8i64  (alignedload node:$ptr))>;
 754 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
 755                                 (v16i32 (alignedload node:$ptr))>;
 756 def alignedloadv32i16 : PatFrag<(ops node:$ptr),
 757                                 (v32i16 (alignedload node:$ptr))>;
 758 def alignedloadv64i8  : PatFrag<(ops node:$ptr),
 759                                 (v64i8  (alignedload node:$ptr))>;
 760
 761 // Like 'load', but uses special alignment checks suitable for use in
 762 // memory operands in most SSE instructions, which are required to
 763 // be naturally aligned on some targets but not on others.  If the subtarget
 764 // allows unaligned accesses, match any load, though this may require
 765 // setting a feature bit in the processor (on startup, for example).
 766 // Opteron 10h and later implement such a feature.
 767 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 768   auto *Ld = cast<LoadSDNode>(N);
 769   return Subtarget->hasSSEUnalignedMem() ||
 770          Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
 771 }]>;
 772
 773 // 128-bit memop pattern fragments
 774 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 775 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 776 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 777 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 778 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
 779 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
 780 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
 781
 782 def X86masked_gather : SDNode<"X86ISD::MGATHER",
 783                               SDTypeProfile<2, 3, [SDTCisVec<0>,
 784                                                    SDTCisVec<1>, SDTCisInt<1>,
 785                                                    SDTCisSameAs<0, 2>,
 786                                                    SDTCisSameAs<1, 3>,
 787                                                    SDTCisPtrTy<4>]>,
 788                              [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 789
 790 def X86masked_scatter : SDNode<"X86ISD::MSCATTER",
 791                               SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 792                                                    SDTCisSameAs<0, 2>,
 793                                                    SDTCVecEltisVT<0, i1>,
 794                                                    SDTCisPtrTy<3>]>,
 795                              [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 796
 797 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 798   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 799   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 800   return Mgt->getIndex().getValueType() == MVT::v4i32;
 801 }]>;
 802
 803 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 804   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 805   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 806   return Mgt->getIndex().getValueType() == MVT::v8i32;
 807 }]>;
 808
 809 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 810   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 811   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 812   return Mgt->getIndex().getValueType() == MVT::v2i64;
 813 }]>;
 814 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 815   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 816   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 817   return Mgt->getIndex().getValueType() == MVT::v4i64;
 818 }]>;
 819 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 820   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 821   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 822   return Mgt->getIndex().getValueType() == MVT::v8i64;
 823 }]>;
 824 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 825   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 826   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 827   return Mgt->getIndex().getValueType() == MVT::v16i32;
 828 }]>;
 829
 830 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 831   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 832   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 833   return Sc->getIndex().getValueType() == MVT::v2i64;
 834 }]>;
 835
 836 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 837   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 838   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 839   return Sc->getIndex().getValueType() == MVT::v4i32;
 840 }]>;
 841
 842 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 843   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 844   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 845   return Sc->getIndex().getValueType() == MVT::v4i64;
 846 }]>;
 847
 848 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 849   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 850   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 851   return Sc->getIndex().getValueType() == MVT::v8i32;
 852 }]>;
 853
 854 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 855   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 856   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 857   return Sc->getIndex().getValueType() == MVT::v8i64;
 858 }]>;
 859 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 860   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 861   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 862   return Sc->getIndex().getValueType() == MVT::v16i32;
 863 }]>;
 864
 865 // 128-bit bitconvert pattern fragments
 866 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
 867 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 868 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 869 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 870 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 871 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 872
 873 // 256-bit bitconvert pattern fragments
 874 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
 875 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
 876 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
 877 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
 878 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
 879 def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>;
 880
 881 // 512-bit bitconvert pattern fragments
 882 def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>;
 883 def bc_v32i16 : PatFrag<(ops node:$in), (v32i16 (bitconvert node:$in))>;
 884 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
 885 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
 886 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
 887 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
 888
 889 def vzmovl_v2i64 : PatFrag<(ops node:$src),
 890                            (bitconvert (v2i64 (X86vzmovl
 891                              (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
 892 def vzmovl_v4i32 : PatFrag<(ops node:$src),
 893                            (bitconvert (v4i32 (X86vzmovl
 894                              (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
 895
 896 def vzload_v2i64 : PatFrag<(ops node:$src),
 897                            (bitconvert (v2i64 (X86vzload node:$src)))>;
 898
 899
 900 def fp32imm0 : PatLeaf<(f32 fpimm), [{
 901   return N->isExactlyValue(+0.0);
 902 }]>;
 903
 904 def fp64imm0 : PatLeaf<(f64 fpimm), [{
 905   return N->isExactlyValue(+0.0);
 906 }]>;
 907
 908 def I8Imm : SDNodeXForm<imm, [{
 909   // Transformation function: get the low 8 bits.
 910   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 911 }]>;
 912
 913 def FROUND_NO_EXC : PatLeaf<(i32 8)>;
 914 def FROUND_CURRENT : PatLeaf<(i32 4)>;
 915
 916 // BYTE_imm - Transform bit immediates into byte immediates.
 917 def BYTE_imm  : SDNodeXForm<imm, [{
 918   // Transformation function: imm >> 3
 919   return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
 920 }]>;
 921
 922 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
 923 // to VEXTRACTF128/VEXTRACTI128 imm.
 924 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
 925   return getExtractVEXTRACTImmediate(N, 128, SDLoc(N));
 926 }]>;
 927
 928 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
 929 // VINSERTF128/VINSERTI128 imm.
 930 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
 931   return getInsertVINSERTImmediate(N, 128, SDLoc(N));
 932 }]>;
 933
 934 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
 935 // to VEXTRACTF64x4 imm.
 936 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
 937   return getExtractVEXTRACTImmediate(N, 256, SDLoc(N));
 938 }]>;
 939
 940 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
 941 // VINSERTF64x4 imm.
 942 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
 943   return getInsertVINSERTImmediate(N, 256, SDLoc(N));
 944 }]>;
 945
 946 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
 947                                    (extract_subvector node:$bigvec,
 948                                                       node:$index), [{}],
 949                                   EXTRACT_get_vextract128_imm>;
 950
 951 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 952                                       node:$index),
 953                                  (insert_subvector node:$bigvec, node:$smallvec,
 954                                                    node:$index), [{}],
 955                                 INSERT_get_vinsert128_imm>;
 956
 957 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
 958                                    (extract_subvector node:$bigvec,
 959                                                       node:$index), [{}],
 960                                   EXTRACT_get_vextract256_imm>;
 961
 962 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 963                                       node:$index),
 964                                  (insert_subvector node:$bigvec, node:$smallvec,
 965                                                    node:$index), [{}],
 966                                 INSERT_get_vinsert256_imm>;
 967
 968 def X86mload : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 969                          (masked_load node:$src1, node:$src2, node:$src3), [{
 970   return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
 971     cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
 972 }]>;
 973
 974 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 975                          (X86mload node:$src1, node:$src2, node:$src3), [{
 976   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 16;
 977 }]>;
 978
 979 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 980                          (X86mload node:$src1, node:$src2, node:$src3), [{
 981   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 32;
 982 }]>;
 983
 984 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 985                          (X86mload node:$src1, node:$src2, node:$src3), [{
 986   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 64;
 987 }]>;
 988
 989 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 990                          (masked_load node:$src1, node:$src2, node:$src3), [{
 991   return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
 992     cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
 993 }]>;
 994
 995 def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 996                          (masked_load node:$src1, node:$src2, node:$src3), [{
 997   return cast<MaskedLoadSDNode>(N)->isExpandingLoad();
 998 }]>;
 999
1000 // Masked store fragments.
1001 // X86mstore can't be implemented in core DAG files because some targets
1002 // do not support vector types (llvm-tblgen will fail).
1003 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1004                         (masked_store node:$src1, node:$src2, node:$src3), [{
1005   return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) &&
1006          (!cast<MaskedStoreSDNode>(N)->isCompressingStore());
1007 }]>;
1008
1009 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1010                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1011   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 16;
1012 }]>;
1013
1014 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1015                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1016   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 32;
1017 }]>;
1018
1019 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1020                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1021   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 64;
1022 }]>;
1023
1024 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1025                          (masked_store node:$src1, node:$src2, node:$src3), [{
1026   return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) &&
1027          (!cast<MaskedStoreSDNode>(N)->isCompressingStore());
1028 }]>;
1029
1030 def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1031                              (masked_store node:$src1, node:$src2, node:$src3), [{
1032     return cast<MaskedStoreSDNode>(N)->isCompressingStore();
1033 }]>;
1034
1035 // masked truncstore fragments
1036 // X86mtruncstore can't be implemented in core DAG files because some targets
1037 // doesn't support vector type ( llvm-tblgen will fail)
1038 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1039                              (masked_store node:$src1, node:$src2, node:$src3), [{
1040     return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
1041 }]>;
1042 def masked_truncstorevi8 :
1043   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1044           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1045   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1046 }]>;
1047 def masked_truncstorevi16 :
1048   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1049           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1050   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1051 }]>;
1052 def masked_truncstorevi32 :
1053   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1054           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1055   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1056 }]>;
1057
1058 def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES",  SDTStore,
1059                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1060
1061 def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS",  SDTStore,
1062                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1063
1064 def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES",  SDTMaskedStore,
1065                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1066
1067 def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS",  SDTMaskedStore,
1068                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1069
1070 def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr),
1071                                (X86TruncSStore node:$val, node:$ptr), [{
1072   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1073 }]>;
1074
1075 def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr),
1076                                (X86TruncUSStore node:$val, node:$ptr), [{
1077   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1078 }]>;
1079
1080 def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr),
1081                                (X86TruncSStore node:$val, node:$ptr), [{
1082   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1083 }]>;
1084
1085 def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr),
1086                                (X86TruncUSStore node:$val, node:$ptr), [{
1087   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1088 }]>;
1089
1090 def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr),
1091                                (X86TruncSStore node:$val, node:$ptr), [{
1092   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1093 }]>;
1094
1095 def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr),
1096                                (X86TruncUSStore node:$val, node:$ptr), [{
1097   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1098 }]>;
1099
1100 def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1101                      (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1102   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1103 }]>;
1104
1105 def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1106                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1107   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1108 }]>;
1109
1110 def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1111                                (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1112   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1113 }]>;
1114
1115 def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1116                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1117   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1118 }]>;
1119
1120 def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1121                                (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1122   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1123 }]>;
1124
1125 def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1126                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1127   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1128 }]>;