contrib/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

   1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides pattern fragments useful for SIMD instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // MMX specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // Low word of MMX to GPR.
  19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
  20                             [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
  21 // GPR to low word of MMX.
  22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
  23                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
  24
  25 //===----------------------------------------------------------------------===//
  26 // MMX Pattern Fragments
  27 //===----------------------------------------------------------------------===//
  28
  29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
  30
  31 //===----------------------------------------------------------------------===//
  32 // SSE specific DAG Nodes.
  33 //===----------------------------------------------------------------------===//
  34
  35 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
  36                                        SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  37                                        SDTCisVT<3, i8>]>;
  38
  39 def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
  40 def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
  41 def X86fmins   : SDNode<"X86ISD::FMINS",     SDTFPBinOp>;
  42 def X86fmaxs   : SDNode<"X86ISD::FMAXS",     SDTFPBinOp>;
  43
  44 // Commutative and Associative FMIN and FMAX.
  45 def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
  46     [SDNPCommutative, SDNPAssociative]>;
  47 def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
  48     [SDNPCommutative, SDNPAssociative]>;
  49
  50 def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
  51                         [SDNPCommutative, SDNPAssociative]>;
  52 def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
  53                         [SDNPCommutative, SDNPAssociative]>;
  54 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
  55                         [SDNPCommutative, SDNPAssociative]>;
  56 def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp>;
  57 def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
  58 def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
  59 def X86frsqrt14s: SDNode<"X86ISD::FRSQRTS",  SDTFPBinOp>;
  60 def X86frcp14s : SDNode<"X86ISD::FRCPS",    SDTFPBinOp>;
  61 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
  62 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
  63 def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
  64 def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
  65 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
  66 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
  67 def X86cmps    : SDNode<"X86ISD::FSETCC",     SDTX86Cmps>;
  68 def X86pshufb  : SDNode<"X86ISD::PSHUFB",
  69                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
  70                                       SDTCisSameAs<0,2>]>>;
  71 def X86psadbw  : SDNode<"X86ISD::PSADBW",
  72                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
  73                                       SDTCVecEltisVT<1, i8>,
  74                                       SDTCisSameSizeAs<0,1>,
  75                                       SDTCisSameAs<1,2>]>, [SDNPCommutative]>;
  76 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
  77                   SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
  78                                        SDTCVecEltisVT<1, i8>,
  79                                        SDTCisSameSizeAs<0,1>,
  80                                        SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
  81 def X86andnp   : SDNode<"X86ISD::ANDNP",
  82                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  83                                       SDTCisSameAs<0,2>]>>;
  84 def X86multishift   : SDNode<"X86ISD::MULTISHIFT",
  85                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
  86                                       SDTCisSameAs<1,2>]>>;
  87 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
  88                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
  89                                       SDTCisPtrTy<2>]>>;
  90 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
  91                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
  92                                       SDTCisPtrTy<2>]>>;
  93 def X86pinsrb  : SDNode<"X86ISD::PINSRB",
  94                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
  95                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
  96 def X86pinsrw  : SDNode<"X86ISD::PINSRW",
  97                  SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
  98                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
  99 def X86insertps : SDNode<"X86ISD::INSERTPS",
 100                  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
 101                                       SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
 102 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
 103                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 104
 105 def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
 106                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 107
 108 def X86vzext   : SDNode<"X86ISD::VZEXT",
 109                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 110                                               SDTCisInt<0>, SDTCisInt<1>,
 111                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 112
 113 def X86vsext   : SDNode<"X86ISD::VSEXT",
 114                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 115                                               SDTCisInt<0>, SDTCisInt<1>,
 116                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 117
 118 def SDTVtrunc    : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 119                                        SDTCisInt<0>, SDTCisInt<1>,
 120                                        SDTCisOpSmallerThanOp<0, 1>]>;
 121
 122 def X86vtrunc    : SDNode<"X86ISD::VTRUNC",   SDTVtrunc>;
 123 def X86vtruncs   : SDNode<"X86ISD::VTRUNCS",  SDTVtrunc>;
 124 def X86vtruncus  : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
 125
 126 def X86vfpext  : SDNode<"X86ISD::VFPEXT",
 127                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>,
 128                                              SDTCVecEltisVT<1, f32>,
 129                                              SDTCisSameSizeAs<0, 1>]>>;
 130 def X86vfpround: SDNode<"X86ISD::VFPROUND",
 131                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
 132                                              SDTCVecEltisVT<1, f64>,
 133                                              SDTCisSameSizeAs<0, 1>]>>;
 134
 135 def X86froundRnd: SDNode<"X86ISD::VFPROUNDS_RND",
 136                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
 137                                              SDTCisSameAs<0, 1>,
 138                                              SDTCVecEltisVT<2, f64>,
 139                                              SDTCisSameSizeAs<0, 2>,
 140                                              SDTCisVT<3, i32>]>>;
 141
 142 def X86fpextRnd  : SDNode<"X86ISD::VFPEXTS_RND",
 143                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f64>,
 144                                              SDTCisSameAs<0, 1>,
 145                                              SDTCVecEltisVT<2, f32>,
 146                                              SDTCisSameSizeAs<0, 2>,
 147                                              SDTCisVT<3, i32>]>>;
 148
 149 def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    SDTIntShiftOp>;
 150 def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    SDTIntShiftOp>;
 151 def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
 152 def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
 153 def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
 154
 155 def X86IntCmpMask : SDTypeProfile<1, 2,
 156     [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, SDTCisSameAs<1, 2>, SDTCisInt<1>,
 157      SDTCisSameNumEltsAs<0, 1>]>;
 158 def X86pcmpeqm  : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
 159 def X86pcmpgtm  : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
 160
 161 def X86CmpMaskCC :
 162       SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 163                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 164                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
 165 def X86CmpMaskCCRound :
 166       SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
 167                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 168                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
 169                        SDTCisVT<4, i32>]>;
 170 def X86CmpMaskCCScalar :
 171       SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
 172
 173 def X86CmpMaskCCScalarRound :
 174       SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
 175                            SDTCisVT<4, i32>]>;
 176
 177 def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;
 178 def X86cmpmRnd  : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
 179 def X86cmpmu    : SDNode<"X86ISD::CMPMU",    X86CmpMaskCC>;
 180 def X86cmpms    : SDNode<"X86ISD::FSETCCM",   X86CmpMaskCCScalar>;
 181 def X86cmpmsRnd : SDNode<"X86ISD::FSETCCM_RND",   X86CmpMaskCCScalarRound>;
 182
 183 def X86vshl    : SDNode<"X86ISD::VSHL",
 184                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 185                                       SDTCisVec<2>]>>;
 186 def X86vsrl    : SDNode<"X86ISD::VSRL",
 187                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 188                                       SDTCisVec<2>]>>;
 189 def X86vsra    : SDNode<"X86ISD::VSRA",
 190                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 191                                       SDTCisVec<2>]>>;
 192
 193 def X86vsrav   : SDNode<"X86ISD::VSRAV" ,
 194                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 195                                              SDTCisSameAs<0,2>]>>;
 196
 197 def X86vshli   : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
 198 def X86vsrli   : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
 199 def X86vsrai   : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
 200
 201 def X86kshiftl : SDNode<"X86ISD::KSHIFTL",
 202                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 203                                              SDTCisSameAs<0, 1>,
 204                                              SDTCisVT<2, i8>]>>;
 205 def X86kshiftr : SDNode<"X86ISD::KSHIFTR",
 206                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 207                                              SDTCisSameAs<0, 1>,
 208                                              SDTCisVT<2, i8>]>>;
 209
 210 def X86vrotli  : SDNode<"X86ISD::VROTLI", SDTIntShiftOp>;
 211 def X86vrotri  : SDNode<"X86ISD::VROTRI", SDTIntShiftOp>;
 212
 213 def X86vprot   : SDNode<"X86ISD::VPROT",
 214                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 215                                              SDTCisSameAs<0,2>]>>;
 216 def X86vproti  : SDNode<"X86ISD::VPROTI",
 217                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 218                                              SDTCisVT<2, i8>]>>;
 219
 220 def X86vpshl   : SDNode<"X86ISD::VPSHL",
 221                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 222                                              SDTCisSameAs<0,2>]>>;
 223 def X86vpsha   : SDNode<"X86ISD::VPSHA",
 224                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 225                                              SDTCisSameAs<0,2>]>>;
 226
 227 def X86vpcom   : SDNode<"X86ISD::VPCOM",
 228                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 229                                              SDTCisSameAs<0,2>,
 230                                              SDTCisVT<3, i8>]>>;
 231 def X86vpcomu  : SDNode<"X86ISD::VPCOMU",
 232                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 233                                              SDTCisSameAs<0,2>,
 234                                              SDTCisVT<3, i8>]>>;
 235 def X86vpermil2 : SDNode<"X86ISD::VPERMIL2",
 236                         SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 237                                              SDTCisSameAs<0,2>,
 238                                              SDTCisSameSizeAs<0,3>,
 239                                              SDTCisSameNumEltsAs<0, 3>,
 240                                              SDTCisFP<0>, SDTCisInt<3>,
 241                                              SDTCisVT<4, i8>]>>;
 242 def X86vpperm : SDNode<"X86ISD::VPPERM",
 243                         SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
 244                                              SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>;
 245
 246 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 247                                           SDTCisVec<1>,
 248                                           SDTCisSameAs<2, 1>]>;
 249
 250 def SDTX86Testm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 251                                        SDTCisSameAs<2, 1>, SDTCVecEltisVT<0, i1>,
 252                                        SDTCisSameNumEltsAs<0, 1>]>;
 253
 254 def X86addus   : SDNode<"X86ISD::ADDUS", SDTIntBinOp, [SDNPCommutative]>;
 255 def X86subus   : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
 256 def X86adds    : SDNode<"X86ISD::ADDS", SDTIntBinOp, [SDNPCommutative]>;
 257 def X86subs    : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
 258 def X86mulhrs  : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>;
 259 def X86avg     : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>;
 260 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
 261 def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
 262 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
 263 def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
 264 def X86testm   : SDNode<"X86ISD::TESTM", SDTX86Testm, [SDNPCommutative]>;
 265 def X86testnm  : SDNode<"X86ISD::TESTNM", SDTX86Testm, [SDNPCommutative]>;
 266
 267 def X86movmsk : SDNode<"X86ISD::MOVMSK",
 268                         SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>;
 269
 270 def X86select  : SDNode<"X86ISD::SELECT",
 271                         SDTypeProfile<1, 3, [SDTCVecEltisVT<1, i1>,
 272                                              SDTCisSameAs<0, 2>,
 273                                              SDTCisSameAs<2, 3>,
 274                                              SDTCisSameNumEltsAs<0, 1>]>>;
 275
 276 def X86selects : SDNode<"X86ISD::SELECTS",
 277                         SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>,
 278                                              SDTCisSameAs<0, 2>,
 279                                              SDTCisSameAs<2, 3>]>>;
 280
 281 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
 282                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 283                                              SDTCVecEltisVT<1, i32>,
 284                                              SDTCisSameSizeAs<0,1>,
 285                                              SDTCisSameAs<1,2>]>,
 286                                              [SDNPCommutative]>;
 287 def X86pmuldq  : SDNode<"X86ISD::PMULDQ",
 288                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 289                                              SDTCVecEltisVT<1, i32>,
 290                                              SDTCisSameSizeAs<0,1>,
 291                                              SDTCisSameAs<1,2>]>,
 292                                              [SDNPCommutative]>;
 293
 294 def X86extrqi : SDNode<"X86ISD::EXTRQI",
 295                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 296                                        SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
 297 def X86insertqi : SDNode<"X86ISD::INSERTQI",
 298                     SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 299                                          SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
 300                                          SDTCisVT<4, i8>]>>;
 301
 302 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
 303 // translated into one of the target nodes below during lowering.
 304 // Note: this is a work in progress...
 305 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 306 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 307                                 SDTCisSameAs<0,2>]>;
 308
 309 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 310                                         SDTCisSameSizeAs<0,2>,
 311                                         SDTCisSameNumEltsAs<0,2>,
 312                                         SDTCisFP<0>, SDTCisInt<2>]>;
 313 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
 314                                  SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
 315 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 316                                  SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
 317 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisVec<0>,
 318                                              SDTCisSameAs<0,1>,
 319                                              SDTCisSameAs<0,2>,
 320                                              SDTCisVT<3, i32>,
 321                                              SDTCisVT<4, i32>]>;
 322 def SDTFPTernaryOpImmRound: SDTypeProfile<1, 5, [SDTCisFP<0>, SDTCisSameAs<0,1>,
 323                                                  SDTCisSameAs<0,2>,
 324                                                  SDTCisInt<3>,
 325                                                  SDTCisSameSizeAs<0, 3>,
 326                                                  SDTCisSameNumEltsAs<0, 3>,
 327                                                  SDTCisVT<4, i32>,
 328                                                  SDTCisVT<5, i32>]>;
 329 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
 330                                                SDTCisSameAs<0,1>,
 331                                                SDTCisVT<2, i32>,
 332                                                SDTCisVT<3, i32>]>;
 333
 334 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 335 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
 336                                           SDTCisInt<0>, SDTCisInt<1>]>;
 337
 338 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 339                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
 340
 341 def SDTTernlog  : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>,
 342                                        SDTCisSameAs<0,1>, SDTCisSameAs<0,2>,
 343                                        SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>;
 344
 345 def SDTFPBinOpRound : SDTypeProfile<1, 3, [      // fadd_round, fmul_round, etc.
 346   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>;
 347
 348 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [      // fsqrt_round, fgetexp_round, etc.
 349   SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>;
 350
 351 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 352                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>,
 353                            SDTCisFP<0>, SDTCisVT<4, i32>]>;
 354
 355 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
 356 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
 357
 358 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
 359
 360 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
 361 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
 362 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
 363
 364 def X86Shufp   : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
 365 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
 366
 367 def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
 368 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
 369 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
 370
 371 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
 372 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
 373
 374 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
 375 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
 376 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
 377
 378 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
 379 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
 380
 381 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>,
 382                                    SDTCisVec<1>, SDTCisInt<1>,
 383                                    SDTCisSameSizeAs<0,1>,
 384                                    SDTCisSameAs<1,2>,
 385                                    SDTCisOpSmallerThanOp<0, 1>]>;
 386 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
 387 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
 388
 389 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
 390 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
 391
 392 def X86vpmaddubsw  : SDNode<"X86ISD::VPMADDUBSW",
 393                             SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
 394                                                  SDTCVecEltisVT<1, i8>,
 395                                                  SDTCisSameSizeAs<0,1>,
 396                                                  SDTCisSameAs<1,2>]>>;
 397 def X86vpmaddwd    : SDNode<"X86ISD::VPMADDWD",
 398                             SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>,
 399                                                  SDTCVecEltisVT<1, i16>,
 400                                                  SDTCisSameSizeAs<0,1>,
 401                                                  SDTCisSameAs<1,2>]>,
 402                             [SDNPCommutative]>;
 403
 404 def X86VPermilpv  : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
 405 def X86VPermilpi  : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
 406 def X86VPermv     : SDNode<"X86ISD::VPERMV",
 407                            SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>,
 408                                                 SDTCisSameNumEltsAs<0,1>,
 409                                                 SDTCisSameSizeAs<0,1>,
 410                                                 SDTCisSameAs<0,2>]>>;
 411 def X86VPermi     : SDNode<"X86ISD::VPERMI",    SDTShuff2OpI>;
 412 def X86VPermt2     : SDNode<"X86ISD::VPERMV3",
 413                     SDTypeProfile<1, 3, [SDTCisVec<0>,
 414                                          SDTCisSameAs<0,1>, SDTCisInt<2>,
 415                                          SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
 416                                          SDTCisSameSizeAs<0,2>,
 417                                          SDTCisSameAs<0,3>]>, []>;
 418
 419 // Even though the index operand should be integer, we need to make it match the
 420 // destination type so that we can pattern match the masked version where the
 421 // index is also the passthru operand.
 422 def X86VPermi2X   : SDNode<"X86ISD::VPERMIV3",
 423                     SDTypeProfile<1, 3, [SDTCisVec<0>,
 424                                          SDTCisSameAs<0,1>,
 425                                          SDTCisSameAs<0,2>,
 426                                          SDTCisSameAs<0,3>]>, []>;
 427
 428 def X86vpternlog  : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
 429
 430 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 431
 432 def X86VFixupimm   : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImmRound>;
 433 def X86VFixupimmScalar   : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImmRound>;
 434 def X86VRange      : SDNode<"X86ISD::VRANGE",    SDTFPBinOpImmRound>;
 435 def X86VReduce     : SDNode<"X86ISD::VREDUCE",   SDTFPUnaryOpImmRound>;
 436 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
 437 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",  SDTFPUnaryOpImmRound>;
 438 def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS",
 439                        SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 440                                             SDTCisFP<1>,
 441                                             SDTCisSameNumEltsAs<0,1>,
 442                                             SDTCisVT<2, i32>]>, []>;
 443 def X86Vfpclasss   : SDNode<"X86ISD::VFPCLASSS",
 444                        SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>,
 445                                             SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;
 446
 447 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 448                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 449                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 450
 451 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 452 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
 453 def X86Vextract   : SDNode<"X86ISD::VEXTRACT",  SDTypeProfile<1, 2,
 454                               [SDTCisVec<1>,
 455                                SDTCisPtrTy<2>]>, []>;
 456
 457 def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
 458
 459 def X86Addsub    : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
 460
 461 def X86faddRnd   : SDNode<"X86ISD::FADD_RND",  SDTFPBinOpRound>;
 462 def X86faddRnds  : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>;
 463 def X86fsubRnd   : SDNode<"X86ISD::FSUB_RND",  SDTFPBinOpRound>;
 464 def X86fsubRnds  : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>;
 465 def X86fmulRnd   : SDNode<"X86ISD::FMUL_RND",  SDTFPBinOpRound>;
 466 def X86fmulRnds  : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>;
 467 def X86fdivRnd   : SDNode<"X86ISD::FDIV_RND",  SDTFPBinOpRound>;
 468 def X86fdivRnds  : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>;
 469 def X86fmaxRnd   : SDNode<"X86ISD::FMAX_RND",  SDTFPBinOpRound>;
 470 def X86fmaxRnds  : SDNode<"X86ISD::FMAXS_RND", SDTFPBinOpRound>;
 471 def X86fminRnd   : SDNode<"X86ISD::FMIN_RND",  SDTFPBinOpRound>;
 472 def X86fminRnds  : SDNode<"X86ISD::FMINS_RND", SDTFPBinOpRound>;
 473 def X86scalef    : SDNode<"X86ISD::SCALEF",         SDTFPBinOpRound>;
 474 def X86scalefs   : SDNode<"X86ISD::SCALEFS",        SDTFPBinOpRound>;
 475 def X86fsqrtRnd     : SDNode<"X86ISD::FSQRT_RND",   SDTFPUnaryOpRound>;
 476 def X86fsqrtRnds    : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>;
 477 def X86fgetexpRnd   : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
 478 def X86fgetexpRnds  : SDNode<"X86ISD::FGETEXPS_RND", SDTFPBinOpRound>;
 479
 480 def X86Fmadd     : SDNode<"X86ISD::FMADD",     SDTFPTernaryOp>;
 481 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFPTernaryOp>;
 482 def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFPTernaryOp>;
 483 def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFPTernaryOp>;
 484 def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFPTernaryOp>;
 485 def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFPTernaryOp>;
 486
 487 def X86FmaddRnd     : SDNode<"X86ISD::FMADD_RND",     SDTFmaRound>;
 488 def X86FnmaddRnd    : SDNode<"X86ISD::FNMADD_RND",    SDTFmaRound>;
 489 def X86FmsubRnd     : SDNode<"X86ISD::FMSUB_RND",     SDTFmaRound>;
 490 def X86FnmsubRnd    : SDNode<"X86ISD::FNMSUB_RND",    SDTFmaRound>;
 491 def X86FmaddsubRnd  : SDNode<"X86ISD::FMADDSUB_RND",  SDTFmaRound>;
 492 def X86FmsubaddRnd  : SDNode<"X86ISD::FMSUBADD_RND",  SDTFmaRound>;
 493
 494 // Scalar FMA intrinsics with passthru bits in operand 1.
 495 def X86FmaddRnds1   : SDNode<"X86ISD::FMADDS1_RND",     SDTFmaRound>;
 496 def X86FnmaddRnds1  : SDNode<"X86ISD::FNMADDS1_RND",    SDTFmaRound>;
 497 def X86FmsubRnds1   : SDNode<"X86ISD::FMSUBS1_RND",     SDTFmaRound>;
 498 def X86FnmsubRnds1  : SDNode<"X86ISD::FNMSUBS1_RND",    SDTFmaRound>;
 499
 500 // Scalar FMA intrinsics with passthru bits in operand 3.
 501 def X86FmaddRnds3   : SDNode<"X86ISD::FMADDS3_RND",     SDTFmaRound>;
 502 def X86FnmaddRnds3  : SDNode<"X86ISD::FNMADDS3_RND",    SDTFmaRound>;
 503 def X86FmsubRnds3   : SDNode<"X86ISD::FMSUBS3_RND",     SDTFmaRound>;
 504 def X86FnmsubRnds3  : SDNode<"X86ISD::FNMSUBS3_RND",    SDTFmaRound>;
 505
 506 def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>,
 507                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 508 def x86vpmadd52l     : SDNode<"X86ISD::VPMADD52L",     SDTIFma>;
 509 def x86vpmadd52h     : SDNode<"X86ISD::VPMADD52H",     SDTIFma>;
 510
 511 def X86rsqrt28   : SDNode<"X86ISD::RSQRT28",  SDTFPUnaryOpRound>;
 512 def X86rcp28     : SDNode<"X86ISD::RCP28",    SDTFPUnaryOpRound>;
 513 def X86exp2      : SDNode<"X86ISD::EXP2",     SDTFPUnaryOpRound>;
 514
 515 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28S",   SDTFPBinOpRound>;
 516 def X86rcp28s    : SDNode<"X86ISD::RCP28S",     SDTFPBinOpRound>;
 517 def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImmRound>;
 518 def X86Reduces   : SDNode<"X86ISD::VREDUCES",   SDTFPBinOpImmRound>;
 519 def X86GetMants  : SDNode<"X86ISD::VGETMANTS",  SDTFPBinOpImmRound>;
 520
 521 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 522                                          SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
 523                                          SDTCisVT<4, i8>]>;
 524 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 525                                          SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
 526                                          SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
 527                                          SDTCisVT<6, i8>]>;
 528
 529 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
 530 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
 531
 532 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
 533                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 534 def X86expand  : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
 535                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 536
 537 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 538                                           SDTCisSameAs<0,1>, SDTCisInt<2>,
 539                                           SDTCisVT<3, i32>]>;
 540
 541 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 542                                         SDTCisInt<0>, SDTCisFP<1>]>;
 543 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 544                                            SDTCisInt<0>, SDTCisFP<1>,
 545                                            SDTCisVT<2, i32>]>;
 546 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
 547                                             SDTCisVec<1>, SDTCisVT<2, i32>]>;
 548
 549 def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 550                                       SDTCisFP<0>, SDTCisInt<1>]>;
 551 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 552                                            SDTCisFP<0>, SDTCisInt<1>,
 553                                            SDTCisVT<2, i32>]>;
 554
 555 // Scalar
 556 def X86SintToFpRnd  : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND",  SDTintToFPRound>;
 557 def X86UintToFpRnd  : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND",  SDTintToFPRound>;
 558
 559 def X86cvtts2IntRnd  : SDNode<"X86ISD::CVTTS2SI_RND",  SDTSFloatToIntRnd>;
 560 def X86cvtts2UIntRnd : SDNode<"X86ISD::CVTTS2UI_RND",  SDTSFloatToIntRnd>;
 561
 562 def  X86cvts2si  : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>;
 563 def  X86cvts2usi : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>;
 564
 565 // Vector with rounding mode
 566
 567 // cvtt fp-to-int staff
 568 def X86cvttp2siRnd    : SDNode<"X86ISD::CVTTP2SI_RND", SDTFloatToIntRnd>;
 569 def X86cvttp2uiRnd    : SDNode<"X86ISD::CVTTP2UI_RND", SDTFloatToIntRnd>;
 570
 571 def X86VSintToFpRnd   : SDNode<"X86ISD::SINT_TO_FP_RND",  SDTVintToFPRound>;
 572 def X86VUintToFpRnd   : SDNode<"X86ISD::UINT_TO_FP_RND",  SDTVintToFPRound>;
 573
 574 // cvt fp-to-int staff
 575 def X86cvtp2IntRnd      : SDNode<"X86ISD::CVTP2SI_RND",  SDTFloatToIntRnd>;
 576 def X86cvtp2UIntRnd     : SDNode<"X86ISD::CVTP2UI_RND",  SDTFloatToIntRnd>;
 577
 578 // Vector without rounding mode
 579
 580 // cvtt fp-to-int staff
 581 def X86cvttp2si      : SDNode<"X86ISD::CVTTP2SI",  SDTFloatToInt>;
 582 def X86cvttp2ui      : SDNode<"X86ISD::CVTTP2UI",  SDTFloatToInt>;
 583
 584 def X86VSintToFP      : SDNode<"X86ISD::CVTSI2P",  SDTVintToFP>;
 585 def X86VUintToFP      : SDNode<"X86ISD::CVTUI2P",  SDTVintToFP>;
 586
 587 // cvt int-to-fp staff
 588 def X86cvtp2Int      : SDNode<"X86ISD::CVTP2SI",  SDTFloatToInt>;
 589 def X86cvtp2UInt     : SDNode<"X86ISD::CVTP2UI",  SDTFloatToInt>;
 590
 591 def X86cvtph2ps     : SDNode<"X86ISD::CVTPH2PS",
 592                               SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
 593                                                    SDTCVecEltisVT<1, i16>,
 594                                                    SDTCisVT<2, i32>]> >;
 595
 596 def X86cvtps2ph   : SDNode<"X86ISD::CVTPS2PH",
 597                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
 598                                              SDTCVecEltisVT<1, f32>,
 599                                              SDTCisVT<2, i32>]> >;
 600 def X86vfpextRnd  : SDNode<"X86ISD::VFPEXT_RND",
 601                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>,
 602                                              SDTCVecEltisVT<1, f32>,
 603                                              SDTCisOpSmallerThanOp<1, 0>,
 604                                              SDTCisVT<2, i32>]>>;
 605 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND",
 606                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
 607                                              SDTCVecEltisVT<1, f64>,
 608                                              SDTCisOpSmallerThanOp<0, 1>,
 609                                              SDTCisVT<2, i32>]>>;
 610
 611 def X86cvt2mask   : SDNode<"X86ISD::CVT2MASK", SDTIntTruncOp>;
 612
 613 //===----------------------------------------------------------------------===//
 614 // SSE Complex Patterns
 615 //===----------------------------------------------------------------------===//
 616
 617 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 618 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 619 // forms.
 620 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
 621                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 622                                    SDNPWantRoot]>;
 623 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
 624                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 625                                    SDNPWantRoot]>;
 626
 627 def ssmem : Operand<v4f32> {
 628   let PrintMethod = "printf32mem";
 629   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
 630   let ParserMatchClass = X86Mem32AsmOperand;
 631   let OperandType = "OPERAND_MEMORY";
 632 }
 633 def sdmem : Operand<v2f64> {
 634   let PrintMethod = "printf64mem";
 635   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
 636   let ParserMatchClass = X86Mem64AsmOperand;
 637   let OperandType = "OPERAND_MEMORY";
 638 }
 639
 640 //===----------------------------------------------------------------------===//
 641 // SSE pattern fragments
 642 //===----------------------------------------------------------------------===//
 643
 644 // Vector load wrappers to prevent folding of non-temporal aligned loads on
 645 // supporting targets.
 646 def vec128load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 647   return !Subtarget->hasSSE41() || !cast<LoadSDNode>(N)->isNonTemporal() ||
 648          cast<LoadSDNode>(N)->getAlignment() < 16;
 649 }]>;
 650 def vec256load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 651   return !Subtarget->hasAVX2() || !cast<LoadSDNode>(N)->isNonTemporal() ||
 652          cast<LoadSDNode>(N)->getAlignment() < 32;
 653 }]>;
 654 def vec512load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 655   return !Subtarget->hasAVX512() || !cast<LoadSDNode>(N)->isNonTemporal() ||
 656          cast<LoadSDNode>(N)->getAlignment() < 64;
 657 }]>;
 658
 659 // 128-bit load pattern fragments
 660 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 661 def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (vec128load node:$ptr))>;
 662 def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (vec128load node:$ptr))>;
 663 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (vec128load node:$ptr))>;
 664
 665 // 256-bit load pattern fragments
 666 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 667 def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32 (vec256load node:$ptr))>;
 668 def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64 (vec256load node:$ptr))>;
 669 def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64 (vec256load node:$ptr))>;
 670
 671 // 512-bit load pattern fragments
 672 def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (vec512load node:$ptr))>;
 673 def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64 (vec512load node:$ptr))>;
 674 def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64 (vec512load node:$ptr))>;
 675
 676 // 128-/256-/512-bit extload pattern fragments
 677 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
 678 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
 679 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
 680
 681 // Like 'store', but always requires 128-bit vector alignment.
 682 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
 683                            (store node:$val, node:$ptr), [{
 684   return cast<StoreSDNode>(N)->getAlignment() >= 16;
 685 }]>;
 686
 687 // Like 'store', but always requires 256-bit vector alignment.
 688 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
 689                               (store node:$val, node:$ptr), [{
 690   return cast<StoreSDNode>(N)->getAlignment() >= 32;
 691 }]>;
 692
 693 // Like 'store', but always requires 512-bit vector alignment.
 694 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
 695                               (store node:$val, node:$ptr), [{
 696   return cast<StoreSDNode>(N)->getAlignment() >= 64;
 697 }]>;
 698
 699 // Like 'load', but always requires 128-bit vector alignment.
 700 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 701   return cast<LoadSDNode>(N)->getAlignment() >= 16;
 702 }]>;
 703
 704 // Like 'load', but always requires 256-bit vector alignment.
 705 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 706   return cast<LoadSDNode>(N)->getAlignment() >= 32;
 707 }]>;
 708
 709 // Like 'load', but always requires 512-bit vector alignment.
 710 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 711   return cast<LoadSDNode>(N)->getAlignment() >= 64;
 712 }]>;
 713
 714 // 128-bit aligned load pattern fragments
 715 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 716 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
 717                                (v4f32 (alignedload node:$ptr))>;
 718 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
 719                                (v2f64 (alignedload node:$ptr))>;
 720 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
 721                                (v2i64 (alignedload node:$ptr))>;
 722
 723 // 256-bit aligned load pattern fragments
 724 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 725 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
 726                                (v8f32 (alignedload256 node:$ptr))>;
 727 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
 728                                (v4f64 (alignedload256 node:$ptr))>;
 729 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
 730                                (v4i64 (alignedload256 node:$ptr))>;
 731
 732 // 512-bit aligned load pattern fragments
 733 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
 734                                 (v16f32 (alignedload512 node:$ptr))>;
 735 def alignedloadv8f64  : PatFrag<(ops node:$ptr),
 736                                 (v8f64  (alignedload512 node:$ptr))>;
 737 def alignedloadv8i64  : PatFrag<(ops node:$ptr),
 738                                 (v8i64  (alignedload512 node:$ptr))>;
 739
 740 // Like 'vec128load', but uses special alignment checks suitable for use in
 741 // memory operands in most SSE instructions, which are required to
 742 // be naturally aligned on some targets but not on others.  If the subtarget
 743 // allows unaligned accesses, match any load, though this may require
 744 // setting a feature bit in the processor (on startup, for example).
 745 // Opteron 10h and later implement such a feature.
 746 def memop : PatFrag<(ops node:$ptr), (vec128load node:$ptr), [{
 747   return Subtarget->hasSSEUnalignedMem() ||
 748          cast<LoadSDNode>(N)->getAlignment() >= 16;
 749 }]>;
 750
 751 // 128-bit memop pattern fragments
 752 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 753 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 754 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 755 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 756
 757 // These are needed to match a scalar memop that is used in a vector-only
 758 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 759 // The memory operand is required to be a 128-bit load, so it must be converted
 760 // from a vector to a scalar.
 761 def memopfsf32_128 : PatFrag<(ops node:$ptr),
 762   (f32 (extractelt (memopv4f32 node:$ptr), (iPTR 0)))>;
 763 def memopfsf64_128 : PatFrag<(ops node:$ptr),
 764   (f64 (extractelt (memopv2f64 node:$ptr), (iPTR 0)))>;
 765
 766
 767 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
 768 // 16-byte boundary.
 769 // FIXME: 8 byte alignment for mmx reads is not required
 770 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 771   return cast<LoadSDNode>(N)->getAlignment() >= 8;
 772 }]>;
 773
 774 def memopmmx  : PatFrag<(ops node:$ptr), (x86mmx  (memop64 node:$ptr))>;
 775
 776 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 777   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 778   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 779     return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
 780             Mgt->getBasePtr().getValueType() == MVT::v4i32);
 781   return false;
 782 }]>;
 783
 784 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 785   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 786   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 787     return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
 788             Mgt->getBasePtr().getValueType() == MVT::v8i32);
 789   return false;
 790 }]>;
 791
 792 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 793   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 794   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 795     return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
 796             Mgt->getBasePtr().getValueType() == MVT::v2i64);
 797   return false;
 798 }]>;
 799 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 800   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 801   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 802     return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
 803             Mgt->getBasePtr().getValueType() == MVT::v4i64);
 804   return false;
 805 }]>;
 806 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 807   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 808   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 809     return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
 810             Mgt->getBasePtr().getValueType() == MVT::v8i64);
 811   return false;
 812 }]>;
 813 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 814   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 815   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 816     return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
 817             Mgt->getBasePtr().getValueType() == MVT::v16i32);
 818   return false;
 819 }]>;
 820
 821 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 822   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 823   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 824     return (Sc->getIndex().getValueType() == MVT::v2i64 ||
 825             Sc->getBasePtr().getValueType() == MVT::v2i64);
 826   return false;
 827 }]>;
 828
 829 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 830   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 831   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 832     return (Sc->getIndex().getValueType() == MVT::v4i32 ||
 833             Sc->getBasePtr().getValueType() == MVT::v4i32);
 834   return false;
 835 }]>;
 836
 837 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 838   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 839   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 840     return (Sc->getIndex().getValueType() == MVT::v4i64 ||
 841             Sc->getBasePtr().getValueType() == MVT::v4i64);
 842   return false;
 843 }]>;
 844
 845 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 846   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 847   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 848     return (Sc->getIndex().getValueType() == MVT::v8i32 ||
 849             Sc->getBasePtr().getValueType() == MVT::v8i32);
 850   return false;
 851 }]>;
 852
 853 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 854   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 855   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 856     return (Sc->getIndex().getValueType() == MVT::v8i64 ||
 857             Sc->getBasePtr().getValueType() == MVT::v8i64);
 858   return false;
 859 }]>;
 860 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 861   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 862   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 863     return (Sc->getIndex().getValueType() == MVT::v16i32 ||
 864             Sc->getBasePtr().getValueType() == MVT::v16i32);
 865   return false;
 866 }]>;
 867
 868 // 128-bit bitconvert pattern fragments
 869 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
 870 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 871 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 872 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 873 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 874 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 875
 876 // 256-bit bitconvert pattern fragments
 877 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
 878 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
 879 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
 880 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
 881 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
 882
 883 // 512-bit bitconvert pattern fragments
 884 def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>;
 885 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
 886 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
 887 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
 888 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
 889
 890 def vzmovl_v2i64 : PatFrag<(ops node:$src),
 891                            (bitconvert (v2i64 (X86vzmovl
 892                              (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
 893 def vzmovl_v4i32 : PatFrag<(ops node:$src),
 894                            (bitconvert (v4i32 (X86vzmovl
 895                              (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
 896
 897 def vzload_v2i64 : PatFrag<(ops node:$src),
 898                            (bitconvert (v2i64 (X86vzload node:$src)))>;
 899
 900
 901 def fp32imm0 : PatLeaf<(f32 fpimm), [{
 902   return N->isExactlyValue(+0.0);
 903 }]>;
 904
 905 def fp64imm0 : PatLeaf<(f64 fpimm), [{
 906   return N->isExactlyValue(+0.0);
 907 }]>;
 908
 909 def I8Imm : SDNodeXForm<imm, [{
 910   // Transformation function: get the low 8 bits.
 911   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 912 }]>;
 913
 914 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
 915 def FROUND_CURRENT : ImmLeaf<i32, [{
 916   return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
 917 }]>;
 918
 919 // BYTE_imm - Transform bit immediates into byte immediates.
 920 def BYTE_imm  : SDNodeXForm<imm, [{
 921   // Transformation function: imm >> 3
 922   return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
 923 }]>;
 924
 925 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
 926 // to VEXTRACTF128/VEXTRACTI128 imm.
 927 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
 928   return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
 929 }]>;
 930
 931 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
 932 // VINSERTF128/VINSERTI128 imm.
 933 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
 934   return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
 935 }]>;
 936
 937 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
 938 // to VEXTRACTF64x4 imm.
 939 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
 940   return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
 941 }]>;
 942
 943 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
 944 // VINSERTF64x4 imm.
 945 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
 946   return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
 947 }]>;
 948
 949 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
 950                                    (extract_subvector node:$bigvec,
 951                                                       node:$index), [{
 952   return X86::isVEXTRACT128Index(N);
 953 }], EXTRACT_get_vextract128_imm>;
 954
 955 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 956                                       node:$index),
 957                                  (insert_subvector node:$bigvec, node:$smallvec,
 958                                                    node:$index), [{
 959   return X86::isVINSERT128Index(N);
 960 }], INSERT_get_vinsert128_imm>;
 961
 962
 963 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
 964                                    (extract_subvector node:$bigvec,
 965                                                       node:$index), [{
 966   return X86::isVEXTRACT256Index(N);
 967 }], EXTRACT_get_vextract256_imm>;
 968
 969 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 970                                       node:$index),
 971                                  (insert_subvector node:$bigvec, node:$smallvec,
 972                                                    node:$index), [{
 973   return X86::isVINSERT256Index(N);
 974 }], INSERT_get_vinsert256_imm>;
 975
 976 def X86mload : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 977                          (masked_load node:$src1, node:$src2, node:$src3), [{
 978   return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
 979     cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
 980 }]>;
 981
 982 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 983                          (X86mload node:$src1, node:$src2, node:$src3), [{
 984   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 16;
 985 }]>;
 986
 987 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 988                          (X86mload node:$src1, node:$src2, node:$src3), [{
 989   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 32;
 990 }]>;
 991
 992 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 993                          (X86mload node:$src1, node:$src2, node:$src3), [{
 994   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 64;
 995 }]>;
 996
 997 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 998                          (masked_load node:$src1, node:$src2, node:$src3), [{
 999   return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
1000     cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
1001 }]>;
1002
1003 def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1004                          (masked_load node:$src1, node:$src2, node:$src3), [{
1005   return cast<MaskedLoadSDNode>(N)->isExpandingLoad();
1006 }]>;
1007
1008 // Masked store fragments.
1009 // X86mstore can't be implemented in core DAG files because some targets
1010 // do not support vector types (llvm-tblgen will fail).
1011 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1012                         (masked_store node:$src1, node:$src2, node:$src3), [{
1013   return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) &&
1014          (!cast<MaskedStoreSDNode>(N)->isCompressingStore());
1015 }]>;
1016
1017 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1018                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1019   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 16;
1020 }]>;
1021
1022 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1023                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1024   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 32;
1025 }]>;
1026
1027 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1028                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1029   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 64;
1030 }]>;
1031
1032 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1033                          (masked_store node:$src1, node:$src2, node:$src3), [{
1034   return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) &&
1035          (!cast<MaskedStoreSDNode>(N)->isCompressingStore());
1036 }]>;
1037
1038 def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1039                              (masked_store node:$src1, node:$src2, node:$src3), [{
1040     return cast<MaskedStoreSDNode>(N)->isCompressingStore();
1041 }]>;
1042
1043 // masked truncstore fragments
1044 // X86mtruncstore can't be implemented in core DAG files because some targets
1045 // doesn't support vector type ( llvm-tblgen will fail)
1046 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1047                              (masked_store node:$src1, node:$src2, node:$src3), [{
1048     return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
1049 }]>;
1050 def masked_truncstorevi8 :
1051   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1052           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1053   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1054 }]>;
1055 def masked_truncstorevi16 :
1056   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1057           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1058   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1059 }]>;
1060 def masked_truncstorevi32 :
1061   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1062           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1063   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1064 }]>;
1065
1066 def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES",  SDTStore,
1067                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1068
1069 def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS",  SDTStore,
1070                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1071
1072 def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES",  SDTMaskedStore,
1073                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1074
1075 def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS",  SDTMaskedStore,
1076                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1077
1078 def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr),
1079                                (X86TruncSStore node:$val, node:$ptr), [{
1080   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1081 }]>;
1082
1083 def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr),
1084                                (X86TruncUSStore node:$val, node:$ptr), [{
1085   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1086 }]>;
1087
1088 def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr),
1089                                (X86TruncSStore node:$val, node:$ptr), [{
1090   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1091 }]>;
1092
1093 def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr),
1094                                (X86TruncUSStore node:$val, node:$ptr), [{
1095   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1096 }]>;
1097
1098 def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr),
1099                                (X86TruncSStore node:$val, node:$ptr), [{
1100   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1101 }]>;
1102
1103 def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr),
1104                                (X86TruncUSStore node:$val, node:$ptr), [{
1105   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1106 }]>;
1107
1108 def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1109                      (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1110   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1111 }]>;
1112
1113 def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1114                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1115   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1116 }]>;
1117
1118 def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1119                                (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1120   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1121 }]>;
1122
1123 def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1124                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1125   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1126 }]>;
1127
1128 def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1129                                (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1130   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1131 }]>;
1132
1133 def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1134                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1135   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1136 }]>;
1137
1138 def assertzext_i1 :
1139   PatFrag<(ops node:$src), (assertzext node:$src), [{
1140     return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i1;
1141 }]>;