contrib/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

   1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides pattern fragments useful for SIMD instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // MMX specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // Low word of MMX to GPR.
  19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
  20                             [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
  21 // GPR to low word of MMX.
  22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
  23                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
  24
  25 //===----------------------------------------------------------------------===//
  26 // MMX Pattern Fragments
  27 //===----------------------------------------------------------------------===//
  28
  29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
  30 def load_mvmmx : PatFrag<(ops node:$ptr),
  31                          (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
  32
  33 //===----------------------------------------------------------------------===//
  34 // SSE specific DAG Nodes.
  35 //===----------------------------------------------------------------------===//
  36
  37 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>,
  38                                        SDTCisFP<1>, SDTCisVT<3, i8>,
  39                                        SDTCisVec<1>]>;
  40 def SDTX86CmpTestSae : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
  41                                      SDTCisSameAs<1, 2>, SDTCisInt<3>]>;
  42
  43 def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
  44 def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
  45
  46 // Commutative and Associative FMIN and FMAX.
  47 def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
  48     [SDNPCommutative, SDNPAssociative]>;
  49 def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
  50     [SDNPCommutative, SDNPAssociative]>;
  51
  52 def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
  53                         [SDNPCommutative, SDNPAssociative]>;
  54 def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
  55                         [SDNPCommutative, SDNPAssociative]>;
  56 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
  57                         [SDNPCommutative, SDNPAssociative]>;
  58 def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp>;
  59 def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
  60 def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
  61 def X86frsqrt14s: SDNode<"X86ISD::FRSQRTS",  SDTFPBinOp>;
  62 def X86frcp14s : SDNode<"X86ISD::FRCPS",    SDTFPBinOp>;
  63 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
  64 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
  65 def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
  66 def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
  67 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
  68 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
  69 def X86cmps    : SDNode<"X86ISD::FSETCC",     SDTX86Cmps>;
  70 def X86pshufb  : SDNode<"X86ISD::PSHUFB",
  71                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
  72                                       SDTCisSameAs<0,2>]>>;
  73 def X86psadbw  : SDNode<"X86ISD::PSADBW",
  74                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
  75                                       SDTCVecEltisVT<1, i8>,
  76                                       SDTCisSameSizeAs<0,1>,
  77                                       SDTCisSameAs<1,2>]>, [SDNPCommutative]>;
  78 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
  79                   SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
  80                                        SDTCVecEltisVT<1, i8>,
  81                                        SDTCisSameSizeAs<0,1>,
  82                                        SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
  83 def X86andnp   : SDNode<"X86ISD::ANDNP",
  84                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  85                                       SDTCisSameAs<0,2>]>>;
  86 def X86multishift   : SDNode<"X86ISD::MULTISHIFT",
  87                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
  88                                       SDTCisSameAs<1,2>]>>;
  89 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
  90                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
  91                                       SDTCisPtrTy<2>]>>;
  92 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
  93                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
  94                                       SDTCisPtrTy<2>]>>;
  95 def X86pinsrb  : SDNode<"X86ISD::PINSRB",
  96                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
  97                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
  98 def X86pinsrw  : SDNode<"X86ISD::PINSRW",
  99                  SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
 100                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 101 def X86insertps : SDNode<"X86ISD::INSERTPS",
 102                  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
 103                                       SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
 104 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
 105                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 106
 107 def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
 108                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 109
 110 def X86vzext   : SDNode<"X86ISD::VZEXT",
 111                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 112                                               SDTCisInt<0>, SDTCisInt<1>,
 113                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 114
 115 def X86vsext   : SDNode<"X86ISD::VSEXT",
 116                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 117                                               SDTCisInt<0>, SDTCisInt<1>,
 118                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 119
 120 def SDTVtrunc    : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 121                                        SDTCisInt<0>, SDTCisInt<1>,
 122                                        SDTCisOpSmallerThanOp<0, 1>]>;
 123
 124 def X86vtrunc    : SDNode<"X86ISD::VTRUNC",   SDTVtrunc>;
 125 def X86vtruncs   : SDNode<"X86ISD::VTRUNCS",  SDTVtrunc>;
 126 def X86vtruncus  : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
 127
 128 def X86vfpext  : SDNode<"X86ISD::VFPEXT",
 129                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>,
 130                                              SDTCVecEltisVT<1, f32>,
 131                                              SDTCisSameSizeAs<0, 1>]>>;
 132 def X86vfpround: SDNode<"X86ISD::VFPROUND",
 133                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
 134                                              SDTCVecEltisVT<1, f64>,
 135                                              SDTCisSameSizeAs<0, 1>]>>;
 136
 137 def X86froundRnd: SDNode<"X86ISD::VFPROUNDS_RND",
 138                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
 139                                              SDTCisSameAs<0, 1>,
 140                                              SDTCVecEltisVT<2, f64>,
 141                                              SDTCisSameSizeAs<0, 2>,
 142                                              SDTCisVT<3, i32>]>>;
 143
 144 def X86fpextRnd  : SDNode<"X86ISD::VFPEXTS_RND",
 145                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f64>,
 146                                              SDTCisSameAs<0, 1>,
 147                                              SDTCVecEltisVT<2, f32>,
 148                                              SDTCisSameSizeAs<0, 2>,
 149                                              SDTCisVT<3, i32>]>>;
 150
 151 def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    SDTIntShiftOp>;
 152 def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    SDTIntShiftOp>;
 153 def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
 154 def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
 155 def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
 156
 157 def X86IntCmpMask : SDTypeProfile<1, 2,
 158     [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, SDTCisSameAs<1, 2>, SDTCisInt<1>,
 159      SDTCisSameNumEltsAs<0, 1>]>;
 160 def X86pcmpeqm  : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
 161 def X86pcmpgtm  : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
 162
 163 def X86CmpMaskCC :
 164       SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 165                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 166                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
 167 def X86CmpMaskCCRound :
 168       SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
 169                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 170                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
 171                        SDTCisVT<4, i32>]>;
 172 def X86CmpMaskCCScalar :
 173       SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
 174
 175 def X86CmpMaskCCScalarRound :
 176       SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
 177                            SDTCisVT<4, i32>]>;
 178
 179 def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;
 180 def X86cmpmRnd  : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
 181 def X86cmpmu    : SDNode<"X86ISD::CMPMU",    X86CmpMaskCC>;
 182 def X86cmpms    : SDNode<"X86ISD::FSETCCM",   X86CmpMaskCCScalar>;
 183 def X86cmpmsRnd : SDNode<"X86ISD::FSETCCM_RND",   X86CmpMaskCCScalarRound>;
 184
 185 def X86vshl    : SDNode<"X86ISD::VSHL",
 186                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 187                                       SDTCisVec<2>]>>;
 188 def X86vsrl    : SDNode<"X86ISD::VSRL",
 189                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 190                                       SDTCisVec<2>]>>;
 191 def X86vsra    : SDNode<"X86ISD::VSRA",
 192                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 193                                       SDTCisVec<2>]>>;
 194
 195 def X86vsrav   : SDNode<"X86ISD::VSRAV" ,
 196                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 197                                              SDTCisSameAs<0,2>]>>;
 198
 199 def X86vshli   : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
 200 def X86vsrli   : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
 201 def X86vsrai   : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
 202
 203 def X86vrotli  : SDNode<"X86ISD::VROTLI", SDTIntShiftOp>;
 204 def X86vrotri  : SDNode<"X86ISD::VROTRI", SDTIntShiftOp>;
 205
 206 def X86vprot   : SDNode<"X86ISD::VPROT",
 207                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 208                                              SDTCisSameAs<0,2>]>>;
 209 def X86vproti  : SDNode<"X86ISD::VPROTI",
 210                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 211                                              SDTCisVT<2, i8>]>>;
 212
 213 def X86vpshl   : SDNode<"X86ISD::VPSHL",
 214                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 215                                              SDTCisSameAs<0,2>]>>;
 216 def X86vpsha   : SDNode<"X86ISD::VPSHA",
 217                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 218                                              SDTCisSameAs<0,2>]>>;
 219
 220 def X86vpcom   : SDNode<"X86ISD::VPCOM",
 221                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 222                                              SDTCisSameAs<0,2>,
 223                                              SDTCisVT<3, i8>]>>;
 224 def X86vpcomu  : SDNode<"X86ISD::VPCOMU",
 225                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 226                                              SDTCisSameAs<0,2>,
 227                                              SDTCisVT<3, i8>]>>;
 228 def X86vpermil2 : SDNode<"X86ISD::VPERMIL2",
 229                         SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 230                                              SDTCisSameAs<0,2>,
 231                                              SDTCisSameSizeAs<0,3>,
 232                                              SDTCisSameNumEltsAs<0, 3>,
 233                                              SDTCisVT<4, i8>]>>;
 234 def X86vpperm : SDNode<"X86ISD::VPPERM",
 235                         SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
 236                                              SDTCisSameAs<0,2>]>>;
 237
 238 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 239                                           SDTCisVec<1>,
 240                                           SDTCisSameAs<2, 1>]>;
 241
 242 def SDTX86Testm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 243                                        SDTCisSameAs<2, 1>, SDTCVecEltisVT<0, i1>,
 244                                        SDTCisSameNumEltsAs<0, 1>]>;
 245
 246 def X86addus   : SDNode<"X86ISD::ADDUS", SDTIntBinOp, [SDNPCommutative]>;
 247 def X86subus   : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
 248 def X86adds    : SDNode<"X86ISD::ADDS", SDTIntBinOp, [SDNPCommutative]>;
 249 def X86subs    : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
 250 def X86mulhrs  : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>;
 251 def X86avg     : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>;
 252 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
 253 def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
 254 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
 255 def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
 256 def X86testm   : SDNode<"X86ISD::TESTM", SDTX86Testm, [SDNPCommutative]>;
 257 def X86testnm  : SDNode<"X86ISD::TESTNM", SDTX86Testm, [SDNPCommutative]>;
 258
 259 def X86movmsk : SDNode<"X86ISD::MOVMSK",
 260                         SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>;
 261
 262 def X86select  : SDNode<"X86ISD::SELECT",
 263                         SDTypeProfile<1, 3, [SDTCVecEltisVT<1, i1>,
 264                                              SDTCisSameAs<0, 2>,
 265                                              SDTCisSameAs<2, 3>,
 266                                              SDTCisSameNumEltsAs<0, 1>]>>;
 267
 268 def X86selects : SDNode<"X86ISD::SELECTS",
 269                         SDTypeProfile<1, 3, [SDTCisVT<1, i1>,
 270                                              SDTCisSameAs<0, 2>,
 271                                              SDTCisSameAs<2, 3>]>>;
 272
 273 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
 274                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 275                                              SDTCVecEltisVT<1, i32>,
 276                                              SDTCisSameSizeAs<0,1>,
 277                                              SDTCisSameAs<1,2>]>,
 278                                              [SDNPCommutative]>;
 279 def X86pmuldq  : SDNode<"X86ISD::PMULDQ",
 280                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 281                                              SDTCVecEltisVT<1, i32>,
 282                                              SDTCisSameSizeAs<0,1>,
 283                                              SDTCisSameAs<1,2>]>,
 284                                              [SDNPCommutative]>;
 285
 286 def X86extrqi : SDNode<"X86ISD::EXTRQI",
 287                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 288                                        SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
 289 def X86insertqi : SDNode<"X86ISD::INSERTQI",
 290                     SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 291                                          SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
 292                                          SDTCisVT<4, i8>]>>;
 293
 294 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
 295 // translated into one of the target nodes below during lowering.
 296 // Note: this is a work in progress...
 297 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 298 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 299                                 SDTCisSameAs<0,2>]>;
 300
 301 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 302                                         SDTCisSameSizeAs<0,2>,
 303                                         SDTCisSameNumEltsAs<0,2>]>;
 304 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
 305                                  SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
 306 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 307                                  SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
 308 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 309                              SDTCisSameAs<0,2>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
 310 def SDTFPTernaryOpImmRound: SDTypeProfile<1, 5, [SDTCisFP<0>, SDTCisSameAs<0,1>,
 311                                                  SDTCisSameAs<0,2>,
 312                                                  SDTCisInt<3>,
 313                                                  SDTCisSameSizeAs<0, 3>,
 314                                                  SDTCisSameNumEltsAs<0, 3>,
 315                                                  SDTCisVT<4, i32>,
 316                                                  SDTCisVT<5, i32>]>;
 317 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 318                               SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
 319
 320 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 321 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
 322                                           SDTCisInt<0>, SDTCisInt<1>]>;
 323
 324 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 325                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
 326
 327 def SDTTernlog  : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 328                                 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>,
 329                                 SDTCisVT<4, i8>]>;
 330
 331 def SDTFPBinOpRound : SDTypeProfile<1, 3, [      // fadd_round, fmul_round, etc.
 332   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>;
 333
 334 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [      // fsqrt_round, fgetexp_round, etc.
 335   SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>;
 336
 337 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 338                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 339 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 340                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>,
 341                            SDTCisVT<4, i32>]>;
 342
 343 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
 344 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
 345
 346 def X86Abs      : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
 347 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
 348
 349 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
 350 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
 351 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
 352
 353 def X86Shufp   : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
 354 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
 355
 356 def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
 357 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
 358 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
 359
 360 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
 361 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
 362
 363 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
 364 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
 365 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
 366
 367 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
 368 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
 369
 370 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 371                                    SDTCisSameSizeAs<0,1>,
 372                                    SDTCisSameAs<1,2>]>;
 373 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
 374 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
 375
 376 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
 377 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
 378
 379 def X86vpmaddubsw  : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
 380 def X86vpmaddwd    : SDNode<"X86ISD::VPMADDWD"   , SDTPack, [SDNPCommutative]>;
 381
 382 def X86VPermilpv  : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
 383 def X86VPermilpi  : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
 384 def X86VPermv     : SDNode<"X86ISD::VPERMV",
 385                            SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>,
 386                                                 SDTCisSameNumEltsAs<0,1>,
 387                                                 SDTCisSameSizeAs<0,1>,
 388                                                 SDTCisSameAs<0,2>]>>;
 389 def X86VPermi     : SDNode<"X86ISD::VPERMI",    SDTShuff2OpI>;
 390 def X86VPermt2     : SDNode<"X86ISD::VPERMV3",
 391                     SDTypeProfile<1, 3, [SDTCisVec<0>,
 392                                          SDTCisSameAs<0,1>, SDTCisInt<2>,
 393                                          SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
 394                                          SDTCisSameSizeAs<0,2>,
 395                                          SDTCisSameAs<0,3>]>, []>;
 396
 397 // Even though the index operand should be integer, we need to make it match the
 398 // destination type so that we can pattern match the masked version where the
 399 // index is also the passthru operand.
 400 def X86VPermi2X   : SDNode<"X86ISD::VPERMIV3",
 401                     SDTypeProfile<1, 3, [SDTCisVec<0>,
 402                                          SDTCisSameAs<0,1>,
 403                                          SDTCisSameAs<0,2>,
 404                                          SDTCisSameAs<0,3>]>, []>;
 405
 406 def X86vpternlog  : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
 407
 408 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 409
 410 def X86VFixupimm   : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImmRound>;
 411 def X86VFixupimmScalar   : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImmRound>;
 412 def X86VRange      : SDNode<"X86ISD::VRANGE",    SDTFPBinOpImmRound>;
 413 def X86VReduce     : SDNode<"X86ISD::VREDUCE",   SDTFPUnaryOpImmRound>;
 414 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
 415 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",  SDTFPUnaryOpImmRound>;
 416 def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS",
 417                        SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 418                                             SDTCisVec<1>, SDTCisFP<1>,
 419                                             SDTCisSameNumEltsAs<0,1>,
 420                                             SDTCisVT<2, i32>]>, []>;
 421 def X86Vfpclasss   : SDNode<"X86ISD::VFPCLASSS",
 422                        SDTypeProfile<1, 2, [SDTCisVT<0, i1>,
 423                                             SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;
 424
 425 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 426                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 427                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 428
 429 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 430 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
 431 def X86Vinsert   : SDNode<"X86ISD::VINSERT",  SDTypeProfile<1, 3,
 432                               [SDTCisSameAs<0, 1>, SDTCisEltOfVec<2, 1>,
 433                                SDTCisPtrTy<3>]>, []>;
 434 def X86Vextract   : SDNode<"X86ISD::VEXTRACT",  SDTypeProfile<1, 2,
 435                               [SDTCisEltOfVec<0, 1>, SDTCisVec<1>,
 436                                SDTCisPtrTy<2>]>, []>;
 437
 438 def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
 439
 440 def X86Addsub    : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
 441
 442 def X86faddRnd   : SDNode<"X86ISD::FADD_RND",  SDTFPBinOpRound>;
 443 def X86fsubRnd   : SDNode<"X86ISD::FSUB_RND",  SDTFPBinOpRound>;
 444 def X86fmulRnd   : SDNode<"X86ISD::FMUL_RND",  SDTFPBinOpRound>;
 445 def X86fdivRnd   : SDNode<"X86ISD::FDIV_RND",  SDTFPBinOpRound>;
 446 def X86fmaxRnd   : SDNode<"X86ISD::FMAX_RND",       SDTFPBinOpRound>;
 447 def X86scalef    : SDNode<"X86ISD::SCALEF",         SDTFPBinOpRound>;
 448 def X86scalefs   : SDNode<"X86ISD::SCALEFS",        SDTFPBinOpRound>;
 449 def X86fminRnd   : SDNode<"X86ISD::FMIN_RND",       SDTFPBinOpRound>;
 450 def X86fsqrtRnd     : SDNode<"X86ISD::FSQRT_RND",   SDTFPUnaryOpRound>;
 451 def X86fsqrtRnds    : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>;
 452 def X86fgetexpRnd   : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
 453 def X86fgetexpRnds  : SDNode<"X86ISD::FGETEXPS_RND", SDTFPBinOpRound>;
 454
 455 def X86Fmadd     : SDNode<"X86ISD::FMADD",     SDTFma>;
 456 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFma>;
 457 def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFma>;
 458 def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFma>;
 459 def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFma>;
 460 def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFma>;
 461
 462 def X86FmaddRnd     : SDNode<"X86ISD::FMADD_RND",     SDTFmaRound>;
 463 def X86FnmaddRnd    : SDNode<"X86ISD::FNMADD_RND",    SDTFmaRound>;
 464 def X86FmsubRnd     : SDNode<"X86ISD::FMSUB_RND",     SDTFmaRound>;
 465 def X86FnmsubRnd    : SDNode<"X86ISD::FNMSUB_RND",    SDTFmaRound>;
 466 def X86FmaddsubRnd  : SDNode<"X86ISD::FMADDSUB_RND",  SDTFmaRound>;
 467 def X86FmsubaddRnd  : SDNode<"X86ISD::FMSUBADD_RND",  SDTFmaRound>;
 468
 469 // Scalar FMA intrinsics with passthru bits in operand 1.
 470 def X86FmaddRnds1   : SDNode<"X86ISD::FMADDS1_RND",     SDTFmaRound>;
 471 def X86FnmaddRnds1  : SDNode<"X86ISD::FNMADDS1_RND",    SDTFmaRound>;
 472 def X86FmsubRnds1   : SDNode<"X86ISD::FMSUBS1_RND",     SDTFmaRound>;
 473 def X86FnmsubRnds1  : SDNode<"X86ISD::FNMSUBS1_RND",    SDTFmaRound>;
 474
 475 // Scalar FMA intrinsics with passthru bits in operand 3.
 476 def X86FmaddRnds3   : SDNode<"X86ISD::FMADDS3_RND",     SDTFmaRound>;
 477 def X86FnmaddRnds3  : SDNode<"X86ISD::FNMADDS3_RND",    SDTFmaRound>;
 478 def X86FmsubRnds3   : SDNode<"X86ISD::FMSUBS3_RND",     SDTFmaRound>;
 479 def X86FnmsubRnds3  : SDNode<"X86ISD::FNMSUBS3_RND",    SDTFmaRound>;
 480
 481 def x86vpmadd52l     : SDNode<"X86ISD::VPMADD52L",     SDTFma>;
 482 def x86vpmadd52h     : SDNode<"X86ISD::VPMADD52H",     SDTFma>;
 483
 484 def X86rsqrt28   : SDNode<"X86ISD::RSQRT28",  SDTFPUnaryOpRound>;
 485 def X86rcp28     : SDNode<"X86ISD::RCP28",    SDTFPUnaryOpRound>;
 486 def X86exp2      : SDNode<"X86ISD::EXP2",     SDTFPUnaryOpRound>;
 487
 488 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28S",   SDTFPBinOpRound>;
 489 def X86rcp28s    : SDNode<"X86ISD::RCP28S",     SDTFPBinOpRound>;
 490 def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImmRound>;
 491 def X86Reduces   : SDNode<"X86ISD::VREDUCES",   SDTFPBinOpImmRound>;
 492 def X86GetMants  : SDNode<"X86ISD::VGETMANTS",  SDTFPBinOpImmRound>;
 493
 494 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 495                                          SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
 496                                          SDTCisVT<4, i8>]>;
 497 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 498                                          SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
 499                                          SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
 500                                          SDTCisVT<6, i8>]>;
 501
 502 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
 503 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
 504
 505 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
 506                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 507 def X86expand  : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
 508                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 509
 510 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 511                                           SDTCisSameAs<0,1>, SDTCisInt<2>,
 512                                           SDTCisVT<3, i32>]>;
 513
 514 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 515                                         SDTCisInt<0>, SDTCisFP<1>]>;
 516 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 517                                            SDTCisInt<0>, SDTCisFP<1>,
 518                                            SDTCisVT<2, i32>]>;
 519 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
 520                                             SDTCisVec<1>, SDTCisVT<2, i32>]>;
 521
 522 def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 523                                       SDTCisFP<0>, SDTCisInt<1>]>;
 524 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 525                                            SDTCisFP<0>, SDTCisInt<1>,
 526                                            SDTCisVT<2, i32>]>;
 527
 528 // Scalar
 529 def X86SintToFpRnd  : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND",  SDTintToFPRound>;
 530 def X86UintToFpRnd  : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND",  SDTintToFPRound>;
 531
 532 def X86cvtts2IntRnd  : SDNode<"X86ISD::CVTTS2SI_RND",  SDTSFloatToIntRnd>;
 533 def X86cvtts2UIntRnd : SDNode<"X86ISD::CVTTS2UI_RND",  SDTSFloatToIntRnd>;
 534
 535 def  X86cvts2si  : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>;
 536 def  X86cvts2usi : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>;
 537
 538 // Vector with rounding mode
 539
 540 // cvtt fp-to-int staff
 541 def X86cvttp2siRnd    : SDNode<"X86ISD::CVTTP2SI_RND", SDTFloatToIntRnd>;
 542 def X86cvttp2uiRnd    : SDNode<"X86ISD::CVTTP2UI_RND", SDTFloatToIntRnd>;
 543
 544 def X86VSintToFpRnd   : SDNode<"X86ISD::SINT_TO_FP_RND",  SDTVintToFPRound>;
 545 def X86VUintToFpRnd   : SDNode<"X86ISD::UINT_TO_FP_RND",  SDTVintToFPRound>;
 546
 547 // cvt fp-to-int staff
 548 def X86cvtp2IntRnd      : SDNode<"X86ISD::CVTP2SI_RND",  SDTFloatToIntRnd>;
 549 def X86cvtp2UIntRnd     : SDNode<"X86ISD::CVTP2UI_RND",  SDTFloatToIntRnd>;
 550
 551 // Vector without rounding mode
 552
 553 // cvtt fp-to-int staff
 554 def X86cvttp2si      : SDNode<"X86ISD::CVTTP2SI",  SDTFloatToInt>;
 555 def X86cvttp2ui      : SDNode<"X86ISD::CVTTP2UI",  SDTFloatToInt>;
 556
 557 def X86VSintToFP      : SDNode<"X86ISD::CVTSI2P",  SDTVintToFP>;
 558 def X86VUintToFP      : SDNode<"X86ISD::CVTUI2P",  SDTVintToFP>;
 559
 560 // cvt int-to-fp staff
 561 def X86cvtp2Int      : SDNode<"X86ISD::CVTP2SI",  SDTFloatToInt>;
 562 def X86cvtp2UInt     : SDNode<"X86ISD::CVTP2UI",  SDTFloatToInt>;
 563
 564 def X86cvtph2ps     : SDNode<"X86ISD::CVTPH2PS",
 565                               SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
 566                                                    SDTCVecEltisVT<1, i16>,
 567                                                    SDTCisVT<2, i32>]> >;
 568
 569 def X86cvtps2ph   : SDNode<"X86ISD::CVTPS2PH",
 570                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
 571                                              SDTCVecEltisVT<1, f32>,
 572                                              SDTCisVT<2, i32>]> >;
 573 def X86vfpextRnd  : SDNode<"X86ISD::VFPEXT_RND",
 574                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>,
 575                                              SDTCVecEltisVT<1, f32>,
 576                                              SDTCisOpSmallerThanOp<1, 0>,
 577                                              SDTCisVT<2, i32>]>>;
 578 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND",
 579                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
 580                                              SDTCVecEltisVT<1, f64>,
 581                                              SDTCisOpSmallerThanOp<0, 1>,
 582                                              SDTCisVT<2, i32>]>>;
 583
 584 def X86cvt2mask   : SDNode<"X86ISD::CVT2MASK", SDTIntTruncOp>;
 585
 586 //===----------------------------------------------------------------------===//
 587 // SSE Complex Patterns
 588 //===----------------------------------------------------------------------===//
 589
 590 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 591 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 592 // forms.
 593 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
 594                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 595                                    SDNPWantRoot]>;
 596 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
 597                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 598                                    SDNPWantRoot]>;
 599
 600 def ssmem : Operand<v4f32> {
 601   let PrintMethod = "printf32mem";
 602   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
 603   let ParserMatchClass = X86Mem32AsmOperand;
 604   let OperandType = "OPERAND_MEMORY";
 605 }
 606 def sdmem : Operand<v2f64> {
 607   let PrintMethod = "printf64mem";
 608   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
 609   let ParserMatchClass = X86Mem64AsmOperand;
 610   let OperandType = "OPERAND_MEMORY";
 611 }
 612
 613 //===----------------------------------------------------------------------===//
 614 // SSE pattern fragments
 615 //===----------------------------------------------------------------------===//
 616
 617 // 128-bit load pattern fragments
 618 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 619 def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
 620 def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
 621 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 622
 623 // 256-bit load pattern fragments
 624 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 625 def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
 626 def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
 627 def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
 628
 629 // 512-bit load pattern fragments
 630 def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
 631 def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
 632 def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
 633
 634 // 128-/256-/512-bit extload pattern fragments
 635 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
 636 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
 637 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
 638
 639 // Like 'store', but always requires 128-bit vector alignment.
 640 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
 641                            (store node:$val, node:$ptr), [{
 642   return cast<StoreSDNode>(N)->getAlignment() >= 16;
 643 }]>;
 644
 645 // Like 'store', but always requires 256-bit vector alignment.
 646 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
 647                               (store node:$val, node:$ptr), [{
 648   return cast<StoreSDNode>(N)->getAlignment() >= 32;
 649 }]>;
 650
 651 // Like 'store', but always requires 512-bit vector alignment.
 652 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
 653                               (store node:$val, node:$ptr), [{
 654   return cast<StoreSDNode>(N)->getAlignment() >= 64;
 655 }]>;
 656
 657 // Like 'load', but always requires 128-bit vector alignment.
 658 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 659   return cast<LoadSDNode>(N)->getAlignment() >= 16;
 660 }]>;
 661
 662 // Like 'load', but always requires 256-bit vector alignment.
 663 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 664   return cast<LoadSDNode>(N)->getAlignment() >= 32;
 665 }]>;
 666
 667 // Like 'load', but always requires 512-bit vector alignment.
 668 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 669   return cast<LoadSDNode>(N)->getAlignment() >= 64;
 670 }]>;
 671
 672 // 128-bit aligned load pattern fragments
 673 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 674 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
 675                                (v4f32 (alignedload node:$ptr))>;
 676 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
 677                                (v2f64 (alignedload node:$ptr))>;
 678 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
 679                                (v2i64 (alignedload node:$ptr))>;
 680
 681 // 256-bit aligned load pattern fragments
 682 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 683 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
 684                                (v8f32 (alignedload256 node:$ptr))>;
 685 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
 686                                (v4f64 (alignedload256 node:$ptr))>;
 687 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
 688                                (v4i64 (alignedload256 node:$ptr))>;
 689
 690 // 512-bit aligned load pattern fragments
 691 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
 692                                 (v16f32 (alignedload512 node:$ptr))>;
 693 def alignedloadv8f64  : PatFrag<(ops node:$ptr),
 694                                 (v8f64  (alignedload512 node:$ptr))>;
 695 def alignedloadv8i64  : PatFrag<(ops node:$ptr),
 696                                 (v8i64  (alignedload512 node:$ptr))>;
 697
 698 // Like 'load', but uses special alignment checks suitable for use in
 699 // memory operands in most SSE instructions, which are required to
 700 // be naturally aligned on some targets but not on others.  If the subtarget
 701 // allows unaligned accesses, match any load, though this may require
 702 // setting a feature bit in the processor (on startup, for example).
 703 // Opteron 10h and later implement such a feature.
 704 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 705   return    Subtarget->hasSSEUnalignedMem()
 706          || cast<LoadSDNode>(N)->getAlignment() >= 16;
 707 }]>;
 708
 709 // 128-bit memop pattern fragments
 710 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 711 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 712 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 713 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 714
 715 // These are needed to match a scalar memop that is used in a vector-only
 716 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 717 // The memory operand is required to be a 128-bit load, so it must be converted
 718 // from a vector to a scalar.
 719 def memopfsf32_128 : PatFrag<(ops node:$ptr),
 720   (f32 (extractelt (memopv4f32 node:$ptr), (iPTR 0)))>;
 721 def memopfsf64_128 : PatFrag<(ops node:$ptr),
 722   (f64 (extractelt (memopv2f64 node:$ptr), (iPTR 0)))>;
 723
 724
 725 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
 726 // 16-byte boundary.
 727 // FIXME: 8 byte alignment for mmx reads is not required
 728 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 729   return cast<LoadSDNode>(N)->getAlignment() >= 8;
 730 }]>;
 731
 732 def memopmmx  : PatFrag<(ops node:$ptr), (x86mmx  (memop64 node:$ptr))>;
 733
 734 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 735   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 736   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 737     return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
 738             Mgt->getBasePtr().getValueType() == MVT::v4i32);
 739   return false;
 740 }]>;
 741
 742 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 743   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 744   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 745     return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
 746             Mgt->getBasePtr().getValueType() == MVT::v8i32);
 747   return false;
 748 }]>;
 749
 750 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 751   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 752   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 753     return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
 754             Mgt->getBasePtr().getValueType() == MVT::v2i64);
 755   return false;
 756 }]>;
 757 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 758   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 759   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 760     return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
 761             Mgt->getBasePtr().getValueType() == MVT::v4i64);
 762   return false;
 763 }]>;
 764 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 765   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 766   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 767     return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
 768             Mgt->getBasePtr().getValueType() == MVT::v8i64);
 769   return false;
 770 }]>;
 771 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 772   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 773   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 774     return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
 775             Mgt->getBasePtr().getValueType() == MVT::v16i32);
 776   return false;
 777 }]>;
 778
 779 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 780   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 781   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 782     return (Sc->getIndex().getValueType() == MVT::v2i64 ||
 783             Sc->getBasePtr().getValueType() == MVT::v2i64);
 784   return false;
 785 }]>;
 786
 787 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 788   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 789   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 790     return (Sc->getIndex().getValueType() == MVT::v4i32 ||
 791             Sc->getBasePtr().getValueType() == MVT::v4i32);
 792   return false;
 793 }]>;
 794
 795 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 796   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 797   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 798     return (Sc->getIndex().getValueType() == MVT::v4i64 ||
 799             Sc->getBasePtr().getValueType() == MVT::v4i64);
 800   return false;
 801 }]>;
 802
 803 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 804   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 805   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 806     return (Sc->getIndex().getValueType() == MVT::v8i32 ||
 807             Sc->getBasePtr().getValueType() == MVT::v8i32);
 808   return false;
 809 }]>;
 810
 811 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 812   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 813   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 814     return (Sc->getIndex().getValueType() == MVT::v8i64 ||
 815             Sc->getBasePtr().getValueType() == MVT::v8i64);
 816   return false;
 817 }]>;
 818 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 819   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 820   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 821     return (Sc->getIndex().getValueType() == MVT::v16i32 ||
 822             Sc->getBasePtr().getValueType() == MVT::v16i32);
 823   return false;
 824 }]>;
 825
 826 // 128-bit bitconvert pattern fragments
 827 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
 828 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 829 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 830 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 831 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 832 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 833
 834 // 256-bit bitconvert pattern fragments
 835 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
 836 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
 837 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
 838 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
 839 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
 840
 841 // 512-bit bitconvert pattern fragments
 842 def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>;
 843 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
 844 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
 845 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
 846 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
 847
 848 def vzmovl_v2i64 : PatFrag<(ops node:$src),
 849                            (bitconvert (v2i64 (X86vzmovl
 850                              (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
 851 def vzmovl_v4i32 : PatFrag<(ops node:$src),
 852                            (bitconvert (v4i32 (X86vzmovl
 853                              (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
 854
 855 def vzload_v2i64 : PatFrag<(ops node:$src),
 856                            (bitconvert (v2i64 (X86vzload node:$src)))>;
 857
 858
 859 def fp32imm0 : PatLeaf<(f32 fpimm), [{
 860   return N->isExactlyValue(+0.0);
 861 }]>;
 862
 863 def fp64imm0 : PatLeaf<(f64 fpimm), [{
 864   return N->isExactlyValue(+0.0);
 865 }]>;
 866
 867 def I8Imm : SDNodeXForm<imm, [{
 868   // Transformation function: get the low 8 bits.
 869   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 870 }]>;
 871
 872 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
 873 def FROUND_CURRENT : ImmLeaf<i32, [{
 874   return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
 875 }]>;
 876
 877 // BYTE_imm - Transform bit immediates into byte immediates.
 878 def BYTE_imm  : SDNodeXForm<imm, [{
 879   // Transformation function: imm >> 3
 880   return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
 881 }]>;
 882
 883 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
 884 // to VEXTRACTF128/VEXTRACTI128 imm.
 885 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
 886   return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
 887 }]>;
 888
 889 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
 890 // VINSERTF128/VINSERTI128 imm.
 891 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
 892   return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
 893 }]>;
 894
 895 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
 896 // to VEXTRACTF64x4 imm.
 897 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
 898   return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
 899 }]>;
 900
 901 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
 902 // VINSERTF64x4 imm.
 903 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
 904   return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
 905 }]>;
 906
 907 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
 908                                    (extract_subvector node:$bigvec,
 909                                                       node:$index), [{
 910   return X86::isVEXTRACT128Index(N);
 911 }], EXTRACT_get_vextract128_imm>;
 912
 913 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 914                                       node:$index),
 915                                  (insert_subvector node:$bigvec, node:$smallvec,
 916                                                    node:$index), [{
 917   return X86::isVINSERT128Index(N);
 918 }], INSERT_get_vinsert128_imm>;
 919
 920
 921 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
 922                                    (extract_subvector node:$bigvec,
 923                                                       node:$index), [{
 924   return X86::isVEXTRACT256Index(N);
 925 }], EXTRACT_get_vextract256_imm>;
 926
 927 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 928                                       node:$index),
 929                                  (insert_subvector node:$bigvec, node:$smallvec,
 930                                                    node:$index), [{
 931   return X86::isVINSERT256Index(N);
 932 }], INSERT_get_vinsert256_imm>;
 933
 934 def X86mload : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 935                          (masked_load node:$src1, node:$src2, node:$src3), [{
 936   return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
 937     cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
 938 }]>;
 939
 940 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 941                          (X86mload node:$src1, node:$src2, node:$src3), [{
 942   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 16;
 943 }]>;
 944
 945 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 946                          (X86mload node:$src1, node:$src2, node:$src3), [{
 947   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 32;
 948 }]>;
 949
 950 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 951                          (X86mload node:$src1, node:$src2, node:$src3), [{
 952   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 64;
 953 }]>;
 954
 955 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 956                          (masked_load node:$src1, node:$src2, node:$src3), [{
 957   return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
 958     cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
 959 }]>;
 960
 961 def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 962                          (masked_load node:$src1, node:$src2, node:$src3), [{
 963   return cast<MaskedLoadSDNode>(N)->isExpandingLoad();
 964 }]>;
 965
 966 // Masked store fragments.
 967 // X86mstore can't be implemented in core DAG files because some targets
 968 // do not support vector types (llvm-tblgen will fail).
 969 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 970                         (masked_store node:$src1, node:$src2, node:$src3), [{
 971   return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) &&
 972          (!cast<MaskedStoreSDNode>(N)->isCompressingStore());
 973 }]>;
 974
 975 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 976                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 977   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 16;
 978 }]>;
 979
 980 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 981                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 982   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 32;
 983 }]>;
 984
 985 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 986                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 987   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 64;
 988 }]>;
 989
 990 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 991                          (masked_store node:$src1, node:$src2, node:$src3), [{
 992   return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) &&
 993          (!cast<MaskedStoreSDNode>(N)->isCompressingStore());
 994 }]>;
 995
 996 def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 997                              (masked_store node:$src1, node:$src2, node:$src3), [{
 998     return cast<MaskedStoreSDNode>(N)->isCompressingStore();
 999 }]>;
1000
1001 // masked truncstore fragments
1002 // X86mtruncstore can't be implemented in core DAG files because some targets
1003 // doesn't support vector type ( llvm-tblgen will fail)
1004 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1005                              (masked_store node:$src1, node:$src2, node:$src3), [{
1006     return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
1007 }]>;
1008 def masked_truncstorevi8 :
1009   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1010           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1011   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1012 }]>;
1013 def masked_truncstorevi16 :
1014   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1015           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1016   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1017 }]>;
1018 def masked_truncstorevi32 :
1019   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1020           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1021   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1022 }]>;
1023
1024 def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES",  SDTStore,
1025                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1026
1027 def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS",  SDTStore,
1028                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1029
1030 def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES",  SDTMaskedStore,
1031                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1032
1033 def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS",  SDTMaskedStore,
1034                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1035
1036 def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr),
1037                                (X86TruncSStore node:$val, node:$ptr), [{
1038   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1039 }]>;
1040
1041 def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr),
1042                                (X86TruncUSStore node:$val, node:$ptr), [{
1043   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1044 }]>;
1045
1046 def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr),
1047                                (X86TruncSStore node:$val, node:$ptr), [{
1048   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1049 }]>;
1050
1051 def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr),
1052                                (X86TruncUSStore node:$val, node:$ptr), [{
1053   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1054 }]>;
1055
1056 def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr),
1057                                (X86TruncSStore node:$val, node:$ptr), [{
1058   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1059 }]>;
1060
1061 def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr),
1062                                (X86TruncUSStore node:$val, node:$ptr), [{
1063   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1064 }]>;
1065
1066 def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1067                      (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1068   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1069 }]>;
1070
1071 def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1072                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1073   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1074 }]>;
1075
1076 def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1077                                (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1078   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1079 }]>;
1080
1081 def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1082                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1083   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1084 }]>;
1085
1086 def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1087                                (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1088   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1089 }]>;
1090
1091 def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1092                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1093   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1094 }]>;
1095
1096 def assertzext_i1 :
1097   PatFrag<(ops node:$src), (assertzext node:$src), [{
1098     return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i1;
1099 }]>;