1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
31 //===----------------------------------------------------------------------===//
32 // SSE specific DAG Nodes.
33 //===----------------------------------------------------------------------===//
35 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
36 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
39 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
40 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
41 def X86fmins : SDNode<"X86ISD::FMINS", SDTFPBinOp>;
42 def X86fmaxs : SDNode<"X86ISD::FMAXS", SDTFPBinOp>;
44 // Commutative and Associative FMIN and FMAX.
45 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
46 [SDNPCommutative, SDNPAssociative]>;
47 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
48 [SDNPCommutative, SDNPAssociative]>;
50 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
51 [SDNPCommutative, SDNPAssociative]>;
52 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
53 [SDNPCommutative, SDNPAssociative]>;
54 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
55 [SDNPCommutative, SDNPAssociative]>;
56 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp>;
57 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
58 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
59 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
60 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
61 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
62 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
63 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
64 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
65 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
66 def X86pshufb : SDNode<"X86ISD::PSHUFB",
67 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
69 def X86psadbw : SDNode<"X86ISD::PSADBW",
70 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
71 SDTCVecEltisVT<1, i8>,
72 SDTCisSameSizeAs<0,1>,
73 SDTCisSameAs<1,2>]>, [SDNPCommutative]>;
74 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
75 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
76 SDTCVecEltisVT<1, i8>,
77 SDTCisSameSizeAs<0,1>,
78 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
79 def X86andnp : SDNode<"X86ISD::ANDNP",
80 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
82 def X86multishift : SDNode<"X86ISD::MULTISHIFT",
83 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
85 def X86pextrb : SDNode<"X86ISD::PEXTRB",
86 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
88 def X86pextrw : SDNode<"X86ISD::PEXTRW",
89 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
91 def X86pinsrb : SDNode<"X86ISD::PINSRB",
92 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
93 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
94 def X86pinsrw : SDNode<"X86ISD::PINSRW",
95 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
96 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
97 def X86insertps : SDNode<"X86ISD::INSERTPS",
98 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
99 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
100 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
101 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
103 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
104 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
106 def X86vzext : SDNode<"X86ISD::VZEXT",
107 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
108 SDTCisInt<0>, SDTCisInt<1>,
109 SDTCisOpSmallerThanOp<1, 0>]>>;
111 def X86vsext : SDNode<"X86ISD::VSEXT",
112 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
113 SDTCisInt<0>, SDTCisInt<1>,
114 SDTCisOpSmallerThanOp<1, 0>]>>;
116 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
117 SDTCisInt<0>, SDTCisInt<1>,
118 SDTCisOpSmallerThanOp<0, 1>]>;
120 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
121 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
122 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
124 def X86vfpext : SDNode<"X86ISD::VFPEXT",
125 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>,
126 SDTCVecEltisVT<1, f32>,
127 SDTCisSameSizeAs<0, 1>]>>;
128 def X86vfpround: SDNode<"X86ISD::VFPROUND",
129 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
130 SDTCVecEltisVT<1, f64>,
131 SDTCisSameSizeAs<0, 1>]>>;
133 def X86froundRnd: SDNode<"X86ISD::VFPROUNDS_RND",
134 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
136 SDTCVecEltisVT<2, f64>,
137 SDTCisSameSizeAs<0, 2>,
140 def X86fpextRnd : SDNode<"X86ISD::VFPEXTS_RND",
141 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f64>,
143 SDTCVecEltisVT<2, f32>,
144 SDTCisSameSizeAs<0, 2>,
147 def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
148 SDTCisVT<2, i8>, SDTCisInt<0>]>;
150 def X86vshldq : SDNode<"X86ISD::VSHLDQ", X86vshiftimm>;
151 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", X86vshiftimm>;
152 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
153 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
154 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
156 def X86IntCmpMask : SDTypeProfile<1, 2,
157 [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, SDTCisSameAs<1, 2>, SDTCisInt<1>,
158 SDTCisSameNumEltsAs<0, 1>]>;
159 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
160 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
163 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
164 SDTCisVec<1>, SDTCisSameAs<2, 1>,
165 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
166 def X86CmpMaskCCRound :
167 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
168 SDTCisVec<1>, SDTCisFP<1>, SDTCisSameAs<2, 1>,
169 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
171 def X86CmpMaskCCScalar :
172 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
175 def X86CmpMaskCCScalarRound :
176 SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
177 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
179 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
180 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
181 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
182 def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>;
183 def X86cmpmsRnd : SDNode<"X86ISD::FSETCCM_RND", X86CmpMaskCCScalarRound>;
185 def X86phminpos: SDNode<"X86ISD::PHMINPOS",
186 SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>;
188 def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
189 SDTCisVec<2>, SDTCisInt<0>,
192 def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>;
193 def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>;
194 def X86vsra : SDNode<"X86ISD::VSRA", X86vshiftuniform>;
196 def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
197 SDTCisSameAs<0,2>, SDTCisInt<0>]>;
199 def X86vsrav : SDNode<"X86ISD::VSRAV", X86vshiftvariable>;
201 def X86vshli : SDNode<"X86ISD::VSHLI", X86vshiftimm>;
202 def X86vsrli : SDNode<"X86ISD::VSRLI", X86vshiftimm>;
203 def X86vsrai : SDNode<"X86ISD::VSRAI", X86vshiftimm>;
205 def X86kshiftl : SDNode<"X86ISD::KSHIFTL",
206 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
209 def X86kshiftr : SDNode<"X86ISD::KSHIFTR",
210 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
214 def X86vrotli : SDNode<"X86ISD::VROTLI", X86vshiftimm>;
215 def X86vrotri : SDNode<"X86ISD::VROTRI", X86vshiftimm>;
217 def X86vpshl : SDNode<"X86ISD::VPSHL", X86vshiftvariable>;
218 def X86vpsha : SDNode<"X86ISD::VPSHA", X86vshiftvariable>;
220 def X86vpcom : SDNode<"X86ISD::VPCOM",
221 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
223 SDTCisVT<3, i8>, SDTCisInt<0>]>>;
224 def X86vpcomu : SDNode<"X86ISD::VPCOMU",
225 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
227 SDTCisVT<3, i8>, SDTCisInt<0>]>>;
228 def X86vpermil2 : SDNode<"X86ISD::VPERMIL2",
229 SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
231 SDTCisSameSizeAs<0,3>,
232 SDTCisSameNumEltsAs<0, 3>,
233 SDTCisFP<0>, SDTCisInt<3>,
235 def X86vpperm : SDNode<"X86ISD::VPPERM",
236 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
237 SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>;
239 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
241 SDTCisSameAs<2, 1>]>;
243 def SDTX86Testm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
244 SDTCisSameAs<2, 1>, SDTCVecEltisVT<0, i1>,
245 SDTCisSameNumEltsAs<0, 1>]>;
247 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp, [SDNPCommutative]>;
248 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
249 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp, [SDNPCommutative]>;
250 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
251 def X86mulhrs : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>;
252 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>;
253 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
254 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
255 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
256 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
257 def X86testm : SDNode<"X86ISD::TESTM", SDTX86Testm, [SDNPCommutative]>;
258 def X86testnm : SDNode<"X86ISD::TESTNM", SDTX86Testm, [SDNPCommutative]>;
260 def X86movmsk : SDNode<"X86ISD::MOVMSK",
261 SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>;
263 def X86selects : SDNode<"X86ISD::SELECTS",
264 SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>,
266 SDTCisSameAs<2, 3>]>>;
268 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
269 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
270 SDTCVecEltisVT<1, i32>,
271 SDTCisSameSizeAs<0,1>,
274 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
275 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
276 SDTCVecEltisVT<1, i32>,
277 SDTCisSameSizeAs<0,1>,
281 def X86extrqi : SDNode<"X86ISD::EXTRQI",
282 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
283 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
284 def X86insertqi : SDNode<"X86ISD::INSERTQI",
285 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
286 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
289 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
290 // translated into one of the target nodes below during lowering.
291 // Note: this is a work in progress...
292 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
293 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
296 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
297 SDTCisSameSizeAs<0,2>,
298 SDTCisSameNumEltsAs<0,2>,
299 SDTCisFP<0>, SDTCisInt<2>]>;
300 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
301 SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
302 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
303 SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
304 def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
308 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisVec<0>,
313 def SDTFPTernaryOpImmRound: SDTypeProfile<1, 5, [SDTCisFP<0>, SDTCisSameAs<0,1>,
316 SDTCisSameSizeAs<0, 3>,
317 SDTCisSameNumEltsAs<0, 3>,
320 def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisVec<0>,
323 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
328 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
329 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
330 SDTCisInt<0>, SDTCisInt<1>]>;
332 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
333 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
335 def SDTTernlog : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>,
336 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>,
337 SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>;
339 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
340 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>;
342 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
343 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>;
345 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
346 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>,
347 SDTCisFP<0>, SDTCisVT<4, i32>]>;
349 def X86PAlignr : SDNode<"X86ISD::PALIGNR",
350 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>,
354 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
356 def X86VShld : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>;
357 def X86VShrd : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>;
358 def X86VShldv : SDNode<"X86ISD::VSHLDV",
359 SDTypeProfile<1, 3, [SDTCisVec<0>,
362 SDTCisSameAs<0,3>]>>;
363 def X86VShrdv : SDNode<"X86ISD::VSHRDV",
364 SDTypeProfile<1, 3, [SDTCisVec<0>,
367 SDTCisSameAs<0,3>]>>;
369 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
371 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
372 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
373 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
375 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
376 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
378 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
379 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
380 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
382 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
383 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
385 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
386 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
387 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
389 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
390 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
392 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>,
393 SDTCisVec<1>, SDTCisInt<1>,
394 SDTCisSameSizeAs<0,1>,
396 SDTCisOpSmallerThanOp<0, 1>]>;
397 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
398 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
400 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
401 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
403 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW",
404 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
405 SDTCVecEltisVT<1, i8>,
406 SDTCisSameSizeAs<0,1>,
407 SDTCisSameAs<1,2>]>>;
408 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD",
409 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>,
410 SDTCVecEltisVT<1, i16>,
411 SDTCisSameSizeAs<0,1>,
415 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
416 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
417 def X86VPermv : SDNode<"X86ISD::VPERMV",
418 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>,
419 SDTCisSameNumEltsAs<0,1>,
420 SDTCisSameSizeAs<0,1>,
421 SDTCisSameAs<0,2>]>>;
422 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
423 def X86VPermt2 : SDNode<"X86ISD::VPERMV3",
424 SDTypeProfile<1, 3, [SDTCisVec<0>,
425 SDTCisSameAs<0,1>, SDTCisInt<2>,
426 SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
427 SDTCisSameSizeAs<0,2>,
428 SDTCisSameAs<0,3>]>, []>;
430 // Even though the index operand should be integer, we need to make it match the
431 // destination type so that we can pattern match the masked version where the
432 // index is also the passthru operand.
433 def X86VPermi2X : SDNode<"X86ISD::VPERMIV3",
434 SDTypeProfile<1, 3, [SDTCisVec<0>,
437 SDTCisSameAs<0,3>]>, []>;
439 def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
441 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
443 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImmRound>;
444 def X86VFixupimmScalar : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImmRound>;
445 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImm>;
446 def X86VRangeRnd : SDNode<"X86ISD::VRANGE_RND", SDTFPBinOpImmRound>;
447 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImm>;
448 def X86VReduceRnd : SDNode<"X86ISD::VREDUCE_RND", SDTFPUnaryOpImmRound>;
449 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImm>;
450 def X86VRndScaleRnd: SDNode<"X86ISD::VRNDSCALE_RND", SDTFPUnaryOpImmRound>;
451 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImm>;
452 def X86VGetMantRnd : SDNode<"X86ISD::VGETMANT_RND", SDTFPUnaryOpImmRound>;
453 def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
454 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
456 SDTCisSameNumEltsAs<0,1>,
457 SDTCisVT<2, i32>]>, []>;
458 def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS",
459 SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>,
460 SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;
462 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
463 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
464 SDTCisSubVecOfVec<1, 0>]>, []>;
466 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
467 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
468 def X86kextract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
469 SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
470 SDTCVecEltisVT<1, i1>,
473 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
475 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
477 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
478 def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>;
479 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
480 def X86fsubRnds : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>;
481 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
482 def X86fmulRnds : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>;
483 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
484 def X86fdivRnds : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>;
485 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
486 def X86fmaxRnds : SDNode<"X86ISD::FMAXS_RND", SDTFPBinOpRound>;
487 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
488 def X86fminRnds : SDNode<"X86ISD::FMINS_RND", SDTFPBinOpRound>;
489 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
490 def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOpRound>;
491 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
492 def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>;
493 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
494 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXPS_RND", SDTFPBinOpRound>;
496 def X86Fmadd : SDNode<"ISD::FMA", SDTFPTernaryOp, [SDNPCommutative]>;
497 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>;
498 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
499 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
500 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFPTernaryOp, [SDNPCommutative]>;
501 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFPTernaryOp, [SDNPCommutative]>;
503 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound, [SDNPCommutative]>;
504 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound, [SDNPCommutative]>;
505 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound, [SDNPCommutative]>;
506 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound, [SDNPCommutative]>;
507 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>;
508 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>;
510 // Scalar FMA4 intrinsics which zero the non-scalar bits.
511 def X86Fmadd4s : SDNode<"X86ISD::FMADD4S", SDTFPTernaryOp, [SDNPCommutative]>;
512 def X86Fnmadd4s : SDNode<"X86ISD::FNMADD4S", SDTFPTernaryOp, [SDNPCommutative]>;
513 def X86Fmsub4s : SDNode<"X86ISD::FMSUB4S", SDTFPTernaryOp, [SDNPCommutative]>;
514 def X86Fnmsub4s : SDNode<"X86ISD::FNMSUB4S", SDTFPTernaryOp, [SDNPCommutative]>;
516 // Scalar FMA intrinsics with passthru bits in operand 1.
517 def X86Fmadds1 : SDNode<"X86ISD::FMADDS1", SDTFPTernaryOp>;
518 def X86Fnmadds1 : SDNode<"X86ISD::FNMADDS1", SDTFPTernaryOp>;
519 def X86Fmsubs1 : SDNode<"X86ISD::FMSUBS1", SDTFPTernaryOp>;
520 def X86Fnmsubs1 : SDNode<"X86ISD::FNMSUBS1", SDTFPTernaryOp>;
522 // Scalar FMA intrinsics with passthru bits in operand 1.
523 def X86FmaddRnds1 : SDNode<"X86ISD::FMADDS1_RND", SDTFmaRound>;
524 def X86FnmaddRnds1 : SDNode<"X86ISD::FNMADDS1_RND", SDTFmaRound>;
525 def X86FmsubRnds1 : SDNode<"X86ISD::FMSUBS1_RND", SDTFmaRound>;
526 def X86FnmsubRnds1 : SDNode<"X86ISD::FNMSUBS1_RND", SDTFmaRound>;
528 def X86Fmadds3 : SDNode<"X86ISD::FMADDS3", SDTFPTernaryOp, [SDNPCommutative]>;
529 def X86Fnmadds3 : SDNode<"X86ISD::FNMADDS3", SDTFPTernaryOp, [SDNPCommutative]>;
530 def X86Fmsubs3 : SDNode<"X86ISD::FMSUBS3", SDTFPTernaryOp, [SDNPCommutative]>;
531 def X86Fnmsubs3 : SDNode<"X86ISD::FNMSUBS3", SDTFPTernaryOp, [SDNPCommutative]>;
533 // Scalar FMA intrinsics with passthru bits in operand 3.
534 def X86FmaddRnds3 : SDNode<"X86ISD::FMADDS3_RND", SDTFmaRound, [SDNPCommutative]>;
535 def X86FnmaddRnds3 : SDNode<"X86ISD::FNMADDS3_RND", SDTFmaRound, [SDNPCommutative]>;
536 def X86FmsubRnds3 : SDNode<"X86ISD::FMSUBS3_RND", SDTFmaRound, [SDNPCommutative]>;
537 def X86FnmsubRnds3 : SDNode<"X86ISD::FNMSUBS3_RND", SDTFmaRound, [SDNPCommutative]>;
539 def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>,
540 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
541 def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>;
542 def x86vpmadd52h : SDNode<"X86ISD::VPMADD52H", SDTIFma, [SDNPCommutative]>;
544 def X86rsqrt14 : SDNode<"X86ISD::RSQRT14", SDTFPUnaryOp>;
545 def X86rcp14 : SDNode<"X86ISD::RCP14", SDTFPUnaryOp>;
548 def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
549 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
550 def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>;
551 def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>;
552 def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>;
553 def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>;
555 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOpRound>;
556 def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOpRound>;
557 def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOpRound>;
559 def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>;
560 def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>;
561 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOpRound>;
562 def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOpRound>;
563 def X86Ranges : SDNode<"X86ISD::VRANGES", SDTFPBinOpImm>;
564 def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>;
565 def X86Reduces : SDNode<"X86ISD::VREDUCES", SDTFPBinOpImm>;
566 def X86GetMants : SDNode<"X86ISD::VGETMANTS", SDTFPBinOpImm>;
567 def X86RangesRnd : SDNode<"X86ISD::VRANGES_RND", SDTFPBinOpImmRound>;
568 def X86RndScalesRnd : SDNode<"X86ISD::VRNDSCALES_RND", SDTFPBinOpImmRound>;
569 def X86ReducesRnd : SDNode<"X86ISD::VREDUCES_RND", SDTFPBinOpImmRound>;
570 def X86GetMantsRnd : SDNode<"X86ISD::VGETMANTS_RND", SDTFPBinOpImmRound>;
572 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
573 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
575 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
576 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
577 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
580 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
581 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
583 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
584 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
585 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
586 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
589 def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB",
590 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
592 SDTCVecEltisVT<0,i1>,
593 SDTCisSameNumEltsAs<0,1>]>>;
595 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
596 SDTCisSameAs<0,1>, SDTCisInt<2>,
599 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
600 SDTCisInt<0>, SDTCisFP<1>]>;
601 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
602 SDTCisInt<0>, SDTCisFP<1>,
604 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
605 SDTCisVec<1>, SDTCisVT<2, i32>]>;
607 def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
608 SDTCisFP<0>, SDTCisInt<1>]>;
609 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
610 SDTCisFP<0>, SDTCisInt<1>,
614 def X86SintToFpRnd : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND", SDTintToFPRound>;
615 def X86UintToFpRnd : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND", SDTintToFPRound>;
617 def X86cvtts2IntRnd : SDNode<"X86ISD::CVTTS2SI_RND", SDTSFloatToIntRnd>;
618 def X86cvtts2UIntRnd : SDNode<"X86ISD::CVTTS2UI_RND", SDTSFloatToIntRnd>;
620 def X86cvts2si : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>;
621 def X86cvts2usi : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>;
623 // Vector with rounding mode
625 // cvtt fp-to-int staff
626 def X86cvttp2siRnd : SDNode<"X86ISD::CVTTP2SI_RND", SDTFloatToIntRnd>;
627 def X86cvttp2uiRnd : SDNode<"X86ISD::CVTTP2UI_RND", SDTFloatToIntRnd>;
629 def X86VSintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTVintToFPRound>;
630 def X86VUintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTVintToFPRound>;
632 // cvt fp-to-int staff
633 def X86cvtp2IntRnd : SDNode<"X86ISD::CVTP2SI_RND", SDTFloatToIntRnd>;
634 def X86cvtp2UIntRnd : SDNode<"X86ISD::CVTP2UI_RND", SDTFloatToIntRnd>;
636 // Vector without rounding mode
638 // cvtt fp-to-int staff
639 def X86cvttp2si : SDNode<"X86ISD::CVTTP2SI", SDTFloatToInt>;
640 def X86cvttp2ui : SDNode<"X86ISD::CVTTP2UI", SDTFloatToInt>;
642 def X86VSintToFP : SDNode<"X86ISD::CVTSI2P", SDTVintToFP>;
643 def X86VUintToFP : SDNode<"X86ISD::CVTUI2P", SDTVintToFP>;
645 // cvt int-to-fp staff
646 def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>;
647 def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>;
650 def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS",
651 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
652 SDTCVecEltisVT<1, i16>]> >;
654 def X86cvtph2psRnd : SDNode<"X86ISD::CVTPH2PS_RND",
655 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
656 SDTCVecEltisVT<1, i16>,
657 SDTCisVT<2, i32>]> >;
659 def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH",
660 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
661 SDTCVecEltisVT<1, f32>,
662 SDTCisVT<2, i32>]> >;
663 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT_RND",
664 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>,
665 SDTCVecEltisVT<1, f32>,
666 SDTCisOpSmallerThanOp<1, 0>,
668 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND",
669 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
670 SDTCVecEltisVT<1, f64>,
671 SDTCisOpSmallerThanOp<0, 1>,
674 def X86cvt2mask : SDNode<"X86ISD::CVT2MASK", SDTIntTruncOp>;
676 // galois field arithmetic
677 def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>;
678 def X86GF2P8affineqb : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>;
679 def X86GF2P8mulb : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>;
681 //===----------------------------------------------------------------------===//
682 // SSE Complex Patterns
683 //===----------------------------------------------------------------------===//
685 // These are 'extloads' from a scalar to the low element of a vector, zeroing
686 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
688 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
689 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
691 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
692 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
695 def ssmem : Operand<v4f32> {
696 let PrintMethod = "printf32mem";
697 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
698 let ParserMatchClass = X86Mem32AsmOperand;
699 let OperandType = "OPERAND_MEMORY";
701 def sdmem : Operand<v2f64> {
702 let PrintMethod = "printf64mem";
703 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
704 let ParserMatchClass = X86Mem64AsmOperand;
705 let OperandType = "OPERAND_MEMORY";
708 //===----------------------------------------------------------------------===//
709 // SSE pattern fragments
710 //===----------------------------------------------------------------------===//
712 // Vector load wrappers to prevent folding of non-temporal aligned loads on
713 // supporting targets.
714 def vecload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
715 return !useNonTemporalLoad(cast<LoadSDNode>(N));
718 // 128-bit load pattern fragments
719 // NOTE: all 128-bit integer vector loads are promoted to v2i64
720 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (vecload node:$ptr))>;
721 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (vecload node:$ptr))>;
722 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (vecload node:$ptr))>;
724 // 256-bit load pattern fragments
725 // NOTE: all 256-bit integer vector loads are promoted to v4i64
726 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (vecload node:$ptr))>;
727 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (vecload node:$ptr))>;
728 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (vecload node:$ptr))>;
730 // 512-bit load pattern fragments
731 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (vecload node:$ptr))>;
732 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (vecload node:$ptr))>;
733 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (vecload node:$ptr))>;
735 // 128-/256-/512-bit extload pattern fragments
736 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
737 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
738 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
740 // Like 'store', but always requires vector size alignment.
741 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
742 (store node:$val, node:$ptr), [{
743 auto *St = cast<StoreSDNode>(N);
744 return St->getAlignment() >= St->getMemoryVT().getStoreSize();
747 // Like 'load', but always requires 128-bit vector alignment.
748 def alignedvecload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
749 auto *Ld = cast<LoadSDNode>(N);
750 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize() &&
751 !useNonTemporalLoad(cast<LoadSDNode>(N));
754 // 128-bit aligned load pattern fragments
755 // NOTE: all 128-bit integer vector loads are promoted to v2i64
756 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
757 (v4f32 (alignedvecload node:$ptr))>;
758 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
759 (v2f64 (alignedvecload node:$ptr))>;
760 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
761 (v2i64 (alignedvecload node:$ptr))>;
763 // 256-bit aligned load pattern fragments
764 // NOTE: all 256-bit integer vector loads are promoted to v4i64
765 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
766 (v8f32 (alignedvecload node:$ptr))>;
767 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
768 (v4f64 (alignedvecload node:$ptr))>;
769 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
770 (v4i64 (alignedvecload node:$ptr))>;
772 // 512-bit aligned load pattern fragments
773 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
774 (v16f32 (alignedvecload node:$ptr))>;
775 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
776 (v8f64 (alignedvecload node:$ptr))>;
777 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
778 (v8i64 (alignedvecload node:$ptr))>;
780 // Like 'vecload', but uses special alignment checks suitable for use in
781 // memory operands in most SSE instructions, which are required to
782 // be naturally aligned on some targets but not on others. If the subtarget
783 // allows unaligned accesses, match any load, though this may require
784 // setting a feature bit in the processor (on startup, for example).
785 // Opteron 10h and later implement such a feature.
786 def memop : PatFrag<(ops node:$ptr), (vecload node:$ptr), [{
787 auto *Ld = cast<LoadSDNode>(N);
788 return Subtarget->hasSSEUnalignedMem() ||
789 Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
792 // 128-bit memop pattern fragments
793 // NOTE: all 128-bit integer vector loads are promoted to v2i64
794 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
795 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
796 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
798 def X86masked_gather : SDNode<"X86ISD::MGATHER",
799 SDTypeProfile<2, 3, [SDTCisVec<0>,
800 SDTCisVec<1>, SDTCisInt<1>,
804 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
806 def X86masked_scatter : SDNode<"X86ISD::MSCATTER",
807 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
809 SDTCVecEltisVT<0, i1>,
811 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
813 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
814 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
815 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
816 return Mgt->getIndex().getValueType() == MVT::v4i32;
819 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
820 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
821 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
822 return Mgt->getIndex().getValueType() == MVT::v8i32;
825 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
826 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
827 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
828 return Mgt->getIndex().getValueType() == MVT::v2i64;
830 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
831 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
832 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
833 return Mgt->getIndex().getValueType() == MVT::v4i64;
835 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
836 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
837 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
838 return Mgt->getIndex().getValueType() == MVT::v8i64;
840 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
841 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
842 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
843 return Mgt->getIndex().getValueType() == MVT::v16i32;
846 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
847 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
848 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
849 return Sc->getIndex().getValueType() == MVT::v2i64;
852 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
853 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
854 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
855 return Sc->getIndex().getValueType() == MVT::v4i32;
858 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
859 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
860 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
861 return Sc->getIndex().getValueType() == MVT::v4i64;
864 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
865 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
866 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
867 return Sc->getIndex().getValueType() == MVT::v8i32;
870 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
871 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
872 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
873 return Sc->getIndex().getValueType() == MVT::v8i64;
875 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
876 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
877 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
878 return Sc->getIndex().getValueType() == MVT::v16i32;
881 // 128-bit bitconvert pattern fragments
882 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
883 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
884 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
885 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
886 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
887 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
889 // 256-bit bitconvert pattern fragments
890 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
891 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
892 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
893 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
894 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
896 // 512-bit bitconvert pattern fragments
897 def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>;
898 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
899 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
900 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
901 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
903 def vzmovl_v2i64 : PatFrag<(ops node:$src),
904 (bitconvert (v2i64 (X86vzmovl
905 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
906 def vzmovl_v4i32 : PatFrag<(ops node:$src),
907 (bitconvert (v4i32 (X86vzmovl
908 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
910 def vzload_v2i64 : PatFrag<(ops node:$src),
911 (bitconvert (v2i64 (X86vzload node:$src)))>;
914 def fp32imm0 : PatLeaf<(f32 fpimm), [{
915 return N->isExactlyValue(+0.0);
918 def fp64imm0 : PatLeaf<(f64 fpimm), [{
919 return N->isExactlyValue(+0.0);
922 def I8Imm : SDNodeXForm<imm, [{
923 // Transformation function: get the low 8 bits.
924 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
927 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
928 def FROUND_CURRENT : ImmLeaf<i32, [{
929 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
932 // BYTE_imm - Transform bit immediates into byte immediates.
933 def BYTE_imm : SDNodeXForm<imm, [{
934 // Transformation function: imm >> 3
935 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
938 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
939 // to VEXTRACTF128/VEXTRACTI128 imm.
940 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
941 return getExtractVEXTRACTImmediate(N, 128, SDLoc(N));
944 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
945 // VINSERTF128/VINSERTI128 imm.
946 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
947 return getInsertVINSERTImmediate(N, 128, SDLoc(N));
950 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
951 // to VEXTRACTF64x4 imm.
952 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
953 return getExtractVEXTRACTImmediate(N, 256, SDLoc(N));
956 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
958 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
959 return getInsertVINSERTImmediate(N, 256, SDLoc(N));
962 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
963 (extract_subvector node:$bigvec,
965 EXTRACT_get_vextract128_imm>;
967 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
969 (insert_subvector node:$bigvec, node:$smallvec,
971 INSERT_get_vinsert128_imm>;
973 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
974 (extract_subvector node:$bigvec,
976 EXTRACT_get_vextract256_imm>;
978 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
980 (insert_subvector node:$bigvec, node:$smallvec,
982 INSERT_get_vinsert256_imm>;
984 def X86mload : PatFrag<(ops node:$src1, node:$src2, node:$src3),
985 (masked_load node:$src1, node:$src2, node:$src3), [{
986 return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
987 cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
990 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
991 (X86mload node:$src1, node:$src2, node:$src3), [{
992 return cast<MaskedLoadSDNode>(N)->getAlignment() >= 16;
995 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
996 (X86mload node:$src1, node:$src2, node:$src3), [{
997 return cast<MaskedLoadSDNode>(N)->getAlignment() >= 32;
1000 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1001 (X86mload node:$src1, node:$src2, node:$src3), [{
1002 return cast<MaskedLoadSDNode>(N)->getAlignment() >= 64;
1005 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1006 (masked_load node:$src1, node:$src2, node:$src3), [{
1007 return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
1008 cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
1011 def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1012 (masked_load node:$src1, node:$src2, node:$src3), [{
1013 return cast<MaskedLoadSDNode>(N)->isExpandingLoad();
1016 // Masked store fragments.
1017 // X86mstore can't be implemented in core DAG files because some targets
1018 // do not support vector types (llvm-tblgen will fail).
1019 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1020 (masked_store node:$src1, node:$src2, node:$src3), [{
1021 return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) &&
1022 (!cast<MaskedStoreSDNode>(N)->isCompressingStore());
1025 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1026 (X86mstore node:$src1, node:$src2, node:$src3), [{
1027 return cast<MaskedStoreSDNode>(N)->getAlignment() >= 16;
1030 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1031 (X86mstore node:$src1, node:$src2, node:$src3), [{
1032 return cast<MaskedStoreSDNode>(N)->getAlignment() >= 32;
1035 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1036 (X86mstore node:$src1, node:$src2, node:$src3), [{
1037 return cast<MaskedStoreSDNode>(N)->getAlignment() >= 64;
1040 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1041 (masked_store node:$src1, node:$src2, node:$src3), [{
1042 return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) &&
1043 (!cast<MaskedStoreSDNode>(N)->isCompressingStore());
1046 def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1047 (masked_store node:$src1, node:$src2, node:$src3), [{
1048 return cast<MaskedStoreSDNode>(N)->isCompressingStore();
1051 // masked truncstore fragments
1052 // X86mtruncstore can't be implemented in core DAG files because some targets
1053 // doesn't support vector type ( llvm-tblgen will fail)
1054 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1055 (masked_store node:$src1, node:$src2, node:$src3), [{
1056 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
1058 def masked_truncstorevi8 :
1059 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1060 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1061 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1063 def masked_truncstorevi16 :
1064 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1065 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1066 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1068 def masked_truncstorevi32 :
1069 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1070 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1071 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1074 def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES", SDTStore,
1075 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1077 def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS", SDTStore,
1078 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1080 def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES", SDTMaskedStore,
1081 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1083 def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS", SDTMaskedStore,
1084 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1086 def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr),
1087 (X86TruncSStore node:$val, node:$ptr), [{
1088 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1091 def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr),
1092 (X86TruncUSStore node:$val, node:$ptr), [{
1093 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1096 def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr),
1097 (X86TruncSStore node:$val, node:$ptr), [{
1098 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1101 def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr),
1102 (X86TruncUSStore node:$val, node:$ptr), [{
1103 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1106 def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr),
1107 (X86TruncSStore node:$val, node:$ptr), [{
1108 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1111 def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr),
1112 (X86TruncUSStore node:$val, node:$ptr), [{
1113 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1116 def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1117 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1118 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1121 def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1122 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1123 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1126 def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1127 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1128 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1131 def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1132 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1133 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1136 def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1137 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1138 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1141 def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1142 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1143 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;