1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
17 #include "MCTargetDesc/X86BaseInfo.h"
18 #include "X86InstrFMA3Info.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/Target/TargetInstrInfo.h"
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
27 class MachineInstrBuilder;
28 class X86RegisterInfo;
32 // X86 specific condition code. These correspond to X86_*_COND in
33 // X86InstrInfo.td. They must be kept in synch.
51 LAST_VALID_COND = COND_S,
53 // Artificial condition codes. These are used by AnalyzeBranch
54 // to indicate a block terminated with two conditional branches that together
55 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
56 // which can't be represented on x86 with a single condition. These
57 // are never used in MachineInstrs and are inverses of one another.
64 // Turn condition code into conditional branch opcode.
65 unsigned GetCondBranchFromCond(CondCode CC);
67 /// \brief Return a set opcode for the given condition and whether it has
69 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
71 /// \brief Return a cmov opcode for the given condition, register size in
72 /// bytes, and operand type.
73 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
74 bool HasMemoryOperand = false);
76 // Turn CMov opcode into condition code.
77 CondCode getCondFromCMovOpc(unsigned Opc);
79 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
80 /// e.g. turning COND_E to COND_NE.
81 CondCode GetOppositeBranchCondition(CondCode CC);
82 } // end namespace X86;
85 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
86 /// a reference to a stub for a global, not the global itself.
87 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
89 case X86II::MO_DLLIMPORT: // dllimport stub.
90 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
91 case X86II::MO_GOT: // normal GOT reference.
92 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
93 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
100 /// isGlobalRelativeToPICBase - Return true if the specified global value
101 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
102 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
103 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
104 switch (TargetFlag) {
105 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
106 case X86II::MO_GOT: // isPICStyleGOT: other global.
107 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
108 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
109 case X86II::MO_TLVP: // ??? Pretty sure..
116 inline static bool isScale(const MachineOperand &MO) {
118 (MO.getImm() == 1 || MO.getImm() == 2 ||
119 MO.getImm() == 4 || MO.getImm() == 8);
122 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
123 if (MI.getOperand(Op).isFI())
125 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
126 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
127 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
128 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
129 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
130 MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
131 MI.getOperand(Op + X86::AddrDisp).isCPI() ||
132 MI.getOperand(Op + X86::AddrDisp).isJTI());
135 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
136 if (MI.getOperand(Op).isFI())
138 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
139 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
142 class X86InstrInfo final : public X86GenInstrInfo {
143 X86Subtarget &Subtarget;
144 const X86RegisterInfo RI;
146 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
147 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
149 typedef DenseMap<unsigned,
150 std::pair<uint16_t, uint16_t> > RegOp2MemOpTableType;
151 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
152 RegOp2MemOpTableType RegOp2MemOpTable0;
153 RegOp2MemOpTableType RegOp2MemOpTable1;
154 RegOp2MemOpTableType RegOp2MemOpTable2;
155 RegOp2MemOpTableType RegOp2MemOpTable3;
156 RegOp2MemOpTableType RegOp2MemOpTable4;
158 /// MemOp2RegOpTable - Load / store unfolding opcode map.
160 typedef DenseMap<unsigned,
161 std::pair<uint16_t, uint16_t> > MemOp2RegOpTableType;
162 MemOp2RegOpTableType MemOp2RegOpTable;
164 static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
165 MemOp2RegOpTableType &M2RTable,
166 uint16_t RegOp, uint16_t MemOp, uint16_t Flags);
168 virtual void anchor();
170 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
171 MachineBasicBlock *&FBB,
172 SmallVectorImpl<MachineOperand> &Cond,
173 SmallVectorImpl<MachineInstr *> &CondBranches,
174 bool AllowModify) const;
177 explicit X86InstrInfo(X86Subtarget &STI);
179 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
180 /// such, whenever a client has an instance of instruction info, it should
181 /// always be able to get register info as well (through this method).
183 const X86RegisterInfo &getRegisterInfo() const { return RI; }
185 /// Returns the stack pointer adjustment that happens inside the frame
186 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
187 int64_t getFrameAdjustment(const MachineInstr &I) const {
188 assert(isFrameInstr(I));
189 return I.getOperand(1).getImm();
192 /// Sets the stack pointer adjustment made inside the frame made up by this
194 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
195 assert(isFrameInstr(I));
196 I.getOperand(1).setImm(V);
199 /// getSPAdjust - This returns the stack pointer adjustment made by
200 /// this instruction. For x86, we need to handle more complex call
201 /// sequences involving PUSHes.
202 int getSPAdjust(const MachineInstr &MI) const override;
204 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
205 /// extension instruction. That is, it's like a copy where it's legal for the
206 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
207 /// true, then it's expected the pre-extension value is available as a subreg
208 /// of the result register. This also returns the sub-register index in
210 bool isCoalescableExtInstr(const MachineInstr &MI,
211 unsigned &SrcReg, unsigned &DstReg,
212 unsigned &SubIdx) const override;
214 unsigned isLoadFromStackSlot(const MachineInstr &MI,
215 int &FrameIndex) const override;
216 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
217 /// stack locations as well. This uses a heuristic so it isn't
218 /// reliable for correctness.
219 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
220 int &FrameIndex) const override;
222 unsigned isStoreToStackSlot(const MachineInstr &MI,
223 int &FrameIndex) const override;
224 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
225 /// stack locations as well. This uses a heuristic so it isn't
226 /// reliable for correctness.
227 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
228 int &FrameIndex) const override;
230 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
231 AliasAnalysis *AA) const override;
232 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
233 unsigned DestReg, unsigned SubIdx,
234 const MachineInstr &Orig,
235 const TargetRegisterInfo &TRI) const override;
237 /// Given an operand within a MachineInstr, insert preceding code to put it
238 /// into the right format for a particular kind of LEA instruction. This may
239 /// involve using an appropriate super-register instead (with an implicit use
240 /// of the original) or creating a new virtual register and inserting COPY
241 /// instructions to get the data into the right class.
243 /// Reference parameters are set to indicate how caller should add this
244 /// operand to the LEA instruction.
245 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
246 unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
247 bool &isKill, bool &isUndef,
248 MachineOperand &ImplicitOp, LiveVariables *LV) const;
250 /// convertToThreeAddress - This method must be implemented by targets that
251 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
252 /// may be able to convert a two-address instruction into a true
253 /// three-address instruction on demand. This allows the X86 target (for
254 /// example) to convert ADD and SHL instructions into LEA instructions if they
255 /// would require register copies due to two-addressness.
257 /// This method returns a null pointer if the transformation cannot be
258 /// performed, otherwise it returns the new instruction.
260 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
262 LiveVariables *LV) const override;
264 /// Returns true iff the routine could find two commutable operands in the
265 /// given machine instruction.
266 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
267 /// input values can be re-defined in this method only if the input values
268 /// are not pre-defined, which is designated by the special value
269 /// 'CommuteAnyOperandIndex' assigned to it.
270 /// If both of indices are pre-defined and refer to some operands, then the
271 /// method simply returns true if the corresponding operands are commutable
272 /// and returns false otherwise.
274 /// For example, calling this method this way:
275 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
276 /// findCommutedOpIndices(MI, Op1, Op2);
277 /// can be interpreted as a query asking to find an operand that would be
278 /// commutable with the operand#1.
279 bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
280 unsigned &SrcOpIdx2) const override;
282 /// Returns true if the routine could find two commutable operands
283 /// in the given FMA instruction \p MI. Otherwise, returns false.
285 /// \p SrcOpIdx1 and \p SrcOpIdx2 are INPUT and OUTPUT arguments.
286 /// The output indices of the commuted operands are returned in these
287 /// arguments. Also, the input values of these arguments may be preset either
288 /// to indices of operands that must be commuted or be equal to a special
289 /// value 'CommuteAnyOperandIndex' which means that the corresponding
290 /// operand index is not set and this method is free to pick any of
291 /// available commutable operands.
292 /// The parameter \p FMA3Group keeps the reference to the group of relative
293 /// FMA3 opcodes including register/memory forms of 132/213/231 opcodes.
295 /// For example, calling this method this way:
296 /// unsigned Idx1 = 1, Idx2 = CommuteAnyOperandIndex;
297 /// findFMA3CommutedOpIndices(MI, Idx1, Idx2, FMA3Group);
298 /// can be interpreted as a query asking if the operand #1 can be swapped
299 /// with any other available operand (e.g. operand #2, operand #3, etc.).
301 /// The returned FMA opcode may differ from the opcode in the given MI.
302 /// For example, commuting the operands #1 and #3 in the following FMA
303 /// FMA213 #1, #2, #3
304 /// results into instruction with adjusted opcode:
305 /// FMA231 #3, #2, #1
306 bool findFMA3CommutedOpIndices(const MachineInstr &MI,
309 const X86InstrFMA3Group &FMA3Group) const;
311 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
312 /// performs the same computations as the given \p MI but which has the
313 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
314 /// It may return 0 if it is unsafe to commute the operands.
315 /// Note that a machine instruction (instead of its opcode) is passed as the
316 /// first parameter to make it possible to analyze the instruction's uses and
317 /// commute the first operand of FMA even when it seems unsafe when you look
318 /// at the opcode. For example, it is Ok to commute the first operand of
319 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
321 /// The returned FMA opcode may differ from the opcode in the given \p MI.
322 /// For example, commuting the operands #1 and #3 in the following FMA
323 /// FMA213 #1, #2, #3
324 /// results into instruction with adjusted opcode:
325 /// FMA231 #3, #2, #1
326 unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI,
329 const X86InstrFMA3Group &FMA3Group) const;
332 bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
333 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
334 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
335 const MachineInstr &TailCall) const override;
336 void replaceBranchWithTailCall(MachineBasicBlock &MBB,
337 SmallVectorImpl<MachineOperand> &Cond,
338 const MachineInstr &TailCall) const override;
340 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
341 MachineBasicBlock *&FBB,
342 SmallVectorImpl<MachineOperand> &Cond,
343 bool AllowModify) const override;
345 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
347 const TargetRegisterInfo *TRI) const override;
348 bool analyzeBranchPredicate(MachineBasicBlock &MBB,
349 TargetInstrInfo::MachineBranchPredicate &MBP,
350 bool AllowModify = false) const override;
352 unsigned removeBranch(MachineBasicBlock &MBB,
353 int *BytesRemoved = nullptr) const override;
354 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
355 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
357 int *BytesAdded = nullptr) const override;
358 bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
359 unsigned, unsigned, int&, int&, int&) const override;
360 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
361 const DebugLoc &DL, unsigned DstReg,
362 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
363 unsigned FalseReg) const override;
364 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
365 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
366 bool KillSrc) const override;
367 void storeRegToStackSlot(MachineBasicBlock &MBB,
368 MachineBasicBlock::iterator MI,
369 unsigned SrcReg, bool isKill, int FrameIndex,
370 const TargetRegisterClass *RC,
371 const TargetRegisterInfo *TRI) const override;
373 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
374 SmallVectorImpl<MachineOperand> &Addr,
375 const TargetRegisterClass *RC,
376 MachineInstr::mmo_iterator MMOBegin,
377 MachineInstr::mmo_iterator MMOEnd,
378 SmallVectorImpl<MachineInstr*> &NewMIs) const;
380 void loadRegFromStackSlot(MachineBasicBlock &MBB,
381 MachineBasicBlock::iterator MI,
382 unsigned DestReg, int FrameIndex,
383 const TargetRegisterClass *RC,
384 const TargetRegisterInfo *TRI) const override;
386 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
387 SmallVectorImpl<MachineOperand> &Addr,
388 const TargetRegisterClass *RC,
389 MachineInstr::mmo_iterator MMOBegin,
390 MachineInstr::mmo_iterator MMOEnd,
391 SmallVectorImpl<MachineInstr*> &NewMIs) const;
393 bool expandPostRAPseudo(MachineInstr &MI) const override;
395 /// Check whether the target can fold a load that feeds a subreg operand
396 /// (or a subreg operand that feeds a store).
397 bool isSubregFoldable() const override { return true; }
399 /// foldMemoryOperand - If this target supports it, fold a load or store of
400 /// the specified stack slot into the specified machine instruction for the
401 /// specified operand(s). If this is possible, the target should perform the
402 /// folding and return true, otherwise it should return false. If it folds
403 /// the instruction, it is likely that the MachineInstruction the iterator
404 /// references has been changed.
406 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
407 ArrayRef<unsigned> Ops,
408 MachineBasicBlock::iterator InsertPt, int FrameIndex,
409 LiveIntervals *LIS = nullptr) const override;
411 /// foldMemoryOperand - Same as the previous version except it allows folding
412 /// of any load and store from / to any address, not just from a specific
414 MachineInstr *foldMemoryOperandImpl(
415 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
416 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
417 LiveIntervals *LIS = nullptr) const override;
419 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
420 /// a store or a load and a store into two or more instruction. If this is
421 /// possible, returns true as well as the new instructions by reference.
423 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
424 bool UnfoldLoad, bool UnfoldStore,
425 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
427 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
428 SmallVectorImpl<SDNode*> &NewNodes) const override;
430 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
431 /// instruction after load / store are unfolded from an instruction of the
432 /// specified opcode. It returns zero if the specified unfolding is not
433 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
434 /// index of the operand which will hold the register holding the loaded
436 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
437 bool UnfoldLoad, bool UnfoldStore,
438 unsigned *LoadRegIndex = nullptr) const override;
440 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
441 /// to determine if two loads are loading from the same base address. It
442 /// should only return true if the base pointers are the same and the
443 /// only differences between the two addresses are the offset. It also returns
444 /// the offsets by reference.
445 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
446 int64_t &Offset2) const override;
448 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
449 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
450 /// be scheduled togther. On some targets if two loads are loading from
451 /// addresses in the same cache line, it's better if they are scheduled
452 /// together. This function takes two integers that represent the load offsets
453 /// from the common base address. It returns true if it decides it's desirable
454 /// to schedule the two loads together. "NumLoads" is the number of loads that
455 /// have already been scheduled after Load1.
456 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
457 int64_t Offset1, int64_t Offset2,
458 unsigned NumLoads) const override;
460 void getNoop(MCInst &NopInst) const override;
463 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
465 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
466 /// instruction that defines the specified register class.
467 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
469 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
470 /// would clobber the EFLAGS condition register. Note the result may be
471 /// conservative. If it cannot definitely determine the safety after visiting
472 /// a few instructions in each direction it assumes it's not safe.
473 bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
474 MachineBasicBlock::iterator I) const;
476 /// True if MI has a condition code def, e.g. EFLAGS, that is
478 bool hasLiveCondCodeDef(MachineInstr &MI) const;
480 /// getGlobalBaseReg - Return a virtual register initialized with the
481 /// the global base register value. Output instructions required to
482 /// initialize the register in the function entry block, if necessary.
484 unsigned getGlobalBaseReg(MachineFunction *MF) const;
486 std::pair<uint16_t, uint16_t>
487 getExecutionDomain(const MachineInstr &MI) const override;
489 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
492 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
493 const TargetRegisterInfo *TRI) const override;
494 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
495 const TargetRegisterInfo *TRI) const override;
496 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
497 const TargetRegisterInfo *TRI) const override;
499 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
501 ArrayRef<MachineOperand> MOs,
502 MachineBasicBlock::iterator InsertPt,
503 unsigned Size, unsigned Alignment,
504 bool AllowCommute) const;
506 bool isHighLatencyDef(int opc) const override;
508 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
509 const MachineRegisterInfo *MRI,
510 const MachineInstr &DefMI, unsigned DefIdx,
511 const MachineInstr &UseMI,
512 unsigned UseIdx) const override;
514 bool useMachineCombiner() const override {
518 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
520 bool hasReassociableOperands(const MachineInstr &Inst,
521 const MachineBasicBlock *MBB) const override;
523 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
524 MachineInstr &NewMI1,
525 MachineInstr &NewMI2) const override;
527 /// analyzeCompare - For a comparison instruction, return the source registers
528 /// in SrcReg and SrcReg2 if having two register operands, and the value it
529 /// compares against in CmpValue. Return true if the comparison instruction
531 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
532 unsigned &SrcReg2, int &CmpMask,
533 int &CmpValue) const override;
535 /// optimizeCompareInstr - Check if there exists an earlier instruction that
536 /// operates on the same source operands and sets flags in the same way as
537 /// Compare; remove Compare if possible.
538 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
539 unsigned SrcReg2, int CmpMask, int CmpValue,
540 const MachineRegisterInfo *MRI) const override;
542 /// optimizeLoadInstr - Try to remove the load by folding it to a register
543 /// operand at the use. We fold the load instructions if and only if the
544 /// def and use are in the same BB. We only look at one load and see
545 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
546 /// defined by the load we are trying to fold. DefMI returns the machine
547 /// instruction that defines FoldAsLoadDefReg, and the function returns
548 /// the machine instruction generated due to folding.
549 MachineInstr *optimizeLoadInstr(MachineInstr &MI,
550 const MachineRegisterInfo *MRI,
551 unsigned &FoldAsLoadDefReg,
552 MachineInstr *&DefMI) const override;
554 std::pair<unsigned, unsigned>
555 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
557 ArrayRef<std::pair<unsigned, const char *>>
558 getSerializableDirectMachineOperandTargetFlags() const override;
560 unsigned getOutliningBenefit(size_t SequenceSize,
562 bool CanBeTailCall) const override;
564 bool isFunctionSafeToOutlineFrom(MachineFunction &MF) const override;
566 llvm::X86GenInstrInfo::MachineOutlinerInstrType
567 getOutliningType(MachineInstr &MI) const override;
569 void insertOutlinerEpilogue(MachineBasicBlock &MBB,
571 bool IsTailCall) const override;
573 void insertOutlinerPrologue(MachineBasicBlock &MBB,
575 bool isTailCall) const override;
577 MachineBasicBlock::iterator
578 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
579 MachineBasicBlock::iterator &It,
581 bool IsTailCall) const override;
583 /// Commutes the operands in the given instruction by changing the operands
584 /// order and/or changing the instruction's opcode and/or the immediate value
587 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
590 /// Do not call this method for a non-commutable instruction or
591 /// non-commutable operands.
592 /// Even though the instruction is commutable, the method may still
593 /// fail to commute the operands, null pointer is returned in such cases.
594 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
595 unsigned CommuteOpIdx1,
596 unsigned CommuteOpIdx2) const override;
599 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
600 MachineFunction::iterator &MFI,
602 LiveVariables *LV) const;
604 /// Handles memory folding for special case instructions, for instance those
605 /// requiring custom manipulation of the address.
606 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
608 ArrayRef<MachineOperand> MOs,
609 MachineBasicBlock::iterator InsertPt,
610 unsigned Size, unsigned Align) const;
612 /// isFrameOperand - Return true and the FrameIndex if the specified
613 /// operand and follow operands form a reference to the stack frame.
614 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
615 int &FrameIndex) const;
617 /// Returns true iff the routine could find two commutable operands in the
618 /// given machine instruction with 3 vector inputs.
619 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
620 /// input values can be re-defined in this method only if the input values
621 /// are not pre-defined, which is designated by the special value
622 /// 'CommuteAnyOperandIndex' assigned to it.
623 /// If both of indices are pre-defined and refer to some operands, then the
624 /// method simply returns true if the corresponding operands are commutable
625 /// and returns false otherwise.
627 /// For example, calling this method this way:
628 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
629 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
630 /// can be interpreted as a query asking to find an operand that would be
631 /// commutable with the operand#1.
632 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
634 unsigned &SrcOpIdx2) const;
637 } // End llvm namespace