1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
17 #include "MCTargetDesc/X86BaseInfo.h"
18 #include "X86InstrFMA3Info.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/CodeGen/ISDOpcodes.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #define GET_INSTRINFO_HEADER
25 #include "X86GenInstrInfo.inc"
28 class MachineInstrBuilder;
29 class X86RegisterInfo;
35 // For instr that was compressed from EVEX to VEX.
36 AC_EVEX_2_VEX = MachineInstr::TAsmComments
39 // X86 specific condition code. These correspond to X86_*_COND in
40 // X86InstrInfo.td. They must be kept in synch.
58 LAST_VALID_COND = COND_S,
60 // Artificial condition codes. These are used by AnalyzeBranch
61 // to indicate a block terminated with two conditional branches that together
62 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
63 // which can't be represented on x86 with a single condition. These
64 // are never used in MachineInstrs and are inverses of one another.
71 // Turn condition code into conditional branch opcode.
72 unsigned GetCondBranchFromCond(CondCode CC);
74 /// Return a pair of condition code for the given predicate and whether
75 /// the instruction operands should be swaped to match the condition code.
76 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
78 /// Return a set opcode for the given condition and whether it has
80 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
82 /// Return a cmov opcode for the given condition, register size in
83 /// bytes, and operand type.
84 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
85 bool HasMemoryOperand = false);
87 // Turn jCC opcode into condition code.
88 CondCode getCondFromBranchOpc(unsigned Opc);
90 // Turn setCC opcode into condition code.
91 CondCode getCondFromSETOpc(unsigned Opc);
93 // Turn CMov opcode into condition code.
94 CondCode getCondFromCMovOpc(unsigned Opc);
96 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
97 /// e.g. turning COND_E to COND_NE.
98 CondCode GetOppositeBranchCondition(CondCode CC);
100 /// Get the VPCMP immediate for the given condition.
101 unsigned getVPCMPImmForCond(ISD::CondCode CC);
103 /// Get the VPCMP immediate if the opcodes are swapped.
104 unsigned getSwappedVPCMPImm(unsigned Imm);
106 /// Get the VPCOM immediate if the opcodes are swapped.
107 unsigned getSwappedVPCOMImm(unsigned Imm);
111 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
112 /// a reference to a stub for a global, not the global itself.
113 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
114 switch (TargetFlag) {
115 case X86II::MO_DLLIMPORT: // dllimport stub.
116 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
117 case X86II::MO_GOT: // normal GOT reference.
118 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
119 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
126 /// isGlobalRelativeToPICBase - Return true if the specified global value
127 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
128 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
129 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
130 switch (TargetFlag) {
131 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
132 case X86II::MO_GOT: // isPICStyleGOT: other global.
133 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
134 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
135 case X86II::MO_TLVP: // ??? Pretty sure..
142 inline static bool isScale(const MachineOperand &MO) {
143 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
144 MO.getImm() == 4 || MO.getImm() == 8);
147 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
148 if (MI.getOperand(Op).isFI())
150 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
151 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
152 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
153 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
154 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
155 MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
156 MI.getOperand(Op + X86::AddrDisp).isCPI() ||
157 MI.getOperand(Op + X86::AddrDisp).isJTI());
160 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
161 if (MI.getOperand(Op).isFI())
163 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
164 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
167 class X86InstrInfo final : public X86GenInstrInfo {
168 X86Subtarget &Subtarget;
169 const X86RegisterInfo RI;
171 virtual void anchor();
173 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
174 MachineBasicBlock *&FBB,
175 SmallVectorImpl<MachineOperand> &Cond,
176 SmallVectorImpl<MachineInstr *> &CondBranches,
177 bool AllowModify) const;
180 explicit X86InstrInfo(X86Subtarget &STI);
182 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
183 /// such, whenever a client has an instance of instruction info, it should
184 /// always be able to get register info as well (through this method).
186 const X86RegisterInfo &getRegisterInfo() const { return RI; }
188 /// Returns the stack pointer adjustment that happens inside the frame
189 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
190 int64_t getFrameAdjustment(const MachineInstr &I) const {
191 assert(isFrameInstr(I));
193 return I.getOperand(2).getImm();
194 return I.getOperand(1).getImm();
197 /// Sets the stack pointer adjustment made inside the frame made up by this
199 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
200 assert(isFrameInstr(I));
202 I.getOperand(2).setImm(V);
204 I.getOperand(1).setImm(V);
207 /// getSPAdjust - This returns the stack pointer adjustment made by
208 /// this instruction. For x86, we need to handle more complex call
209 /// sequences involving PUSHes.
210 int getSPAdjust(const MachineInstr &MI) const override;
212 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
213 /// extension instruction. That is, it's like a copy where it's legal for the
214 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
215 /// true, then it's expected the pre-extension value is available as a subreg
216 /// of the result register. This also returns the sub-register index in
218 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
219 unsigned &DstReg, unsigned &SubIdx) const override;
221 unsigned isLoadFromStackSlot(const MachineInstr &MI,
222 int &FrameIndex) const override;
223 unsigned isLoadFromStackSlot(const MachineInstr &MI,
225 unsigned &MemBytes) const override;
226 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
227 /// stack locations as well. This uses a heuristic so it isn't
228 /// reliable for correctness.
229 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
230 int &FrameIndex) const override;
232 unsigned isStoreToStackSlot(const MachineInstr &MI,
233 int &FrameIndex) const override;
234 unsigned isStoreToStackSlot(const MachineInstr &MI,
236 unsigned &MemBytes) const override;
237 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
238 /// stack locations as well. This uses a heuristic so it isn't
239 /// reliable for correctness.
240 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
241 int &FrameIndex) const override;
243 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
244 AliasAnalysis *AA) const override;
245 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
246 unsigned DestReg, unsigned SubIdx,
247 const MachineInstr &Orig,
248 const TargetRegisterInfo &TRI) const override;
250 /// Given an operand within a MachineInstr, insert preceding code to put it
251 /// into the right format for a particular kind of LEA instruction. This may
252 /// involve using an appropriate super-register instead (with an implicit use
253 /// of the original) or creating a new virtual register and inserting COPY
254 /// instructions to get the data into the right class.
256 /// Reference parameters are set to indicate how caller should add this
257 /// operand to the LEA instruction.
258 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
259 unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
260 bool &isKill, bool &isUndef, MachineOperand &ImplicitOp,
261 LiveVariables *LV) const;
263 /// convertToThreeAddress - This method must be implemented by targets that
264 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
265 /// may be able to convert a two-address instruction into a true
266 /// three-address instruction on demand. This allows the X86 target (for
267 /// example) to convert ADD and SHL instructions into LEA instructions if they
268 /// would require register copies due to two-addressness.
270 /// This method returns a null pointer if the transformation cannot be
271 /// performed, otherwise it returns the new instruction.
273 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
275 LiveVariables *LV) const override;
277 /// Returns true iff the routine could find two commutable operands in the
278 /// given machine instruction.
279 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
280 /// input values can be re-defined in this method only if the input values
281 /// are not pre-defined, which is designated by the special value
282 /// 'CommuteAnyOperandIndex' assigned to it.
283 /// If both of indices are pre-defined and refer to some operands, then the
284 /// method simply returns true if the corresponding operands are commutable
285 /// and returns false otherwise.
287 /// For example, calling this method this way:
288 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
289 /// findCommutedOpIndices(MI, Op1, Op2);
290 /// can be interpreted as a query asking to find an operand that would be
291 /// commutable with the operand#1.
292 bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
293 unsigned &SrcOpIdx2) const override;
295 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
296 /// performs the same computations as the given \p MI but which has the
297 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
298 /// It may return 0 if it is unsafe to commute the operands.
299 /// Note that a machine instruction (instead of its opcode) is passed as the
300 /// first parameter to make it possible to analyze the instruction's uses and
301 /// commute the first operand of FMA even when it seems unsafe when you look
302 /// at the opcode. For example, it is Ok to commute the first operand of
303 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
305 /// The returned FMA opcode may differ from the opcode in the given \p MI.
306 /// For example, commuting the operands #1 and #3 in the following FMA
307 /// FMA213 #1, #2, #3
308 /// results into instruction with adjusted opcode:
309 /// FMA231 #3, #2, #1
311 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
313 const X86InstrFMA3Group &FMA3Group) const;
316 bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
317 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
318 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
319 const MachineInstr &TailCall) const override;
320 void replaceBranchWithTailCall(MachineBasicBlock &MBB,
321 SmallVectorImpl<MachineOperand> &Cond,
322 const MachineInstr &TailCall) const override;
324 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
325 MachineBasicBlock *&FBB,
326 SmallVectorImpl<MachineOperand> &Cond,
327 bool AllowModify) const override;
329 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
331 const TargetRegisterInfo *TRI) const override;
332 bool analyzeBranchPredicate(MachineBasicBlock &MBB,
333 TargetInstrInfo::MachineBranchPredicate &MBP,
334 bool AllowModify = false) const override;
336 unsigned removeBranch(MachineBasicBlock &MBB,
337 int *BytesRemoved = nullptr) const override;
338 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
339 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
341 int *BytesAdded = nullptr) const override;
342 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
343 unsigned, unsigned, int &, int &, int &) const override;
344 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
345 const DebugLoc &DL, unsigned DstReg,
346 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
347 unsigned FalseReg) const override;
348 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
349 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
350 bool KillSrc) const override;
351 bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Src,
352 const MachineOperand *&Dest) const override;
353 void storeRegToStackSlot(MachineBasicBlock &MBB,
354 MachineBasicBlock::iterator MI, unsigned SrcReg,
355 bool isKill, int FrameIndex,
356 const TargetRegisterClass *RC,
357 const TargetRegisterInfo *TRI) const override;
359 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
360 SmallVectorImpl<MachineOperand> &Addr,
361 const TargetRegisterClass *RC,
362 MachineInstr::mmo_iterator MMOBegin,
363 MachineInstr::mmo_iterator MMOEnd,
364 SmallVectorImpl<MachineInstr *> &NewMIs) const;
366 void loadRegFromStackSlot(MachineBasicBlock &MBB,
367 MachineBasicBlock::iterator MI, unsigned DestReg,
368 int FrameIndex, const TargetRegisterClass *RC,
369 const TargetRegisterInfo *TRI) const override;
371 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
372 SmallVectorImpl<MachineOperand> &Addr,
373 const TargetRegisterClass *RC,
374 MachineInstr::mmo_iterator MMOBegin,
375 MachineInstr::mmo_iterator MMOEnd,
376 SmallVectorImpl<MachineInstr *> &NewMIs) const;
378 bool expandPostRAPseudo(MachineInstr &MI) const override;
380 /// Check whether the target can fold a load that feeds a subreg operand
381 /// (or a subreg operand that feeds a store).
382 bool isSubregFoldable() const override { return true; }
384 /// foldMemoryOperand - If this target supports it, fold a load or store of
385 /// the specified stack slot into the specified machine instruction for the
386 /// specified operand(s). If this is possible, the target should perform the
387 /// folding and return true, otherwise it should return false. If it folds
388 /// the instruction, it is likely that the MachineInstruction the iterator
389 /// references has been changed.
391 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
392 ArrayRef<unsigned> Ops,
393 MachineBasicBlock::iterator InsertPt, int FrameIndex,
394 LiveIntervals *LIS = nullptr) const override;
396 /// foldMemoryOperand - Same as the previous version except it allows folding
397 /// of any load and store from / to any address, not just from a specific
399 MachineInstr *foldMemoryOperandImpl(
400 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
401 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
402 LiveIntervals *LIS = nullptr) const override;
404 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
405 /// a store or a load and a store into two or more instruction. If this is
406 /// possible, returns true as well as the new instructions by reference.
408 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
409 bool UnfoldLoad, bool UnfoldStore,
410 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
412 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
413 SmallVectorImpl<SDNode *> &NewNodes) const override;
415 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
416 /// instruction after load / store are unfolded from an instruction of the
417 /// specified opcode. It returns zero if the specified unfolding is not
418 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
419 /// index of the operand which will hold the register holding the loaded
422 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
423 unsigned *LoadRegIndex = nullptr) const override;
425 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
426 /// to determine if two loads are loading from the same base address. It
427 /// should only return true if the base pointers are the same and the
428 /// only differences between the two addresses are the offset. It also returns
429 /// the offsets by reference.
430 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
431 int64_t &Offset2) const override;
433 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
434 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
435 /// should be scheduled togther. On some targets if two loads are loading from
436 /// addresses in the same cache line, it's better if they are scheduled
437 /// together. This function takes two integers that represent the load offsets
438 /// from the common base address. It returns true if it decides it's desirable
439 /// to schedule the two loads together. "NumLoads" is the number of loads that
440 /// have already been scheduled after Load1.
441 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
443 unsigned NumLoads) const override;
445 void getNoop(MCInst &NopInst) const override;
448 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
450 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
451 /// instruction that defines the specified register class.
452 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
454 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
455 /// would clobber the EFLAGS condition register. Note the result may be
456 /// conservative. If it cannot definitely determine the safety after visiting
457 /// a few instructions in each direction it assumes it's not safe.
458 bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
459 MachineBasicBlock::iterator I) const;
461 /// True if MI has a condition code def, e.g. EFLAGS, that is
463 bool hasLiveCondCodeDef(MachineInstr &MI) const;
465 /// getGlobalBaseReg - Return a virtual register initialized with the
466 /// the global base register value. Output instructions required to
467 /// initialize the register in the function entry block, if necessary.
469 unsigned getGlobalBaseReg(MachineFunction *MF) const;
471 std::pair<uint16_t, uint16_t>
472 getExecutionDomain(const MachineInstr &MI) const override;
474 uint16_t getExecutionDomainCustom(const MachineInstr &MI) const;
476 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
478 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
481 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
482 const TargetRegisterInfo *TRI) const override;
483 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
484 const TargetRegisterInfo *TRI) const override;
485 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
486 const TargetRegisterInfo *TRI) const override;
488 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
490 ArrayRef<MachineOperand> MOs,
491 MachineBasicBlock::iterator InsertPt,
492 unsigned Size, unsigned Alignment,
493 bool AllowCommute) const;
495 bool isHighLatencyDef(int opc) const override;
497 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
498 const MachineRegisterInfo *MRI,
499 const MachineInstr &DefMI, unsigned DefIdx,
500 const MachineInstr &UseMI,
501 unsigned UseIdx) const override;
503 bool useMachineCombiner() const override { return true; }
505 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
507 bool hasReassociableOperands(const MachineInstr &Inst,
508 const MachineBasicBlock *MBB) const override;
510 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
511 MachineInstr &NewMI1,
512 MachineInstr &NewMI2) const override;
514 /// analyzeCompare - For a comparison instruction, return the source registers
515 /// in SrcReg and SrcReg2 if having two register operands, and the value it
516 /// compares against in CmpValue. Return true if the comparison instruction
518 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
519 unsigned &SrcReg2, int &CmpMask,
520 int &CmpValue) const override;
522 /// optimizeCompareInstr - Check if there exists an earlier instruction that
523 /// operates on the same source operands and sets flags in the same way as
524 /// Compare; remove Compare if possible.
525 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
526 unsigned SrcReg2, int CmpMask, int CmpValue,
527 const MachineRegisterInfo *MRI) const override;
529 /// optimizeLoadInstr - Try to remove the load by folding it to a register
530 /// operand at the use. We fold the load instructions if and only if the
531 /// def and use are in the same BB. We only look at one load and see
532 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
533 /// defined by the load we are trying to fold. DefMI returns the machine
534 /// instruction that defines FoldAsLoadDefReg, and the function returns
535 /// the machine instruction generated due to folding.
536 MachineInstr *optimizeLoadInstr(MachineInstr &MI,
537 const MachineRegisterInfo *MRI,
538 unsigned &FoldAsLoadDefReg,
539 MachineInstr *&DefMI) const override;
541 std::pair<unsigned, unsigned>
542 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
544 ArrayRef<std::pair<unsigned, const char *>>
545 getSerializableDirectMachineOperandTargetFlags() const override;
547 virtual outliner::OutlinedFunction getOutliningCandidateInfo(
548 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
550 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
551 bool OutlineFromLinkOnceODRs) const override;
554 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
556 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
557 const outliner::OutlinedFunction &OF) const override;
559 MachineBasicBlock::iterator
560 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
561 MachineBasicBlock::iterator &It, MachineFunction &MF,
562 const outliner::Candidate &C) const override;
565 /// Commutes the operands in the given instruction by changing the operands
566 /// order and/or changing the instruction's opcode and/or the immediate value
569 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
572 /// Do not call this method for a non-commutable instruction or
573 /// non-commutable operands.
574 /// Even though the instruction is commutable, the method may still
575 /// fail to commute the operands, null pointer is returned in such cases.
576 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
577 unsigned CommuteOpIdx1,
578 unsigned CommuteOpIdx2) const override;
581 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
582 MachineFunction::iterator &MFI,
584 LiveVariables *LV) const;
586 /// Handles memory folding for special case instructions, for instance those
587 /// requiring custom manipulation of the address.
588 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
590 ArrayRef<MachineOperand> MOs,
591 MachineBasicBlock::iterator InsertPt,
592 unsigned Size, unsigned Align) const;
594 /// isFrameOperand - Return true and the FrameIndex if the specified
595 /// operand and follow operands form a reference to the stack frame.
596 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
597 int &FrameIndex) const;
599 /// Returns true iff the routine could find two commutable operands in the
600 /// given machine instruction with 3 vector inputs.
601 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
602 /// input values can be re-defined in this method only if the input values
603 /// are not pre-defined, which is designated by the special value
604 /// 'CommuteAnyOperandIndex' assigned to it.
605 /// If both of indices are pre-defined and refer to some operands, then the
606 /// method simply returns true if the corresponding operands are commutable
607 /// and returns false otherwise.
609 /// For example, calling this method this way:
610 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
611 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
612 /// can be interpreted as a query asking to find an operand that would be
613 /// commutable with the operand#1.
615 /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
616 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
619 bool IsIntrinsic = false) const;