1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
17 #include "MCTargetDesc/X86BaseInfo.h"
18 #include "X86InstrFMA3Info.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/Target/TargetInstrInfo.h"
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
27 class MachineInstrBuilder;
28 class X86RegisterInfo;
32 // X86 specific condition code. These correspond to X86_*_COND in
33 // X86InstrInfo.td. They must be kept in synch.
51 LAST_VALID_COND = COND_S,
53 // Artificial condition codes. These are used by AnalyzeBranch
54 // to indicate a block terminated with two conditional branches that together
55 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
56 // which can't be represented on x86 with a single condition. These
57 // are never used in MachineInstrs and are inverses of one another.
64 // Turn condition code into conditional branch opcode.
65 unsigned GetCondBranchFromCond(CondCode CC);
67 /// \brief Return a set opcode for the given condition and whether it has
69 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
71 /// \brief Return a cmov opcode for the given condition, register size in
72 /// bytes, and operand type.
73 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
74 bool HasMemoryOperand = false);
76 // Turn CMov opcode into condition code.
77 CondCode getCondFromCMovOpc(unsigned Opc);
79 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
80 /// e.g. turning COND_E to COND_NE.
81 CondCode GetOppositeBranchCondition(CondCode CC);
82 } // end namespace X86;
85 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
86 /// a reference to a stub for a global, not the global itself.
87 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
89 case X86II::MO_DLLIMPORT: // dllimport stub.
90 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
91 case X86II::MO_GOT: // normal GOT reference.
92 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
93 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
100 /// isGlobalRelativeToPICBase - Return true if the specified global value
101 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
102 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
103 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
104 switch (TargetFlag) {
105 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
106 case X86II::MO_GOT: // isPICStyleGOT: other global.
107 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
108 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
109 case X86II::MO_TLVP: // ??? Pretty sure..
116 inline static bool isScale(const MachineOperand &MO) {
118 (MO.getImm() == 1 || MO.getImm() == 2 ||
119 MO.getImm() == 4 || MO.getImm() == 8);
122 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
123 if (MI.getOperand(Op).isFI())
125 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
126 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
127 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
128 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
129 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
130 MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
131 MI.getOperand(Op + X86::AddrDisp).isCPI() ||
132 MI.getOperand(Op + X86::AddrDisp).isJTI());
135 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
136 if (MI.getOperand(Op).isFI())
138 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
139 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
142 class X86InstrInfo final : public X86GenInstrInfo {
143 X86Subtarget &Subtarget;
144 const X86RegisterInfo RI;
146 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
147 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
149 typedef DenseMap<unsigned,
150 std::pair<uint16_t, uint16_t> > RegOp2MemOpTableType;
151 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
152 RegOp2MemOpTableType RegOp2MemOpTable0;
153 RegOp2MemOpTableType RegOp2MemOpTable1;
154 RegOp2MemOpTableType RegOp2MemOpTable2;
155 RegOp2MemOpTableType RegOp2MemOpTable3;
156 RegOp2MemOpTableType RegOp2MemOpTable4;
158 /// MemOp2RegOpTable - Load / store unfolding opcode map.
160 typedef DenseMap<unsigned,
161 std::pair<uint16_t, uint16_t> > MemOp2RegOpTableType;
162 MemOp2RegOpTableType MemOp2RegOpTable;
164 static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
165 MemOp2RegOpTableType &M2RTable,
166 uint16_t RegOp, uint16_t MemOp, uint16_t Flags);
168 virtual void anchor();
170 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
171 MachineBasicBlock *&FBB,
172 SmallVectorImpl<MachineOperand> &Cond,
173 SmallVectorImpl<MachineInstr *> &CondBranches,
174 bool AllowModify) const;
177 explicit X86InstrInfo(X86Subtarget &STI);
179 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
180 /// such, whenever a client has an instance of instruction info, it should
181 /// always be able to get register info as well (through this method).
183 const X86RegisterInfo &getRegisterInfo() const { return RI; }
185 /// getSPAdjust - This returns the stack pointer adjustment made by
186 /// this instruction. For x86, we need to handle more complex call
187 /// sequences involving PUSHes.
188 int getSPAdjust(const MachineInstr &MI) const override;
190 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
191 /// extension instruction. That is, it's like a copy where it's legal for the
192 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
193 /// true, then it's expected the pre-extension value is available as a subreg
194 /// of the result register. This also returns the sub-register index in
196 bool isCoalescableExtInstr(const MachineInstr &MI,
197 unsigned &SrcReg, unsigned &DstReg,
198 unsigned &SubIdx) const override;
200 unsigned isLoadFromStackSlot(const MachineInstr &MI,
201 int &FrameIndex) const override;
202 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
203 /// stack locations as well. This uses a heuristic so it isn't
204 /// reliable for correctness.
205 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
206 int &FrameIndex) const override;
208 unsigned isStoreToStackSlot(const MachineInstr &MI,
209 int &FrameIndex) const override;
210 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
211 /// stack locations as well. This uses a heuristic so it isn't
212 /// reliable for correctness.
213 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
214 int &FrameIndex) const override;
216 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
217 AliasAnalysis *AA) const override;
218 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
219 unsigned DestReg, unsigned SubIdx,
220 const MachineInstr &Orig,
221 const TargetRegisterInfo &TRI) const override;
223 /// Given an operand within a MachineInstr, insert preceding code to put it
224 /// into the right format for a particular kind of LEA instruction. This may
225 /// involve using an appropriate super-register instead (with an implicit use
226 /// of the original) or creating a new virtual register and inserting COPY
227 /// instructions to get the data into the right class.
229 /// Reference parameters are set to indicate how caller should add this
230 /// operand to the LEA instruction.
231 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
232 unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
233 bool &isKill, bool &isUndef,
234 MachineOperand &ImplicitOp, LiveVariables *LV) const;
236 /// convertToThreeAddress - This method must be implemented by targets that
237 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
238 /// may be able to convert a two-address instruction into a true
239 /// three-address instruction on demand. This allows the X86 target (for
240 /// example) to convert ADD and SHL instructions into LEA instructions if they
241 /// would require register copies due to two-addressness.
243 /// This method returns a null pointer if the transformation cannot be
244 /// performed, otherwise it returns the new instruction.
246 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
248 LiveVariables *LV) const override;
250 /// Returns true iff the routine could find two commutable operands in the
251 /// given machine instruction.
252 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
253 /// input values can be re-defined in this method only if the input values
254 /// are not pre-defined, which is designated by the special value
255 /// 'CommuteAnyOperandIndex' assigned to it.
256 /// If both of indices are pre-defined and refer to some operands, then the
257 /// method simply returns true if the corresponding operands are commutable
258 /// and returns false otherwise.
260 /// For example, calling this method this way:
261 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
262 /// findCommutedOpIndices(MI, Op1, Op2);
263 /// can be interpreted as a query asking to find an operand that would be
264 /// commutable with the operand#1.
265 bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
266 unsigned &SrcOpIdx2) const override;
268 /// Returns true if the routine could find two commutable operands
269 /// in the given FMA instruction \p MI. Otherwise, returns false.
271 /// \p SrcOpIdx1 and \p SrcOpIdx2 are INPUT and OUTPUT arguments.
272 /// The output indices of the commuted operands are returned in these
273 /// arguments. Also, the input values of these arguments may be preset either
274 /// to indices of operands that must be commuted or be equal to a special
275 /// value 'CommuteAnyOperandIndex' which means that the corresponding
276 /// operand index is not set and this method is free to pick any of
277 /// available commutable operands.
278 /// The parameter \p FMA3Group keeps the reference to the group of relative
279 /// FMA3 opcodes including register/memory forms of 132/213/231 opcodes.
281 /// For example, calling this method this way:
282 /// unsigned Idx1 = 1, Idx2 = CommuteAnyOperandIndex;
283 /// findFMA3CommutedOpIndices(MI, Idx1, Idx2, FMA3Group);
284 /// can be interpreted as a query asking if the operand #1 can be swapped
285 /// with any other available operand (e.g. operand #2, operand #3, etc.).
287 /// The returned FMA opcode may differ from the opcode in the given MI.
288 /// For example, commuting the operands #1 and #3 in the following FMA
289 /// FMA213 #1, #2, #3
290 /// results into instruction with adjusted opcode:
291 /// FMA231 #3, #2, #1
292 bool findFMA3CommutedOpIndices(const MachineInstr &MI,
295 const X86InstrFMA3Group &FMA3Group) const;
297 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
298 /// performs the same computations as the given \p MI but which has the
299 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
300 /// It may return 0 if it is unsafe to commute the operands.
301 /// Note that a machine instruction (instead of its opcode) is passed as the
302 /// first parameter to make it possible to analyze the instruction's uses and
303 /// commute the first operand of FMA even when it seems unsafe when you look
304 /// at the opcode. For example, it is Ok to commute the first operand of
305 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
307 /// The returned FMA opcode may differ from the opcode in the given \p MI.
308 /// For example, commuting the operands #1 and #3 in the following FMA
309 /// FMA213 #1, #2, #3
310 /// results into instruction with adjusted opcode:
311 /// FMA231 #3, #2, #1
312 unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI,
315 const X86InstrFMA3Group &FMA3Group) const;
318 bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
319 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
320 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
321 const MachineInstr &TailCall) const override;
322 void replaceBranchWithTailCall(MachineBasicBlock &MBB,
323 SmallVectorImpl<MachineOperand> &Cond,
324 const MachineInstr &TailCall) const override;
326 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
327 MachineBasicBlock *&FBB,
328 SmallVectorImpl<MachineOperand> &Cond,
329 bool AllowModify) const override;
331 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
333 const TargetRegisterInfo *TRI) const override;
334 bool analyzeBranchPredicate(MachineBasicBlock &MBB,
335 TargetInstrInfo::MachineBranchPredicate &MBP,
336 bool AllowModify = false) const override;
338 unsigned removeBranch(MachineBasicBlock &MBB,
339 int *BytesRemoved = nullptr) const override;
340 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
341 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
343 int *BytesAdded = nullptr) const override;
344 bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
345 unsigned, unsigned, int&, int&, int&) const override;
346 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
347 const DebugLoc &DL, unsigned DstReg,
348 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
349 unsigned FalseReg) const override;
350 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
351 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
352 bool KillSrc) const override;
353 void storeRegToStackSlot(MachineBasicBlock &MBB,
354 MachineBasicBlock::iterator MI,
355 unsigned SrcReg, bool isKill, int FrameIndex,
356 const TargetRegisterClass *RC,
357 const TargetRegisterInfo *TRI) const override;
359 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
360 SmallVectorImpl<MachineOperand> &Addr,
361 const TargetRegisterClass *RC,
362 MachineInstr::mmo_iterator MMOBegin,
363 MachineInstr::mmo_iterator MMOEnd,
364 SmallVectorImpl<MachineInstr*> &NewMIs) const;
366 void loadRegFromStackSlot(MachineBasicBlock &MBB,
367 MachineBasicBlock::iterator MI,
368 unsigned DestReg, int FrameIndex,
369 const TargetRegisterClass *RC,
370 const TargetRegisterInfo *TRI) const override;
372 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
373 SmallVectorImpl<MachineOperand> &Addr,
374 const TargetRegisterClass *RC,
375 MachineInstr::mmo_iterator MMOBegin,
376 MachineInstr::mmo_iterator MMOEnd,
377 SmallVectorImpl<MachineInstr*> &NewMIs) const;
379 bool expandPostRAPseudo(MachineInstr &MI) const override;
381 /// Check whether the target can fold a load that feeds a subreg operand
382 /// (or a subreg operand that feeds a store).
383 bool isSubregFoldable() const override { return true; }
385 /// foldMemoryOperand - If this target supports it, fold a load or store of
386 /// the specified stack slot into the specified machine instruction for the
387 /// specified operand(s). If this is possible, the target should perform the
388 /// folding and return true, otherwise it should return false. If it folds
389 /// the instruction, it is likely that the MachineInstruction the iterator
390 /// references has been changed.
392 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
393 ArrayRef<unsigned> Ops,
394 MachineBasicBlock::iterator InsertPt, int FrameIndex,
395 LiveIntervals *LIS = nullptr) const override;
397 /// foldMemoryOperand - Same as the previous version except it allows folding
398 /// of any load and store from / to any address, not just from a specific
400 MachineInstr *foldMemoryOperandImpl(
401 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
402 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
403 LiveIntervals *LIS = nullptr) const override;
405 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
406 /// a store or a load and a store into two or more instruction. If this is
407 /// possible, returns true as well as the new instructions by reference.
409 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
410 bool UnfoldLoad, bool UnfoldStore,
411 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
413 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
414 SmallVectorImpl<SDNode*> &NewNodes) const override;
416 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
417 /// instruction after load / store are unfolded from an instruction of the
418 /// specified opcode. It returns zero if the specified unfolding is not
419 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
420 /// index of the operand which will hold the register holding the loaded
422 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
423 bool UnfoldLoad, bool UnfoldStore,
424 unsigned *LoadRegIndex = nullptr) const override;
426 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
427 /// to determine if two loads are loading from the same base address. It
428 /// should only return true if the base pointers are the same and the
429 /// only differences between the two addresses are the offset. It also returns
430 /// the offsets by reference.
431 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
432 int64_t &Offset2) const override;
434 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
435 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
436 /// be scheduled togther. On some targets if two loads are loading from
437 /// addresses in the same cache line, it's better if they are scheduled
438 /// together. This function takes two integers that represent the load offsets
439 /// from the common base address. It returns true if it decides it's desirable
440 /// to schedule the two loads together. "NumLoads" is the number of loads that
441 /// have already been scheduled after Load1.
442 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
443 int64_t Offset1, int64_t Offset2,
444 unsigned NumLoads) const override;
446 bool shouldScheduleAdjacent(const MachineInstr &First,
447 const MachineInstr &Second) const override;
449 void getNoopForMachoTarget(MCInst &NopInst) const override;
452 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
454 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
455 /// instruction that defines the specified register class.
456 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
458 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
459 /// would clobber the EFLAGS condition register. Note the result may be
460 /// conservative. If it cannot definitely determine the safety after visiting
461 /// a few instructions in each direction it assumes it's not safe.
462 bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
463 MachineBasicBlock::iterator I) const;
465 /// True if MI has a condition code def, e.g. EFLAGS, that is
467 bool hasLiveCondCodeDef(MachineInstr &MI) const;
469 /// getGlobalBaseReg - Return a virtual register initialized with the
470 /// the global base register value. Output instructions required to
471 /// initialize the register in the function entry block, if necessary.
473 unsigned getGlobalBaseReg(MachineFunction *MF) const;
475 std::pair<uint16_t, uint16_t>
476 getExecutionDomain(const MachineInstr &MI) const override;
478 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
481 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
482 const TargetRegisterInfo *TRI) const override;
483 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
484 const TargetRegisterInfo *TRI) const override;
485 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
486 const TargetRegisterInfo *TRI) const override;
488 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
490 ArrayRef<MachineOperand> MOs,
491 MachineBasicBlock::iterator InsertPt,
492 unsigned Size, unsigned Alignment,
493 bool AllowCommute) const;
495 bool isHighLatencyDef(int opc) const override;
497 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
498 const MachineRegisterInfo *MRI,
499 const MachineInstr &DefMI, unsigned DefIdx,
500 const MachineInstr &UseMI,
501 unsigned UseIdx) const override;
503 bool useMachineCombiner() const override {
507 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
509 bool hasReassociableOperands(const MachineInstr &Inst,
510 const MachineBasicBlock *MBB) const override;
512 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
513 MachineInstr &NewMI1,
514 MachineInstr &NewMI2) const override;
516 /// analyzeCompare - For a comparison instruction, return the source registers
517 /// in SrcReg and SrcReg2 if having two register operands, and the value it
518 /// compares against in CmpValue. Return true if the comparison instruction
520 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
521 unsigned &SrcReg2, int &CmpMask,
522 int &CmpValue) const override;
524 /// optimizeCompareInstr - Check if there exists an earlier instruction that
525 /// operates on the same source operands and sets flags in the same way as
526 /// Compare; remove Compare if possible.
527 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
528 unsigned SrcReg2, int CmpMask, int CmpValue,
529 const MachineRegisterInfo *MRI) const override;
531 /// optimizeLoadInstr - Try to remove the load by folding it to a register
532 /// operand at the use. We fold the load instructions if and only if the
533 /// def and use are in the same BB. We only look at one load and see
534 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
535 /// defined by the load we are trying to fold. DefMI returns the machine
536 /// instruction that defines FoldAsLoadDefReg, and the function returns
537 /// the machine instruction generated due to folding.
538 MachineInstr *optimizeLoadInstr(MachineInstr &MI,
539 const MachineRegisterInfo *MRI,
540 unsigned &FoldAsLoadDefReg,
541 MachineInstr *&DefMI) const override;
543 std::pair<unsigned, unsigned>
544 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
546 ArrayRef<std::pair<unsigned, const char *>>
547 getSerializableDirectMachineOperandTargetFlags() const override;
549 bool isTailCall(const MachineInstr &Inst) const override;
552 /// Commutes the operands in the given instruction by changing the operands
553 /// order and/or changing the instruction's opcode and/or the immediate value
556 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
559 /// Do not call this method for a non-commutable instruction or
560 /// non-commutable operands.
561 /// Even though the instruction is commutable, the method may still
562 /// fail to commute the operands, null pointer is returned in such cases.
563 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
564 unsigned CommuteOpIdx1,
565 unsigned CommuteOpIdx2) const override;
568 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
569 MachineFunction::iterator &MFI,
571 LiveVariables *LV) const;
573 /// Handles memory folding for special case instructions, for instance those
574 /// requiring custom manipulation of the address.
575 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
577 ArrayRef<MachineOperand> MOs,
578 MachineBasicBlock::iterator InsertPt,
579 unsigned Size, unsigned Align) const;
581 /// isFrameOperand - Return true and the FrameIndex if the specified
582 /// operand and follow operands form a reference to the stack frame.
583 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
584 int &FrameIndex) const;
586 /// Returns true iff the routine could find two commutable operands in the
587 /// given machine instruction with 3 vector inputs.
588 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
589 /// input values can be re-defined in this method only if the input values
590 /// are not pre-defined, which is designated by the special value
591 /// 'CommuteAnyOperandIndex' assigned to it.
592 /// If both of indices are pre-defined and refer to some operands, then the
593 /// method simply returns true if the corresponding operands are commutable
594 /// and returns false otherwise.
596 /// For example, calling this method this way:
597 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
598 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
599 /// can be interpreted as a query asking to find an operand that would be
600 /// commutable with the operand#1.
601 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
603 unsigned &SrcOpIdx2) const;
606 } // End llvm namespace