1 //===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MPX instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
18 def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins i32mem:$src),
19 OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
20 Requires<[HasMPX, Not64BitMode]>;
21 def 64rm: RI<opc, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
22 OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
23 Requires<[HasMPX, In64BitMode]>;
27 defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
29 multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
31 def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, i32mem:$src2),
32 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
33 Requires<[HasMPX, Not64BitMode]>;
34 def 64rm: RI<opc, MRMSrcMem, (outs), (ins BNDR:$src1, i64mem:$src2),
35 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
36 Requires<[HasMPX, In64BitMode]>;
38 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
39 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
40 Requires<[HasMPX, Not64BitMode]>;
41 def 64rr: RI<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
42 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
43 Requires<[HasMPX, In64BitMode]>;
45 defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS;
46 defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD;
47 defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD;
49 def BNDMOVRMrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
50 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
53 def BNDMOVRM32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
54 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
55 Requires<[HasMPX, Not64BitMode]>;
56 def BNDMOVRM64rm : RI<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
57 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
58 Requires<[HasMPX, In64BitMode]>;
60 def BNDMOVMRrr : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
61 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
64 def BNDMOVMR32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
65 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
66 Requires<[HasMPX, Not64BitMode]>;
67 def BNDMOVMR64mr : RI<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
68 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
69 Requires<[HasMPX, In64BitMode]>;
71 def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
72 "bndstx\t{$src, $dst|$dst, $src}", []>, PS,
76 def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
77 "bndldx\t{$src, $dst|$dst, $src}", []>, PS,