1 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instructions that are generally used in
11 // privileged modes. These are not typically used by the compiler, but are
12 // supported for the assembler and disassembler.
14 //===----------------------------------------------------------------------===//
16 let SchedRW = [WriteSystem] in {
17 let Defs = [RAX, RDX] in
18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
21 let Defs = [RAX, RCX, RDX] in
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)],
25 // CPU flow control instructions
27 let mayLoad = 1, mayStore = 0, hasSideEffects = 1 in {
28 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
29 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
32 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
33 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
35 // Interrupt and SysCall Instructions.
36 let Uses = [EFLAGS] in
37 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
38 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
39 [(int_x86_int (i8 3))], IIC_INT3>;
42 // The long form of "int $3" turns into int3 as a size optimization.
43 // FIXME: This doesn't work because InstAlias can't match immediate constants.
44 //def : InstAlias<"int\t$3", (INT3)>;
46 let SchedRW = [WriteSystem] in {
48 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
49 [(int_x86_int imm:$trap)], IIC_INT>;
52 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
53 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
54 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
55 Requires<[In64BitMode]>;
57 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
58 IIC_SYS_ENTER_EXIT>, TB;
60 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
61 IIC_SYS_ENTER_EXIT>, TB;
62 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
63 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
66 def : Pat<(debugtrap),
67 (INT3)>, Requires<[NotPS4]>;
68 def : Pat<(debugtrap),
69 (INT (i8 0x41))>, Requires<[IsPS4]>;
71 //===----------------------------------------------------------------------===//
72 // Input/Output Instructions.
74 let SchedRW = [WriteSystem] in {
75 let Defs = [AL], Uses = [DX] in
76 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
77 "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
78 let Defs = [AX], Uses = [DX] in
79 def IN16rr : I<0xED, RawFrm, (outs), (ins),
80 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize16;
81 let Defs = [EAX], Uses = [DX] in
82 def IN32rr : I<0xED, RawFrm, (outs), (ins),
83 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
86 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
87 "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
89 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
90 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
92 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
93 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
95 let Uses = [DX, AL] in
96 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
97 "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
98 let Uses = [DX, AX] in
99 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
100 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
101 let Uses = [DX, EAX] in
102 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
103 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
106 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
107 "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
109 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
110 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
112 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
113 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
117 //===----------------------------------------------------------------------===//
118 // Moves to and from debug registers
120 let SchedRW = [WriteSystem] in {
121 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
122 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
123 Requires<[Not64BitMode]>;
124 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
125 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
126 Requires<[In64BitMode]>;
128 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
129 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
130 Requires<[Not64BitMode]>;
131 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
132 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
133 Requires<[In64BitMode]>;
136 //===----------------------------------------------------------------------===//
137 // Moves to and from control registers
139 let SchedRW = [WriteSystem] in {
140 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
141 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
142 Requires<[Not64BitMode]>;
143 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
144 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
145 Requires<[In64BitMode]>;
147 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
148 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
149 Requires<[Not64BitMode]>;
150 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
151 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
152 Requires<[In64BitMode]>;
155 //===----------------------------------------------------------------------===//
156 // Segment override instruction prefixes
158 let SchedRW = [WriteNop] in {
159 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", [], IIC_NOP>;
160 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", [], IIC_NOP>;
161 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", [], IIC_NOP>;
162 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", [], IIC_NOP>;
163 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", [], IIC_NOP>;
164 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", [], IIC_NOP>;
167 //===----------------------------------------------------------------------===//
168 // Moves to and from segment registers.
171 let SchedRW = [WriteMove] in {
172 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
173 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
174 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
175 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
176 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
177 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
178 let mayStore = 1 in {
179 def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
180 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSizeIgnore;
182 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
183 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
184 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
185 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
186 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
187 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
189 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
190 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSizeIgnore;
194 //===----------------------------------------------------------------------===//
195 // Segmentation support instructions.
197 let SchedRW = [WriteSystem] in {
198 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
201 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
202 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
204 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
205 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
208 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
210 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
211 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
213 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
214 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
216 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
218 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
219 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
220 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
221 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
224 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
225 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
227 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
228 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
231 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
232 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
234 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
235 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
238 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
239 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
240 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
241 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
243 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
246 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
247 "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
248 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
249 "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
250 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
251 "str{q}\t$dst", [], IIC_STR>, TB;
253 def STRm : I<0x00, MRM1m, (outs), (ins i16mem:$dst),
254 "str{w}\t$dst", [], IIC_STR>, TB;
256 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
257 "ltr{w}\t$src", [], IIC_LTR>, TB;
259 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
260 "ltr{w}\t$src", [], IIC_LTR>, TB;
262 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
263 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
264 OpSize16, Requires<[Not64BitMode]>;
265 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
266 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
267 OpSize32, Requires<[Not64BitMode]>;
268 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
269 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
270 OpSize16, Requires<[Not64BitMode]>;
271 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
272 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
273 OpSize32, Requires<[Not64BitMode]>;
274 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
275 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
276 OpSize16, Requires<[Not64BitMode]>;
277 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
278 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
279 OpSize32, Requires<[Not64BitMode]>;
280 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
281 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
282 OpSize16, Requires<[Not64BitMode]>;
283 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
284 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
285 OpSize32, Requires<[Not64BitMode]>;
286 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
287 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
288 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
289 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
290 OpSize32, Requires<[Not64BitMode]>;
291 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
292 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
293 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
294 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
295 OpSize32, Requires<[Not64BitMode]>;
296 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
297 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
298 OpSize32, Requires<[In64BitMode]>;
299 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
300 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
301 OpSize32, Requires<[In64BitMode]>;
303 // No "pop cs" instruction.
304 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
305 "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
306 OpSize16, Requires<[Not64BitMode]>;
307 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
308 "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
309 OpSize32, Requires<[Not64BitMode]>;
311 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
312 "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
313 OpSize16, Requires<[Not64BitMode]>;
314 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
315 "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
316 OpSize32, Requires<[Not64BitMode]>;
318 def POPES16 : I<0x07, RawFrm, (outs), (ins),
319 "pop{w}\t{%es|es}", [], IIC_POP_SR>,
320 OpSize16, Requires<[Not64BitMode]>;
321 def POPES32 : I<0x07, RawFrm, (outs), (ins),
322 "pop{l}\t{%es|es}", [], IIC_POP_SR>,
323 OpSize32, Requires<[Not64BitMode]>;
325 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
326 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
327 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
328 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
329 OpSize32, Requires<[Not64BitMode]>;
330 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
331 "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
332 OpSize32, Requires<[In64BitMode]>;
334 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
335 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
336 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
337 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
338 OpSize32, Requires<[Not64BitMode]>;
339 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
340 "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
341 OpSize32, Requires<[In64BitMode]>;
344 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
345 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
346 Requires<[Not64BitMode]>;
347 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
348 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
349 Requires<[Not64BitMode]>;
351 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
352 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
353 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
354 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
355 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
356 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
358 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
359 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
360 Requires<[Not64BitMode]>;
361 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
362 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
363 Requires<[Not64BitMode]>;
365 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
366 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
367 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
368 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
369 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
370 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
372 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
373 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
374 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
375 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
377 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
378 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
381 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
382 "verr\t$seg", [], IIC_VERR>, TB;
383 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
384 "verw\t$seg", [], IIC_VERW_MEM>, TB;
386 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
387 "verr\t$seg", [], IIC_VERR>, TB;
388 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
389 "verw\t$seg", [], IIC_VERW_REG>, TB;
393 //===----------------------------------------------------------------------===//
394 // Descriptor-table support instructions
396 let SchedRW = [WriteSystem] in {
397 def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
398 "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
399 def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
400 "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
401 def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
402 "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
403 def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
404 "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
405 def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
406 "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
407 def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
408 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
409 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
410 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
412 def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
413 "sldt{w}\t$dst", [], IIC_SLDT>, TB;
414 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
415 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
417 // LLDT is not interpreted specially in 64-bit mode because there is no sign
419 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
420 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
422 def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst),
423 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
425 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
426 "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
427 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
428 "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
429 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
430 "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
431 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
432 "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
433 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
434 "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
435 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
436 "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
437 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
438 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
440 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
441 "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
444 //===----------------------------------------------------------------------===//
445 // Specialized register support
446 let SchedRW = [WriteSystem] in {
447 let Uses = [EAX, ECX, EDX] in
448 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
449 let Defs = [EAX, EDX], Uses = [ECX] in
450 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
452 let Defs = [RAX, RDX], Uses = [ECX] in
453 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>,
456 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
457 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
458 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
459 "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
460 // no m form encodable; use SMSW16m
461 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
462 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
464 // For memory operands, there is only a 16-bit form
465 def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
466 "smsw{w}\t$dst", [], IIC_SMSW>, TB;
468 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
469 "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
471 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
472 "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
474 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
475 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
478 //===----------------------------------------------------------------------===//
479 // Cache instructions
480 let SchedRW = [WriteSystem] in {
481 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
482 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
485 //===----------------------------------------------------------------------===//
487 let SchedRW = [WriteSystem], Predicates = [HasSHSTK] in{
488 let Uses = [SSP] in {
489 let Defs = [SSP] in {
490 def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
491 [(int_x86_incsspd GR32:$src)]>, XS;
492 def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
493 [(int_x86_incsspq GR64:$src)]>, XS;
496 let Constraints = "$src = $dst" in {
497 def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
499 [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
500 def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
502 [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS;
505 let Defs = [SSP] in {
506 def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
507 [(int_x86_saveprevssp)]>, XS;
508 def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
510 [(int_x86_rstorssp addr:$src)]>, XS;
514 def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
515 "wrssd\t{$src, $dst|$dst, $src}",
516 [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS;
517 def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
518 "wrssq\t{$src, $dst|$dst, $src}",
519 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS;
520 def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
521 "wrussd\t{$src, $dst|$dst, $src}",
522 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
523 def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
524 "wrussq\t{$src, $dst|$dst, $src}",
525 [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD;
527 let Defs = [SSP] in {
528 let Uses = [SSP] in {
529 def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
530 [(int_x86_setssbsy)]>, XS;
533 def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
535 [(int_x86_clrssbsy addr:$src)]>, XS;
537 } // SchedRW && HasSHSTK
539 //===----------------------------------------------------------------------===//
540 // XSAVE instructions
541 let SchedRW = [WriteSystem] in {
542 let Predicates = [HasXSAVE] in {
543 let Defs = [EDX, EAX], Uses = [ECX] in
544 def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
546 let Uses = [EDX, EAX, ECX] in
547 def XSETBV : I<0x01, MRM_D1, (outs), (ins),
549 [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
553 let Uses = [EDX, EAX] in {
554 def XSAVE : I<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
556 [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
557 def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
559 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
560 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
562 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
563 def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
565 [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
566 def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
568 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>;
569 def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
571 [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>;
572 def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
574 [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>;
575 def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
577 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>;
578 def XSAVES : I<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
580 [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
581 def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
583 [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
584 def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
586 [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
587 def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
589 [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>;
593 //===----------------------------------------------------------------------===//
594 // VIA PadLock crypto instructions
595 let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
596 def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
598 def : InstAlias<"xstorerng", (XSTORE)>;
600 let SchedRW = [WriteSystem] in {
601 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
602 def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
603 def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
604 def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
605 def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
606 def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
609 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
610 def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
611 def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
613 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
614 def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
617 //==-----------------------------------------------------------------------===//
618 // PKU - enable protection key
619 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
620 def WRPKRU : PseudoI<(outs), (ins GR32:$src),
621 [(int_x86_wrpkru GR32:$src)]>;
622 def RDPKRU : PseudoI<(outs GR32:$dst), (ins),
623 [(set GR32:$dst, (int_x86_rdpkru))]>;
626 let SchedRW = [WriteSystem] in {
627 let Defs = [EAX, EDX], Uses = [ECX] in
628 def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", [], IIC_PKU>, TB;
629 let Uses = [EAX, ECX, EDX] in
630 def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", [], IIC_PKU>, TB;
633 //===----------------------------------------------------------------------===//
634 // FS/GS Base Instructions
635 let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
636 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
638 [(set GR32:$dst, (int_x86_rdfsbase_32))],
639 IIC_SEGMENT_BASE_R>, XS;
640 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
642 [(set GR64:$dst, (int_x86_rdfsbase_64))],
643 IIC_SEGMENT_BASE_R>, XS;
644 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
646 [(set GR32:$dst, (int_x86_rdgsbase_32))],
647 IIC_SEGMENT_BASE_R>, XS;
648 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
650 [(set GR64:$dst, (int_x86_rdgsbase_64))],
651 IIC_SEGMENT_BASE_R>, XS;
652 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
654 [(int_x86_wrfsbase_32 GR32:$src)],
655 IIC_SEGMENT_BASE_W>, XS;
656 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
658 [(int_x86_wrfsbase_64 GR64:$src)],
659 IIC_SEGMENT_BASE_W>, XS;
660 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
662 [(int_x86_wrgsbase_32 GR32:$src)], IIC_SEGMENT_BASE_W>, XS;
663 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
665 [(int_x86_wrgsbase_64 GR64:$src)],
666 IIC_SEGMENT_BASE_W>, XS;
669 //===----------------------------------------------------------------------===//
670 // INVPCID Instruction
671 let SchedRW = [WriteSystem] in {
672 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
673 "invpcid\t{$src2, $src1|$src1, $src2}", [], IIC_INVPCID>, T8PD,
674 Requires<[Not64BitMode]>;
675 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
676 "invpcid\t{$src2, $src1|$src1, $src2}", [], IIC_INVPCID>, T8PD,
677 Requires<[In64BitMode]>;
680 //===----------------------------------------------------------------------===//
682 let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
683 def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", [], IIC_SMAP>, TB;
684 def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", [], IIC_SMAP>, TB;
687 //===----------------------------------------------------------------------===//
689 let SchedRW = [WriteSystem] in {
690 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
691 def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", [], IIC_SMX>, TB;
695 //===----------------------------------------------------------------------===//
696 // TS flag control instruction.
697 let SchedRW = [WriteSystem] in {
698 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
701 //===----------------------------------------------------------------------===//
702 // IF (inside EFLAGS) management instructions.
703 let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
704 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
705 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
708 //===----------------------------------------------------------------------===//
710 let SchedRW = [WriteSystem] in {
711 def RDPID32 : I<0xC7, MRM7r, (outs GR32:$src), (ins),
712 "rdpid\t$src", [], IIC_RDPID>, XS,
713 Requires<[Not64BitMode]>;
714 def RDPID64 : I<0xC7, MRM7r, (outs GR64:$src), (ins),
715 "rdpid\t$src", [], IIC_RDPID>, XS,
716 Requires<[In64BitMode]>;
719 //===----------------------------------------------------------------------===//
720 // PTWRITE Instruction
721 let SchedRW = [WriteSystem] in {
723 def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
724 "ptwrite{l}\t$dst", [], IIC_PTWRITE>, XS;
725 def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
726 "ptwrite{q}\t$dst", [], IIC_PTWRITE>, XS,
727 Requires<[In64BitMode]>;
729 def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
730 "ptwrite{l}\t$dst", [], IIC_PTWRITE>, XS;
731 def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
732 "ptwrite{q}\t$dst", [], IIC_PTWRITE>, XS,
733 Requires<[In64BitMode]>;