1 //===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes XOP (eXtended OPerations)
12 //===----------------------------------------------------------------------===//
14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
16 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
17 [(set VR128:$dst, (Int VR128:$src))]>, XOP;
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
19 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
20 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
23 let ExeDomain = SSEPackedInt in {
24 defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, loadv2i64>;
25 defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, loadv2i64>;
26 defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, loadv2i64>;
27 defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, loadv2i64>;
28 defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, loadv2i64>;
29 defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, loadv2i64>;
30 defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, loadv2i64>;
31 defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, loadv2i64>;
32 defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, loadv2i64>;
33 defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, loadv2i64>;
34 defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, loadv2i64>;
35 defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, loadv2i64>;
36 defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, loadv2i64>;
37 defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, loadv2i64>;
38 defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, loadv2i64>;
41 // Scalar load 2 addr operand instructions
42 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
43 Operand memop, ComplexPattern mem_cpat> {
44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
45 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
46 [(set VR128:$dst, (Int VR128:$src))]>, XOP;
47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
48 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
49 [(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP;
52 multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
54 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
55 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
56 [(set VR128:$dst, (Int VR128:$src))]>, XOP;
57 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
58 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
59 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
62 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
64 def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
65 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
66 [(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L;
67 def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
68 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
69 [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L;
72 let ExeDomain = SSEPackedSingle in {
73 defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
75 defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, loadv4f32>;
76 defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, loadv8f32>;
79 let ExeDomain = SSEPackedDouble in {
80 defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
82 defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, loadv2f64>;
83 defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, loadv4f64>;
86 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
88 def rr : IXOP<opc, MRMSrcReg4VOp3, (outs VR128:$dst),
89 (ins VR128:$src1, VR128:$src2),
90 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
92 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
93 XOP, Sched<[WriteVarVecShift]>;
94 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
95 (ins VR128:$src1, i128mem:$src2),
96 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
98 (vt128 (OpNode (vt128 VR128:$src1),
99 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
100 XOP_4V, VEX_W, Sched<[WriteVarVecShift, ReadAfterLd]>;
101 def mr : IXOP<opc, MRMSrcMem4VOp3, (outs VR128:$dst),
102 (ins i128mem:$src1, VR128:$src2),
103 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
105 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))),
106 (vt128 VR128:$src2))))]>,
107 XOP, Sched<[WriteVarVecShift, ReadAfterLd]>;
109 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
110 def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
111 (ins VR128:$src1, VR128:$src2),
112 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
114 XOP_4V, VEX_W, Sched<[WriteVarVecShift]>, FoldGenData<NAME#rr>;
117 let ExeDomain = SSEPackedInt in {
118 defm VPROTB : xop3op<0x90, "vprotb", X86vprot, v16i8>;
119 defm VPROTD : xop3op<0x92, "vprotd", X86vprot, v4i32>;
120 defm VPROTQ : xop3op<0x93, "vprotq", X86vprot, v2i64>;
121 defm VPROTW : xop3op<0x91, "vprotw", X86vprot, v8i16>;
122 defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8>;
123 defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32>;
124 defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64>;
125 defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16>;
126 defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8>;
127 defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32>;
128 defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64>;
129 defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16>;
132 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
134 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
135 (ins VR128:$src1, u8imm:$src2),
136 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
138 (vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>, XOP;
139 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
140 (ins i128mem:$src1, u8imm:$src2),
141 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
143 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>, XOP;
146 let ExeDomain = SSEPackedInt in {
147 defm VPROTB : xop3opimm<0xC0, "vprotb", X86vproti, v16i8>;
148 defm VPROTD : xop3opimm<0xC2, "vprotd", X86vproti, v4i32>;
149 defm VPROTQ : xop3opimm<0xC3, "vprotq", X86vproti, v2i64>;
150 defm VPROTW : xop3opimm<0xC1, "vprotw", X86vproti, v8i16>;
153 // Instruction where second source can be memory, but third must be register
154 multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
155 let isCommutable = 1 in
156 def rr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
157 (ins VR128:$src1, VR128:$src2, VR128:$src3),
158 !strconcat(OpcodeStr,
159 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
161 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V;
162 def rm : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst),
163 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
164 !strconcat(OpcodeStr,
165 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
167 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
168 VR128:$src3))]>, XOP_4V;
171 let ExeDomain = SSEPackedInt in {
172 defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
173 defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
174 defm VPMACSWW : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
175 defm VPMACSWD : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
176 defm VPMACSSWW : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
177 defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
178 defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
179 defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
180 defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
181 defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
182 defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
183 defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
186 // IFMA patterns - for cases where we can safely ignore the overflow bits from
187 // the multiply or easily match with existing intrinsics.
188 let Predicates = [HasXOP] in {
189 def : Pat<(v8i16 (add (mul (v8i16 VR128:$src1), (v8i16 VR128:$src2)),
190 (v8i16 VR128:$src3))),
191 (VPMACSWWrr VR128:$src1, VR128:$src2, VR128:$src3)>;
192 def : Pat<(v4i32 (add (mul (v4i32 VR128:$src1), (v4i32 VR128:$src2)),
193 (v4i32 VR128:$src3))),
194 (VPMACSDDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
195 def : Pat<(v2i64 (add (X86pmuldq (X86PShufd (v4i32 VR128:$src1), (i8 -11)),
196 (X86PShufd (v4i32 VR128:$src2), (i8 -11))),
197 (v2i64 VR128:$src3))),
198 (VPMACSDQHrr VR128:$src1, VR128:$src2, VR128:$src3)>;
199 def : Pat<(v2i64 (add (X86pmuldq (v4i32 VR128:$src1), (v4i32 VR128:$src2)),
200 (v2i64 VR128:$src3))),
201 (VPMACSDQLrr VR128:$src1, VR128:$src2, VR128:$src3)>;
202 def : Pat<(v4i32 (add (X86vpmaddwd (v8i16 VR128:$src1), (v8i16 VR128:$src2)),
203 (v4i32 VR128:$src3))),
204 (VPMADCSWDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
207 // Instruction where second source can be memory, third must be imm8
208 multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128> {
209 let isCommutable = 1 in
210 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
211 (ins VR128:$src1, VR128:$src2, XOPCC:$cc),
212 !strconcat("vpcom${cc}", Suffix,
213 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
215 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
218 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
219 (ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
220 !strconcat("vpcom${cc}", Suffix,
221 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
223 (vt128 (OpNode (vt128 VR128:$src1),
224 (vt128 (bitconvert (loadv2i64 addr:$src2))),
227 let isAsmParserOnly = 1, hasSideEffects = 0 in {
228 def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
229 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
230 !strconcat("vpcom", Suffix,
231 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
234 def mi_alt : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
235 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
236 !strconcat("vpcom", Suffix,
237 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
242 let ExeDomain = SSEPackedInt in { // SSE integer instructions
243 defm VPCOMB : xopvpcom<0xCC, "b", X86vpcom, v16i8>;
244 defm VPCOMW : xopvpcom<0xCD, "w", X86vpcom, v8i16>;
245 defm VPCOMD : xopvpcom<0xCE, "d", X86vpcom, v4i32>;
246 defm VPCOMQ : xopvpcom<0xCF, "q", X86vpcom, v2i64>;
247 defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8>;
248 defm VPCOMUW : xopvpcom<0xED, "uw", X86vpcomu, v8i16>;
249 defm VPCOMUD : xopvpcom<0xEE, "ud", X86vpcomu, v4i32>;
250 defm VPCOMUQ : xopvpcom<0xEF, "uq", X86vpcomu, v2i64>;
253 multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
255 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
256 (ins VR128:$src1, VR128:$src2, VR128:$src3),
257 !strconcat(OpcodeStr,
258 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
260 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
261 (vt128 VR128:$src3))))]>,
263 def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs VR128:$dst),
264 (ins VR128:$src1, VR128:$src2, i128mem:$src3),
265 !strconcat(OpcodeStr,
266 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
268 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
269 (vt128 (bitconvert (loadv2i64 addr:$src3))))))]>,
271 def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst),
272 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
273 !strconcat(OpcodeStr,
274 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
276 (v16i8 (OpNode (vt128 VR128:$src1), (vt128 (bitconvert (loadv2i64 addr:$src2))),
277 (vt128 VR128:$src3))))]>,
280 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
281 def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs VR128:$dst),
282 (ins VR128:$src1, VR128:$src2, VR128:$src3),
283 !strconcat(OpcodeStr,
284 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
285 []>, XOP_4V, VEX_W, FoldGenData<NAME#rrr>;
288 let ExeDomain = SSEPackedInt in {
289 defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8>;
292 // Instruction where either second or third source can be memory
293 multiclass xop4op_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
294 X86MemOperand x86memop, ValueType VT> {
295 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs RC:$dst),
296 (ins RC:$src1, RC:$src2, RC:$src3),
297 !strconcat(OpcodeStr,
298 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
299 [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
300 (X86andnp RC:$src3, RC:$src2))))]>, XOP_4V;
301 def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs RC:$dst),
302 (ins RC:$src1, RC:$src2, x86memop:$src3),
303 !strconcat(OpcodeStr,
304 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
305 [(set RC:$dst, (VT (or (and (load addr:$src3), RC:$src1),
306 (X86andnp (load addr:$src3), RC:$src2))))]>,
308 def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs RC:$dst),
309 (ins RC:$src1, x86memop:$src2, RC:$src3),
310 !strconcat(OpcodeStr,
311 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
312 [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
313 (X86andnp RC:$src3, (load addr:$src2)))))]>,
316 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
317 def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs RC:$dst),
318 (ins RC:$src1, RC:$src2, RC:$src3),
319 !strconcat(OpcodeStr,
320 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
321 []>, XOP_4V, VEX_W, FoldGenData<NAME#rrr>;
324 let ExeDomain = SSEPackedInt in {
325 defm VPCMOV : xop4op_int<0xA2, "vpcmov", VR128, i128mem, v2i64>;
326 defm VPCMOVY : xop4op_int<0xA2, "vpcmov", VR256, i256mem, v4i64>, VEX_L;
329 multiclass xop_vpermil2<bits<8> Opc, string OpcodeStr, RegisterClass RC,
330 X86MemOperand intmemop, X86MemOperand fpmemop,
331 ValueType VT, PatFrag FPLdFrag,
333 def rr : IXOP5<Opc, MRMSrcReg, (outs RC:$dst),
334 (ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4),
335 !strconcat(OpcodeStr,
336 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
338 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 imm:$src4))))]>;
339 def rm : IXOP5<Opc, MRMSrcMemOp4, (outs RC:$dst),
340 (ins RC:$src1, RC:$src2, intmemop:$src3, u8imm:$src4),
341 !strconcat(OpcodeStr,
342 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
344 (VT (X86vpermil2 RC:$src1, RC:$src2,
345 (bitconvert (IntLdFrag addr:$src3)),
346 (i8 imm:$src4))))]>, VEX_W;
347 def mr : IXOP5<Opc, MRMSrcMem, (outs RC:$dst),
348 (ins RC:$src1, fpmemop:$src2, RC:$src3, u8imm:$src4),
349 !strconcat(OpcodeStr,
350 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
352 (VT (X86vpermil2 RC:$src1, (FPLdFrag addr:$src2),
353 RC:$src3, (i8 imm:$src4))))]>;
355 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
356 def rr_REV : IXOP5<Opc, MRMSrcRegOp4, (outs RC:$dst),
357 (ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4),
358 !strconcat(OpcodeStr,
359 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
360 []>, VEX_W, FoldGenData<NAME#rr>;
363 let ExeDomain = SSEPackedDouble in {
364 defm VPERMIL2PD : xop_vpermil2<0x49, "vpermil2pd", VR128, i128mem, f128mem,
365 v2f64, loadv2f64, loadv2i64>;
366 defm VPERMIL2PDY : xop_vpermil2<0x49, "vpermil2pd", VR256, i256mem, f256mem,
367 v4f64, loadv4f64, loadv4i64>, VEX_L;
370 let ExeDomain = SSEPackedSingle in {
371 defm VPERMIL2PS : xop_vpermil2<0x48, "vpermil2ps", VR128, i128mem, f128mem,
372 v4f32, loadv4f32, loadv2i64>;
373 defm VPERMIL2PSY : xop_vpermil2<0x48, "vpermil2ps", VR256, i256mem, f256mem,
374 v8f32, loadv8f32, loadv4i64>, VEX_L;