1 //===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the targeting of the Machinelegalizer class for X86.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #include "X86LegalizerInfo.h"
15 #include "X86Subtarget.h"
16 #include "X86TargetMachine.h"
17 #include "llvm/CodeGen/ValueTypes.h"
18 #include "llvm/IR/DerivedTypes.h"
19 #include "llvm/IR/Type.h"
20 #include "llvm/Target/TargetOpcodes.h"
23 using namespace TargetOpcode;
25 #ifndef LLVM_BUILD_GLOBAL_ISEL
26 #error "You shouldn't build this"
29 X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
30 const X86TargetMachine &TM)
31 : Subtarget(STI), TM(TM) {
33 setLegalizerInfo32bit();
34 setLegalizerInfo64bit();
35 setLegalizerInfoSSE1();
36 setLegalizerInfoSSE2();
37 setLegalizerInfoSSE41();
38 setLegalizerInfoAVX2();
39 setLegalizerInfoAVX512();
40 setLegalizerInfoAVX512DQ();
41 setLegalizerInfoAVX512BW();
46 void X86LegalizerInfo::setLegalizerInfo32bit() {
48 if (Subtarget.is64Bit())
51 const LLT p0 = LLT::pointer(0, 32);
52 const LLT s1 = LLT::scalar(1);
53 const LLT s8 = LLT::scalar(8);
54 const LLT s16 = LLT::scalar(16);
55 const LLT s32 = LLT::scalar(32);
56 const LLT s64 = LLT::scalar(64);
58 for (unsigned BinOp : {G_ADD, G_SUB, G_MUL})
59 for (auto Ty : {s8, s16, s32})
60 setAction({BinOp, Ty}, Legal);
62 for (unsigned Op : {G_UADDE}) {
63 setAction({Op, s32}, Legal);
64 setAction({Op, 1, s1}, Legal);
67 for (unsigned MemOp : {G_LOAD, G_STORE}) {
68 for (auto Ty : {s8, s16, s32, p0})
69 setAction({MemOp, Ty}, Legal);
71 // And everything's fine in addrspace 0.
72 setAction({MemOp, 1, p0}, Legal);
76 setAction({G_FRAME_INDEX, p0}, Legal);
78 setAction({G_GEP, p0}, Legal);
79 setAction({G_GEP, 1, s32}, Legal);
81 for (auto Ty : {s1, s8, s16})
82 setAction({G_GEP, 1, Ty}, WidenScalar);
85 for (auto Ty : {s8, s16, s32, p0})
86 setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
88 setAction({TargetOpcode::G_CONSTANT, s1}, WidenScalar);
89 setAction({TargetOpcode::G_CONSTANT, s64}, NarrowScalar);
92 setAction({G_ZEXT, s32}, Legal);
93 setAction({G_SEXT, s32}, Legal);
95 for (auto Ty : {s1, s8, s16}) {
96 setAction({G_ZEXT, 1, Ty}, Legal);
97 setAction({G_SEXT, 1, Ty}, Legal);
101 setAction({G_ICMP, s1}, Legal);
103 for (auto Ty : {s8, s16, s32, p0})
104 setAction({G_ICMP, 1, Ty}, Legal);
107 void X86LegalizerInfo::setLegalizerInfo64bit() {
109 if (!Subtarget.is64Bit())
112 const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8);
113 const LLT s1 = LLT::scalar(1);
114 const LLT s8 = LLT::scalar(8);
115 const LLT s16 = LLT::scalar(16);
116 const LLT s32 = LLT::scalar(32);
117 const LLT s64 = LLT::scalar(64);
119 for (unsigned BinOp : {G_ADD, G_SUB, G_MUL})
120 for (auto Ty : {s8, s16, s32, s64})
121 setAction({BinOp, Ty}, Legal);
123 for (unsigned MemOp : {G_LOAD, G_STORE}) {
124 for (auto Ty : {s8, s16, s32, s64, p0})
125 setAction({MemOp, Ty}, Legal);
127 // And everything's fine in addrspace 0.
128 setAction({MemOp, 1, p0}, Legal);
132 setAction({G_FRAME_INDEX, p0}, Legal);
134 setAction({G_GEP, p0}, Legal);
135 setAction({G_GEP, 1, s32}, Legal);
136 setAction({G_GEP, 1, s64}, Legal);
138 for (auto Ty : {s1, s8, s16})
139 setAction({G_GEP, 1, Ty}, WidenScalar);
142 for (auto Ty : {s8, s16, s32, s64, p0})
143 setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
145 setAction({TargetOpcode::G_CONSTANT, s1}, WidenScalar);
148 for (auto Ty : {s32, s64}) {
149 setAction({G_ZEXT, Ty}, Legal);
150 setAction({G_SEXT, Ty}, Legal);
153 for (auto Ty : {s1, s8, s16, s32}) {
154 setAction({G_ZEXT, 1, Ty}, Legal);
155 setAction({G_SEXT, 1, Ty}, Legal);
159 setAction({G_ICMP, s1}, Legal);
161 for (auto Ty : {s8, s16, s32, s64, p0})
162 setAction({G_ICMP, 1, Ty}, Legal);
165 void X86LegalizerInfo::setLegalizerInfoSSE1() {
166 if (!Subtarget.hasSSE1())
169 const LLT s32 = LLT::scalar(32);
170 const LLT v4s32 = LLT::vector(4, 32);
171 const LLT v2s64 = LLT::vector(2, 64);
173 for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
174 for (auto Ty : {s32, v4s32})
175 setAction({BinOp, Ty}, Legal);
177 for (unsigned MemOp : {G_LOAD, G_STORE})
178 for (auto Ty : {v4s32, v2s64})
179 setAction({MemOp, Ty}, Legal);
182 void X86LegalizerInfo::setLegalizerInfoSSE2() {
183 if (!Subtarget.hasSSE2())
186 const LLT s64 = LLT::scalar(64);
187 const LLT v16s8 = LLT::vector(16, 8);
188 const LLT v8s16 = LLT::vector(8, 16);
189 const LLT v4s32 = LLT::vector(4, 32);
190 const LLT v2s64 = LLT::vector(2, 64);
192 for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
193 for (auto Ty : {s64, v2s64})
194 setAction({BinOp, Ty}, Legal);
196 for (unsigned BinOp : {G_ADD, G_SUB})
197 for (auto Ty : {v16s8, v8s16, v4s32, v2s64})
198 setAction({BinOp, Ty}, Legal);
200 setAction({G_MUL, v8s16}, Legal);
203 void X86LegalizerInfo::setLegalizerInfoSSE41() {
204 if (!Subtarget.hasSSE41())
207 const LLT v4s32 = LLT::vector(4, 32);
209 setAction({G_MUL, v4s32}, Legal);
212 void X86LegalizerInfo::setLegalizerInfoAVX2() {
213 if (!Subtarget.hasAVX2())
216 const LLT v32s8 = LLT::vector(32, 8);
217 const LLT v16s16 = LLT::vector(16, 16);
218 const LLT v8s32 = LLT::vector(8, 32);
219 const LLT v4s64 = LLT::vector(4, 64);
221 for (unsigned BinOp : {G_ADD, G_SUB})
222 for (auto Ty : {v32s8, v16s16, v8s32, v4s64})
223 setAction({BinOp, Ty}, Legal);
225 for (auto Ty : {v16s16, v8s32})
226 setAction({G_MUL, Ty}, Legal);
229 void X86LegalizerInfo::setLegalizerInfoAVX512() {
230 if (!Subtarget.hasAVX512())
233 const LLT v16s32 = LLT::vector(16, 32);
234 const LLT v8s64 = LLT::vector(8, 64);
236 for (unsigned BinOp : {G_ADD, G_SUB})
237 for (auto Ty : {v16s32, v8s64})
238 setAction({BinOp, Ty}, Legal);
240 setAction({G_MUL, v16s32}, Legal);
242 /************ VLX *******************/
243 if (!Subtarget.hasVLX())
246 const LLT v4s32 = LLT::vector(4, 32);
247 const LLT v8s32 = LLT::vector(8, 32);
249 for (auto Ty : {v4s32, v8s32})
250 setAction({G_MUL, Ty}, Legal);
253 void X86LegalizerInfo::setLegalizerInfoAVX512DQ() {
254 if (!(Subtarget.hasAVX512() && Subtarget.hasDQI()))
257 const LLT v8s64 = LLT::vector(8, 64);
259 setAction({G_MUL, v8s64}, Legal);
261 /************ VLX *******************/
262 if (!Subtarget.hasVLX())
265 const LLT v2s64 = LLT::vector(2, 64);
266 const LLT v4s64 = LLT::vector(4, 64);
268 for (auto Ty : {v2s64, v4s64})
269 setAction({G_MUL, Ty}, Legal);
272 void X86LegalizerInfo::setLegalizerInfoAVX512BW() {
273 if (!(Subtarget.hasAVX512() && Subtarget.hasBWI()))
276 const LLT v64s8 = LLT::vector(64, 8);
277 const LLT v32s16 = LLT::vector(32, 16);
279 for (unsigned BinOp : {G_ADD, G_SUB})
280 for (auto Ty : {v64s8, v32s16})
281 setAction({BinOp, Ty}, Legal);
283 setAction({G_MUL, v32s16}, Legal);
285 /************ VLX *******************/
286 if (!Subtarget.hasVLX())
289 const LLT v8s16 = LLT::vector(8, 16);
290 const LLT v16s16 = LLT::vector(16, 16);
292 for (auto Ty : {v8s16, v16s16})
293 setAction({G_MUL, Ty}, Legal);