1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
47 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
48 cl::desc("Enable use of a base pointer for complex stack frames"));
50 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
51 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
52 X86_MC::getDwarfRegFlavour(TT, false),
53 X86_MC::getDwarfRegFlavour(TT, true),
54 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
55 X86_MC::initLLVMToSEHAndCVRegMapping(this);
57 // Cache some information.
58 Is64Bit = TT.isArch64Bit();
59 IsWin64 = Is64Bit && TT.isOSWindows();
61 // Use a callee-saved register as the base pointer. These registers must
62 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
63 // requires GOT in the EBX register before function calls via PLT GOT pointer.
66 // This matches the simplified 32-bit pointer code in the data layout
68 // FIXME: Should use the data layout?
69 bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
70 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
71 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
72 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
82 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
83 // ExecutionDepsFixer and PostRAScheduler require liveness.
88 X86RegisterInfo::getSEHRegNum(unsigned i) const {
89 return getEncodingValue(i);
92 const TargetRegisterClass *
93 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
95 // The sub_8bit sub-register index is more constrained in 32-bit mode.
96 // It behaves just like the sub_8bit_hi index.
97 if (!Is64Bit && Idx == X86::sub_8bit)
98 Idx = X86::sub_8bit_hi;
100 // Forward to TableGen's default version.
101 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
104 const TargetRegisterClass *
105 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
106 const TargetRegisterClass *B,
107 unsigned SubIdx) const {
108 // The sub_8bit sub-register index is more constrained in 32-bit mode.
109 if (!Is64Bit && SubIdx == X86::sub_8bit) {
110 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
114 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
117 const TargetRegisterClass *
118 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
119 const MachineFunction &MF) const {
120 // Don't allow super-classes of GR8_NOREX. This class is only used after
121 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
122 // to the full GR8 register class in 64-bit mode, so we cannot allow the
123 // reigster class inflation.
125 // The GR8_NOREX class is always used in a way that won't be constrained to a
126 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
128 if (RC == &X86::GR8_NOREXRegClass)
131 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
133 const TargetRegisterClass *Super = RC;
134 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
136 switch (Super->getID()) {
137 case X86::FR32RegClassID:
138 case X86::FR64RegClassID:
139 // If AVX-512 isn't supported we should only inflate to these classes.
140 if (!Subtarget.hasAVX512() &&
141 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
144 case X86::VR128RegClassID:
145 case X86::VR256RegClassID:
146 // If VLX isn't supported we should only inflate to these classes.
147 if (!Subtarget.hasVLX() &&
148 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
151 case X86::VR128XRegClassID:
152 case X86::VR256XRegClassID:
153 // If VLX isn't support we shouldn't inflate to these classes.
154 if (Subtarget.hasVLX() &&
155 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
158 case X86::FR32XRegClassID:
159 case X86::FR64XRegClassID:
160 // If AVX-512 isn't support we shouldn't inflate to these classes.
161 if (Subtarget.hasAVX512() &&
162 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
165 case X86::GR8RegClassID:
166 case X86::GR16RegClassID:
167 case X86::GR32RegClassID:
168 case X86::GR64RegClassID:
169 case X86::RFP32RegClassID:
170 case X86::RFP64RegClassID:
171 case X86::RFP80RegClassID:
172 case X86::VR512RegClassID:
173 // Don't return a super-class that would shrink the spill size.
174 // That can happen with the vector and float classes.
175 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
183 const TargetRegisterClass *
184 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
185 unsigned Kind) const {
186 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
188 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
189 case 0: // Normal GPRs.
190 if (Subtarget.isTarget64BitLP64())
191 return &X86::GR64RegClass;
192 // If the target is 64bit but we have been told to use 32bit addresses,
193 // we can still use 64-bit register as long as we know the high bits
195 // Reflect that in the returned register class.
197 // When the target also allows 64-bit frame pointer and we do have a
198 // frame, this is fine to use it for the address accesses as well.
199 const X86FrameLowering *TFI = getFrameLowering(MF);
200 return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
201 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
202 : &X86::LOW32_ADDR_ACCESSRegClass;
204 return &X86::GR32RegClass;
205 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
206 if (Subtarget.isTarget64BitLP64())
207 return &X86::GR64_NOSPRegClass;
208 // NOSP does not contain RIP, so no special case here.
209 return &X86::GR32_NOSPRegClass;
210 case 2: // NOREX GPRs.
211 if (Subtarget.isTarget64BitLP64())
212 return &X86::GR64_NOREXRegClass;
213 return &X86::GR32_NOREXRegClass;
214 case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
215 if (Subtarget.isTarget64BitLP64())
216 return &X86::GR64_NOREX_NOSPRegClass;
217 // NOSP does not contain RIP, so no special case here.
218 return &X86::GR32_NOREX_NOSPRegClass;
219 case 4: // Available for tailcall (not callee-saved GPRs).
220 return getGPRsForTailCall(MF);
224 const TargetRegisterClass *
225 X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
226 const Function *F = MF.getFunction();
227 if (IsWin64 || (F && F->getCallingConv() == CallingConv::X86_64_Win64))
228 return &X86::GR64_TCW64RegClass;
230 return &X86::GR64_TCRegClass;
232 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
234 return &X86::GR32RegClass;
235 return &X86::GR32_TCRegClass;
238 const TargetRegisterClass *
239 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
240 if (RC == &X86::CCRRegClass) {
242 return &X86::GR64RegClass;
244 return &X86::GR32RegClass;
250 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
251 MachineFunction &MF) const {
252 const X86FrameLowering *TFI = getFrameLowering(MF);
254 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
255 switch (RC->getID()) {
258 case X86::GR32RegClassID:
260 case X86::GR64RegClassID:
262 case X86::VR128RegClassID:
263 return Is64Bit ? 10 : 4;
264 case X86::VR64RegClassID:
270 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
271 assert(MF && "MachineFunction required");
273 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
274 bool HasSSE = Subtarget.hasSSE1();
275 bool HasAVX = Subtarget.hasAVX();
276 bool HasAVX512 = Subtarget.hasAVX512();
277 bool CallsEHReturn = MF->callsEHReturn();
279 CallingConv::ID CC = MF->getFunction()->getCallingConv();
281 // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
282 // convention because it has the CSR list.
283 if (MF->getFunction()->hasFnAttribute("no_caller_saved_registers"))
284 CC = CallingConv::X86_INTR;
287 case CallingConv::GHC:
288 case CallingConv::HiPE:
289 return CSR_NoRegs_SaveList;
290 case CallingConv::AnyReg:
292 return CSR_64_AllRegs_AVX_SaveList;
293 return CSR_64_AllRegs_SaveList;
294 case CallingConv::PreserveMost:
295 return CSR_64_RT_MostRegs_SaveList;
296 case CallingConv::PreserveAll:
298 return CSR_64_RT_AllRegs_AVX_SaveList;
299 return CSR_64_RT_AllRegs_SaveList;
300 case CallingConv::CXX_FAST_TLS:
302 return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
303 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
305 case CallingConv::Intel_OCL_BI: {
306 if (HasAVX512 && IsWin64)
307 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
308 if (HasAVX512 && Is64Bit)
309 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
310 if (HasAVX && IsWin64)
311 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
312 if (HasAVX && Is64Bit)
313 return CSR_64_Intel_OCL_BI_AVX_SaveList;
314 if (!HasAVX && !IsWin64 && Is64Bit)
315 return CSR_64_Intel_OCL_BI_SaveList;
318 case CallingConv::HHVM:
319 return CSR_64_HHVM_SaveList;
320 case CallingConv::X86_RegCall:
323 return (HasSSE ? CSR_Win64_RegCall_SaveList :
324 CSR_Win64_RegCall_NoSSE_SaveList);
326 return (HasSSE ? CSR_SysV64_RegCall_SaveList :
327 CSR_SysV64_RegCall_NoSSE_SaveList);
330 return (HasSSE ? CSR_32_RegCall_SaveList :
331 CSR_32_RegCall_NoSSE_SaveList);
333 case CallingConv::Cold:
335 return CSR_64_MostRegs_SaveList;
337 case CallingConv::X86_64_Win64:
339 return CSR_Win64_NoSSE_SaveList;
340 return CSR_Win64_SaveList;
341 case CallingConv::X86_64_SysV:
343 return CSR_64EHRet_SaveList;
344 return CSR_64_SaveList;
345 case CallingConv::X86_INTR:
348 return CSR_64_AllRegs_AVX512_SaveList;
350 return CSR_64_AllRegs_AVX_SaveList;
352 return CSR_64_AllRegs_SaveList;
353 return CSR_64_AllRegs_NoSSE_SaveList;
356 return CSR_32_AllRegs_AVX512_SaveList;
358 return CSR_32_AllRegs_AVX_SaveList;
360 return CSR_32_AllRegs_SSE_SaveList;
361 return CSR_32_AllRegs_SaveList;
370 return CSR_Win64_NoSSE_SaveList;
371 return CSR_Win64_SaveList;
374 return CSR_64EHRet_SaveList;
375 if (Subtarget.getTargetLowering()->supportSwiftError() &&
376 MF->getFunction()->getAttributes().hasAttrSomewhere(
377 Attribute::SwiftError))
378 return CSR_64_SwiftError_SaveList;
379 return CSR_64_SaveList;
382 return CSR_32EHRet_SaveList;
383 return CSR_32_SaveList;
386 const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
387 const MachineFunction *MF) const {
388 assert(MF && "Invalid MachineFunction pointer.");
389 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
390 MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
391 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
396 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
397 CallingConv::ID CC) const {
398 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
399 bool HasSSE = Subtarget.hasSSE1();
400 bool HasAVX = Subtarget.hasAVX();
401 bool HasAVX512 = Subtarget.hasAVX512();
404 case CallingConv::GHC:
405 case CallingConv::HiPE:
406 return CSR_NoRegs_RegMask;
407 case CallingConv::AnyReg:
409 return CSR_64_AllRegs_AVX_RegMask;
410 return CSR_64_AllRegs_RegMask;
411 case CallingConv::PreserveMost:
412 return CSR_64_RT_MostRegs_RegMask;
413 case CallingConv::PreserveAll:
415 return CSR_64_RT_AllRegs_AVX_RegMask;
416 return CSR_64_RT_AllRegs_RegMask;
417 case CallingConv::CXX_FAST_TLS:
419 return CSR_64_TLS_Darwin_RegMask;
421 case CallingConv::Intel_OCL_BI: {
422 if (HasAVX512 && IsWin64)
423 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
424 if (HasAVX512 && Is64Bit)
425 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
426 if (HasAVX && IsWin64)
427 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
428 if (HasAVX && Is64Bit)
429 return CSR_64_Intel_OCL_BI_AVX_RegMask;
430 if (!HasAVX && !IsWin64 && Is64Bit)
431 return CSR_64_Intel_OCL_BI_RegMask;
434 case CallingConv::HHVM:
435 return CSR_64_HHVM_RegMask;
436 case CallingConv::X86_RegCall:
439 return (HasSSE ? CSR_Win64_RegCall_RegMask :
440 CSR_Win64_RegCall_NoSSE_RegMask);
442 return (HasSSE ? CSR_SysV64_RegCall_RegMask :
443 CSR_SysV64_RegCall_NoSSE_RegMask);
446 return (HasSSE ? CSR_32_RegCall_RegMask :
447 CSR_32_RegCall_NoSSE_RegMask);
449 case CallingConv::Cold:
451 return CSR_64_MostRegs_RegMask;
453 case CallingConv::X86_64_Win64:
454 return CSR_Win64_RegMask;
455 case CallingConv::X86_64_SysV:
456 return CSR_64_RegMask;
457 case CallingConv::X86_INTR:
460 return CSR_64_AllRegs_AVX512_RegMask;
462 return CSR_64_AllRegs_AVX_RegMask;
464 return CSR_64_AllRegs_RegMask;
465 return CSR_64_AllRegs_NoSSE_RegMask;
468 return CSR_32_AllRegs_AVX512_RegMask;
470 return CSR_32_AllRegs_AVX_RegMask;
472 return CSR_32_AllRegs_SSE_RegMask;
473 return CSR_32_AllRegs_RegMask;
479 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
483 return CSR_Win64_RegMask;
484 if (Subtarget.getTargetLowering()->supportSwiftError() &&
485 MF.getFunction()->getAttributes().hasAttrSomewhere(
486 Attribute::SwiftError))
487 return CSR_64_SwiftError_RegMask;
488 return CSR_64_RegMask;
490 return CSR_32_RegMask;
494 X86RegisterInfo::getNoPreservedMask() const {
495 return CSR_NoRegs_RegMask;
498 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
499 return CSR_64_TLS_Darwin_RegMask;
502 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
503 BitVector Reserved(getNumRegs());
504 const X86FrameLowering *TFI = getFrameLowering(MF);
506 // Set the stack-pointer register and its aliases as reserved.
507 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
511 // Set the instruction pointer register and its aliases as reserved.
512 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
516 // Set the frame-pointer register and its aliases as reserved if needed.
517 if (TFI->hasFP(MF)) {
518 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
523 // Set the base-pointer register and its aliases as reserved if needed.
524 if (hasBasePointer(MF)) {
525 CallingConv::ID CC = MF.getFunction()->getCallingConv();
526 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
527 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
529 "Stack realignment in presence of dynamic allocas is not supported with"
530 "this calling convention.");
532 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
533 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
538 // Mark the segment registers as reserved.
539 Reserved.set(X86::CS);
540 Reserved.set(X86::SS);
541 Reserved.set(X86::DS);
542 Reserved.set(X86::ES);
543 Reserved.set(X86::FS);
544 Reserved.set(X86::GS);
546 // Mark the floating point stack registers as reserved.
547 for (unsigned n = 0; n != 8; ++n)
548 Reserved.set(X86::ST0 + n);
550 // Reserve the registers that only exist in 64-bit mode.
552 // These 8-bit registers are part of the x86-64 extension even though their
553 // super-registers are old 32-bits.
554 Reserved.set(X86::SIL);
555 Reserved.set(X86::DIL);
556 Reserved.set(X86::BPL);
557 Reserved.set(X86::SPL);
559 for (unsigned n = 0; n != 8; ++n) {
561 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
565 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
569 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
570 for (unsigned n = 16; n != 32; ++n) {
571 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
576 assert(checkAllSuperRegsMarked(Reserved,
577 {X86::SIL, X86::DIL, X86::BPL, X86::SPL}));
581 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
582 // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
583 // because the calling convention defines the EFLAGS register as NOT
586 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
587 // an assert to track this and clear the register afterwards to avoid
588 // unnecessary crashes during release builds.
589 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
590 "EFLAGS are not live-out from a patchpoint.");
592 // Also clean other registers that don't need preserving (IP).
593 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
594 Mask[Reg / 32] &= ~(1U << (Reg % 32));
597 //===----------------------------------------------------------------------===//
598 // Stack Frame Processing methods
599 //===----------------------------------------------------------------------===//
601 static bool CantUseSP(const MachineFrameInfo &MFI) {
602 return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
605 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
606 const MachineFrameInfo &MFI = MF.getFrameInfo();
608 if (!EnableBasePointer)
611 // When we need stack realignment, we can't address the stack from the frame
612 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
613 // can't address variables from the stack pointer. MS inline asm can
614 // reference locals while also adjusting the stack pointer. When we can't
615 // use both the SP and the FP, we need a separate base pointer register.
616 bool CantUseFP = needsStackRealignment(MF);
617 return CantUseFP && CantUseSP(MFI);
620 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
621 if (!TargetRegisterInfo::canRealignStack(MF))
624 const MachineFrameInfo &MFI = MF.getFrameInfo();
625 const MachineRegisterInfo *MRI = &MF.getRegInfo();
627 // Stack realignment requires a frame pointer. If we already started
628 // register allocation with frame pointer elimination, it is too late now.
629 if (!MRI->canReserveReg(FramePtr))
632 // If a base pointer is necessary. Check that it isn't too late to reserve
635 return MRI->canReserveReg(BasePtr);
639 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
640 unsigned Reg, int &FrameIdx) const {
641 // Since X86 defines assignCalleeSavedSpillSlots which always return true
642 // this function neither used nor tested.
643 llvm_unreachable("Unused function on X86. Otherwise need a test case.");
646 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
647 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
648 // TODO: In this case we should be really trying first to entirely eliminate
649 // this instruction which is a plain copy.
650 static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
651 MachineInstr &MI = *II;
652 unsigned Opc = II->getOpcode();
653 // Check if this is a LEA of the form 'lea (%esp), %ebx'
654 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
655 MI.getOperand(2).getImm() != 1 ||
656 MI.getOperand(3).getReg() != X86::NoRegister ||
657 MI.getOperand(4).getImm() != 0 ||
658 MI.getOperand(5).getReg() != X86::NoRegister)
660 unsigned BasePtr = MI.getOperand(1).getReg();
661 // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
662 // be replaced with a 32-bit operand MOV which will zero extend the upper
663 // 32-bits of the super register.
664 if (Opc == X86::LEA64_32r)
665 BasePtr = getX86SubSuperRegister(BasePtr, 32);
666 unsigned NewDestReg = MI.getOperand(0).getReg();
667 const X86InstrInfo *TII =
668 MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
669 TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
670 MI.getOperand(1).isKill());
671 MI.eraseFromParent();
676 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
677 int SPAdj, unsigned FIOperandNum,
678 RegScavenger *RS) const {
679 MachineInstr &MI = *II;
680 MachineFunction &MF = *MI.getParent()->getParent();
681 const X86FrameLowering *TFI = getFrameLowering(MF);
682 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
684 // Determine base register and offset.
688 assert((!needsStackRealignment(MF) ||
689 MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
690 "Return instruction can only reference SP relative frame objects");
691 FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0);
693 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr);
696 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
697 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
698 // offset is from the traditional base pointer location. On 64-bit, the
699 // offset is from the SP at the end of the prologue, not the FP location. This
700 // matches the behavior of llvm.frameaddress.
701 unsigned Opc = MI.getOpcode();
702 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
703 MachineOperand &FI = MI.getOperand(FIOperandNum);
704 FI.ChangeToImmediate(FIOffset);
708 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
709 // register as source operand, semantic is the same and destination is
710 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
711 // Don't change BasePtr since it is used later for stack adjustment.
712 unsigned MachineBasePtr = BasePtr;
713 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
714 MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
716 // This must be part of a four operand memory reference. Replace the
717 // FrameIndex with base register. Add an offset to the offset.
718 MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
720 if (BasePtr == StackPtr)
723 // The frame index format for stackmaps and patchpoints is different from the
724 // X86 format. It only has a FI and an offset.
725 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
726 assert(BasePtr == FramePtr && "Expected the FP as base register");
727 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
728 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
732 if (MI.getOperand(FIOperandNum+3).isImm()) {
733 // Offset is a 32-bit integer.
734 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
735 int Offset = FIOffset + Imm;
736 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
737 "Requesting 64-bit offset in 32-bit immediate!");
738 if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
739 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
741 // Offset is symbolic. This is extremely rare.
742 uint64_t Offset = FIOffset +
743 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
744 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
748 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
749 const X86FrameLowering *TFI = getFrameLowering(MF);
750 return TFI->hasFP(MF) ? FramePtr : StackPtr;
754 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
755 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
756 unsigned FrameReg = getFrameRegister(MF);
757 if (Subtarget.isTarget64BitILP32())
758 FrameReg = getX86SubSuperRegister(FrameReg, 32);