1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
47 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
48 cl::desc("Enable use of a base pointer for complex stack frames"));
50 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
51 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
52 X86_MC::getDwarfRegFlavour(TT, false),
53 X86_MC::getDwarfRegFlavour(TT, true),
54 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
55 X86_MC::initLLVMToSEHAndCVRegMapping(this);
57 // Cache some information.
58 Is64Bit = TT.isArch64Bit();
59 IsWin64 = Is64Bit && TT.isOSWindows();
61 // Use a callee-saved register as the base pointer. These registers must
62 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
63 // requires GOT in the EBX register before function calls via PLT GOT pointer.
66 // This matches the simplified 32-bit pointer code in the data layout
68 // FIXME: Should use the data layout?
69 bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
70 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
71 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
72 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
82 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
83 // ExeDepsFixer and PostRAScheduler require liveness.
88 X86RegisterInfo::getSEHRegNum(unsigned i) const {
89 return getEncodingValue(i);
92 const TargetRegisterClass *
93 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
95 // The sub_8bit sub-register index is more constrained in 32-bit mode.
96 // It behaves just like the sub_8bit_hi index.
97 if (!Is64Bit && Idx == X86::sub_8bit)
98 Idx = X86::sub_8bit_hi;
100 // Forward to TableGen's default version.
101 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
104 const TargetRegisterClass *
105 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
106 const TargetRegisterClass *B,
107 unsigned SubIdx) const {
108 // The sub_8bit sub-register index is more constrained in 32-bit mode.
109 if (!Is64Bit && SubIdx == X86::sub_8bit) {
110 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
114 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
117 const TargetRegisterClass *
118 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
119 const MachineFunction &MF) const {
120 // Don't allow super-classes of GR8_NOREX. This class is only used after
121 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
122 // to the full GR8 register class in 64-bit mode, so we cannot allow the
123 // reigster class inflation.
125 // The GR8_NOREX class is always used in a way that won't be constrained to a
126 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
128 if (RC == &X86::GR8_NOREXRegClass)
131 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
133 const TargetRegisterClass *Super = RC;
134 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
136 switch (Super->getID()) {
137 case X86::FR32RegClassID:
138 case X86::FR64RegClassID:
139 // If AVX-512 isn't supported we should only inflate to these classes.
140 if (!Subtarget.hasAVX512() && Super->getSize() == RC->getSize())
143 case X86::VR128RegClassID:
144 case X86::VR256RegClassID:
145 // If VLX isn't supported we should only inflate to these classes.
146 if (!Subtarget.hasVLX() && Super->getSize() == RC->getSize())
149 case X86::VR128XRegClassID:
150 case X86::VR256XRegClassID:
151 // If VLX isn't support we shouldn't inflate to these classes.
152 if (Subtarget.hasVLX() && Super->getSize() == RC->getSize())
155 case X86::FR32XRegClassID:
156 case X86::FR64XRegClassID:
157 // If AVX-512 isn't support we shouldn't inflate to these classes.
158 if (Subtarget.hasAVX512() && Super->getSize() == RC->getSize())
161 case X86::GR8RegClassID:
162 case X86::GR16RegClassID:
163 case X86::GR32RegClassID:
164 case X86::GR64RegClassID:
165 case X86::RFP32RegClassID:
166 case X86::RFP64RegClassID:
167 case X86::RFP80RegClassID:
168 case X86::VR512RegClassID:
169 // Don't return a super-class that would shrink the spill size.
170 // That can happen with the vector and float classes.
171 if (Super->getSize() == RC->getSize())
179 const TargetRegisterClass *
180 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
181 unsigned Kind) const {
182 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
184 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
185 case 0: // Normal GPRs.
186 if (Subtarget.isTarget64BitLP64())
187 return &X86::GR64RegClass;
188 // If the target is 64bit but we have been told to use 32bit addresses,
189 // we can still use 64-bit register as long as we know the high bits
191 // Reflect that in the returned register class.
193 // When the target also allows 64-bit frame pointer and we do have a
194 // frame, this is fine to use it for the address accesses as well.
195 const X86FrameLowering *TFI = getFrameLowering(MF);
196 return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
197 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
198 : &X86::LOW32_ADDR_ACCESSRegClass;
200 return &X86::GR32RegClass;
201 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
202 if (Subtarget.isTarget64BitLP64())
203 return &X86::GR64_NOSPRegClass;
204 // NOSP does not contain RIP, so no special case here.
205 return &X86::GR32_NOSPRegClass;
206 case 2: // NOREX GPRs.
207 if (Subtarget.isTarget64BitLP64())
208 return &X86::GR64_NOREXRegClass;
209 return &X86::GR32_NOREXRegClass;
210 case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
211 if (Subtarget.isTarget64BitLP64())
212 return &X86::GR64_NOREX_NOSPRegClass;
213 // NOSP does not contain RIP, so no special case here.
214 return &X86::GR32_NOREX_NOSPRegClass;
215 case 4: // Available for tailcall (not callee-saved GPRs).
216 return getGPRsForTailCall(MF);
220 const TargetRegisterClass *
221 X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
222 const Function *F = MF.getFunction();
223 if (IsWin64 || (F && F->getCallingConv() == CallingConv::X86_64_Win64))
224 return &X86::GR64_TCW64RegClass;
226 return &X86::GR64_TCRegClass;
228 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
230 return &X86::GR32RegClass;
231 return &X86::GR32_TCRegClass;
234 const TargetRegisterClass *
235 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
236 if (RC == &X86::CCRRegClass) {
238 return &X86::GR64RegClass;
240 return &X86::GR32RegClass;
246 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
247 MachineFunction &MF) const {
248 const X86FrameLowering *TFI = getFrameLowering(MF);
250 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
251 switch (RC->getID()) {
254 case X86::GR32RegClassID:
256 case X86::GR64RegClassID:
258 case X86::VR128RegClassID:
259 return Is64Bit ? 10 : 4;
260 case X86::VR64RegClassID:
266 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
267 assert(MF && "MachineFunction required");
269 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
270 bool HasSSE = Subtarget.hasSSE1();
271 bool HasAVX = Subtarget.hasAVX();
272 bool HasAVX512 = Subtarget.hasAVX512();
273 bool CallsEHReturn = MF->callsEHReturn();
275 switch (MF->getFunction()->getCallingConv()) {
276 case CallingConv::GHC:
277 case CallingConv::HiPE:
278 return CSR_NoRegs_SaveList;
279 case CallingConv::AnyReg:
281 return CSR_64_AllRegs_AVX_SaveList;
282 return CSR_64_AllRegs_SaveList;
283 case CallingConv::PreserveMost:
284 return CSR_64_RT_MostRegs_SaveList;
285 case CallingConv::PreserveAll:
287 return CSR_64_RT_AllRegs_AVX_SaveList;
288 return CSR_64_RT_AllRegs_SaveList;
289 case CallingConv::CXX_FAST_TLS:
291 return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
292 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
294 case CallingConv::Intel_OCL_BI: {
295 if (HasAVX512 && IsWin64)
296 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
297 if (HasAVX512 && Is64Bit)
298 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
299 if (HasAVX && IsWin64)
300 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
301 if (HasAVX && Is64Bit)
302 return CSR_64_Intel_OCL_BI_AVX_SaveList;
303 if (!HasAVX && !IsWin64 && Is64Bit)
304 return CSR_64_Intel_OCL_BI_SaveList;
307 case CallingConv::HHVM:
308 return CSR_64_HHVM_SaveList;
309 case CallingConv::X86_RegCall:
312 return (HasSSE ? CSR_Win64_RegCall_SaveList :
313 CSR_Win64_RegCall_NoSSE_SaveList);
315 return (HasSSE ? CSR_SysV64_RegCall_SaveList :
316 CSR_SysV64_RegCall_NoSSE_SaveList);
319 return (HasSSE ? CSR_32_RegCall_SaveList :
320 CSR_32_RegCall_NoSSE_SaveList);
322 case CallingConv::Cold:
324 return CSR_64_MostRegs_SaveList;
326 case CallingConv::X86_64_Win64:
328 return CSR_Win64_NoSSE_SaveList;
329 return CSR_Win64_SaveList;
330 case CallingConv::X86_64_SysV:
332 return CSR_64EHRet_SaveList;
333 return CSR_64_SaveList;
334 case CallingConv::X86_INTR:
337 return CSR_64_AllRegs_AVX512_SaveList;
339 return CSR_64_AllRegs_AVX_SaveList;
340 return CSR_64_AllRegs_SaveList;
343 return CSR_32_AllRegs_AVX512_SaveList;
345 return CSR_32_AllRegs_AVX_SaveList;
347 return CSR_32_AllRegs_SSE_SaveList;
348 return CSR_32_AllRegs_SaveList;
357 return CSR_Win64_NoSSE_SaveList;
358 return CSR_Win64_SaveList;
361 return CSR_64EHRet_SaveList;
362 if (Subtarget.getTargetLowering()->supportSwiftError() &&
363 MF->getFunction()->getAttributes().hasAttrSomewhere(
364 Attribute::SwiftError))
365 return CSR_64_SwiftError_SaveList;
366 return CSR_64_SaveList;
369 return CSR_32EHRet_SaveList;
370 return CSR_32_SaveList;
373 const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
374 const MachineFunction *MF) const {
375 assert(MF && "Invalid MachineFunction pointer.");
376 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
377 MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
378 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
383 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
384 CallingConv::ID CC) const {
385 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
386 bool HasSSE = Subtarget.hasSSE1();
387 bool HasAVX = Subtarget.hasAVX();
388 bool HasAVX512 = Subtarget.hasAVX512();
391 case CallingConv::GHC:
392 case CallingConv::HiPE:
393 return CSR_NoRegs_RegMask;
394 case CallingConv::AnyReg:
396 return CSR_64_AllRegs_AVX_RegMask;
397 return CSR_64_AllRegs_RegMask;
398 case CallingConv::PreserveMost:
399 return CSR_64_RT_MostRegs_RegMask;
400 case CallingConv::PreserveAll:
402 return CSR_64_RT_AllRegs_AVX_RegMask;
403 return CSR_64_RT_AllRegs_RegMask;
404 case CallingConv::CXX_FAST_TLS:
406 return CSR_64_TLS_Darwin_RegMask;
408 case CallingConv::Intel_OCL_BI: {
409 if (HasAVX512 && IsWin64)
410 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
411 if (HasAVX512 && Is64Bit)
412 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
413 if (HasAVX && IsWin64)
414 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
415 if (HasAVX && Is64Bit)
416 return CSR_64_Intel_OCL_BI_AVX_RegMask;
417 if (!HasAVX && !IsWin64 && Is64Bit)
418 return CSR_64_Intel_OCL_BI_RegMask;
421 case CallingConv::HHVM:
422 return CSR_64_HHVM_RegMask;
423 case CallingConv::X86_RegCall:
426 return (HasSSE ? CSR_Win64_RegCall_RegMask :
427 CSR_Win64_RegCall_NoSSE_RegMask);
429 return (HasSSE ? CSR_SysV64_RegCall_RegMask :
430 CSR_SysV64_RegCall_NoSSE_RegMask);
433 return (HasSSE ? CSR_32_RegCall_RegMask :
434 CSR_32_RegCall_NoSSE_RegMask);
436 case CallingConv::Cold:
438 return CSR_64_MostRegs_RegMask;
440 case CallingConv::X86_64_Win64:
441 return CSR_Win64_RegMask;
442 case CallingConv::X86_64_SysV:
443 return CSR_64_RegMask;
444 case CallingConv::X86_INTR:
447 return CSR_64_AllRegs_AVX512_RegMask;
449 return CSR_64_AllRegs_AVX_RegMask;
450 return CSR_64_AllRegs_RegMask;
453 return CSR_32_AllRegs_AVX512_RegMask;
455 return CSR_32_AllRegs_AVX_RegMask;
457 return CSR_32_AllRegs_SSE_RegMask;
458 return CSR_32_AllRegs_RegMask;
464 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
468 return CSR_Win64_RegMask;
469 if (Subtarget.getTargetLowering()->supportSwiftError() &&
470 MF.getFunction()->getAttributes().hasAttrSomewhere(
471 Attribute::SwiftError))
472 return CSR_64_SwiftError_RegMask;
473 return CSR_64_RegMask;
475 return CSR_32_RegMask;
479 X86RegisterInfo::getNoPreservedMask() const {
480 return CSR_NoRegs_RegMask;
483 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
484 return CSR_64_TLS_Darwin_RegMask;
487 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
488 BitVector Reserved(getNumRegs());
489 const X86FrameLowering *TFI = getFrameLowering(MF);
491 // Set the stack-pointer register and its aliases as reserved.
492 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
496 // Set the instruction pointer register and its aliases as reserved.
497 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
501 // Set the frame-pointer register and its aliases as reserved if needed.
502 if (TFI->hasFP(MF)) {
503 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
508 // Set the base-pointer register and its aliases as reserved if needed.
509 if (hasBasePointer(MF)) {
510 CallingConv::ID CC = MF.getFunction()->getCallingConv();
511 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
512 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
514 "Stack realignment in presence of dynamic allocas is not supported with"
515 "this calling convention.");
517 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
518 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
523 // Mark the segment registers as reserved.
524 Reserved.set(X86::CS);
525 Reserved.set(X86::SS);
526 Reserved.set(X86::DS);
527 Reserved.set(X86::ES);
528 Reserved.set(X86::FS);
529 Reserved.set(X86::GS);
531 // Mark the floating point stack registers as reserved.
532 for (unsigned n = 0; n != 8; ++n)
533 Reserved.set(X86::ST0 + n);
535 // Reserve the registers that only exist in 64-bit mode.
537 // These 8-bit registers are part of the x86-64 extension even though their
538 // super-registers are old 32-bits.
539 Reserved.set(X86::SIL);
540 Reserved.set(X86::DIL);
541 Reserved.set(X86::BPL);
542 Reserved.set(X86::SPL);
544 for (unsigned n = 0; n != 8; ++n) {
546 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
550 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
554 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
555 for (unsigned n = 16; n != 32; ++n) {
556 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
561 assert(checkAllSuperRegsMarked(Reserved,
562 {X86::SIL, X86::DIL, X86::BPL, X86::SPL}));
566 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
567 // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
568 // because the calling convention defines the EFLAGS register as NOT
571 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
572 // an assert to track this and clear the register afterwards to avoid
573 // unnecessary crashes during release builds.
574 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
575 "EFLAGS are not live-out from a patchpoint.");
577 // Also clean other registers that don't need preserving (IP).
578 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
579 Mask[Reg / 32] &= ~(1U << (Reg % 32));
582 //===----------------------------------------------------------------------===//
583 // Stack Frame Processing methods
584 //===----------------------------------------------------------------------===//
586 static bool CantUseSP(const MachineFrameInfo &MFI) {
587 return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
590 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
591 const MachineFrameInfo &MFI = MF.getFrameInfo();
593 if (!EnableBasePointer)
596 // When we need stack realignment, we can't address the stack from the frame
597 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
598 // can't address variables from the stack pointer. MS inline asm can
599 // reference locals while also adjusting the stack pointer. When we can't
600 // use both the SP and the FP, we need a separate base pointer register.
601 bool CantUseFP = needsStackRealignment(MF);
602 return CantUseFP && CantUseSP(MFI);
605 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
606 if (!TargetRegisterInfo::canRealignStack(MF))
609 const MachineFrameInfo &MFI = MF.getFrameInfo();
610 const MachineRegisterInfo *MRI = &MF.getRegInfo();
612 // Stack realignment requires a frame pointer. If we already started
613 // register allocation with frame pointer elimination, it is too late now.
614 if (!MRI->canReserveReg(FramePtr))
617 // If a base pointer is necessary. Check that it isn't too late to reserve
620 return MRI->canReserveReg(BasePtr);
624 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
625 unsigned Reg, int &FrameIdx) const {
626 // Since X86 defines assignCalleeSavedSpillSlots which always return true
627 // this function neither used nor tested.
628 llvm_unreachable("Unused function on X86. Otherwise need a test case.");
631 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
632 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
633 // TODO: In this case we should be really trying first to entirely eliminate
634 // this instruction which is a plain copy.
635 static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
636 MachineInstr &MI = *II;
637 unsigned Opc = II->getOpcode();
638 // Check if this is a LEA of the form 'lea (%esp), %ebx'
639 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
640 MI.getOperand(2).getImm() != 1 ||
641 MI.getOperand(3).getReg() != X86::NoRegister ||
642 MI.getOperand(4).getImm() != 0 ||
643 MI.getOperand(5).getReg() != X86::NoRegister)
645 unsigned BasePtr = MI.getOperand(1).getReg();
646 // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
647 // be replaced with a 32-bit operand MOV which will zero extend the upper
648 // 32-bits of the super register.
649 if (Opc == X86::LEA64_32r)
650 BasePtr = getX86SubSuperRegister(BasePtr, 32);
651 unsigned NewDestReg = MI.getOperand(0).getReg();
652 const X86InstrInfo *TII =
653 MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
654 TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
655 MI.getOperand(1).isKill());
656 MI.eraseFromParent();
661 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
662 int SPAdj, unsigned FIOperandNum,
663 RegScavenger *RS) const {
664 MachineInstr &MI = *II;
665 MachineFunction &MF = *MI.getParent()->getParent();
666 const X86FrameLowering *TFI = getFrameLowering(MF);
667 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
670 unsigned Opc = MI.getOpcode();
671 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
672 Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
674 if (hasBasePointer(MF))
675 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
676 else if (needsStackRealignment(MF))
677 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
681 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
683 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
684 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
685 // offset is from the traditional base pointer location. On 64-bit, the
686 // offset is from the SP at the end of the prologue, not the FP location. This
687 // matches the behavior of llvm.frameaddress.
688 unsigned IgnoredFrameReg;
689 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
690 MachineOperand &FI = MI.getOperand(FIOperandNum);
692 Offset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
693 FI.ChangeToImmediate(Offset);
697 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
698 // register as source operand, semantic is the same and destination is
699 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
700 // Don't change BasePtr since it is used later for stack adjustment.
701 unsigned MachineBasePtr = BasePtr;
702 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
703 MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
705 // This must be part of a four operand memory reference. Replace the
706 // FrameIndex with base register. Add an offset to the offset.
707 MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
709 // Now add the frame object offset to the offset from EBP.
712 // Tail call jmp happens after FP is popped.
713 const MachineFrameInfo &MFI = MF.getFrameInfo();
714 FIOffset = MFI.getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
716 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
718 if (BasePtr == StackPtr)
721 // The frame index format for stackmaps and patchpoints is different from the
722 // X86 format. It only has a FI and an offset.
723 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
724 assert(BasePtr == FramePtr && "Expected the FP as base register");
725 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
726 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
730 if (MI.getOperand(FIOperandNum+3).isImm()) {
731 // Offset is a 32-bit integer.
732 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
733 int Offset = FIOffset + Imm;
734 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
735 "Requesting 64-bit offset in 32-bit immediate!");
736 if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
737 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
739 // Offset is symbolic. This is extremely rare.
740 uint64_t Offset = FIOffset +
741 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
742 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
746 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
747 const X86FrameLowering *TFI = getFrameLowering(MF);
748 return TFI->hasFP(MF) ? FramePtr : StackPtr;
752 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
753 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
754 unsigned FrameReg = getFrameRegister(MF);
755 if (Subtarget.isTarget64BitILP32())
756 FrameReg = getX86SubSuperRegister(FrameReg, 32);