contrib/llvm/lib/Target/X86/X86SchedBroadwell.td

   1 //=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for Broadwell to support instruction
  11 // scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 def BroadwellModel : SchedMachineModel {
  16   // All x86 instructions are modeled as a single micro-op, and BW can decode 4
  17   // instructions per cycle.
  18   let IssueWidth = 4;
  19   let MicroOpBufferSize = 192; // Based on the reorder buffer.
  20   let LoadLatency = 5;
  21   let MispredictPenalty = 16;
  22
  23   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  24   let LoopMicroOpBufferSize = 50;
  25
  26   // This flag is set to allow the scheduler to assign a default model to
  27   // unrecognized opcodes.
  28   let CompleteModel = 0;
  29 }
  30
  31 let SchedModel = BroadwellModel in {
  32
  33 // Broadwell can issue micro-ops to 8 different ports in one cycle.
  34
  35 // Ports 0, 1, 5, and 6 handle all computation.
  36 // Port 4 gets the data half of stores. Store data can be available later than
  37 // the store address, but since we don't model the latency of stores, we can
  38 // ignore that.
  39 // Ports 2 and 3 are identical. They handle loads and the address half of
  40 // stores. Port 7 can handle address calculations.
  41 def BWPort0 : ProcResource<1>;
  42 def BWPort1 : ProcResource<1>;
  43 def BWPort2 : ProcResource<1>;
  44 def BWPort3 : ProcResource<1>;
  45 def BWPort4 : ProcResource<1>;
  46 def BWPort5 : ProcResource<1>;
  47 def BWPort6 : ProcResource<1>;
  48 def BWPort7 : ProcResource<1>;
  49
  50 // Many micro-ops are capable of issuing on multiple ports.
  51 def BWPort01  : ProcResGroup<[BWPort0, BWPort1]>;
  52 def BWPort23  : ProcResGroup<[BWPort2, BWPort3]>;
  53 def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
  54 def BWPort04  : ProcResGroup<[BWPort0, BWPort4]>;
  55 def BWPort05  : ProcResGroup<[BWPort0, BWPort5]>;
  56 def BWPort06  : ProcResGroup<[BWPort0, BWPort6]>;
  57 def BWPort15  : ProcResGroup<[BWPort1, BWPort5]>;
  58 def BWPort16  : ProcResGroup<[BWPort1, BWPort6]>;
  59 def BWPort56  : ProcResGroup<[BWPort5, BWPort6]>;
  60 def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
  61 def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
  62 def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
  63
  64 // 60 Entry Unified Scheduler
  65 def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
  66                               BWPort5, BWPort6, BWPort7]> {
  67   let BufferSize=60;
  68 }
  69
  70 // Integer division issued on port 0.
  71 def BWDivider : ProcResource<1>;
  72 // FP division and sqrt on port 0.
  73 def BWFPDivider : ProcResource<1>;
  74
  75 // Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  76 // cycles after the memory operand.
  77 def : ReadAdvance<ReadAfterLd, 5>;
  78
  79 // Many SchedWrites are defined in pairs with and without a folded load.
  80 // Instructions with folded loads are usually micro-fused, so they only appear
  81 // as two micro-ops when queued in the reservation station.
  82 // This multiclass defines the resource usage for variants with and without
  83 // folded loads.
  84 multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
  85                           list<ProcResourceKind> ExePorts,
  86                           int Lat, list<int> Res = [1], int UOps = 1,
  87                           int LoadLat = 5> {
  88   // Register variant is using a single cycle on ExePort.
  89   def : WriteRes<SchedRW, ExePorts> {
  90     let Latency = Lat;
  91     let ResourceCycles = Res;
  92     let NumMicroOps = UOps;
  93   }
  94
  95   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
  96   // the latency (default = 5).
  97   def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
  98     let Latency = !add(Lat, LoadLat);
  99     let ResourceCycles = !listconcat([1], Res);
 100     let NumMicroOps = !add(UOps, 1);
 101   }
 102 }
 103
 104 // A folded store needs a cycle on port 4 for the store data, and an extra port
 105 // 2/3/7 cycle to recompute the address.
 106 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
 107
 108 // Arithmetic.
 109 defm : BWWriteResPair<WriteALU,    [BWPort0156], 1>; // Simple integer ALU op.
 110 defm : BWWriteResPair<WriteADC,    [BWPort06], 1>; // Integer ALU + flags op.
 111 defm : BWWriteResPair<WriteIMul,   [BWPort1], 3>; // Integer multiplication.
 112 defm : BWWriteResPair<WriteIMul64, [BWPort1], 3>; // Integer 64-bit multiplication.
 113 defm : BWWriteResPair<WriteDiv8,   [BWPort0, BWDivider], 25, [1, 10]>;
 114 defm : BWWriteResPair<WriteDiv16,  [BWPort0, BWDivider], 25, [1, 10]>;
 115 defm : BWWriteResPair<WriteDiv32,  [BWPort0, BWDivider], 25, [1, 10]>;
 116 defm : BWWriteResPair<WriteDiv64,  [BWPort0, BWDivider], 25, [1, 10]>;
 117 defm : BWWriteResPair<WriteIDiv8,  [BWPort0, BWDivider], 25, [1, 10]>;
 118 defm : BWWriteResPair<WriteIDiv16, [BWPort0, BWDivider], 25, [1, 10]>;
 119 defm : BWWriteResPair<WriteIDiv32, [BWPort0, BWDivider], 25, [1, 10]>;
 120 defm : BWWriteResPair<WriteIDiv64, [BWPort0, BWDivider], 25, [1, 10]>;
 121
 122 defm : X86WriteRes<WriteBSWAP32,   [BWPort15], 1, [1], 1>;
 123 defm : X86WriteRes<WriteBSWAP64,   [BWPort06, BWPort15], 2, [1, 1], 2>;
 124
 125 defm : BWWriteResPair<WriteCRC32, [BWPort1],   3>;
 126 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 127
 128 def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
 129
 130 defm : BWWriteResPair<WriteCMOV,  [BWPort06], 1>; // Conditional move.
 131 defm : BWWriteResPair<WriteCMOV2, [BWPort06,BWPort0156], 2, [1,1], 2>; // // Conditional (CF + ZF flag) move.
 132 defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move.
 133
 134 def  : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
 135 def  : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
 136   let Latency = 2;
 137   let NumMicroOps = 3;
 138 }
 139 def  : WriteRes<WriteLAHFSAHF, [BWPort06]>;
 140 def  : WriteRes<WriteBitTest,[BWPort06]>; // Bit Test instrs
 141
 142 // Bit counts.
 143 defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;
 144 defm : BWWriteResPair<WriteBSR, [BWPort1], 3>;
 145 defm : BWWriteResPair<WriteLZCNT,          [BWPort1], 3>;
 146 defm : BWWriteResPair<WriteTZCNT,          [BWPort1], 3>;
 147 defm : BWWriteResPair<WritePOPCNT,         [BWPort1], 3>;
 148
 149 // Integer shifts and rotates.
 150 defm : BWWriteResPair<WriteShift, [BWPort06],  1>;
 151
 152 // SHLD/SHRD.
 153 defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>;
 154 defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>;
 155 defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>;
 156 defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>;
 157
 158 // BMI1 BEXTR, BMI2 BZHI
 159 defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
 160 defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>;
 161
 162 // Loads, stores, and moves, not folded with other operations.
 163 defm : X86WriteRes<WriteLoad,    [BWPort23], 5, [1], 1>;
 164 defm : X86WriteRes<WriteStore,   [BWPort237, BWPort4], 1, [1,1], 1>;
 165 defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>;
 166 defm : X86WriteRes<WriteMove,    [BWPort0156], 1, [1], 1>;
 167
 168 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 169 // These can often bypass execution ports completely.
 170 def : WriteRes<WriteZero,  []>;
 171
 172 // Treat misc copies as a move.
 173 def : InstRW<[WriteMove], (instrs COPY)>;
 174
 175 // Branches don't produce values, so they have no latency, but they still
 176 // consume resources. Indirect branches can fold loads.
 177 defm : BWWriteResPair<WriteJump,  [BWPort06],   1>;
 178
 179 // Floating point. This covers both scalar and vector operations.
 180 defm : X86WriteRes<WriteFLD0,          [BWPort01], 1, [1], 1>;
 181 defm : X86WriteRes<WriteFLD1,          [BWPort01], 1, [2], 2>;
 182 defm : X86WriteRes<WriteFLDC,          [BWPort01], 1, [2], 2>;
 183 defm : X86WriteRes<WriteFLoad,         [BWPort23], 5, [1], 1>;
 184 defm : X86WriteRes<WriteFLoadX,        [BWPort23], 5, [1], 1>;
 185 defm : X86WriteRes<WriteFLoadY,        [BWPort23], 6, [1], 1>;
 186 defm : X86WriteRes<WriteFMaskedLoad,   [BWPort23,BWPort5], 7, [1,2], 3>;
 187 defm : X86WriteRes<WriteFMaskedLoadY,  [BWPort23,BWPort5], 8, [1,2], 3>;
 188 defm : X86WriteRes<WriteFStore,        [BWPort237,BWPort4], 1, [1,1], 2>;
 189 defm : X86WriteRes<WriteFStoreX,       [BWPort237,BWPort4], 1, [1,1], 2>;
 190 defm : X86WriteRes<WriteFStoreY,       [BWPort237,BWPort4], 1, [1,1], 2>;
 191 defm : X86WriteRes<WriteFStoreNT,      [BWPort237,BWPort4], 1, [1,1], 2>;
 192 defm : X86WriteRes<WriteFStoreNTX,     [BWPort237,BWPort4], 1, [1,1], 2>;
 193 defm : X86WriteRes<WriteFStoreNTY,     [BWPort237,BWPort4], 1, [1,1], 2>;
 194 defm : X86WriteRes<WriteFMaskedStore,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 195 defm : X86WriteRes<WriteFMaskedStoreY, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 196 defm : X86WriteRes<WriteFMove,         [BWPort5], 1, [1], 1>;
 197 defm : X86WriteRes<WriteFMoveX,        [BWPort5], 1, [1], 1>;
 198 defm : X86WriteRes<WriteFMoveY,        [BWPort5], 1, [1], 1>;
 199
 200 defm : BWWriteResPair<WriteFAdd,    [BWPort1],  3, [1], 1, 5>; // Floating point add/sub.
 201 defm : BWWriteResPair<WriteFAddX,   [BWPort1],  3, [1], 1, 5>; // Floating point add/sub (XMM).
 202 defm : BWWriteResPair<WriteFAddY,   [BWPort1],  3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).
 203 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 204 defm : BWWriteResPair<WriteFAdd64,  [BWPort1],  3, [1], 1, 5>; // Floating point double add/sub.
 205 defm : BWWriteResPair<WriteFAdd64X, [BWPort1],  3, [1], 1, 5>; // Floating point double add/sub (XMM).
 206 defm : BWWriteResPair<WriteFAdd64Y, [BWPort1],  3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM).
 207 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 208
 209 defm : BWWriteResPair<WriteFCmp,    [BWPort1],  3, [1], 1, 5>; // Floating point compare.
 210 defm : BWWriteResPair<WriteFCmpX,   [BWPort1],  3, [1], 1, 5>; // Floating point compare (XMM).
 211 defm : BWWriteResPair<WriteFCmpY,   [BWPort1],  3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
 212 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 213 defm : BWWriteResPair<WriteFCmp64,  [BWPort1],  3, [1], 1, 5>; // Floating point double compare.
 214 defm : BWWriteResPair<WriteFCmp64X, [BWPort1],  3, [1], 1, 5>; // Floating point double compare (XMM).
 215 defm : BWWriteResPair<WriteFCmp64Y, [BWPort1],  3, [1], 1, 6>; // Floating point double compare (YMM/ZMM).
 216 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 217
 218 defm : BWWriteResPair<WriteFCom,    [BWPort1],  3>; // Floating point compare to flags.
 219
 220 defm : BWWriteResPair<WriteFMul,    [BWPort01], 3, [1], 1, 5>; // Floating point multiplication.
 221 defm : BWWriteResPair<WriteFMulX,   [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM).
 222 defm : BWWriteResPair<WriteFMulY,   [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
 223 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 224 defm : BWWriteResPair<WriteFMul64,  [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication.
 225 defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM).
 226 defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM).
 227 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 228
 229 //defm : BWWriteResPair<WriteFDiv,     [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 230 defm : BWWriteResPair<WriteFDivX,    [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM).
 231 defm : BWWriteResPair<WriteFDivY,    [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM).
 232 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 233 //defm : BWWriteResPair<WriteFDiv64,   [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division.
 234 defm : BWWriteResPair<WriteFDiv64X,  [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM).
 235 defm : BWWriteResPair<WriteFDiv64Y,  [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM).
 236 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 237
 238 defm : X86WriteRes<WriteFSqrt,       [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root.
 239 defm : X86WriteRes<WriteFSqrtLd,     [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>;
 240 defm : BWWriteResPair<WriteFSqrtX,   [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM).
 241 defm : BWWriteResPair<WriteFSqrtY,   [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM).
 242 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 243 defm : X86WriteRes<WriteFSqrt64,     [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root.
 244 defm : X86WriteRes<WriteFSqrt64Ld,   [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>;
 245 defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM).
 246 defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM).
 247 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 248 defm : BWWriteResPair<WriteFSqrt80,  [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root.
 249
 250 defm : BWWriteResPair<WriteFRcp,   [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal estimate.
 251 defm : BWWriteResPair<WriteFRcpX,  [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal estimate (XMM).
 252 defm : BWWriteResPair<WriteFRcpY,  [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM).
 253 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 254
 255 defm : BWWriteResPair<WriteFRsqrt, [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal square root estimate.
 256 defm : BWWriteResPair<WriteFRsqrtX,[BWPort0],  5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM).
 257 defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM).
 258 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 259
 260 defm : BWWriteResPair<WriteFMA,    [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add.
 261 defm : BWWriteResPair<WriteFMAX,   [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM).
 262 defm : BWWriteResPair<WriteFMAY,   [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM).
 263 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 264 defm : BWWriteResPair<WriteDPPD,   [BWPort0,BWPort1,BWPort5],  9, [1,1,1], 3, 5>; // Floating point double dot product.
 265 defm : BWWriteResPair<WriteDPPS,   [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 5>; // Floating point single dot product.
 266 defm : BWWriteResPair<WriteDPPSY,  [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 6>; // Floating point single dot product (YMM).
 267 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
 268 defm : BWWriteResPair<WriteFSign,     [BWPort5], 1>; // Floating point fabs/fchs.
 269 defm : X86WriteRes<WriteFRnd,            [BWPort23],  6, [1],   1>; // Floating point rounding.
 270 defm : X86WriteRes<WriteFRndY,           [BWPort23],  6, [1],   1>; // Floating point rounding (YMM/ZMM).
 271 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 272 defm : X86WriteRes<WriteFRndLd,  [BWPort1,BWPort23], 11, [2,1], 3>;
 273 defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>;
 274 defm : BWWriteResPair<WriteFLogic,    [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals.
 275 defm : BWWriteResPair<WriteFLogicY,   [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM).
 276 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 277 defm : BWWriteResPair<WriteFTest,     [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions.
 278 defm : BWWriteResPair<WriteFTestY,    [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM).
 279 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 280 defm : BWWriteResPair<WriteFShuffle,  [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles.
 281 defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM).
 282 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 283 defm : BWWriteResPair<WriteFVarShuffle,  [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles.
 284 defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
 285 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 286 defm : BWWriteResPair<WriteFBlend,  [BWPort015], 1, [1], 1, 5>; // Floating point vector blends.
 287 defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends.
 288 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 289 defm : BWWriteResPair<WriteFVarBlend,  [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends.
 290 defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends.
 291 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 292
 293 // FMA Scheduling helper class.
 294 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 295
 296 // Vector integer operations.
 297 defm : X86WriteRes<WriteVecLoad,         [BWPort23], 5, [1], 1>;
 298 defm : X86WriteRes<WriteVecLoadX,        [BWPort23], 5, [1], 1>;
 299 defm : X86WriteRes<WriteVecLoadY,        [BWPort23], 6, [1], 1>;
 300 defm : X86WriteRes<WriteVecLoadNT,       [BWPort23], 5, [1], 1>;
 301 defm : X86WriteRes<WriteVecLoadNTY,      [BWPort23], 6, [1], 1>;
 302 defm : X86WriteRes<WriteVecMaskedLoad,   [BWPort23,BWPort5], 7, [1,2], 3>;
 303 defm : X86WriteRes<WriteVecMaskedLoadY,  [BWPort23,BWPort5], 8, [1,2], 3>;
 304 defm : X86WriteRes<WriteVecStore,        [BWPort237,BWPort4], 1, [1,1], 2>;
 305 defm : X86WriteRes<WriteVecStoreX,       [BWPort237,BWPort4], 1, [1,1], 2>;
 306 defm : X86WriteRes<WriteVecStoreY,       [BWPort237,BWPort4], 1, [1,1], 2>;
 307 defm : X86WriteRes<WriteVecStoreNT,      [BWPort237,BWPort4], 1, [1,1], 2>;
 308 defm : X86WriteRes<WriteVecStoreNTY,     [BWPort237,BWPort4], 1, [1,1], 2>;
 309 defm : X86WriteRes<WriteVecMaskedStore,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 310 defm : X86WriteRes<WriteVecMaskedStoreY, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 311 defm : X86WriteRes<WriteVecMove,         [BWPort015], 1, [1], 1>;
 312 defm : X86WriteRes<WriteVecMoveX,        [BWPort015], 1, [1], 1>;
 313 defm : X86WriteRes<WriteVecMoveY,        [BWPort015], 1, [1], 1>;
 314 defm : X86WriteRes<WriteVecMoveToGpr,    [BWPort0], 1, [1], 1>;
 315 defm : X86WriteRes<WriteVecMoveFromGpr,  [BWPort5], 1, [1], 1>;
 316
 317 defm : X86WriteRes<WriteEMMS,            [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>;
 318
 319 defm : BWWriteResPair<WriteVecALU,   [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 320 defm : BWWriteResPair<WriteVecALUX,  [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 321 defm : BWWriteResPair<WriteVecALUY,  [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM).
 322 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 323 defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
 324 defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
 325 defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM).
 326 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 327 defm : BWWriteResPair<WriteVecTest,  [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions.
 328 defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM).
 329 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 330 defm : BWWriteResPair<WriteVecIMul,  [BWPort0],  5, [1], 1, 5>; // Vector integer multiply.
 331 defm : BWWriteResPair<WriteVecIMulX, [BWPort0],  5, [1], 1, 5>; // Vector integer multiply.
 332 defm : BWWriteResPair<WriteVecIMulY, [BWPort0],  5, [1], 1, 6>; // Vector integer multiply.
 333 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 334 defm : BWWriteResPair<WritePMULLD,   [BWPort0], 10, [2], 2, 5>; // Vector PMULLD.
 335 defm : BWWriteResPair<WritePMULLDY,  [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM).
 336 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 337 defm : BWWriteResPair<WriteShuffle,  [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
 338 defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
 339 defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM).
 340 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 341 defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 342 defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 343 defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM).
 344 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 345 defm : BWWriteResPair<WriteBlend,  [BWPort5], 1, [1], 1, 5>; // Vector blends.
 346 defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM).
 347 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 348 defm : BWWriteResPair<WriteVarBlend,  [BWPort5], 2, [2], 2, 5>; // Vector variable blends.
 349 defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM).
 350 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 351 defm : BWWriteResPair<WriteMPSAD,  [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD.
 352 defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD.
 353 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 354 defm : BWWriteResPair<WritePSADBW,   [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
 355 defm : BWWriteResPair<WritePSADBWX,  [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
 356 defm : BWWriteResPair<WritePSADBWY,  [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM).
 357 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 358 defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS.
 359
 360 // Vector integer shifts.
 361 defm : BWWriteResPair<WriteVecShift,     [BWPort0], 1, [1], 1, 5>;
 362 defm : BWWriteResPair<WriteVecShiftX,    [BWPort0,BWPort5],  2, [1,1], 2, 5>;
 363 defm : X86WriteRes<WriteVecShiftY,       [BWPort0,BWPort5],  4, [1,1], 2>;
 364 defm : X86WriteRes<WriteVecShiftYLd,     [BWPort0,BWPort23], 7, [1,1], 2>;
 365 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 366
 367 defm : BWWriteResPair<WriteVecShiftImm,  [BWPort0],  1, [1], 1, 5>;
 368 defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0],  1, [1], 1, 5>; // Vector integer immediate shifts (XMM).
 369 defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0],  1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM).
 370 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 371 defm : BWWriteResPair<WriteVarVecShift,  [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts.
 372 defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM).
 373 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 374
 375 // Vector insert/extract operations.
 376 def : WriteRes<WriteVecInsert, [BWPort5]> {
 377   let Latency = 2;
 378   let NumMicroOps = 2;
 379   let ResourceCycles = [2];
 380 }
 381 def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> {
 382   let Latency = 6;
 383   let NumMicroOps = 2;
 384 }
 385
 386 def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> {
 387   let Latency = 2;
 388   let NumMicroOps = 2;
 389 }
 390 def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> {
 391   let Latency = 2;
 392   let NumMicroOps = 3;
 393 }
 394
 395 // Conversion between integer and float.
 396 defm : BWWriteResPair<WriteCvtSS2I,   [BWPort1], 3>;
 397 defm : BWWriteResPair<WriteCvtPS2I,   [BWPort1], 3>;
 398 defm : BWWriteResPair<WriteCvtPS2IY,  [BWPort1], 3>;
 399 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 400 defm : BWWriteResPair<WriteCvtSD2I,   [BWPort1], 3>;
 401 defm : BWWriteResPair<WriteCvtPD2I,   [BWPort1], 3>;
 402 defm : BWWriteResPair<WriteCvtPD2IY,  [BWPort1], 3>;
 403 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 404
 405 defm : BWWriteResPair<WriteCvtI2SS,   [BWPort1], 4>;
 406 defm : BWWriteResPair<WriteCvtI2PS,   [BWPort1], 4>;
 407 defm : BWWriteResPair<WriteCvtI2PSY,  [BWPort1], 4>;
 408 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 409 defm : BWWriteResPair<WriteCvtI2SD,   [BWPort1], 4>;
 410 defm : BWWriteResPair<WriteCvtI2PD,   [BWPort1], 4>;
 411 defm : BWWriteResPair<WriteCvtI2PDY,  [BWPort1], 4>;
 412 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 413
 414 defm : BWWriteResPair<WriteCvtSS2SD,  [BWPort1], 3>;
 415 defm : BWWriteResPair<WriteCvtPS2PD,  [BWPort1], 3>;
 416 defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort1], 3>;
 417 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 418 defm : BWWriteResPair<WriteCvtSD2SS,  [BWPort1], 3>;
 419 defm : BWWriteResPair<WriteCvtPD2PS,  [BWPort1], 3>;
 420 defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1], 3>;
 421 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 422
 423 defm : X86WriteRes<WriteCvtPH2PS,     [BWPort0,BWPort5], 2, [1,1], 2>;
 424 defm : X86WriteRes<WriteCvtPH2PSY,    [BWPort0,BWPort5], 2, [1,1], 2>;
 425 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 426 defm : X86WriteRes<WriteCvtPH2PSLd,  [BWPort0,BWPort23], 6, [1,1], 2>;
 427 defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>;
 428 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 429
 430 defm : X86WriteRes<WriteCvtPS2PH,    [BWPort1,BWPort5], 4, [1,1], 2>;
 431 defm : X86WriteRes<WriteCvtPS2PHY,   [BWPort1,BWPort5], 6, [1,1], 2>;
 432 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 433 defm : X86WriteRes<WriteCvtPS2PHSt,  [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>;
 434 defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>;
 435 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 436
 437 // Strings instructions.
 438
 439 // Packed Compare Implicit Length Strings, Return Mask
 440 def : WriteRes<WritePCmpIStrM, [BWPort0]> {
 441   let Latency = 11;
 442   let NumMicroOps = 3;
 443   let ResourceCycles = [3];
 444 }
 445 def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
 446   let Latency = 16;
 447   let NumMicroOps = 4;
 448   let ResourceCycles = [3,1];
 449 }
 450
 451 // Packed Compare Explicit Length Strings, Return Mask
 452 def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
 453   let Latency = 19;
 454   let NumMicroOps = 9;
 455   let ResourceCycles = [4,3,1,1];
 456 }
 457 def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
 458   let Latency = 24;
 459   let NumMicroOps = 10;
 460   let ResourceCycles = [4,3,1,1,1];
 461 }
 462
 463 // Packed Compare Implicit Length Strings, Return Index
 464 def : WriteRes<WritePCmpIStrI, [BWPort0]> {
 465   let Latency = 11;
 466   let NumMicroOps = 3;
 467   let ResourceCycles = [3];
 468 }
 469 def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
 470   let Latency = 16;
 471   let NumMicroOps = 4;
 472   let ResourceCycles = [3,1];
 473 }
 474
 475 // Packed Compare Explicit Length Strings, Return Index
 476 def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
 477   let Latency = 18;
 478   let NumMicroOps = 8;
 479   let ResourceCycles = [4,3,1];
 480 }
 481 def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
 482   let Latency = 23;
 483   let NumMicroOps = 9;
 484   let ResourceCycles = [4,3,1,1];
 485 }
 486
 487 // MOVMSK Instructions.
 488 def : WriteRes<WriteFMOVMSK,    [BWPort0]> { let Latency = 3; }
 489 def : WriteRes<WriteVecMOVMSK,  [BWPort0]> { let Latency = 3; }
 490 def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; }
 491 def : WriteRes<WriteMMXMOVMSK,  [BWPort0]> { let Latency = 1; }
 492
 493 // AES instructions.
 494 def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
 495   let Latency = 7;
 496   let NumMicroOps = 1;
 497   let ResourceCycles = [1];
 498 }
 499 def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
 500   let Latency = 12;
 501   let NumMicroOps = 2;
 502   let ResourceCycles = [1,1];
 503 }
 504
 505 def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
 506   let Latency = 14;
 507   let NumMicroOps = 2;
 508   let ResourceCycles = [2];
 509 }
 510 def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
 511   let Latency = 19;
 512   let NumMicroOps = 3;
 513   let ResourceCycles = [2,1];
 514 }
 515
 516 def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
 517   let Latency = 29;
 518   let NumMicroOps = 11;
 519   let ResourceCycles = [2,7,2];
 520 }
 521 def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
 522   let Latency = 33;
 523   let NumMicroOps = 11;
 524   let ResourceCycles = [2,7,1,1];
 525 }
 526
 527 // Carry-less multiplication instructions.
 528 defm : BWWriteResPair<WriteCLMul,  [BWPort0], 5>;
 529
 530 // Catch-all for expensive system instructions.
 531 def : WriteRes<WriteSystem,     [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 532
 533 // AVX2.
 534 defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles.
 535 defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles.
 536 defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width vector shuffles.
 537 defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width vector variable shuffles.
 538
 539 // Old microcoded instructions that nobody use.
 540 def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 541
 542 // Fence instructions.
 543 def : WriteRes<WriteFence,  [BWPort23, BWPort4]>;
 544
 545 // Load/store MXCSR.
 546 def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 547 def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 548
 549 // Nop, not very useful expect it provides a model for nops!
 550 def : WriteRes<WriteNop, []>;
 551
 552 ////////////////////////////////////////////////////////////////////////////////
 553 // Horizontal add/sub  instructions.
 554 ////////////////////////////////////////////////////////////////////////////////
 555
 556 defm : BWWriteResPair<WriteFHAdd,   [BWPort1,BWPort5], 5, [1,2], 3, 5>;
 557 defm : BWWriteResPair<WriteFHAddY,  [BWPort1,BWPort5], 5, [1,2], 3, 6>;
 558 defm : BWWriteResPair<WritePHAdd,  [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 559 defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 560 defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>;
 561
 562 // Remaining instrs.
 563
 564 def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
 565   let Latency = 1;
 566   let NumMicroOps = 1;
 567   let ResourceCycles = [1];
 568 }
 569 def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr",
 570                                            "VPSRLVQ(Y?)rr")>;
 571
 572 def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
 573   let Latency = 1;
 574   let NumMicroOps = 1;
 575   let ResourceCycles = [1];
 576 }
 577 def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r",
 578                                            "UCOM_F(P?)r")>;
 579
 580 def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
 581   let Latency = 1;
 582   let NumMicroOps = 1;
 583   let ResourceCycles = [1];
 584 }
 585 def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVQ2DQrr")>;
 586
 587 def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
 588   let Latency = 1;
 589   let NumMicroOps = 1;
 590   let ResourceCycles = [1];
 591 }
 592 def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 593
 594 def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
 595   let Latency = 1;
 596   let NumMicroOps = 1;
 597   let ResourceCycles = [1];
 598 }
 599 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
 600
 601 def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
 602   let Latency = 1;
 603   let NumMicroOps = 1;
 604   let ResourceCycles = [1];
 605 }
 606 def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
 607
 608 def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
 609   let Latency = 1;
 610   let NumMicroOps = 1;
 611   let ResourceCycles = [1];
 612 }
 613 def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
 614                                            "BLSI(32|64)rr",
 615                                            "BLSMSK(32|64)rr",
 616                                            "BLSR(32|64)rr")>;
 617
 618 def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
 619   let Latency = 1;
 620   let NumMicroOps = 1;
 621   let ResourceCycles = [1];
 622 }
 623 def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>;
 624
 625 def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
 626   let Latency = 1;
 627   let NumMicroOps = 1;
 628   let ResourceCycles = [1];
 629 }
 630 def: InstRW<[BWWriteResGroup9], (instregex "SGDT64m",
 631                                            "SIDT64m",
 632                                            "SMSW16m",
 633                                            "STRm",
 634                                            "SYSCALL")>;
 635
 636 def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
 637   let Latency = 1;
 638   let NumMicroOps = 2;
 639   let ResourceCycles = [1,1];
 640 }
 641 def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
 642                                             "ST_FP(32|64|80)m")>;
 643
 644 def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
 645   let Latency = 2;
 646   let NumMicroOps = 2;
 647   let ResourceCycles = [2];
 648 }
 649 def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
 650
 651 def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
 652   let Latency = 2;
 653   let NumMicroOps = 2;
 654   let ResourceCycles = [2];
 655 }
 656 def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
 657                                             "ROL(8|16|32|64)ri",
 658                                             "ROR(8|16|32|64)r1",
 659                                             "ROR(8|16|32|64)ri")>;
 660
 661 def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
 662   let Latency = 2;
 663   let NumMicroOps = 2;
 664   let ResourceCycles = [2];
 665 }
 666 def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
 667                                          MFENCE,
 668                                          WAIT,
 669                                          XGETBV)>;
 670
 671 def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
 672   let Latency = 2;
 673   let NumMicroOps = 2;
 674   let ResourceCycles = [1,1];
 675 }
 676 def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr",
 677                                             "(V?)CVTSS2SDrr")>;
 678
 679 def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
 680   let Latency = 2;
 681   let NumMicroOps = 2;
 682   let ResourceCycles = [1,1];
 683 }
 684 def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
 685
 686 def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
 687   let Latency = 2;
 688   let NumMicroOps = 2;
 689   let ResourceCycles = [1,1];
 690 }
 691 def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
 692
 693 def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
 694   let Latency = 2;
 695   let NumMicroOps = 2;
 696   let ResourceCycles = [1,1];
 697 }
 698 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
 699
 700 def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
 701   let Latency = 2;
 702   let NumMicroOps = 2;
 703   let ResourceCycles = [1,1];
 704 }
 705 def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
 706 def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
 707 def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
 708                                             "ADC8ri",
 709                                             "SBB8i8",
 710                                             "SBB8ri",
 711                                             "SET(A|BE)r")>;
 712
 713 def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
 714   let Latency = 2;
 715   let NumMicroOps = 3;
 716   let ResourceCycles = [1,1,1];
 717 }
 718 def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>;
 719
 720 def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
 721   let Latency = 2;
 722   let NumMicroOps = 3;
 723   let ResourceCycles = [1,1,1];
 724 }
 725 def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
 726
 727 def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
 728   let Latency = 2;
 729   let NumMicroOps = 3;
 730   let ResourceCycles = [1,1,1];
 731 }
 732 def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r,
 733                                          STOSB, STOSL, STOSQ, STOSW)>;
 734 def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
 735                                             "PUSH64i8")>;
 736
 737 def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
 738   let Latency = 3;
 739   let NumMicroOps = 1;
 740   let ResourceCycles = [1];
 741 }
 742 def: InstRW<[BWWriteResGroup27], (instregex "MMX_CVTPI2PSirr",
 743                                             "PDEP(32|64)rr",
 744                                             "PEXT(32|64)rr",
 745                                             "(V?)CVTDQ2PS(Y?)rr")>;
 746
 747 def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
 748   let Latency = 4;
 749   let NumMicroOps = 2;
 750   let ResourceCycles = [1,1];
 751 }
 752 def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
 753
 754 def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
 755   let Latency = 3;
 756   let NumMicroOps = 1;
 757   let ResourceCycles = [1];
 758 }
 759 def: InstRW<[BWWriteResGroup28], (instregex "VPBROADCASTBrr",
 760                                             "VPBROADCASTWrr")>;
 761
 762 def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
 763   let Latency = 2;
 764   let NumMicroOps = 3;
 765   let ResourceCycles = [3];
 766 }
 767 def: InstRW<[BWWriteResGroup30], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr,
 768                                          XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr,
 769                                          XCHG16ar, XCHG32ar, XCHG64ar)>;
 770
 771 def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
 772   let Latency = 3;
 773   let NumMicroOps = 3;
 774   let ResourceCycles = [2,1];
 775 }
 776 def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
 777                                             "MMX_PACKSSWBirr",
 778                                             "MMX_PACKUSWBirr")>;
 779
 780 def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
 781   let Latency = 3;
 782   let NumMicroOps = 3;
 783   let ResourceCycles = [1,2];
 784 }
 785 def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
 786
 787 def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
 788   let Latency = 3;
 789   let NumMicroOps = 3;
 790   let ResourceCycles = [1,2];
 791 }
 792 def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
 793                                             "RCL(8|16|32|64)ri",
 794                                             "RCR(8|16|32|64)r1",
 795                                             "RCR(8|16|32|64)ri")>;
 796
 797 def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
 798   let Latency = 3;
 799   let NumMicroOps = 3;
 800   let ResourceCycles = [2,1];
 801 }
 802 def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
 803                                             "ROR(8|16|32|64)rCL",
 804                                             "SAR(8|16|32|64)rCL",
 805                                             "SHL(8|16|32|64)rCL",
 806                                             "SHR(8|16|32|64)rCL")>;
 807
 808 def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
 809   let Latency = 3;
 810   let NumMicroOps = 4;
 811   let ResourceCycles = [1,1,1,1];
 812 }
 813 def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
 814
 815 def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
 816   let Latency = 3;
 817   let NumMicroOps = 4;
 818   let ResourceCycles = [1,1,1,1];
 819 }
 820 def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>;
 821 def: InstRW<[BWWriteResGroup38], (instregex "SET(A|BE)m")>;
 822
 823 def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
 824   let Latency = 4;
 825   let NumMicroOps = 2;
 826   let ResourceCycles = [1,1];
 827 }
 828 def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr",
 829                                             "(V?)CVT(T?)SD2SIrr",
 830                                             "(V?)CVT(T?)SS2SI64rr",
 831                                             "(V?)CVT(T?)SS2SIrr")>;
 832
 833 def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
 834   let Latency = 4;
 835   let NumMicroOps = 2;
 836   let ResourceCycles = [1,1];
 837 }
 838 def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr")>;
 839
 840 def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
 841   let Latency = 4;
 842   let NumMicroOps = 2;
 843   let ResourceCycles = [1,1];
 844 }
 845 def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>;
 846
 847 def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
 848   let Latency = 4;
 849   let NumMicroOps = 2;
 850   let ResourceCycles = [1,1];
 851 }
 852 def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
 853 def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPI2PDirr",
 854                                             "MMX_CVT(T?)PD2PIirr",
 855                                             "MMX_CVT(T?)PS2PIirr",
 856                                             "(V?)CVTDQ2PDrr",
 857                                             "(V?)CVTPD2PSrr",
 858                                             "(V?)CVTSD2SSrr",
 859                                             "(V?)CVTSI642SDrr",
 860                                             "(V?)CVTSI2SDrr",
 861                                             "(V?)CVTSI2SSrr",
 862                                             "(V?)CVT(T?)PD2DQrr")>;
 863
 864 def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
 865   let Latency = 4;
 866   let NumMicroOps = 4;
 867   let ResourceCycles = [1,1,2];
 868 }
 869 def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
 870
 871 def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
 872   let Latency = 4;
 873   let NumMicroOps = 3;
 874   let ResourceCycles = [1,1,1];
 875 }
 876 def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>;
 877
 878 def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
 879   let Latency = 4;
 880   let NumMicroOps = 3;
 881   let ResourceCycles = [1,1,1];
 882 }
 883 def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m",
 884                                             "IST_F(16|32)m")>;
 885
 886 def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
 887   let Latency = 4;
 888   let NumMicroOps = 4;
 889   let ResourceCycles = [4];
 890 }
 891 def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>;
 892
 893 def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
 894   let Latency = 4;
 895   let NumMicroOps = 4;
 896   let ResourceCycles = [1,3];
 897 }
 898 def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>;
 899
 900 def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
 901   let Latency = 5;
 902   let NumMicroOps = 1;
 903   let ResourceCycles = [1];
 904 }
 905 def: InstRW<[BWWriteResGroup47], (instregex "(V?)PCMPGTQ(Y?)rr",
 906                                             "MUL_(FPrST0|FST0r|FrST0)")>;
 907
 908 def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
 909   let Latency = 5;
 910   let NumMicroOps = 1;
 911   let ResourceCycles = [1];
 912 }
 913 def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm16",
 914                                             "MOVSX(16|32|64)rm32",
 915                                             "MOVSX(16|32|64)rm8",
 916                                             "MOVZX(16|32|64)rm16",
 917                                             "MOVZX(16|32|64)rm8",
 918                                             "VBROADCASTSSrm",
 919                                             "(V?)MOVDDUPrm",
 920                                             "(V?)MOVSHDUPrm",
 921                                             "(V?)MOVSLDUPrm",
 922                                             "VPBROADCASTDrm",
 923                                             "VPBROADCASTQrm")>;
 924
 925 def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
 926   let Latency = 5;
 927   let NumMicroOps = 3;
 928   let ResourceCycles = [1,2];
 929 }
 930 def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>;
 931
 932 def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
 933   let Latency = 5;
 934   let NumMicroOps = 3;
 935   let ResourceCycles = [1,1,1];
 936 }
 937 def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
 938
 939 def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
 940   let Latency = 4;
 941   let NumMicroOps = 3;
 942   let ResourceCycles = [1,1,1];
 943 }
 944 def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>;
 945
 946 def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
 947   let Latency = 5;
 948   let NumMicroOps = 5;
 949   let ResourceCycles = [1,4];
 950 }
 951 def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>;
 952
 953 def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
 954   let Latency = 5;
 955   let NumMicroOps = 5;
 956   let ResourceCycles = [1,4];
 957 }
 958 def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>;
 959
 960 def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
 961   let Latency = 5;
 962   let NumMicroOps = 5;
 963   let ResourceCycles = [2,3];
 964 }
 965 def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
 966
 967 def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
 968   let Latency = 5;
 969   let NumMicroOps = 6;
 970   let ResourceCycles = [1,1,4];
 971 }
 972 def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>;
 973
 974 def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
 975   let Latency = 6;
 976   let NumMicroOps = 1;
 977   let ResourceCycles = [1];
 978 }
 979 def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m",
 980                                             "VBROADCASTF128",
 981                                             "VBROADCASTI128",
 982                                             "VBROADCASTSDYrm",
 983                                             "VBROADCASTSSYrm",
 984                                             "VMOVDDUPYrm",
 985                                             "VMOVSHDUPYrm",
 986                                             "VMOVSLDUPYrm",
 987                                             "VPBROADCASTDYrm",
 988                                             "VPBROADCASTQYrm")>;
 989
 990 def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
 991   let Latency = 6;
 992   let NumMicroOps = 2;
 993   let ResourceCycles = [1,1];
 994 }
 995 def: InstRW<[BWWriteResGroup59], (instregex "(V?)CVTPS2PDrm",
 996                                             "(V?)CVTSS2SDrm",
 997                                             "VPSLLVQrm",
 998                                             "VPSRLVQrm")>;
 999
1000 def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1001   let Latency = 6;
1002   let NumMicroOps = 2;
1003   let ResourceCycles = [1,1];
1004 }
1005 def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1006                                             "VCVTPD2PSYrr",
1007                                             "VCVT(T?)PD2DQYrr")>;
1008
1009 def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1010   let Latency = 6;
1011   let NumMicroOps = 2;
1012   let ResourceCycles = [1,1];
1013 }
1014 def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1015                                             "JMP(16|32|64)m")>;
1016
1017 def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1018   let Latency = 6;
1019   let NumMicroOps = 2;
1020   let ResourceCycles = [1,1];
1021 }
1022 def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>;
1023
1024 def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1025   let Latency = 6;
1026   let NumMicroOps = 2;
1027   let ResourceCycles = [1,1];
1028 }
1029 def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1030                                             "BLSI(32|64)rm",
1031                                             "BLSMSK(32|64)rm",
1032                                             "BLSR(32|64)rm",
1033                                             "MOVBE(16|32|64)rm")>;
1034
1035 def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1036   let Latency = 6;
1037   let NumMicroOps = 2;
1038   let ResourceCycles = [1,1];
1039 }
1040 def: InstRW<[BWWriteResGroup65], (instregex "VINSERTF128rm",
1041                                             "VINSERTI128rm",
1042                                             "VPBLENDDrmi")>;
1043
1044 def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1045   let Latency = 6;
1046   let NumMicroOps = 2;
1047   let ResourceCycles = [1,1];
1048 }
1049 def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
1050 def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
1051
1052 def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1053   let Latency = 6;
1054   let NumMicroOps = 4;
1055   let ResourceCycles = [1,1,1,1];
1056 }
1057 def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1058
1059 def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1060   let Latency = 6;
1061   let NumMicroOps = 4;
1062   let ResourceCycles = [1,1,1,1];
1063 }
1064 def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
1065                                             "BTR(16|32|64)mi8",
1066                                             "BTS(16|32|64)mi8",
1067                                             "SAR(8|16|32|64)m1",
1068                                             "SAR(8|16|32|64)mi",
1069                                             "SHL(8|16|32|64)m1",
1070                                             "SHL(8|16|32|64)mi",
1071                                             "SHR(8|16|32|64)m1",
1072                                             "SHR(8|16|32|64)mi")>;
1073
1074 def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1075   let Latency = 6;
1076   let NumMicroOps = 4;
1077   let ResourceCycles = [1,1,1,1];
1078 }
1079 def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
1080                                             "PUSH(16|32|64)rmm")>;
1081
1082 def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1083   let Latency = 6;
1084   let NumMicroOps = 6;
1085   let ResourceCycles = [1,5];
1086 }
1087 def: InstRW<[BWWriteResGroup71], (instrs STD)>;
1088
1089 def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1090   let Latency = 7;
1091   let NumMicroOps = 2;
1092   let ResourceCycles = [1,1];
1093 }
1094 def: InstRW<[BWWriteResGroup73], (instregex "VPSLLVQYrm",
1095                                             "VPSRLVQYrm")>;
1096
1097 def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1098   let Latency = 7;
1099   let NumMicroOps = 2;
1100   let ResourceCycles = [1,1];
1101 }
1102 def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>;
1103
1104 def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1105   let Latency = 7;
1106   let NumMicroOps = 2;
1107   let ResourceCycles = [1,1];
1108 }
1109 def: InstRW<[BWWriteResGroup77], (instregex "VPBLENDDYrmi")>;
1110
1111 def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1112   let Latency = 7;
1113   let NumMicroOps = 3;
1114   let ResourceCycles = [2,1];
1115 }
1116 def: InstRW<[BWWriteResGroup79], (instregex "MMX_PACKSSDWirm",
1117                                             "MMX_PACKSSWBirm",
1118                                             "MMX_PACKUSWBirm")>;
1119
1120 def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1121   let Latency = 7;
1122   let NumMicroOps = 3;
1123   let ResourceCycles = [1,2];
1124 }
1125 def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
1126                                          SCASB, SCASL, SCASQ, SCASW)>;
1127
1128 def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1129   let Latency = 7;
1130   let NumMicroOps = 3;
1131   let ResourceCycles = [1,1,1];
1132 }
1133 def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>;
1134
1135 def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1136   let Latency = 7;
1137   let NumMicroOps = 3;
1138   let ResourceCycles = [1,1,1];
1139 }
1140 def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>;
1141
1142 def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1143   let Latency = 7;
1144   let NumMicroOps = 5;
1145   let ResourceCycles = [1,1,1,2];
1146 }
1147 def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
1148                                             "ROL(8|16|32|64)mi",
1149                                             "ROR(8|16|32|64)m1",
1150                                             "ROR(8|16|32|64)mi")>;
1151
1152 def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1153   let Latency = 7;
1154   let NumMicroOps = 5;
1155   let ResourceCycles = [1,1,1,2];
1156 }
1157 def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
1158
1159 def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1160   let Latency = 7;
1161   let NumMicroOps = 5;
1162   let ResourceCycles = [1,1,1,1,1];
1163 }
1164 def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
1165                                             "FARCALL64")>;
1166
1167 def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1168   let Latency = 7;
1169   let NumMicroOps = 7;
1170   let ResourceCycles = [2,2,1,2];
1171 }
1172 def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
1173
1174 def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1175   let Latency = 8;
1176   let NumMicroOps = 2;
1177   let ResourceCycles = [1,1];
1178 }
1179 def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
1180                                             "PDEP(32|64)rm",
1181                                             "PEXT(32|64)rm",
1182                                             "(V?)CVTDQ2PSrm")>;
1183
1184 def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1185   let Latency = 8;
1186   let NumMicroOps = 3;
1187   let ResourceCycles = [1,1,1];
1188 }
1189 def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rmi, IMUL16rmi8)>;
1190
1191 def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort06, BWPort0156, BWPort23]> {
1192   let Latency = 9;
1193   let NumMicroOps = 5;
1194   let ResourceCycles = [1,1,2,1];
1195 }
1196 def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
1197
1198 def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1199   let Latency = 8;
1200   let NumMicroOps = 2;
1201   let ResourceCycles = [1,1];
1202 }
1203 def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
1204                                             "VPMOVSXBQYrm",
1205                                             "VPMOVSXBWYrm",
1206                                             "VPMOVSXDQYrm",
1207                                             "VPMOVSXWDYrm",
1208                                             "VPMOVSXWQYrm",
1209                                             "VPMOVZXWDYrm")>;
1210
1211 def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1212   let Latency = 8;
1213   let NumMicroOps = 5;
1214   let ResourceCycles = [1,1,1,2];
1215 }
1216 def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
1217                                             "RCL(8|16|32|64)mi",
1218                                             "RCR(8|16|32|64)m1",
1219                                             "RCR(8|16|32|64)mi")>;
1220
1221 def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1222   let Latency = 8;
1223   let NumMicroOps = 5;
1224   let ResourceCycles = [1,1,2,1];
1225 }
1226 def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
1227
1228 def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1229   let Latency = 8;
1230   let NumMicroOps = 6;
1231   let ResourceCycles = [1,1,1,3];
1232 }
1233 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
1234
1235 def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1236   let Latency = 8;
1237   let NumMicroOps = 6;
1238   let ResourceCycles = [1,1,1,2,1];
1239 }
1240 def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
1241 def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(8|16|32|64)rm",
1242                                              "ROL(8|16|32|64)mCL",
1243                                              "SAR(8|16|32|64)mCL",
1244                                              "SHL(8|16|32|64)mCL",
1245                                              "SHR(8|16|32|64)mCL")>;
1246
1247 def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
1248   let Latency = 9;
1249   let NumMicroOps = 2;
1250   let ResourceCycles = [1,1];
1251 }
1252 def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1253                                              "ILD_F(16|32|64)m",
1254                                              "VCVTPS2DQYrm",
1255                                              "VCVTTPS2DQYrm")>;
1256
1257 def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1258   let Latency = 9;
1259   let NumMicroOps = 3;
1260   let ResourceCycles = [1,1,1];
1261 }
1262 def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm",
1263                                              "(V?)CVT(T?)SD2SI64rm",
1264                                              "(V?)CVT(T?)SD2SIrm",
1265                                              "VCVTTSS2SI64rm",
1266                                              "(V?)CVTTSS2SIrm")>;
1267
1268 def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1269   let Latency = 9;
1270   let NumMicroOps = 3;
1271   let ResourceCycles = [1,1,1];
1272 }
1273 def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
1274
1275 def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1276   let Latency = 9;
1277   let NumMicroOps = 3;
1278   let ResourceCycles = [1,1,1];
1279 }
1280 def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
1281 def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2PSrm",
1282                                              "CVT(T?)PD2DQrm",
1283                                              "MMX_CVTPI2PDirm",
1284                                              "MMX_CVT(T?)PD2PIirm",
1285                                              "(V?)CVTDQ2PDrm",
1286                                              "(V?)CVTSD2SSrm")>;
1287
1288 def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
1289   let Latency = 9;
1290   let NumMicroOps = 3;
1291   let ResourceCycles = [1,1,1];
1292 }
1293 def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
1294                                              "VPBROADCASTW(Y?)rm")>;
1295
1296 def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1297   let Latency = 9;
1298   let NumMicroOps = 5;
1299   let ResourceCycles = [1,1,3];
1300 }
1301 def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
1302
1303 def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1304   let Latency = 9;
1305   let NumMicroOps = 5;
1306   let ResourceCycles = [1,2,1,1];
1307 }
1308 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1309                                              "LSL(16|32|64)rm")>;
1310
1311 def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
1312   let Latency = 10;
1313   let NumMicroOps = 2;
1314   let ResourceCycles = [1,1];
1315 }
1316 def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>;
1317
1318 def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
1319   let Latency = 10;
1320   let NumMicroOps = 3;
1321   let ResourceCycles = [2,1];
1322 }
1323 def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>;
1324
1325 def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
1326   let Latency = 10;
1327   let NumMicroOps = 4;
1328   let ResourceCycles = [1,1,1,1];
1329 }
1330 def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
1331
1332 def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
1333   let Latency = 9;
1334   let NumMicroOps = 4;
1335   let ResourceCycles = [1,1,1,1];
1336 }
1337 def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
1338
1339 def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1340   let Latency = 11;
1341   let NumMicroOps = 1;
1342   let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
1343 }
1344 def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair
1345
1346 def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
1347   let Latency = 11;
1348   let NumMicroOps = 2;
1349   let ResourceCycles = [1,1];
1350 }
1351 def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m",
1352                                              "VPCMPGTQYrm")>;
1353
1354 def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1355   let Latency = 11;
1356   let NumMicroOps = 3;
1357   let ResourceCycles = [1,1,1];
1358 }
1359 def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
1360
1361 def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1362   let Latency = 11;
1363   let NumMicroOps = 7;
1364   let ResourceCycles = [2,2,3];
1365 }
1366 def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
1367                                              "RCR(16|32|64)rCL")>;
1368
1369 def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1370   let Latency = 11;
1371   let NumMicroOps = 9;
1372   let ResourceCycles = [1,4,1,3];
1373 }
1374 def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
1375
1376 def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
1377   let Latency = 11;
1378   let NumMicroOps = 11;
1379   let ResourceCycles = [2,9];
1380 }
1381 def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
1382 def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
1383
1384 def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
1385   let Latency = 12;
1386   let NumMicroOps = 3;
1387   let ResourceCycles = [2,1];
1388 }
1389 def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1390
1391 def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1392   let Latency = 14;
1393   let NumMicroOps = 1;
1394   let ResourceCycles = [1,4];
1395 }
1396 def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair
1397
1398 def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1399   let Latency = 14;
1400   let NumMicroOps = 3;
1401   let ResourceCycles = [1,1,1];
1402 }
1403 def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>;
1404
1405 def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1406   let Latency = 14;
1407   let NumMicroOps = 8;
1408   let ResourceCycles = [2,2,1,3];
1409 }
1410 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
1411
1412 def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1413   let Latency = 14;
1414   let NumMicroOps = 10;
1415   let ResourceCycles = [2,3,1,4];
1416 }
1417 def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
1418
1419 def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
1420   let Latency = 14;
1421   let NumMicroOps = 12;
1422   let ResourceCycles = [2,1,4,5];
1423 }
1424 def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>;
1425
1426 def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
1427   let Latency = 15;
1428   let NumMicroOps = 1;
1429   let ResourceCycles = [1];
1430 }
1431 def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1432
1433 def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1434   let Latency = 15;
1435   let NumMicroOps = 10;
1436   let ResourceCycles = [1,1,1,4,1,2];
1437 }
1438 def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
1439
1440 def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1441   let Latency = 16;
1442   let NumMicroOps = 2;
1443   let ResourceCycles = [1,1,5];
1444 }
1445 def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair
1446
1447 def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1448   let Latency = 16;
1449   let NumMicroOps = 14;
1450   let ResourceCycles = [1,1,1,4,2,5];
1451 }
1452 def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>;
1453
1454 def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
1455   let Latency = 16;
1456   let NumMicroOps = 16;
1457   let ResourceCycles = [16];
1458 }
1459 def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
1460
1461 def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
1462   let Latency = 18;
1463   let NumMicroOps = 8;
1464   let ResourceCycles = [1,1,1,5];
1465 }
1466 def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
1467 def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
1468
1469 def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1470   let Latency = 18;
1471   let NumMicroOps = 11;
1472   let ResourceCycles = [2,1,1,3,1,3];
1473 }
1474 def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
1475
1476 def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1477   let Latency = 19;
1478   let NumMicroOps = 2;
1479   let ResourceCycles = [1,1,8];
1480 }
1481 def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair
1482
1483 def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
1484   let Latency = 20;
1485   let NumMicroOps = 1;
1486   let ResourceCycles = [1];
1487 }
1488 def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1489
1490 def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1491   let Latency = 20;
1492   let NumMicroOps = 8;
1493   let ResourceCycles = [1,1,1,1,1,1,2];
1494 }
1495 def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>;
1496
1497 def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
1498   let Latency = 21;
1499   let NumMicroOps = 2;
1500   let ResourceCycles = [1,1];
1501 }
1502 def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>;
1503
1504 def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1505   let Latency = 21;
1506   let NumMicroOps = 19;
1507   let ResourceCycles = [2,1,4,1,1,4,6];
1508 }
1509 def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>;
1510
1511 def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1512   let Latency = 22;
1513   let NumMicroOps = 18;
1514   let ResourceCycles = [1,1,16];
1515 }
1516 def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
1517
1518 def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1519   let Latency = 23;
1520   let NumMicroOps = 19;
1521   let ResourceCycles = [3,1,15];
1522 }
1523 def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
1524
1525 def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1526   let Latency = 24;
1527   let NumMicroOps = 3;
1528   let ResourceCycles = [1,1,1];
1529 }
1530 def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>;
1531
1532 def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
1533   let Latency = 26;
1534   let NumMicroOps = 2;
1535   let ResourceCycles = [1,1];
1536 }
1537 def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>;
1538
1539 def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1540   let Latency = 29;
1541   let NumMicroOps = 3;
1542   let ResourceCycles = [1,1,1];
1543 }
1544 def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>;
1545
1546 def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1547   let Latency = 22;
1548   let NumMicroOps = 7;
1549   let ResourceCycles = [1,3,2,1];
1550 }
1551 def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
1552
1553 def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1554   let Latency = 23;
1555   let NumMicroOps = 9;
1556   let ResourceCycles = [1,3,4,1];
1557 }
1558 def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
1559
1560 def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1561   let Latency = 24;
1562   let NumMicroOps = 9;
1563   let ResourceCycles = [1,5,2,1];
1564 }
1565 def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
1566
1567 def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1568   let Latency = 25;
1569   let NumMicroOps = 7;
1570   let ResourceCycles = [1,3,2,1];
1571 }
1572 def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
1573                                             VGATHERDPSrm)>;
1574
1575 def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1576   let Latency = 26;
1577   let NumMicroOps = 9;
1578   let ResourceCycles = [1,5,2,1];
1579 }
1580 def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
1581
1582 def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1583   let Latency = 26;
1584   let NumMicroOps = 14;
1585   let ResourceCycles = [1,4,8,1];
1586 }
1587 def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
1588
1589 def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1590   let Latency = 27;
1591   let NumMicroOps = 9;
1592   let ResourceCycles = [1,5,2,1];
1593 }
1594 def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
1595
1596 def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1597   let Latency = 29;
1598   let NumMicroOps = 27;
1599   let ResourceCycles = [1,5,1,1,19];
1600 }
1601 def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>;
1602
1603 def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1604   let Latency = 30;
1605   let NumMicroOps = 28;
1606   let ResourceCycles = [1,6,1,1,19];
1607 }
1608 def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>;
1609 def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
1610
1611 def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
1612   let Latency = 34;
1613   let NumMicroOps = 8;
1614   let ResourceCycles = [2,2,2,1,1];
1615 }
1616 def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
1617
1618 def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
1619   let Latency = 34;
1620   let NumMicroOps = 23;
1621   let ResourceCycles = [1,5,3,4,10];
1622 }
1623 def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
1624                                              "IN(8|16|32)rr")>;
1625
1626 def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
1627   let Latency = 35;
1628   let NumMicroOps = 8;
1629   let ResourceCycles = [2,2,2,1,1];
1630 }
1631 def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
1632
1633 def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1634   let Latency = 35;
1635   let NumMicroOps = 23;
1636   let ResourceCycles = [1,5,2,1,4,10];
1637 }
1638 def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
1639                                              "OUT(8|16|32)rr")>;
1640
1641 def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
1642   let Latency = 42;
1643   let NumMicroOps = 22;
1644   let ResourceCycles = [2,20];
1645 }
1646 def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
1647
1648 def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
1649   let Latency = 60;
1650   let NumMicroOps = 64;
1651   let ResourceCycles = [2,2,8,1,10,2,39];
1652 }
1653 def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>;
1654
1655 def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1656   let Latency = 63;
1657   let NumMicroOps = 88;
1658   let ResourceCycles = [4,4,31,1,2,1,45];
1659 }
1660 def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
1661
1662 def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1663   let Latency = 63;
1664   let NumMicroOps = 90;
1665   let ResourceCycles = [4,2,33,1,2,1,47];
1666 }
1667 def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
1668
1669 def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
1670   let Latency = 75;
1671   let NumMicroOps = 15;
1672   let ResourceCycles = [6,3,6];
1673 }
1674 def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>;
1675
1676 def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
1677   let Latency = 80;
1678   let NumMicroOps = 32;
1679   let ResourceCycles = [7,7,3,3,1,11];
1680 }
1681 def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
1682
1683 def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
1684   let Latency = 115;
1685   let NumMicroOps = 100;
1686   let ResourceCycles = [9,9,11,8,1,11,21,30];
1687 }
1688 def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>;
1689
1690 def: InstRW<[WriteZero], (instrs CLC)>;
1691
1692 } // SchedModel