contrib/llvm/lib/Target/X86/X86SchedHaswell.td

   1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for Haswell to support instruction
  11 // scheduling and other instruction cost heuristics.
  12 //
  13 // Note that we define some instructions here that are not supported by haswell,
  14 // but we still have to define them because KNL uses the HSW model.
  15 // They are currently tagged with a comment `Unsupported = 1`.
  16 // FIXME: Use Unsupported = 1 once KNL has its own model.
  17 //
  18 //===----------------------------------------------------------------------===//
  19
  20 def HaswellModel : SchedMachineModel {
  21   // All x86 instructions are modeled as a single micro-op, and HW can decode 4
  22   // instructions per cycle.
  23   let IssueWidth = 4;
  24   let MicroOpBufferSize = 192; // Based on the reorder buffer.
  25   let LoadLatency = 5;
  26   let MispredictPenalty = 16;
  27
  28   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  29   let LoopMicroOpBufferSize = 50;
  30
  31   // This flag is set to allow the scheduler to assign a default model to
  32   // unrecognized opcodes.
  33   let CompleteModel = 0;
  34 }
  35
  36 let SchedModel = HaswellModel in {
  37
  38 // Haswell can issue micro-ops to 8 different ports in one cycle.
  39
  40 // Ports 0, 1, 5, and 6 handle all computation.
  41 // Port 4 gets the data half of stores. Store data can be available later than
  42 // the store address, but since we don't model the latency of stores, we can
  43 // ignore that.
  44 // Ports 2 and 3 are identical. They handle loads and the address half of
  45 // stores. Port 7 can handle address calculations.
  46 def HWPort0 : ProcResource<1>;
  47 def HWPort1 : ProcResource<1>;
  48 def HWPort2 : ProcResource<1>;
  49 def HWPort3 : ProcResource<1>;
  50 def HWPort4 : ProcResource<1>;
  51 def HWPort5 : ProcResource<1>;
  52 def HWPort6 : ProcResource<1>;
  53 def HWPort7 : ProcResource<1>;
  54
  55 // Many micro-ops are capable of issuing on multiple ports.
  56 def HWPort01  : ProcResGroup<[HWPort0, HWPort1]>;
  57 def HWPort23  : ProcResGroup<[HWPort2, HWPort3]>;
  58 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
  59 def HWPort04  : ProcResGroup<[HWPort0, HWPort4]>;
  60 def HWPort05  : ProcResGroup<[HWPort0, HWPort5]>;
  61 def HWPort06  : ProcResGroup<[HWPort0, HWPort6]>;
  62 def HWPort15  : ProcResGroup<[HWPort1, HWPort5]>;
  63 def HWPort16  : ProcResGroup<[HWPort1, HWPort6]>;
  64 def HWPort56  : ProcResGroup<[HWPort5, HWPort6]>;
  65 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
  66 def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
  67 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
  68
  69 // 60 Entry Unified Scheduler
  70 def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
  71                               HWPort5, HWPort6, HWPort7]> {
  72   let BufferSize=60;
  73 }
  74
  75 // Integer division issued on port 0.
  76 def HWDivider : ProcResource<1>;
  77 // FP division and sqrt on port 0.
  78 def HWFPDivider : ProcResource<1>;
  79
  80 // Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  81 // cycles after the memory operand.
  82 def : ReadAdvance<ReadAfterLd, 5>;
  83
  84 // Many SchedWrites are defined in pairs with and without a folded load.
  85 // Instructions with folded loads are usually micro-fused, so they only appear
  86 // as two micro-ops when queued in the reservation station.
  87 // This multiclass defines the resource usage for variants with and without
  88 // folded loads.
  89 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
  90                           list<ProcResourceKind> ExePorts,
  91                           int Lat, list<int> Res = [1], int UOps = 1,
  92                           int LoadLat = 5> {
  93   // Register variant is using a single cycle on ExePort.
  94   def : WriteRes<SchedRW, ExePorts> {
  95     let Latency = Lat;
  96     let ResourceCycles = Res;
  97     let NumMicroOps = UOps;
  98   }
  99
 100   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 101   // the latency (default = 5).
 102   def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> {
 103     let Latency = !add(Lat, LoadLat);
 104     let ResourceCycles = !listconcat([1], Res);
 105     let NumMicroOps = !add(UOps, 1);
 106   }
 107 }
 108
 109 // A folded store needs a cycle on port 4 for the store data, and an extra port
 110 // 2/3/7 cycle to recompute the address.
 111 def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;
 112
 113 // Store_addr on 237.
 114 // Store_data on 4.
 115 defm : X86WriteRes<WriteStore,   [HWPort237, HWPort4], 1, [1,1], 1>;
 116 defm : X86WriteRes<WriteStoreNT, [HWPort237, HWPort4], 1, [1,1], 2>;
 117 defm : X86WriteRes<WriteLoad,    [HWPort23], 5, [1], 1>;
 118 defm : X86WriteRes<WriteMove,    [HWPort0156], 1, [1], 1>;
 119 def  : WriteRes<WriteZero,       []>;
 120
 121 // Arithmetic.
 122 defm : HWWriteResPair<WriteALU,    [HWPort0156], 1>;
 123 defm : HWWriteResPair<WriteADC,    [HWPort06, HWPort0156], 2, [1,1], 2>;
 124 defm : HWWriteResPair<WriteIMul,   [HWPort1],   3>;
 125 defm : HWWriteResPair<WriteIMul64, [HWPort1],   3>;
 126
 127 defm : X86WriteRes<WriteBSWAP32,   [HWPort15], 1, [1], 1>;
 128 defm : X86WriteRes<WriteBSWAP64,   [HWPort06, HWPort15], 2, [1,1], 2>;
 129
 130 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 131
 132 // Integer shifts and rotates.
 133 defm : HWWriteResPair<WriteShift,  [HWPort06],  1>;
 134
 135 // SHLD/SHRD.
 136 defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>;
 137 defm : X86WriteRes<WriteSHDrrcl,[HWPort1, HWPort06, HWPort0156], 6, [1, 1, 2], 4>;
 138 defm : X86WriteRes<WriteSHDmri, [HWPort1, HWPort23, HWPort237, HWPort0156], 10, [1, 1, 1, 1], 4>;
 139 defm : X86WriteRes<WriteSHDmrcl,[HWPort1, HWPort23, HWPort237, HWPort06, HWPort0156], 12, [1, 1, 1, 1, 2], 6>;
 140
 141 defm : HWWriteResPair<WriteJump,   [HWPort06],  1>;
 142 defm : HWWriteResPair<WriteCRC32,  [HWPort1],   3>;
 143
 144 defm : HWWriteResPair<WriteCMOV,  [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move.
 145 defm : HWWriteResPair<WriteCMOV2, [HWPort06,HWPort0156], 3, [1,2], 3>; // Conditional (CF + ZF flag) move.
 146 defm : X86WriteRes<WriteFCMOV, [HWPort1], 3, [1], 1>; // x87 conditional move.
 147 def  : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
 148 def  : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> {
 149   let Latency = 2;
 150   let NumMicroOps = 3;
 151 }
 152 def  : WriteRes<WriteLAHFSAHF, [HWPort06]>;
 153 def  : WriteRes<WriteBitTest,[HWPort06]>;
 154
 155 // This is for simple LEAs with one or two input operands.
 156 // The complex ones can only execute on port 1, and they require two cycles on
 157 // the port to read all inputs. We don't model that.
 158 def : WriteRes<WriteLEA, [HWPort15]>;
 159
 160 // Bit counts.
 161 defm : HWWriteResPair<WriteBSF, [HWPort1], 3>;
 162 defm : HWWriteResPair<WriteBSR, [HWPort1], 3>;
 163 defm : HWWriteResPair<WriteLZCNT,          [HWPort1], 3>;
 164 defm : HWWriteResPair<WriteTZCNT,          [HWPort1], 3>;
 165 defm : HWWriteResPair<WritePOPCNT,         [HWPort1], 3>;
 166
 167 // BMI1 BEXTR, BMI2 BZHI
 168 defm : HWWriteResPair<WriteBEXTR, [HWPort06,HWPort15], 2, [1,1], 2>;
 169 defm : HWWriteResPair<WriteBZHI, [HWPort15], 1>;
 170
 171 defm : HWWriteResPair<WriteDiv8,   [HWPort0, HWDivider], 25, [1,10], 1, 4>;
 172 defm : HWWriteResPair<WriteDiv16,  [HWPort0, HWDivider], 25, [1,10], 1, 4>;
 173 defm : HWWriteResPair<WriteDiv32,  [HWPort0, HWDivider], 25, [1,10], 1, 4>;
 174 defm : HWWriteResPair<WriteDiv64,  [HWPort0, HWDivider], 25, [1,10], 1, 4>;
 175 defm : HWWriteResPair<WriteIDiv8,  [HWPort0, HWDivider], 25, [1,10], 1, 4>;
 176 defm : HWWriteResPair<WriteIDiv16, [HWPort0, HWDivider], 25, [1,10], 1, 4>;
 177 defm : HWWriteResPair<WriteIDiv32, [HWPort0, HWDivider], 25, [1,10], 1, 4>;
 178 defm : HWWriteResPair<WriteIDiv64, [HWPort0, HWDivider], 25, [1,10], 1, 4>;
 179
 180 // Scalar and vector floating point.
 181 defm : X86WriteRes<WriteFLD0,          [HWPort01], 1, [1], 1>;
 182 defm : X86WriteRes<WriteFLD1,          [HWPort01], 1, [2], 2>;
 183 defm : X86WriteRes<WriteFLDC,          [HWPort01], 1, [2], 2>;
 184 defm : X86WriteRes<WriteFLoad,         [HWPort23], 5, [1], 1>;
 185 defm : X86WriteRes<WriteFLoadX,        [HWPort23], 6, [1], 1>;
 186 defm : X86WriteRes<WriteFLoadY,        [HWPort23], 7, [1], 1>;
 187 defm : X86WriteRes<WriteFMaskedLoad,   [HWPort23,HWPort5], 8, [1,2], 3>;
 188 defm : X86WriteRes<WriteFMaskedLoadY,  [HWPort23,HWPort5], 9, [1,2], 3>;
 189 defm : X86WriteRes<WriteFStore,        [HWPort237,HWPort4], 1, [1,1], 2>;
 190 defm : X86WriteRes<WriteFStoreX,       [HWPort237,HWPort4], 1, [1,1], 2>;
 191 defm : X86WriteRes<WriteFStoreY,       [HWPort237,HWPort4], 1, [1,1], 2>;
 192 defm : X86WriteRes<WriteFStoreNT,      [HWPort237,HWPort4], 1, [1,1], 2>;
 193 defm : X86WriteRes<WriteFStoreNTX,     [HWPort237,HWPort4], 1, [1,1], 2>;
 194 defm : X86WriteRes<WriteFStoreNTY,     [HWPort237,HWPort4], 1, [1,1], 2>;
 195 defm : X86WriteRes<WriteFMaskedStore,  [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
 196 defm : X86WriteRes<WriteFMaskedStoreY, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
 197 defm : X86WriteRes<WriteFMove,         [HWPort5], 1, [1], 1>;
 198 defm : X86WriteRes<WriteFMoveX,        [HWPort5], 1, [1], 1>;
 199 defm : X86WriteRes<WriteFMoveY,        [HWPort5], 1, [1], 1>;
 200 defm : X86WriteRes<WriteEMMS,          [HWPort01,HWPort15,HWPort015,HWPort0156], 31, [8,1,21,1], 31>;
 201
 202 defm : HWWriteResPair<WriteFAdd,    [HWPort1],  3, [1], 1, 5>;
 203 defm : HWWriteResPair<WriteFAddX,   [HWPort1],  3, [1], 1, 6>;
 204 defm : HWWriteResPair<WriteFAddY,   [HWPort1],  3, [1], 1, 7>;
 205 defm : HWWriteResPair<WriteFAddZ,   [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
 206 defm : HWWriteResPair<WriteFAdd64,  [HWPort1],  3, [1], 1, 5>;
 207 defm : HWWriteResPair<WriteFAdd64X, [HWPort1],  3, [1], 1, 6>;
 208 defm : HWWriteResPair<WriteFAdd64Y, [HWPort1],  3, [1], 1, 7>;
 209 defm : HWWriteResPair<WriteFAdd64Z, [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
 210
 211 defm : HWWriteResPair<WriteFCmp,    [HWPort1],  3, [1], 1, 5>;
 212 defm : HWWriteResPair<WriteFCmpX,   [HWPort1],  3, [1], 1, 6>;
 213 defm : HWWriteResPair<WriteFCmpY,   [HWPort1],  3, [1], 1, 7>;
 214 defm : HWWriteResPair<WriteFCmpZ,   [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
 215 defm : HWWriteResPair<WriteFCmp64,  [HWPort1],  3, [1], 1, 5>;
 216 defm : HWWriteResPair<WriteFCmp64X, [HWPort1],  3, [1], 1, 6>;
 217 defm : HWWriteResPair<WriteFCmp64Y, [HWPort1],  3, [1], 1, 7>;
 218 defm : HWWriteResPair<WriteFCmp64Z, [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
 219
 220 defm : HWWriteResPair<WriteFCom,    [HWPort1],  3>;
 221
 222 defm : HWWriteResPair<WriteFMul,    [HWPort01],  5, [1], 1, 5>;
 223 defm : HWWriteResPair<WriteFMulX,   [HWPort01],  5, [1], 1, 6>;
 224 defm : HWWriteResPair<WriteFMulY,   [HWPort01],  5, [1], 1, 7>;
 225 defm : HWWriteResPair<WriteFMulZ,   [HWPort01],  5, [1], 1, 7>; // Unsupported = 1
 226 defm : HWWriteResPair<WriteFMul64,  [HWPort01],  5, [1], 1, 5>;
 227 defm : HWWriteResPair<WriteFMul64X, [HWPort01],  5, [1], 1, 6>;
 228 defm : HWWriteResPair<WriteFMul64Y, [HWPort01],  5, [1], 1, 7>;
 229 defm : HWWriteResPair<WriteFMul64Z, [HWPort01],  5, [1], 1, 7>; // Unsupported = 1
 230
 231 defm : HWWriteResPair<WriteFDiv,    [HWPort0,HWFPDivider], 13, [1,7], 1, 5>;
 232 defm : HWWriteResPair<WriteFDivX,   [HWPort0,HWFPDivider], 13, [1,7], 1, 6>;
 233 defm : HWWriteResPair<WriteFDivY,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>;
 234 defm : HWWriteResPair<WriteFDivZ,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1
 235 defm : HWWriteResPair<WriteFDiv64,  [HWPort0,HWFPDivider], 20, [1,14], 1, 5>;
 236 defm : HWWriteResPair<WriteFDiv64X, [HWPort0,HWFPDivider], 20, [1,14], 1, 6>;
 237 defm : HWWriteResPair<WriteFDiv64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>;
 238 defm : HWWriteResPair<WriteFDiv64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1
 239
 240 defm : HWWriteResPair<WriteFRcp,   [HWPort0],  5, [1], 1, 5>;
 241 defm : HWWriteResPair<WriteFRcpX,  [HWPort0],  5, [1], 1, 6>;
 242 defm : HWWriteResPair<WriteFRcpY,  [HWPort0,HWPort015], 11, [2,1], 3, 7>;
 243 defm : HWWriteResPair<WriteFRcpZ,  [HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1
 244
 245 defm : HWWriteResPair<WriteFRsqrt, [HWPort0],  5, [1], 1, 5>;
 246 defm : HWWriteResPair<WriteFRsqrtX,[HWPort0],  5, [1], 1, 6>;
 247 defm : HWWriteResPair<WriteFRsqrtY,[HWPort0,HWPort015], 11, [2,1], 3, 7>;
 248 defm : HWWriteResPair<WriteFRsqrtZ,[HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1
 249
 250 defm : HWWriteResPair<WriteFSqrt,    [HWPort0,HWFPDivider], 11, [1,7], 1, 5>;
 251 defm : HWWriteResPair<WriteFSqrtX,   [HWPort0,HWFPDivider], 11, [1,7], 1, 6>;
 252 defm : HWWriteResPair<WriteFSqrtY,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>;
 253 defm : HWWriteResPair<WriteFSqrtZ,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1
 254 defm : HWWriteResPair<WriteFSqrt64,  [HWPort0,HWFPDivider], 16, [1,14], 1, 5>;
 255 defm : HWWriteResPair<WriteFSqrt64X, [HWPort0,HWFPDivider], 16, [1,14], 1, 6>;
 256 defm : HWWriteResPair<WriteFSqrt64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>;
 257 defm : HWWriteResPair<WriteFSqrt64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1
 258 defm : HWWriteResPair<WriteFSqrt80,  [HWPort0,HWFPDivider], 23, [1,17]>;
 259
 260 defm : HWWriteResPair<WriteFMA,   [HWPort01], 5, [1], 1, 5>;
 261 defm : HWWriteResPair<WriteFMAX,  [HWPort01], 5, [1], 1, 6>;
 262 defm : HWWriteResPair<WriteFMAY,  [HWPort01], 5, [1], 1, 7>;
 263 defm : HWWriteResPair<WriteFMAZ,  [HWPort01], 5, [1], 1, 7>; // Unsupported = 1
 264 defm : HWWriteResPair<WriteDPPD,  [HWPort0,HWPort1,HWPort5],  9, [1,1,1], 3, 6>;
 265 defm : HWWriteResPair<WriteDPPS,  [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 6>;
 266 defm : HWWriteResPair<WriteDPPSY, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>;
 267 defm : HWWriteResPair<WriteDPPSZ, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; // Unsupported = 1
 268 defm : HWWriteResPair<WriteFSign,  [HWPort0], 1>;
 269 defm : X86WriteRes<WriteFRnd,            [HWPort23],  6, [1],   1>;
 270 defm : X86WriteRes<WriteFRndY,           [HWPort23],  6, [1],   1>;
 271 defm : X86WriteRes<WriteFRndZ,           [HWPort23],  6, [1],   1>; // Unsupported = 1
 272 defm : X86WriteRes<WriteFRndLd,  [HWPort1,HWPort23], 12, [2,1], 3>;
 273 defm : X86WriteRes<WriteFRndYLd, [HWPort1,HWPort23], 13, [2,1], 3>;
 274 defm : X86WriteRes<WriteFRndZLd, [HWPort1,HWPort23], 13, [2,1], 3>; // Unsupported = 1
 275 defm : HWWriteResPair<WriteFLogic,  [HWPort5], 1, [1], 1, 6>;
 276 defm : HWWriteResPair<WriteFLogicY, [HWPort5], 1, [1], 1, 7>;
 277 defm : HWWriteResPair<WriteFLogicZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
 278 defm : HWWriteResPair<WriteFTest,   [HWPort0], 1, [1], 1, 6>;
 279 defm : HWWriteResPair<WriteFTestY,  [HWPort0], 1, [1], 1, 7>;
 280 defm : HWWriteResPair<WriteFTestZ,  [HWPort0], 1, [1], 1, 7>; // Unsupported = 1
 281 defm : HWWriteResPair<WriteFShuffle,  [HWPort5], 1, [1], 1, 6>;
 282 defm : HWWriteResPair<WriteFShuffleY, [HWPort5], 1, [1], 1, 7>;
 283 defm : HWWriteResPair<WriteFShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
 284 defm : HWWriteResPair<WriteFVarShuffle,  [HWPort5], 1, [1], 1, 6>;
 285 defm : HWWriteResPair<WriteFVarShuffleY, [HWPort5], 1, [1], 1, 7>;
 286 defm : HWWriteResPair<WriteFVarShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
 287 defm : HWWriteResPair<WriteFBlend,  [HWPort015], 1, [1], 1, 6>;
 288 defm : HWWriteResPair<WriteFBlendY, [HWPort015], 1, [1], 1, 7>;
 289 defm : HWWriteResPair<WriteFBlendZ, [HWPort015], 1, [1], 1, 7>; // Unsupported = 1
 290 defm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3, [1], 1, 7>;
 291 defm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3, [1], 1, 7>;
 292 defm : HWWriteResPair<WriteFVarBlend,  [HWPort5], 2, [2], 2, 6>;
 293 defm : HWWriteResPair<WriteFVarBlendY, [HWPort5], 2, [2], 2, 7>;
 294 defm : HWWriteResPair<WriteFVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1
 295
 296 // Conversion between integer and float.
 297 defm : HWWriteResPair<WriteCvtSD2I,   [HWPort1], 3>;
 298 defm : HWWriteResPair<WriteCvtPD2I,   [HWPort1], 3>;
 299 defm : HWWriteResPair<WriteCvtPD2IY,  [HWPort1], 3>;
 300 defm : HWWriteResPair<WriteCvtPD2IZ,  [HWPort1], 3>; // Unsupported = 1
 301 defm : HWWriteResPair<WriteCvtSS2I,   [HWPort1], 3>;
 302 defm : HWWriteResPair<WriteCvtPS2I,   [HWPort1], 3>;
 303 defm : HWWriteResPair<WriteCvtPS2IY,  [HWPort1], 3>;
 304 defm : HWWriteResPair<WriteCvtPS2IZ,  [HWPort1], 3>; // Unsupported = 1
 305
 306 defm : HWWriteResPair<WriteCvtI2SD,   [HWPort1], 4>;
 307 defm : HWWriteResPair<WriteCvtI2PD,   [HWPort1], 4>;
 308 defm : HWWriteResPair<WriteCvtI2PDY,  [HWPort1], 4>;
 309 defm : HWWriteResPair<WriteCvtI2PDZ,  [HWPort1], 4>; // Unsupported = 1
 310 defm : HWWriteResPair<WriteCvtI2SS,   [HWPort1], 4>;
 311 defm : HWWriteResPair<WriteCvtI2PS,   [HWPort1], 4>;
 312 defm : HWWriteResPair<WriteCvtI2PSY,  [HWPort1], 4>;
 313 defm : HWWriteResPair<WriteCvtI2PSZ,  [HWPort1], 4>; // Unsupported = 1
 314
 315 defm : HWWriteResPair<WriteCvtSS2SD,  [HWPort1], 3>;
 316 defm : HWWriteResPair<WriteCvtPS2PD,  [HWPort1], 3>;
 317 defm : HWWriteResPair<WriteCvtPS2PDY, [HWPort1], 3>;
 318 defm : HWWriteResPair<WriteCvtPS2PDZ, [HWPort1], 3>; // Unsupported = 1
 319 defm : HWWriteResPair<WriteCvtSD2SS,  [HWPort1], 3>;
 320 defm : HWWriteResPair<WriteCvtPD2PS,  [HWPort1], 3>;
 321 defm : HWWriteResPair<WriteCvtPD2PSY, [HWPort1], 3>;
 322 defm : HWWriteResPair<WriteCvtPD2PSZ, [HWPort1], 3>; // Unsupported = 1
 323
 324 defm : X86WriteRes<WriteCvtPH2PS,     [HWPort0,HWPort5], 2, [1,1], 2>;
 325 defm : X86WriteRes<WriteCvtPH2PSY,    [HWPort0,HWPort5], 2, [1,1], 2>;
 326 defm : X86WriteRes<WriteCvtPH2PSZ,    [HWPort0,HWPort5], 2, [1,1], 2>; // Unsupported = 1
 327 defm : X86WriteRes<WriteCvtPH2PSLd,  [HWPort0,HWPort23], 6, [1,1], 2>;
 328 defm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort0,HWPort23], 7, [1,1], 2>;
 329 defm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort0,HWPort23], 7, [1,1], 2>; // Unsupported = 1
 330
 331 defm : X86WriteRes<WriteCvtPS2PH,    [HWPort1,HWPort5], 4, [1,1], 2>;
 332 defm : X86WriteRes<WriteCvtPS2PHY,   [HWPort1,HWPort5], 6, [1,1], 2>;
 333 defm : X86WriteRes<WriteCvtPS2PHZ,   [HWPort1,HWPort5], 6, [1,1], 2>; // Unsupported = 1
 334 defm : X86WriteRes<WriteCvtPS2PHSt,  [HWPort1,HWPort4,HWPort5,HWPort237], 5, [1,1,1,1], 4>;
 335 defm : X86WriteRes<WriteCvtPS2PHYSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>;
 336 defm : X86WriteRes<WriteCvtPS2PHZSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; // Unsupported = 1
 337
 338 // Vector integer operations.
 339 defm : X86WriteRes<WriteVecLoad,         [HWPort23], 5, [1], 1>;
 340 defm : X86WriteRes<WriteVecLoadX,        [HWPort23], 6, [1], 1>;
 341 defm : X86WriteRes<WriteVecLoadY,        [HWPort23], 7, [1], 1>;
 342 defm : X86WriteRes<WriteVecLoadNT,       [HWPort23], 6, [1], 1>;
 343 defm : X86WriteRes<WriteVecLoadNTY,      [HWPort23], 7, [1], 1>;
 344 defm : X86WriteRes<WriteVecMaskedLoad,   [HWPort23,HWPort5], 8, [1,2], 3>;
 345 defm : X86WriteRes<WriteVecMaskedLoadY,  [HWPort23,HWPort5], 9, [1,2], 3>;
 346 defm : X86WriteRes<WriteVecStore,        [HWPort237,HWPort4], 1, [1,1], 2>;
 347 defm : X86WriteRes<WriteVecStoreX,       [HWPort237,HWPort4], 1, [1,1], 2>;
 348 defm : X86WriteRes<WriteVecStoreY,       [HWPort237,HWPort4], 1, [1,1], 2>;
 349 defm : X86WriteRes<WriteVecStoreNT,      [HWPort237,HWPort4], 1, [1,1], 2>;
 350 defm : X86WriteRes<WriteVecStoreNTY,     [HWPort237,HWPort4], 1, [1,1], 2>;
 351 defm : X86WriteRes<WriteVecMaskedStore,  [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
 352 defm : X86WriteRes<WriteVecMaskedStoreY, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
 353 defm : X86WriteRes<WriteVecMove,         [HWPort015], 1, [1], 1>;
 354 defm : X86WriteRes<WriteVecMoveX,        [HWPort015], 1, [1], 1>;
 355 defm : X86WriteRes<WriteVecMoveY,        [HWPort015], 1, [1], 1>;
 356 defm : X86WriteRes<WriteVecMoveToGpr,    [HWPort0], 1, [1], 1>;
 357 defm : X86WriteRes<WriteVecMoveFromGpr,  [HWPort5], 1, [1], 1>;
 358
 359 defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 5>;
 360 defm : HWWriteResPair<WriteVecLogicX,[HWPort015], 1, [1], 1, 6>;
 361 defm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>;
 362 defm : HWWriteResPair<WriteVecLogicZ,[HWPort015], 1, [1], 1, 7>; // Unsupported = 1
 363 defm : HWWriteResPair<WriteVecTest,  [HWPort0,HWPort5], 2, [1,1], 2, 6>;
 364 defm : HWWriteResPair<WriteVecTestY, [HWPort0,HWPort5], 4, [1,1], 2, 7>;
 365 defm : HWWriteResPair<WriteVecTestZ, [HWPort0,HWPort5], 4, [1,1], 2, 7>; // Unsupported = 1
 366 defm : HWWriteResPair<WriteVecALU,   [HWPort15],  1, [1], 1, 5>;
 367 defm : HWWriteResPair<WriteVecALUX,  [HWPort15],  1, [1], 1, 6>;
 368 defm : HWWriteResPair<WriteVecALUY,  [HWPort15],  1, [1], 1, 7>;
 369 defm : HWWriteResPair<WriteVecALUZ,  [HWPort15],  1, [1], 1, 7>; // Unsupported = 1
 370 defm : HWWriteResPair<WriteVecIMul,  [HWPort0],  5, [1], 1, 5>;
 371 defm : HWWriteResPair<WriteVecIMulX, [HWPort0],  5, [1], 1, 6>;
 372 defm : HWWriteResPair<WriteVecIMulY, [HWPort0],  5, [1], 1, 7>;
 373 defm : HWWriteResPair<WriteVecIMulZ, [HWPort0],  5, [1], 1, 7>; // Unsupported = 1
 374 defm : HWWriteResPair<WritePMULLD,   [HWPort0], 10, [2], 2, 6>;
 375 defm : HWWriteResPair<WritePMULLDY,  [HWPort0], 10, [2], 2, 7>;
 376 defm : HWWriteResPair<WritePMULLDZ,  [HWPort0], 10, [2], 2, 7>; // Unsupported = 1
 377 defm : HWWriteResPair<WriteShuffle,  [HWPort5],  1, [1], 1, 5>;
 378 defm : HWWriteResPair<WriteShuffleX, [HWPort5],  1, [1], 1, 6>;
 379 defm : HWWriteResPair<WriteShuffleY, [HWPort5],  1, [1], 1, 7>;
 380 defm : HWWriteResPair<WriteShuffleZ, [HWPort5],  1, [1], 1, 7>; // Unsupported = 1
 381 defm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1, [1], 1, 5>;
 382 defm : HWWriteResPair<WriteVarShuffleX,[HWPort5], 1, [1], 1, 6>;
 383 defm : HWWriteResPair<WriteVarShuffleY,[HWPort5], 1, [1], 1, 7>;
 384 defm : HWWriteResPair<WriteVarShuffleZ,[HWPort5], 1, [1], 1, 7>; // Unsupported = 1
 385 defm : HWWriteResPair<WriteBlend,  [HWPort5], 1, [1], 1, 6>;
 386 defm : HWWriteResPair<WriteBlendY, [HWPort5], 1, [1], 1, 7>;
 387 defm : HWWriteResPair<WriteBlendZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
 388 defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3, [1], 1, 7>;
 389 defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3, [1], 1, 7>;
 390 defm : HWWriteResPair<WriteVarBlend,  [HWPort5], 2, [2], 2, 6>;
 391 defm : HWWriteResPair<WriteVarBlendY, [HWPort5], 2, [2], 2, 7>;
 392 defm : HWWriteResPair<WriteVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1
 393 defm : HWWriteResPair<WriteMPSAD,  [HWPort0, HWPort5], 7, [1, 2], 3, 6>;
 394 defm : HWWriteResPair<WriteMPSADY, [HWPort0, HWPort5], 7, [1, 2], 3, 7>;
 395 defm : HWWriteResPair<WriteMPSADZ, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; // Unsupported = 1
 396 defm : HWWriteResPair<WritePSADBW,  [HWPort0], 5, [1], 1, 5>;
 397 defm : HWWriteResPair<WritePSADBWX, [HWPort0], 5, [1], 1, 6>;
 398 defm : HWWriteResPair<WritePSADBWY, [HWPort0], 5, [1], 1, 7>;
 399 defm : HWWriteResPair<WritePSADBWZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1
 400 defm : HWWriteResPair<WritePHMINPOS, [HWPort0],  5, [1], 1, 6>;
 401
 402 // Vector integer shifts.
 403 defm : HWWriteResPair<WriteVecShift,     [HWPort0], 1, [1], 1, 5>;
 404 defm : HWWriteResPair<WriteVecShiftX,    [HWPort0,HWPort5],  2, [1,1], 2, 6>;
 405 defm : X86WriteRes<WriteVecShiftY,       [HWPort0,HWPort5],  4, [1,1], 2>;
 406 defm : X86WriteRes<WriteVecShiftZ,       [HWPort0,HWPort5],  4, [1,1], 2>; // Unsupported = 1
 407 defm : X86WriteRes<WriteVecShiftYLd,     [HWPort0,HWPort23], 8, [1,1], 2>;
 408 defm : X86WriteRes<WriteVecShiftZLd,     [HWPort0,HWPort23], 8, [1,1], 2>; // Unsupported = 1
 409
 410 defm : HWWriteResPair<WriteVecShiftImm,  [HWPort0], 1, [1], 1, 5>;
 411 defm : HWWriteResPair<WriteVecShiftImmX, [HWPort0], 1, [1], 1, 6>;
 412 defm : HWWriteResPair<WriteVecShiftImmY, [HWPort0], 1, [1], 1, 7>;
 413 defm : HWWriteResPair<WriteVecShiftImmZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1
 414 defm : HWWriteResPair<WriteVarVecShift,  [HWPort0, HWPort5], 3, [2,1], 3, 6>;
 415 defm : HWWriteResPair<WriteVarVecShiftY, [HWPort0, HWPort5], 3, [2,1], 3, 7>;
 416 defm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; // Unsupported = 1
 417
 418 // Vector insert/extract operations.
 419 def : WriteRes<WriteVecInsert, [HWPort5]> {
 420   let Latency = 2;
 421   let NumMicroOps = 2;
 422   let ResourceCycles = [2];
 423 }
 424 def : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> {
 425   let Latency = 6;
 426   let NumMicroOps = 2;
 427 }
 428 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 429
 430 def : WriteRes<WriteVecExtract, [HWPort0,HWPort5]> {
 431   let Latency = 2;
 432   let NumMicroOps = 2;
 433 }
 434 def : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> {
 435   let Latency = 2;
 436   let NumMicroOps = 3;
 437 }
 438
 439 // String instructions.
 440
 441 // Packed Compare Implicit Length Strings, Return Mask
 442 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
 443   let Latency = 11;
 444   let NumMicroOps = 3;
 445   let ResourceCycles = [3];
 446 }
 447 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
 448   let Latency = 17;
 449   let NumMicroOps = 4;
 450   let ResourceCycles = [3,1];
 451 }
 452
 453 // Packed Compare Explicit Length Strings, Return Mask
 454 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> {
 455   let Latency = 19;
 456   let NumMicroOps = 9;
 457   let ResourceCycles = [4,3,1,1];
 458 }
 459 def : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> {
 460   let Latency = 25;
 461   let NumMicroOps = 10;
 462   let ResourceCycles = [4,3,1,1,1];
 463 }
 464
 465 // Packed Compare Implicit Length Strings, Return Index
 466 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
 467   let Latency = 11;
 468   let NumMicroOps = 3;
 469   let ResourceCycles = [3];
 470 }
 471 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
 472   let Latency = 17;
 473   let NumMicroOps = 4;
 474   let ResourceCycles = [3,1];
 475 }
 476
 477 // Packed Compare Explicit Length Strings, Return Index
 478 def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> {
 479   let Latency = 18;
 480   let NumMicroOps = 8;
 481   let ResourceCycles = [4,3,1];
 482 }
 483 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> {
 484   let Latency = 24;
 485   let NumMicroOps = 9;
 486   let ResourceCycles = [4,3,1,1];
 487 }
 488
 489 // MOVMSK Instructions.
 490 def : WriteRes<WriteFMOVMSK,    [HWPort0]> { let Latency = 3; }
 491 def : WriteRes<WriteVecMOVMSK,  [HWPort0]> { let Latency = 3; }
 492 def : WriteRes<WriteVecMOVMSKY, [HWPort0]> { let Latency = 3; }
 493 def : WriteRes<WriteMMXMOVMSK,  [HWPort0]> { let Latency = 1; }
 494
 495 // AES Instructions.
 496 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
 497   let Latency = 7;
 498   let NumMicroOps = 1;
 499   let ResourceCycles = [1];
 500 }
 501 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
 502   let Latency = 13;
 503   let NumMicroOps = 2;
 504   let ResourceCycles = [1,1];
 505 }
 506
 507 def : WriteRes<WriteAESIMC, [HWPort5]> {
 508   let Latency = 14;
 509   let NumMicroOps = 2;
 510   let ResourceCycles = [2];
 511 }
 512 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
 513   let Latency = 20;
 514   let NumMicroOps = 3;
 515   let ResourceCycles = [2,1];
 516 }
 517
 518 def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> {
 519   let Latency = 29;
 520   let NumMicroOps = 11;
 521   let ResourceCycles = [2,7,2];
 522 }
 523 def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> {
 524   let Latency = 34;
 525   let NumMicroOps = 11;
 526   let ResourceCycles = [2,7,1,1];
 527 }
 528
 529 // Carry-less multiplication instructions.
 530 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
 531   let Latency = 11;
 532   let NumMicroOps = 3;
 533   let ResourceCycles = [2,1];
 534 }
 535 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
 536   let Latency = 17;
 537   let NumMicroOps = 4;
 538   let ResourceCycles = [2,1,1];
 539 }
 540
 541 // Load/store MXCSR.
 542 def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 543 def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 544
 545 def : WriteRes<WriteSystem,     [HWPort0156]> { let Latency = 100; }
 546 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
 547 def : WriteRes<WriteFence,  [HWPort23, HWPort4]>;
 548 def : WriteRes<WriteNop, []>;
 549
 550 //================ Exceptions ================//
 551
 552 //-- Specific Scheduling Models --//
 553
 554 // Starting with P0.
 555 def HWWriteP0 : SchedWriteRes<[HWPort0]>;
 556
 557 def HWWriteP01 : SchedWriteRes<[HWPort01]>;
 558
 559 def HWWrite2P01 : SchedWriteRes<[HWPort01]> {
 560   let NumMicroOps = 2;
 561 }
 562 def HWWrite3P01 : SchedWriteRes<[HWPort01]> {
 563   let NumMicroOps = 3;
 564 }
 565
 566 def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
 567   let NumMicroOps = 2;
 568 }
 569
 570 def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
 571   let NumMicroOps = 3;
 572   let ResourceCycles = [2, 1];
 573 }
 574
 575 // Starting with P1.
 576 def HWWriteP1 : SchedWriteRes<[HWPort1]>;
 577
 578
 579 def HWWrite2P1 : SchedWriteRes<[HWPort1]> {
 580   let NumMicroOps = 2;
 581   let ResourceCycles = [2];
 582 }
 583
 584 // Notation:
 585 // - r: register.
 586 // - mm: 64 bit mmx register.
 587 // - x = 128 bit xmm register.
 588 // - (x)mm = mmx or xmm register.
 589 // - y = 256 bit ymm register.
 590 // - v = any vector register.
 591 // - m = memory.
 592
 593 //=== Integer Instructions ===//
 594 //-- Move instructions --//
 595
 596 // XLAT.
 597 def HWWriteXLAT : SchedWriteRes<[]> {
 598   let Latency = 7;
 599   let NumMicroOps = 3;
 600 }
 601 def : InstRW<[HWWriteXLAT], (instrs XLAT)>;
 602
 603 // PUSHA.
 604 def HWWritePushA : SchedWriteRes<[]> {
 605   let NumMicroOps = 19;
 606 }
 607 def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>;
 608
 609 // POPA.
 610 def HWWritePopA : SchedWriteRes<[]> {
 611   let NumMicroOps = 18;
 612 }
 613 def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>;
 614
 615 //-- Arithmetic instructions --//
 616
 617 // DIV.
 618 // r8.
 619 def HWWriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
 620   let Latency = 22;
 621   let NumMicroOps = 9;
 622 }
 623 def : InstRW<[HWWriteDiv8], (instregex "DIV8r")>;
 624
 625 // IDIV.
 626 // r8.
 627 def HWWriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
 628   let Latency = 23;
 629   let NumMicroOps = 9;
 630 }
 631 def : InstRW<[HWWriteIDiv8], (instregex "IDIV8r")>;
 632
 633 // BT.
 634 // m,r.
 635 def HWWriteBTmr : SchedWriteRes<[]> {
 636   let NumMicroOps = 10;
 637 }
 638 def : InstRW<[HWWriteBTmr], (instregex "BT(16|32|64)mr")>;
 639
 640 // BTR BTS BTC.
 641 // m,r.
 642 def HWWriteBTRSCmr : SchedWriteRes<[]> {
 643   let NumMicroOps = 11;
 644 }
 645 def : InstRW<[HWWriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
 646
 647 //-- Control transfer instructions --//
 648
 649 // CALL.
 650 // i.
 651 def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
 652   let NumMicroOps = 4;
 653   let ResourceCycles = [1, 2, 1];
 654 }
 655 def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
 656
 657 // BOUND.
 658 // r,m.
 659 def HWWriteBOUND : SchedWriteRes<[]> {
 660   let NumMicroOps = 15;
 661 }
 662 def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>;
 663
 664 // INTO.
 665 def HWWriteINTO : SchedWriteRes<[]> {
 666   let NumMicroOps = 4;
 667 }
 668 def : InstRW<[HWWriteINTO], (instrs INTO)>;
 669
 670 //-- String instructions --//
 671
 672 // LODSB/W.
 673 def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>;
 674
 675 // LODSD/Q.
 676 def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>;
 677
 678 // MOVS.
 679 def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
 680   let Latency = 4;
 681   let NumMicroOps = 5;
 682   let ResourceCycles = [2, 1, 2];
 683 }
 684 def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
 685
 686 // CMPS.
 687 def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
 688   let Latency = 4;
 689   let NumMicroOps = 5;
 690   let ResourceCycles = [2, 3];
 691 }
 692 def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
 693
 694 //-- Other --//
 695
 696 // RDPMC.f
 697 def HWWriteRDPMC : SchedWriteRes<[]> {
 698   let NumMicroOps = 34;
 699 }
 700 def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>;
 701
 702 // RDRAND.
 703 def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
 704   let NumMicroOps = 17;
 705   let ResourceCycles = [1, 16];
 706 }
 707 def : InstRW<[HWWriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
 708
 709 //=== Floating Point x87 Instructions ===//
 710 //-- Move instructions --//
 711
 712 // FLD.
 713 // m80.
 714 def : InstRW<[HWWriteP01], (instregex "LD_Frr")>;
 715
 716 // FBLD.
 717 // m80.
 718 def HWWriteFBLD : SchedWriteRes<[]> {
 719   let Latency = 47;
 720   let NumMicroOps = 43;
 721 }
 722 def : InstRW<[HWWriteFBLD], (instregex "FBLDm")>;
 723
 724 // FST(P).
 725 // r.
 726 def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>;
 727
 728 // FFREE.
 729 def : InstRW<[HWWriteP01], (instregex "FFREE")>;
 730
 731 // FNSAVE.
 732 def HWWriteFNSAVE : SchedWriteRes<[]> {
 733   let NumMicroOps = 147;
 734 }
 735 def : InstRW<[HWWriteFNSAVE], (instregex "FSAVEm")>;
 736
 737 // FRSTOR.
 738 def HWWriteFRSTOR : SchedWriteRes<[]> {
 739   let NumMicroOps = 90;
 740 }
 741 def : InstRW<[HWWriteFRSTOR], (instregex "FRSTORm")>;
 742
 743 //-- Arithmetic instructions --//
 744
 745 // FCOMPP FUCOMPP.
 746 // r.
 747 def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>;
 748
 749 // FCOMI(P) FUCOMI(P).
 750 // m.
 751 def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
 752
 753 // FTST.
 754 def : InstRW<[HWWriteP1], (instregex "TST_F")>;
 755
 756 // FXAM.
 757 def : InstRW<[HWWrite2P1], (instrs FXAM)>;
 758
 759 // FPREM.
 760 def HWWriteFPREM : SchedWriteRes<[]> {
 761   let Latency = 19;
 762   let NumMicroOps = 28;
 763 }
 764 def : InstRW<[HWWriteFPREM], (instrs FPREM)>;
 765
 766 // FPREM1.
 767 def HWWriteFPREM1 : SchedWriteRes<[]> {
 768   let Latency = 27;
 769   let NumMicroOps = 41;
 770 }
 771 def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>;
 772
 773 // FRNDINT.
 774 def HWWriteFRNDINT : SchedWriteRes<[]> {
 775   let Latency = 11;
 776   let NumMicroOps = 17;
 777 }
 778 def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>;
 779
 780 //-- Math instructions --//
 781
 782 // FSCALE.
 783 def HWWriteFSCALE : SchedWriteRes<[]> {
 784   let Latency = 75; // 49-125
 785   let NumMicroOps = 50; // 25-75
 786 }
 787 def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>;
 788
 789 // FXTRACT.
 790 def HWWriteFXTRACT : SchedWriteRes<[]> {
 791   let Latency = 15;
 792   let NumMicroOps = 17;
 793 }
 794 def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>;
 795
 796 ////////////////////////////////////////////////////////////////////////////////
 797 // Horizontal add/sub  instructions.
 798 ////////////////////////////////////////////////////////////////////////////////
 799
 800 defm : HWWriteResPair<WriteFHAdd,  [HWPort1, HWPort5], 5, [1,2], 3, 6>;
 801 defm : HWWriteResPair<WriteFHAddY, [HWPort1, HWPort5], 5, [1,2], 3, 7>;
 802 defm : HWWriteResPair<WritePHAdd,  [HWPort5, HWPort15], 3, [2,1], 3, 5>;
 803 defm : HWWriteResPair<WritePHAddX, [HWPort5, HWPort15], 3, [2,1], 3, 6>;
 804 defm : HWWriteResPair<WritePHAddY, [HWPort5, HWPort15], 3, [2,1], 3, 7>;
 805
 806 //=== Floating Point XMM and YMM Instructions ===//
 807
 808 // Remaining instrs.
 809
 810 def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {
 811   let Latency = 6;
 812   let NumMicroOps = 1;
 813   let ResourceCycles = [1];
 814 }
 815 def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm",
 816                                            "(V?)MOVSHDUPrm",
 817                                            "(V?)MOVSLDUPrm",
 818                                            "VPBROADCAST(D|Q)rm")>;
 819
 820 def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
 821   let Latency = 7;
 822   let NumMicroOps = 1;
 823   let ResourceCycles = [1];
 824 }
 825 def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m",
 826                                              "VBROADCASTF128",
 827                                              "VBROADCASTI128",
 828                                              "VBROADCASTSDYrm",
 829                                              "VBROADCASTSSYrm",
 830                                              "VMOVDDUPYrm",
 831                                              "VMOVSHDUPYrm",
 832                                              "VMOVSLDUPYrm",
 833                                              "VPBROADCAST(D|Q)Yrm")>;
 834
 835 def HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> {
 836   let Latency = 5;
 837   let NumMicroOps = 1;
 838   let ResourceCycles = [1];
 839 }
 840 def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm16",
 841                                              "MOVSX(16|32|64)rm32",
 842                                              "MOVSX(16|32|64)rm8",
 843                                              "MOVZX(16|32|64)rm16",
 844                                              "MOVZX(16|32|64)rm8",
 845                                              "(V?)MOVDDUPrm")>;
 846
 847 def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
 848   let Latency = 1;
 849   let NumMicroOps = 2;
 850   let ResourceCycles = [1,1];
 851 }
 852 def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm",
 853                                            "ST_FP(32|64|80)m",
 854                                            "VMPTRSTm")>;
 855
 856 def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
 857   let Latency = 1;
 858   let NumMicroOps = 1;
 859   let ResourceCycles = [1];
 860 }
 861 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr",
 862                                            "VPSRLVQ(Y?)rr")>;
 863
 864 def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
 865   let Latency = 1;
 866   let NumMicroOps = 1;
 867   let ResourceCycles = [1];
 868 }
 869 def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r",
 870                                            "UCOM_F(P?)r")>;
 871
 872 def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
 873   let Latency = 1;
 874   let NumMicroOps = 1;
 875   let ResourceCycles = [1];
 876 }
 877 def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVQ2DQrr")>;
 878
 879 def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
 880   let Latency = 1;
 881   let NumMicroOps = 1;
 882   let ResourceCycles = [1];
 883 }
 884 def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>;
 885
 886 def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {
 887   let Latency = 1;
 888   let NumMicroOps = 1;
 889   let ResourceCycles = [1];
 890 }
 891 def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;
 892
 893 def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
 894   let Latency = 1;
 895   let NumMicroOps = 1;
 896   let ResourceCycles = [1];
 897 }
 898 def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>;
 899
 900 def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
 901   let Latency = 1;
 902   let NumMicroOps = 1;
 903   let ResourceCycles = [1];
 904 }
 905 def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr",
 906                                            "BLSI(32|64)rr",
 907                                            "BLSMSK(32|64)rr",
 908                                            "BLSR(32|64)rr")>;
 909
 910 def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
 911   let Latency = 1;
 912   let NumMicroOps = 1;
 913   let ResourceCycles = [1];
 914 }
 915 def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>;
 916
 917 def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
 918   let Latency = 1;
 919   let NumMicroOps = 1;
 920   let ResourceCycles = [1];
 921 }
 922 def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE,
 923                                          CMC, STC)>;
 924 def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m",
 925                                             "SIDT64m",
 926                                             "SMSW16m",
 927                                             "STRm",
 928                                             "SYSCALL")>;
 929
 930 def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
 931   let Latency = 6;
 932   let NumMicroOps = 2;
 933   let ResourceCycles = [1,1];
 934 }
 935 def: InstRW<[HWWriteResGroup11], (instregex "(V?)CVTPS2PDrm")>;
 936
 937 def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {
 938   let Latency = 7;
 939   let NumMicroOps = 2;
 940   let ResourceCycles = [1,1];
 941 }
 942 def: InstRW<[HWWriteResGroup11_1], (instregex "(V?)CVTSS2SDrm",
 943                                               "VPSLLVQrm",
 944                                               "VPSRLVQrm")>;
 945
 946 def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> {
 947   let Latency = 8;
 948   let NumMicroOps = 2;
 949   let ResourceCycles = [1,1];
 950 }
 951 def: InstRW<[HWWriteResGroup11_2], (instregex "VPSLLVQYrm",
 952                                               "VPSRLVQYrm")>;
 953
 954 def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
 955   let Latency = 8;
 956   let NumMicroOps = 2;
 957   let ResourceCycles = [1,1];
 958 }
 959 def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTPI2PSirm",
 960                                             "PDEP(32|64)rm",
 961                                             "PEXT(32|64)rm")>;
 962
 963 def HWWriteResGroup12_1 : SchedWriteRes<[HWPort1,HWPort0156,HWPort23]> {
 964   let Latency = 8;
 965   let NumMicroOps = 3;
 966   let ResourceCycles = [1,1,1];
 967 }
 968 def: InstRW<[HWWriteResGroup12_1], (instrs IMUL16rmi, IMUL16rmi8)>;
 969
 970 def HWWriteResGroup12_2 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156,HWPort23]> {
 971   let Latency = 9;
 972   let NumMicroOps = 5;
 973   let ResourceCycles = [1,1,2,1];
 974 }
 975 def: InstRW<[HWWriteResGroup12_2], (instrs IMUL16m, MUL16m)>;
 976
 977 def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {
 978   let Latency = 6;
 979   let NumMicroOps = 2;
 980   let ResourceCycles = [1,1];
 981 }
 982 def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm",
 983                                             "(V?)PMOV(SX|ZX)BQrm",
 984                                             "(V?)PMOV(SX|ZX)BWrm",
 985                                             "(V?)PMOV(SX|ZX)DQrm",
 986                                             "(V?)PMOV(SX|ZX)WDrm",
 987                                             "(V?)PMOV(SX|ZX)WQrm")>;
 988
 989 def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> {
 990   let Latency = 8;
 991   let NumMicroOps = 2;
 992   let ResourceCycles = [1,1];
 993 }
 994 def: InstRW<[HWWriteResGroup13_1], (instregex "VPMOVSXBDYrm",
 995                                               "VPMOVSXBQYrm",
 996                                               "VPMOVSXWQYrm")>;
 997
 998 def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
 999   let Latency = 6;
1000   let NumMicroOps = 2;
1001   let ResourceCycles = [1,1];
1002 }
1003 def: InstRW<[HWWriteResGroup14], (instregex "FARJMP64",
1004                                             "JMP(16|32|64)m")>;
1005
1006 def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort06]> {
1007   let Latency = 6;
1008   let NumMicroOps = 2;
1009   let ResourceCycles = [1,1];
1010 }
1011 def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>;
1012
1013 def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
1014   let Latency = 6;
1015   let NumMicroOps = 2;
1016   let ResourceCycles = [1,1];
1017 }
1018 def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
1019                                             "BLSI(32|64)rm",
1020                                             "BLSMSK(32|64)rm",
1021                                             "BLSR(32|64)rm",
1022                                             "MOVBE(16|32|64)rm")>;
1023
1024 def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> {
1025   let Latency = 7;
1026   let NumMicroOps = 2;
1027   let ResourceCycles = [1,1];
1028 }
1029 def: InstRW<[HWWriteResGroup17], (instregex "VINSERTF128rm",
1030                                             "VINSERTI128rm",
1031                                             "VPBLENDDrmi")>;
1032
1033 def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> {
1034   let Latency = 8;
1035   let NumMicroOps = 2;
1036   let ResourceCycles = [1,1];
1037 }
1038 def: InstRW<[HWWriteResGroup17_2], (instregex "VPBLENDDYrmi")>;
1039
1040 def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
1041   let Latency = 6;
1042   let NumMicroOps = 2;
1043   let ResourceCycles = [1,1];
1044 }
1045 def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;
1046 def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
1047
1048 def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
1049   let Latency = 2;
1050   let NumMicroOps = 2;
1051   let ResourceCycles = [1,1];
1052 }
1053 def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>;
1054
1055 def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
1056   let Latency = 2;
1057   let NumMicroOps = 3;
1058   let ResourceCycles = [1,1,1];
1059 }
1060 def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>;
1061
1062 def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {
1063   let Latency = 2;
1064   let NumMicroOps = 3;
1065   let ResourceCycles = [1,1,1];
1066 }
1067 def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>;
1068
1069 def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
1070   let Latency = 2;
1071   let NumMicroOps = 3;
1072   let ResourceCycles = [1,1,1];
1073 }
1074 def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>;
1075
1076 def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
1077   let Latency = 2;
1078   let NumMicroOps = 3;
1079   let ResourceCycles = [1,1,1];
1080 }
1081 def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r,
1082                                          STOSB, STOSL, STOSQ, STOSW)>;
1083 def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr",
1084                                             "PUSH64i8")>;
1085
1086 def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
1087   let Latency = 7;
1088   let NumMicroOps = 4;
1089   let ResourceCycles = [1,1,1,1];
1090 }
1091 def: InstRW<[HWWriteResGroup25], (instregex "BTC(16|32|64)mi8",
1092                                             "BTR(16|32|64)mi8",
1093                                             "BTS(16|32|64)mi8",
1094                                             "SAR(8|16|32|64)m1",
1095                                             "SAR(8|16|32|64)mi",
1096                                             "SHL(8|16|32|64)m1",
1097                                             "SHL(8|16|32|64)mi",
1098                                             "SHR(8|16|32|64)m1",
1099                                             "SHR(8|16|32|64)mi")>;
1100
1101 def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1102   let Latency = 7;
1103   let NumMicroOps = 4;
1104   let ResourceCycles = [1,1,1,1];
1105 }
1106 def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm",
1107                                             "PUSH(16|32|64)rmm")>;
1108
1109 def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> {
1110   let Latency = 2;
1111   let NumMicroOps = 2;
1112   let ResourceCycles = [2];
1113 }
1114 def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>;
1115
1116 def HWWriteResGroup29 : SchedWriteRes<[HWPort06]> {
1117   let Latency = 2;
1118   let NumMicroOps = 2;
1119   let ResourceCycles = [2];
1120 }
1121 def: InstRW<[HWWriteResGroup29], (instregex "ROL(8|16|32|64)r1",
1122                                             "ROL(8|16|32|64)ri",
1123                                             "ROR(8|16|32|64)r1",
1124                                             "ROR(8|16|32|64)ri")>;
1125
1126 def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
1127   let Latency = 2;
1128   let NumMicroOps = 2;
1129   let ResourceCycles = [2];
1130 }
1131 def: InstRW<[HWWriteResGroup30], (instrs LFENCE,
1132                                          MFENCE,
1133                                          WAIT,
1134                                          XGETBV)>;
1135
1136 def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> {
1137   let Latency = 2;
1138   let NumMicroOps = 2;
1139   let ResourceCycles = [1,1];
1140 }
1141 def: InstRW<[HWWriteResGroup31], (instregex "(V?)CVTPS2PDrr",
1142                                             "(V?)CVTSS2SDrr")>;
1143
1144 def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> {
1145   let Latency = 2;
1146   let NumMicroOps = 2;
1147   let ResourceCycles = [1,1];
1148 }
1149 def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>;
1150
1151 def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> {
1152   let Latency = 2;
1153   let NumMicroOps = 2;
1154   let ResourceCycles = [1,1];
1155 }
1156 def: InstRW<[HWWriteResGroup33], (instregex "MMX_MOVDQ2Qrr")>;
1157
1158 def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
1159   let Latency = 2;
1160   let NumMicroOps = 2;
1161   let ResourceCycles = [1,1];
1162 }
1163 def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;
1164 def: InstRW<[HWWriteResGroup35], (instregex "SET(A|BE)r")>;
1165
1166 def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {
1167   let Latency = 7;
1168   let NumMicroOps = 3;
1169   let ResourceCycles = [2,1];
1170 }
1171 def: InstRW<[HWWriteResGroup36_2], (instregex "MMX_PACKSSDWirm",
1172                                               "MMX_PACKSSWBirm",
1173                                               "MMX_PACKUSWBirm")>;
1174
1175 def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> {
1176   let Latency = 7;
1177   let NumMicroOps = 3;
1178   let ResourceCycles = [1,2];
1179 }
1180 def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64,
1181                                          SCASB, SCASL, SCASQ, SCASW)>;
1182
1183 def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> {
1184   let Latency = 7;
1185   let NumMicroOps = 3;
1186   let ResourceCycles = [1,1,1];
1187 }
1188 def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>;
1189
1190 def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
1191   let Latency = 7;
1192   let NumMicroOps = 3;
1193   let ResourceCycles = [1,1,1];
1194 }
1195 def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>;
1196
1197 def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
1198   let Latency = 3;
1199   let NumMicroOps = 4;
1200   let ResourceCycles = [1,1,1,1];
1201 }
1202 def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;
1203
1204 def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
1205   let Latency = 3;
1206   let NumMicroOps = 4;
1207   let ResourceCycles = [1,1,1,1];
1208 }
1209 def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>;
1210 def: InstRW<[HWWriteResGroup45], (instregex "SET(A|BE)m")>;
1211
1212 def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
1213   let Latency = 8;
1214   let NumMicroOps = 5;
1215   let ResourceCycles = [1,1,1,2];
1216 }
1217 def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m1",
1218                                             "ROL(8|16|32|64)mi",
1219                                             "ROR(8|16|32|64)m1",
1220                                             "ROR(8|16|32|64)mi")>;
1221
1222 def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1223   let Latency = 8;
1224   let NumMicroOps = 5;
1225   let ResourceCycles = [1,1,1,2];
1226 }
1227 def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>;
1228
1229 def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1230   let Latency = 8;
1231   let NumMicroOps = 5;
1232   let ResourceCycles = [1,1,1,1,1];
1233 }
1234 def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m",
1235                                             "FARCALL64")>;
1236
1237 def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
1238   let Latency = 3;
1239   let NumMicroOps = 1;
1240   let ResourceCycles = [1];
1241 }
1242 def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr",
1243                                             "PDEP(32|64)rr",
1244                                             "PEXT(32|64)rr",
1245                                             "(V?)CVTDQ2PS(Y?)rr")>;
1246
1247 def HWWriteResGroup50_16i : SchedWriteRes<[HWPort1, HWPort0156]> {
1248   let Latency = 4;
1249   let NumMicroOps = 2;
1250   let ResourceCycles = [1,1];
1251 }
1252 def: InstRW<[HWWriteResGroup50_16i], (instrs IMUL16rri, IMUL16rri8)>;
1253
1254 def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {
1255   let Latency = 3;
1256   let NumMicroOps = 1;
1257   let ResourceCycles = [1];
1258 }
1259 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>;
1260
1261 def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> {
1262   let Latency = 9;
1263   let NumMicroOps = 2;
1264   let ResourceCycles = [1,1];
1265 }
1266 def: InstRW<[HWWriteResGroup52], (instregex "(V?)CVTPS2DQrm",
1267                                             "(V?)CVTTPS2DQrm")>;
1268
1269 def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {
1270   let Latency = 10;
1271   let NumMicroOps = 2;
1272   let ResourceCycles = [1,1];
1273 }
1274 def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1275                                               "ILD_F(16|32|64)m",
1276                                               "VCVTDQ2PSYrm",
1277                                               "VCVTPS2DQYrm",
1278                                               "VCVTTPS2DQYrm")>;
1279
1280 def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> {
1281   let Latency = 9;
1282   let NumMicroOps = 2;
1283   let ResourceCycles = [1,1];
1284 }
1285 def: InstRW<[HWWriteResGroup53_1], (instregex "VPMOVSXBWYrm",
1286                                               "VPMOVSXDQYrm",
1287                                               "VPMOVSXWDYrm",
1288                                               "VPMOVZXWDYrm")>;
1289
1290 def HWWriteResGroup54 : SchedWriteRes<[HWPort0156]> {
1291   let Latency = 2;
1292   let NumMicroOps = 3;
1293   let ResourceCycles = [3];
1294 }
1295 def: InstRW<[HWWriteResGroup54], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr,
1296                                          XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr,
1297                                          XCHG16ar, XCHG32ar, XCHG64ar)>;
1298
1299 def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> {
1300   let Latency = 3;
1301   let NumMicroOps = 3;
1302   let ResourceCycles = [2,1];
1303 }
1304 def: InstRW<[HWWriteResGroup57], (instregex "MMX_PACKSSDWirr",
1305                                             "MMX_PACKSSWBirr",
1306                                             "MMX_PACKUSWBirr")>;
1307
1308 def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {
1309   let Latency = 3;
1310   let NumMicroOps = 3;
1311   let ResourceCycles = [1,2];
1312 }
1313 def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
1314
1315 def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {
1316   let Latency = 3;
1317   let NumMicroOps = 3;
1318   let ResourceCycles = [1,2];
1319 }
1320 def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r1",
1321                                             "RCL(8|16|32|64)ri",
1322                                             "RCR(8|16|32|64)r1",
1323                                             "RCR(8|16|32|64)ri")>;
1324
1325 def HWWriteResGroup60 : SchedWriteRes<[HWPort06,HWPort0156]> {
1326   let Latency = 3;
1327   let NumMicroOps = 3;
1328   let ResourceCycles = [2,1];
1329 }
1330 def: InstRW<[HWWriteResGroup60], (instregex "ROL(8|16|32|64)rCL",
1331                                             "ROR(8|16|32|64)rCL",
1332                                             "SAR(8|16|32|64)rCL",
1333                                             "SHL(8|16|32|64)rCL",
1334                                             "SHR(8|16|32|64)rCL")>;
1335
1336 def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {
1337   let Latency = 4;
1338   let NumMicroOps = 3;
1339   let ResourceCycles = [1,1,1];
1340 }
1341 def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>;
1342
1343 def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> {
1344   let Latency = 4;
1345   let NumMicroOps = 3;
1346   let ResourceCycles = [1,1,1];
1347 }
1348 def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m",
1349                                             "IST_F(16|32)m")>;
1350
1351 def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
1352   let Latency = 9;
1353   let NumMicroOps = 5;
1354   let ResourceCycles = [1,1,1,2];
1355 }
1356 def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m1",
1357                                             "RCL(8|16|32|64)mi",
1358                                             "RCR(8|16|32|64)m1",
1359                                             "RCR(8|16|32|64)mi")>;
1360
1361 def HWWriteResGroup67 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
1362   let Latency = 9;
1363   let NumMicroOps = 5;
1364   let ResourceCycles = [1,1,2,1];
1365 }
1366 def: InstRW<[HWWriteResGroup67], (instregex "ROR(8|16|32|64)mCL")>;
1367
1368 def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1369   let Latency = 9;
1370   let NumMicroOps = 6;
1371   let ResourceCycles = [1,1,1,3];
1372 }
1373 def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
1374
1375 def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1376   let Latency = 9;
1377   let NumMicroOps = 6;
1378   let ResourceCycles = [1,1,1,2,1];
1379 }
1380 def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(8|16|32|64)rm",
1381                                             "ROL(8|16|32|64)mCL",
1382                                             "SAR(8|16|32|64)mCL",
1383                                             "SHL(8|16|32|64)mCL",
1384                                             "SHR(8|16|32|64)mCL")>;
1385 def: SchedAlias<WriteADCRMW, HWWriteResGroup69>;
1386
1387 def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {
1388   let Latency = 4;
1389   let NumMicroOps = 2;
1390   let ResourceCycles = [1,1];
1391 }
1392 def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr",
1393                                             "(V?)CVT(T?)SS2SI(64)?rr")>;
1394
1395 def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> {
1396   let Latency = 4;
1397   let NumMicroOps = 2;
1398   let ResourceCycles = [1,1];
1399 }
1400 def: InstRW<[HWWriteResGroup71], (instregex "VCVTPS2PDYrr")>;
1401
1402 def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> {
1403   let Latency = 4;
1404   let NumMicroOps = 2;
1405   let ResourceCycles = [1,1];
1406 }
1407 def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>;
1408
1409 def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
1410   let Latency = 4;
1411   let NumMicroOps = 2;
1412   let ResourceCycles = [1,1];
1413 }
1414 def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPI2PDirr",
1415                                             "MMX_CVT(T?)PD2PIirr",
1416                                             "MMX_CVT(T?)PS2PIirr",
1417                                             "(V?)CVTDQ2PDrr",
1418                                             "(V?)CVTPD2PSrr",
1419                                             "(V?)CVTSD2SSrr",
1420                                             "(V?)CVTSI(64)?2SDrr",
1421                                             "(V?)CVTSI2SSrr",
1422                                             "(V?)CVT(T?)PD2DQrr")>;
1423
1424 def HWWriteResGroup74 : SchedWriteRes<[HWPort1,HWPort6]> {
1425   let Latency = 4;
1426   let NumMicroOps = 2;
1427   let ResourceCycles = [1,1];
1428 }
1429 def: InstRW<[HWWriteResGroup74], (instrs IMUL64r, MUL64r, MULX64rr)>;
1430
1431 def HWWriteResGroup74_16 : SchedWriteRes<[HWPort1, HWPort06, HWPort0156]> {
1432   let Latency = 4;
1433   let NumMicroOps = 4;
1434   let ResourceCycles = [1,1,2];
1435 }
1436 def: InstRW<[HWWriteResGroup74_16], (instrs IMUL16r, MUL16r)>;
1437
1438 def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> {
1439   let Latency = 11;
1440   let NumMicroOps = 3;
1441   let ResourceCycles = [2,1];
1442 }
1443 def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>;
1444
1445 def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1446   let Latency = 9;
1447   let NumMicroOps = 3;
1448   let ResourceCycles = [1,1,1];
1449 }
1450 def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm",
1451                                             "(V?)CVTSS2SI(64)?rm",
1452                                             "(V?)CVTTSD2SI(64)?rm",
1453                                             "VCVTTSS2SI64rm",
1454                                             "(V?)CVTTSS2SIrm")>;
1455
1456 def HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
1457   let Latency = 10;
1458   let NumMicroOps = 3;
1459   let ResourceCycles = [1,1,1];
1460 }
1461 def: InstRW<[HWWriteResGroup77], (instregex "VCVTPS2PDYrm")>;
1462
1463 def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1464   let Latency = 10;
1465   let NumMicroOps = 3;
1466   let ResourceCycles = [1,1,1];
1467 }
1468 def: InstRW<[HWWriteResGroup78], (instregex "CVTPD2PSrm",
1469                                             "CVT(T?)PD2DQrm",
1470                                             "MMX_CVT(T?)PD2PIirm",
1471                                             "(V?)CVTDQ2PDrm")>;
1472
1473 def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1474   let Latency = 9;
1475   let NumMicroOps = 3;
1476   let ResourceCycles = [1,1,1];
1477 }
1478 def: InstRW<[HWWriteResGroup78_1], (instregex "MMX_CVTPI2PDirm",
1479                                               "(V?)CVTSD2SSrm")>;
1480
1481 def HWWriteResGroup79 : SchedWriteRes<[HWPort1,HWPort6,HWPort23]> {
1482   let Latency = 9;
1483   let NumMicroOps = 3;
1484   let ResourceCycles = [1,1,1];
1485 }
1486 def: InstRW<[HWWriteResGroup79], (instrs IMUL64m, MUL64m, MULX64rm)>;
1487
1488 def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> {
1489   let Latency = 9;
1490   let NumMicroOps = 3;
1491   let ResourceCycles = [1,1,1];
1492 }
1493 def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>;
1494
1495 def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> {
1496   let Latency = 4;
1497   let NumMicroOps = 4;
1498   let ResourceCycles = [4];
1499 }
1500 def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>;
1501
1502 def HWWriteResGroup82 : SchedWriteRes<[HWPort015,HWPort0156]> {
1503   let Latency = 4;
1504   let NumMicroOps = 4;
1505   let ResourceCycles = [1,3];
1506 }
1507 def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>;
1508
1509 def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> {
1510   let Latency = 4;
1511   let NumMicroOps = 4;
1512   let ResourceCycles = [1,1,2];
1513 }
1514 def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
1515
1516 def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> {
1517   let Latency = 9;
1518   let NumMicroOps = 5;
1519   let ResourceCycles = [1,2,1,1];
1520 }
1521 def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
1522                                             "LSL(16|32|64)rm")>;
1523
1524 def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
1525   let Latency = 5;
1526   let NumMicroOps = 6;
1527   let ResourceCycles = [1,1,4];
1528 }
1529 def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>;
1530
1531 def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> {
1532   let Latency = 5;
1533   let NumMicroOps = 1;
1534   let ResourceCycles = [1];
1535 }
1536 def: InstRW<[HWWriteResGroup89], (instregex "(V?)PCMPGTQ(Y?)rr",
1537                                             "MUL_(FPrST0|FST0r|FrST0)")>;
1538
1539 def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> {
1540   let Latency = 11;
1541   let NumMicroOps = 2;
1542   let ResourceCycles = [1,1];
1543 }
1544 def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>;
1545
1546 def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> {
1547   let Latency = 12;
1548   let NumMicroOps = 2;
1549   let ResourceCycles = [1,1];
1550 }
1551 def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m",
1552                                               "VPCMPGTQYrm")>;
1553
1554 def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> {
1555   let Latency = 5;
1556   let NumMicroOps = 3;
1557   let ResourceCycles = [1,2];
1558 }
1559 def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>;
1560
1561 def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {
1562   let Latency = 5;
1563   let NumMicroOps = 3;
1564   let ResourceCycles = [1,1,1];
1565 }
1566 def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>;
1567
1568 def HWWriteResGroup95 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
1569   let Latency = 4;
1570   let NumMicroOps = 3;
1571   let ResourceCycles = [1,1,1];
1572 }
1573 def: InstRW<[HWWriteResGroup95], (instrs IMUL32r, MUL32r, MULX32rr)>;
1574
1575 def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> {
1576   let Latency = 10;
1577   let NumMicroOps = 4;
1578   let ResourceCycles = [1,1,1,1];
1579 }
1580 def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>;
1581
1582 def HWWriteResGroup98 : SchedWriteRes<[HWPort1,HWPort23,HWPort06,HWPort0156]> {
1583   let Latency = 9;
1584   let NumMicroOps = 4;
1585   let ResourceCycles = [1,1,1,1];
1586 }
1587 def: InstRW<[HWWriteResGroup98], (instrs IMUL32m, MUL32m, MULX32rm)>;
1588
1589 def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {
1590   let Latency = 5;
1591   let NumMicroOps = 5;
1592   let ResourceCycles = [1,4];
1593 }
1594 def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>;
1595
1596 def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> {
1597   let Latency = 5;
1598   let NumMicroOps = 5;
1599   let ResourceCycles = [1,4];
1600 }
1601 def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>;
1602
1603 def HWWriteResGroup101 : SchedWriteRes<[HWPort06,HWPort0156]> {
1604   let Latency = 5;
1605   let NumMicroOps = 5;
1606   let ResourceCycles = [2,3];
1607 }
1608 def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG(8|16|32|64)rr")>;
1609
1610 def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> {
1611   let Latency = 6;
1612   let NumMicroOps = 2;
1613   let ResourceCycles = [1,1];
1614 }
1615 def: InstRW<[HWWriteResGroup102], (instregex "VCVTDQ2PDYrr",
1616                                              "VCVTPD2PSYrr",
1617                                              "VCVT(T?)PD2DQYrr")>;
1618
1619 def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> {
1620   let Latency = 13;
1621   let NumMicroOps = 3;
1622   let ResourceCycles = [2,1];
1623 }
1624 def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1625
1626 def HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1627   let Latency = 12;
1628   let NumMicroOps = 3;
1629   let ResourceCycles = [1,1,1];
1630 }
1631 def: InstRW<[HWWriteResGroup104], (instregex "VCVTDQ2PDYrm")>;
1632
1633 def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> {
1634   let Latency = 6;
1635   let NumMicroOps = 4;
1636   let ResourceCycles = [1,1,1,1];
1637 }
1638 def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>;
1639
1640 def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> {
1641   let Latency = 6;
1642   let NumMicroOps = 6;
1643   let ResourceCycles = [1,5];
1644 }
1645 def: InstRW<[HWWriteResGroup108], (instrs STD)>;
1646
1647 def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> {
1648   let Latency = 7;
1649   let NumMicroOps = 7;
1650   let ResourceCycles = [2,2,1,2];
1651 }
1652 def: InstRW<[HWWriteResGroup114], (instrs LOOP)>;
1653
1654 def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1655   let Latency = 15;
1656   let NumMicroOps = 3;
1657   let ResourceCycles = [1,1,1];
1658 }
1659 def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>;
1660
1661 def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1662   let Latency = 16;
1663   let NumMicroOps = 10;
1664   let ResourceCycles = [1,1,1,4,1,2];
1665 }
1666 def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>;
1667
1668 def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
1669   let Latency = 11;
1670   let NumMicroOps = 7;
1671   let ResourceCycles = [2,2,3];
1672 }
1673 def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL",
1674                                              "RCR(16|32|64)rCL")>;
1675
1676 def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
1677   let Latency = 11;
1678   let NumMicroOps = 9;
1679   let ResourceCycles = [1,4,1,3];
1680 }
1681 def: InstRW<[HWWriteResGroup130], (instregex "RCL8rCL")>;
1682
1683 def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> {
1684   let Latency = 11;
1685   let NumMicroOps = 11;
1686   let ResourceCycles = [2,9];
1687 }
1688 def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>;
1689
1690 def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1691   let Latency = 17;
1692   let NumMicroOps = 14;
1693   let ResourceCycles = [1,1,1,4,2,5];
1694 }
1695 def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>;
1696
1697 def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1698   let Latency = 19;
1699   let NumMicroOps = 11;
1700   let ResourceCycles = [2,1,1,3,1,3];
1701 }
1702 def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;
1703
1704 def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
1705   let Latency = 14;
1706   let NumMicroOps = 10;
1707   let ResourceCycles = [2,3,1,4];
1708 }
1709 def: InstRW<[HWWriteResGroup142], (instregex "RCR8rCL")>;
1710
1711 def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> {
1712   let Latency = 19;
1713   let NumMicroOps = 15;
1714   let ResourceCycles = [1,14];
1715 }
1716 def: InstRW<[HWWriteResGroup143], (instregex "POPF16")>;
1717
1718 def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1719   let Latency = 21;
1720   let NumMicroOps = 8;
1721   let ResourceCycles = [1,1,1,1,1,1,2];
1722 }
1723 def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>;
1724
1725 def HWWriteResGroup145 : SchedWriteRes<[HWPort5]> {
1726   let Latency = 16;
1727   let NumMicroOps = 16;
1728   let ResourceCycles = [16];
1729 }
1730 def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>;
1731
1732 def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1733   let Latency = 22;
1734   let NumMicroOps = 19;
1735   let ResourceCycles = [2,1,4,1,1,4,6];
1736 }
1737 def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>;
1738
1739 def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {
1740   let Latency = 17;
1741   let NumMicroOps = 15;
1742   let ResourceCycles = [2,1,2,4,2,4];
1743 }
1744 def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>;
1745
1746 def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> {
1747   let Latency = 18;
1748   let NumMicroOps = 8;
1749   let ResourceCycles = [1,1,1,5];
1750 }
1751 def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>;
1752
1753 def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
1754   let Latency = 23;
1755   let NumMicroOps = 19;
1756   let ResourceCycles = [3,1,15];
1757 }
1758 def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>;
1759
1760 def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> {
1761   let Latency = 20;
1762   let NumMicroOps = 1;
1763   let ResourceCycles = [1];
1764 }
1765 def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1766
1767 def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> {
1768   let Latency = 27;
1769   let NumMicroOps = 2;
1770   let ResourceCycles = [1,1];
1771 }
1772 def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>;
1773
1774 def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> {
1775   let Latency = 20;
1776   let NumMicroOps = 10;
1777   let ResourceCycles = [1,2,7];
1778 }
1779 def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>;
1780
1781 def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1782   let Latency = 30;
1783   let NumMicroOps = 3;
1784   let ResourceCycles = [1,1,1];
1785 }
1786 def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>;
1787
1788 def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> {
1789   let Latency = 24;
1790   let NumMicroOps = 1;
1791   let ResourceCycles = [1];
1792 }
1793 def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1794
1795 def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> {
1796   let Latency = 31;
1797   let NumMicroOps = 2;
1798   let ResourceCycles = [1,1];
1799 }
1800 def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>;
1801
1802 def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1803   let Latency = 30;
1804   let NumMicroOps = 27;
1805   let ResourceCycles = [1,5,1,1,19];
1806 }
1807 def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>;
1808
1809 def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1810   let Latency = 31;
1811   let NumMicroOps = 28;
1812   let ResourceCycles = [1,6,1,1,19];
1813 }
1814 def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>;
1815 def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
1816
1817 def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1818   let Latency = 34;
1819   let NumMicroOps = 3;
1820   let ResourceCycles = [1,1,1];
1821 }
1822 def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>;
1823
1824 def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> {
1825   let Latency = 35;
1826   let NumMicroOps = 23;
1827   let ResourceCycles = [1,5,3,4,10];
1828 }
1829 def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri",
1830                                              "IN(8|16|32)rr")>;
1831
1832 def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1833   let Latency = 36;
1834   let NumMicroOps = 23;
1835   let ResourceCycles = [1,5,2,1,4,10];
1836 }
1837 def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir",
1838                                              "OUT(8|16|32)rr")>;
1839
1840 def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> {
1841   let Latency = 41;
1842   let NumMicroOps = 18;
1843   let ResourceCycles = [1,1,2,3,1,1,1,8];
1844 }
1845 def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>;
1846
1847 def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> {
1848   let Latency = 42;
1849   let NumMicroOps = 22;
1850   let ResourceCycles = [2,20];
1851 }
1852 def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>;
1853
1854 def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> {
1855   let Latency = 61;
1856   let NumMicroOps = 64;
1857   let ResourceCycles = [2,2,8,1,10,2,39];
1858 }
1859 def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>;
1860
1861 def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
1862   let Latency = 64;
1863   let NumMicroOps = 88;
1864   let ResourceCycles = [4,4,31,1,2,1,45];
1865 }
1866 def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>;
1867
1868 def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
1869   let Latency = 64;
1870   let NumMicroOps = 90;
1871   let ResourceCycles = [4,2,33,1,2,1,47];
1872 }
1873 def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>;
1874
1875 def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> {
1876   let Latency = 75;
1877   let NumMicroOps = 15;
1878   let ResourceCycles = [6,3,6];
1879 }
1880 def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>;
1881
1882 def HWWriteResGroup181 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {
1883   let Latency = 98;
1884   let NumMicroOps = 32;
1885   let ResourceCycles = [7,7,3,3,1,11];
1886 }
1887 def: InstRW<[HWWriteResGroup181], (instregex "DIV(16|32|64)r")>;
1888
1889 def HWWriteResGroup182 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156]> {
1890   let Latency = 112;
1891   let NumMicroOps = 66;
1892   let ResourceCycles = [4,2,4,8,14,34];
1893 }
1894 def: InstRW<[HWWriteResGroup182], (instregex "IDIV(16|32|64)r")>;
1895
1896 def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> {
1897   let Latency = 115;
1898   let NumMicroOps = 100;
1899   let ResourceCycles = [9,9,11,8,1,11,21,30];
1900 }
1901 def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>;
1902
1903 def HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, HWPort06, HWPort23]> {
1904   let Latency = 26;
1905   let NumMicroOps = 12;
1906   let ResourceCycles = [2,2,1,3,2,2];
1907 }
1908 def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm,
1909                                           VPGATHERDQrm,
1910                                           VPGATHERDDrm)>;
1911
1912 def HWWriteResGroup185 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1913   let Latency = 24;
1914   let NumMicroOps = 22;
1915   let ResourceCycles = [5,3,4,1,5,4];
1916 }
1917 def: InstRW<[HWWriteResGroup185], (instrs VGATHERQPDYrm,
1918                                           VPGATHERQQYrm)>;
1919
1920 def HWWriteResGroup186 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1921   let Latency = 28;
1922   let NumMicroOps = 22;
1923   let ResourceCycles = [5,3,4,1,5,4];
1924 }
1925 def: InstRW<[HWWriteResGroup186], (instrs VPGATHERQDYrm)>;
1926
1927 def HWWriteResGroup187 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1928   let Latency = 25;
1929   let NumMicroOps = 22;
1930   let ResourceCycles = [5,3,4,1,5,4];
1931 }
1932 def: InstRW<[HWWriteResGroup187], (instrs VPGATHERQDrm)>;
1933
1934 def HWWriteResGroup188 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1935   let Latency = 27;
1936   let NumMicroOps = 20;
1937   let ResourceCycles = [3,3,4,1,5,4];
1938 }
1939 def: InstRW<[HWWriteResGroup188], (instrs VGATHERDPDYrm,
1940                                           VPGATHERDQYrm)>;
1941
1942 def HWWriteResGroup189 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1943   let Latency = 27;
1944   let NumMicroOps = 34;
1945   let ResourceCycles = [5,3,8,1,9,8];
1946 }
1947 def: InstRW<[HWWriteResGroup189], (instrs VGATHERDPSYrm,
1948                                           VPGATHERDDYrm)>;
1949
1950 def HWWriteResGroup190 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1951   let Latency = 23;
1952   let NumMicroOps = 14;
1953   let ResourceCycles = [3,3,2,1,3,2];
1954 }
1955 def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPDrm,
1956                                           VPGATHERQQrm)>;
1957
1958 def HWWriteResGroup191 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1959   let Latency = 28;
1960   let NumMicroOps = 15;
1961   let ResourceCycles = [3,3,2,1,4,2];
1962 }
1963 def: InstRW<[HWWriteResGroup191], (instrs VGATHERQPSYrm)>;
1964
1965 def HWWriteResGroup192 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1966   let Latency = 25;
1967   let NumMicroOps = 15;
1968   let ResourceCycles = [3,3,2,1,4,2];
1969 }
1970 def: InstRW<[HWWriteResGroup192], (instrs VGATHERQPSrm,
1971                                           VGATHERDPSrm)>;
1972
1973 def: InstRW<[WriteZero], (instrs CLC)>;
1974
1975 } // SchedModel