1 //===-- X86SchedPredicates.td - X86 Scheduling Predicates --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines scheduling predicate definitions that are common to
11 // all X86 subtargets.
13 //===----------------------------------------------------------------------===//
15 // A predicate used to identify dependency-breaking instructions that clear the
16 // content of the destination register. Note that this predicate only checks if
17 // input registers are the same. This predicate doesn't make any assumptions on
18 // the expected instruction opcodes, because different processors may implement
19 // different zero-idioms.
20 def ZeroIdiomPredicate : CheckSameRegOperand<1, 2>;
22 // A predicate used to check if an instruction is a LEA, and if it uses all
23 // three source operands: base, index, and offset.
24 def IsThreeOperandsLEAPredicate: CheckAll<[
25 CheckOpcode<[LEA32r, LEA64r, LEA64_32r, LEA16r]>,
29 CheckNot<CheckInvalidRegOperand<1>>,
31 // isRegOperand(Index)
33 CheckNot<CheckInvalidRegOperand<3>>,
35 // hasLEAOffset(Offset)
39 CheckNot<CheckZeroOperand<4>>
41 CheckNonPortable<"MI.getOperand(4).isGlobal()">
45 // This predicate evaluates to true only if the input machine instruction is a
46 // 3-operands LEA. Tablegen automatically generates a new method for it in
48 def IsThreeOperandsLEAFn :
49 TIIPredicate<"X86", "isThreeOperandsLEA", IsThreeOperandsLEAPredicate>;