1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Sandy Bridge to support instruction
11 // scheduling and other instruction cost heuristics.
13 // Note that we define some instructions here that are not supported by SNB,
14 // but we still have to define them because SNB is the default subtarget for
15 // X86. These instructions are tagged with a comment `Unsupported = 1`.
17 //===----------------------------------------------------------------------===//
19 def SandyBridgeModel : SchedMachineModel {
20 // All x86 instructions are modeled as a single micro-op, and SB can decode 4
21 // instructions per cycle.
22 // FIXME: Identify instructions that aren't a single fused micro-op.
24 let MicroOpBufferSize = 168; // Based on the reorder buffer.
26 let MispredictPenalty = 16;
28 // Based on the LSD (loop-stream detector) queue size.
29 let LoopMicroOpBufferSize = 28;
31 // This flag is set to allow the scheduler to assign
32 // a default model to unrecognized opcodes.
33 let CompleteModel = 0;
36 let SchedModel = SandyBridgeModel in {
38 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
40 // Ports 0, 1, and 5 handle all computation.
41 def SBPort0 : ProcResource<1>;
42 def SBPort1 : ProcResource<1>;
43 def SBPort5 : ProcResource<1>;
45 // Ports 2 and 3 are identical. They handle loads and the address half of
47 def SBPort23 : ProcResource<2>;
49 // Port 4 gets the data half of stores. Store data can be available later than
50 // the store address, but since we don't model the latency of stores, we can
52 def SBPort4 : ProcResource<1>;
54 // Many micro-ops are capable of issuing on multiple ports.
55 def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
56 def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>;
57 def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
58 def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
60 // 54 Entry Unified Scheduler
61 def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> {
65 // Integer division issued on port 0.
66 def SBDivider : ProcResource<1>;
67 // FP division and sqrt on port 0.
68 def SBFPDivider : ProcResource<1>;
70 // Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
71 // cycles after the memory operand.
72 def : ReadAdvance<ReadAfterLd, 5>;
74 // Many SchedWrites are defined in pairs with and without a folded load.
75 // Instructions with folded loads are usually micro-fused, so they only appear
76 // as two micro-ops when queued in the reservation station.
77 // This multiclass defines the resource usage for variants with and without
79 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
80 list<ProcResourceKind> ExePorts,
81 int Lat, list<int> Res = [1], int UOps = 1,
83 // Register variant is using a single cycle on ExePort.
84 def : WriteRes<SchedRW, ExePorts> {
86 let ResourceCycles = Res;
87 let NumMicroOps = UOps;
90 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
91 // the latency (default = 5).
92 def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> {
93 let Latency = !add(Lat, LoadLat);
94 let ResourceCycles = !listconcat([1], Res);
95 let NumMicroOps = !add(UOps, 1);
99 // A folded store needs a cycle on port 4 for the store data, and an extra port
100 // 2/3 cycle to recompute the address.
101 def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
103 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
104 def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>;
105 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; }
106 def : WriteRes<WriteMove, [SBPort015]>;
107 def : WriteRes<WriteZero, []>;
110 defm : SBWriteResPair<WriteALU, [SBPort015], 1>;
111 defm : SBWriteResPair<WriteADC, [SBPort05,SBPort015], 2, [1,1], 2>;
112 defm : SBWriteResPair<WriteIMul, [SBPort1], 3>;
113 defm : SBWriteResPair<WriteIMul64, [SBPort1], 3>;
115 defm : X86WriteRes<WriteBSWAP32, [SBPort1], 1, [1], 1>;
116 defm : X86WriteRes<WriteBSWAP64, [SBPort1,SBPort05], 2, [1,1], 2>;
118 defm : SBWriteResPair<WriteDiv8, [SBPort0, SBDivider], 25, [1, 10]>;
119 defm : SBWriteResPair<WriteDiv16, [SBPort0, SBDivider], 25, [1, 10]>;
120 defm : SBWriteResPair<WriteDiv32, [SBPort0, SBDivider], 25, [1, 10]>;
121 defm : SBWriteResPair<WriteDiv64, [SBPort0, SBDivider], 25, [1, 10]>;
122 defm : SBWriteResPair<WriteIDiv8, [SBPort0, SBDivider], 25, [1, 10]>;
123 defm : SBWriteResPair<WriteIDiv16, [SBPort0, SBDivider], 25, [1, 10]>;
124 defm : SBWriteResPair<WriteIDiv32, [SBPort0, SBDivider], 25, [1, 10]>;
125 defm : SBWriteResPair<WriteIDiv64, [SBPort0, SBDivider], 25, [1, 10]>;
127 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
130 defm : X86WriteRes<WriteSHDrri, [SBPort05, SBPort015], 2, [1, 1], 2>;
131 defm : X86WriteRes<WriteSHDrrcl,[SBPort05, SBPort015], 4, [3, 1], 4>;
132 defm : X86WriteRes<WriteSHDmri, [SBPort4,SBPort23,SBPort05,SBPort015], 8, [1, 2, 1, 1], 5>;
133 defm : X86WriteRes<WriteSHDmrcl,[SBPort4,SBPort23,SBPort05,SBPort015], 10, [1, 2, 3, 1], 7>;
135 defm : SBWriteResPair<WriteShift, [SBPort05], 1>;
136 defm : SBWriteResPair<WriteJump, [SBPort5], 1>;
137 defm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>;
139 defm : SBWriteResPair<WriteCMOV, [SBPort05,SBPort015], 2, [1,1], 2>; // Conditional move.
140 defm : SBWriteResPair<WriteCMOV2, [SBPort05,SBPort015], 3, [2,1], 3>; // Conditional (CF + ZF flag) move.
141 defm : X86WriteRes<WriteFCMOV, [SBPort5,SBPort05], 3, [2,1], 3>; // x87 conditional move.
142 def : WriteRes<WriteSETCC, [SBPort05]>; // Setcc.
143 def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> {
147 def : WriteRes<WriteLAHFSAHF, [SBPort05]>;
148 def : WriteRes<WriteBitTest,[SBPort05]>;
150 // This is for simple LEAs with one or two input operands.
151 // The complex ones can only execute on port 1, and they require two cycles on
152 // the port to read all inputs. We don't model that.
153 def : WriteRes<WriteLEA, [SBPort01]>;
156 defm : SBWriteResPair<WriteBSF, [SBPort1], 3, [1], 1, 5>;
157 defm : SBWriteResPair<WriteBSR, [SBPort1], 3, [1], 1, 5>;
158 defm : SBWriteResPair<WriteLZCNT, [SBPort1], 3, [1], 1, 5>;
159 defm : SBWriteResPair<WriteTZCNT, [SBPort1], 3, [1], 1, 5>;
160 defm : SBWriteResPair<WritePOPCNT, [SBPort1], 3, [1], 1, 6>;
162 // BMI1 BEXTR, BMI2 BZHI
163 // NOTE: These don't exist on Sandy Bridge. Ports are guesses.
164 defm : SBWriteResPair<WriteBEXTR, [SBPort05,SBPort1], 2, [1,1], 2>;
165 defm : SBWriteResPair<WriteBZHI, [SBPort1], 1>;
167 // Scalar and vector floating point.
168 defm : X86WriteRes<WriteFLD0, [SBPort5], 1, [1], 1>;
169 defm : X86WriteRes<WriteFLD1, [SBPort0,SBPort5], 1, [1,1], 2>;
170 defm : X86WriteRes<WriteFLDC, [SBPort0,SBPort1], 1, [1,1], 2>;
171 defm : X86WriteRes<WriteFLoad, [SBPort23], 5, [1], 1>;
172 defm : X86WriteRes<WriteFLoadX, [SBPort23], 6, [1], 1>;
173 defm : X86WriteRes<WriteFLoadY, [SBPort23], 7, [1], 1>;
174 defm : X86WriteRes<WriteFMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>;
175 defm : X86WriteRes<WriteFMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>;
176 defm : X86WriteRes<WriteFStore, [SBPort23,SBPort4], 1, [1,1], 1>;
177 defm : X86WriteRes<WriteFStoreX, [SBPort23,SBPort4], 1, [1,1], 1>;
178 defm : X86WriteRes<WriteFStoreY, [SBPort23,SBPort4], 1, [1,1], 1>;
179 defm : X86WriteRes<WriteFStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>;
180 defm : X86WriteRes<WriteFStoreNTX, [SBPort23,SBPort4], 1, [1,1], 1>;
181 defm : X86WriteRes<WriteFStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>;
182 defm : X86WriteRes<WriteFMaskedStore, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
183 defm : X86WriteRes<WriteFMaskedStoreY, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
184 defm : X86WriteRes<WriteFMove, [SBPort5], 1, [1], 1>;
185 defm : X86WriteRes<WriteFMoveX, [SBPort5], 1, [1], 1>;
186 defm : X86WriteRes<WriteFMoveY, [SBPort5], 1, [1], 1>;
187 defm : X86WriteRes<WriteEMMS, [SBPort015], 31, [31], 31>;
189 defm : SBWriteResPair<WriteFAdd, [SBPort1], 3, [1], 1, 6>;
190 defm : SBWriteResPair<WriteFAddX, [SBPort1], 3, [1], 1, 6>;
191 defm : SBWriteResPair<WriteFAddY, [SBPort1], 3, [1], 1, 7>;
192 defm : SBWriteResPair<WriteFAddZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1
193 defm : SBWriteResPair<WriteFAdd64, [SBPort1], 3, [1], 1, 6>;
194 defm : SBWriteResPair<WriteFAdd64X, [SBPort1], 3, [1], 1, 6>;
195 defm : SBWriteResPair<WriteFAdd64Y, [SBPort1], 3, [1], 1, 7>;
196 defm : SBWriteResPair<WriteFAdd64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1
198 defm : SBWriteResPair<WriteFCmp, [SBPort1], 3, [1], 1, 6>;
199 defm : SBWriteResPair<WriteFCmpX, [SBPort1], 3, [1], 1, 6>;
200 defm : SBWriteResPair<WriteFCmpY, [SBPort1], 3, [1], 1, 7>;
201 defm : SBWriteResPair<WriteFCmpZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1
202 defm : SBWriteResPair<WriteFCmp64, [SBPort1], 3, [1], 1, 6>;
203 defm : SBWriteResPair<WriteFCmp64X, [SBPort1], 3, [1], 1, 6>;
204 defm : SBWriteResPair<WriteFCmp64Y, [SBPort1], 3, [1], 1, 7>;
205 defm : SBWriteResPair<WriteFCmp64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1
207 defm : SBWriteResPair<WriteFCom, [SBPort1], 3>;
209 defm : SBWriteResPair<WriteFMul, [SBPort0], 5, [1], 1, 6>;
210 defm : SBWriteResPair<WriteFMulX, [SBPort0], 5, [1], 1, 6>;
211 defm : SBWriteResPair<WriteFMulY, [SBPort0], 5, [1], 1, 7>;
212 defm : SBWriteResPair<WriteFMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1
213 defm : SBWriteResPair<WriteFMul64, [SBPort0], 5, [1], 1, 6>;
214 defm : SBWriteResPair<WriteFMul64X, [SBPort0], 5, [1], 1, 6>;
215 defm : SBWriteResPair<WriteFMul64Y, [SBPort0], 5, [1], 1, 7>;
216 defm : SBWriteResPair<WriteFMul64Z, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1
218 defm : SBWriteResPair<WriteFDiv, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>;
219 defm : SBWriteResPair<WriteFDivX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>;
220 defm : SBWriteResPair<WriteFDivY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>;
221 defm : SBWriteResPair<WriteFDivZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1
222 defm : SBWriteResPair<WriteFDiv64, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>;
223 defm : SBWriteResPair<WriteFDiv64X, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>;
224 defm : SBWriteResPair<WriteFDiv64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>;
225 defm : SBWriteResPair<WriteFDiv64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1
227 defm : SBWriteResPair<WriteFRcp, [SBPort0], 5, [1], 1, 6>;
228 defm : SBWriteResPair<WriteFRcpX, [SBPort0], 5, [1], 1, 6>;
229 defm : SBWriteResPair<WriteFRcpY, [SBPort0,SBPort05], 7, [2,1], 3, 7>;
230 defm : SBWriteResPair<WriteFRcpZ, [SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1
232 defm : SBWriteResPair<WriteFRsqrt, [SBPort0], 5, [1], 1, 6>;
233 defm : SBWriteResPair<WriteFRsqrtX,[SBPort0], 5, [1], 1, 6>;
234 defm : SBWriteResPair<WriteFRsqrtY,[SBPort0,SBPort05], 7, [2,1], 3, 7>;
235 defm : SBWriteResPair<WriteFRsqrtZ,[SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1
237 defm : SBWriteResPair<WriteFSqrt, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>;
238 defm : SBWriteResPair<WriteFSqrtX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>;
239 defm : SBWriteResPair<WriteFSqrtY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>;
240 defm : SBWriteResPair<WriteFSqrtZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1
241 defm : SBWriteResPair<WriteFSqrt64, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>;
242 defm : SBWriteResPair<WriteFSqrt64X, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>;
243 defm : SBWriteResPair<WriteFSqrt64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>;
244 defm : SBWriteResPair<WriteFSqrt64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1
245 defm : SBWriteResPair<WriteFSqrt80, [SBPort0,SBFPDivider], 24, [1,24], 1, 6>;
247 defm : SBWriteResPair<WriteDPPD, [SBPort0,SBPort1,SBPort5], 9, [1,1,1], 3, 6>;
248 defm : SBWriteResPair<WriteDPPS, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 6>;
249 defm : SBWriteResPair<WriteDPPSY, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>;
250 defm : SBWriteResPair<WriteDPPSZ, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; // Unsupported = 1
251 defm : SBWriteResPair<WriteFSign, [SBPort5], 1>;
252 defm : SBWriteResPair<WriteFRnd, [SBPort1], 3, [1], 1, 6>;
253 defm : SBWriteResPair<WriteFRndY, [SBPort1], 3, [1], 1, 7>;
254 defm : SBWriteResPair<WriteFRndZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1
255 defm : SBWriteResPair<WriteFLogic, [SBPort5], 1, [1], 1, 6>;
256 defm : SBWriteResPair<WriteFLogicY, [SBPort5], 1, [1], 1, 7>;
257 defm : SBWriteResPair<WriteFLogicZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1
258 defm : SBWriteResPair<WriteFTest, [SBPort0], 1, [1], 1, 6>;
259 defm : SBWriteResPair<WriteFTestY, [SBPort0], 1, [1], 1, 7>;
260 defm : SBWriteResPair<WriteFTestZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1
261 defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1, [1], 1, 6>;
262 defm : SBWriteResPair<WriteFShuffleY,[SBPort5], 1, [1], 1, 7>;
263 defm : SBWriteResPair<WriteFShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1
264 defm : SBWriteResPair<WriteFVarShuffle, [SBPort5], 1, [1], 1, 6>;
265 defm : SBWriteResPair<WriteFVarShuffleY,[SBPort5], 1, [1], 1, 7>;
266 defm : SBWriteResPair<WriteFVarShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1
267 defm : SBWriteResPair<WriteFBlend, [SBPort05], 1, [1], 1, 6>;
268 defm : SBWriteResPair<WriteFBlendY, [SBPort05], 1, [1], 1, 7>;
269 defm : SBWriteResPair<WriteFBlendZ, [SBPort05], 1, [1], 1, 7>; // Unsupported = 1
270 defm : SBWriteResPair<WriteFVarBlend, [SBPort05], 2, [2], 2, 6>;
271 defm : SBWriteResPair<WriteFVarBlendY,[SBPort05], 2, [2], 2, 7>;
272 defm : SBWriteResPair<WriteFVarBlendZ,[SBPort05], 2, [2], 2, 7>; // Unsupported = 1
274 // Conversion between integer and float.
275 defm : SBWriteResPair<WriteCvtSS2I, [SBPort0,SBPort1], 5, [1,1], 2>;
276 defm : SBWriteResPair<WriteCvtPS2I, [SBPort1], 3, [1], 1, 6>;
277 defm : SBWriteResPair<WriteCvtPS2IY, [SBPort1], 3, [1], 1, 7>;
278 defm : SBWriteResPair<WriteCvtPS2IZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1
279 defm : SBWriteResPair<WriteCvtSD2I, [SBPort0,SBPort1], 5, [1,1], 2>;
280 defm : SBWriteResPair<WriteCvtPD2I, [SBPort1,SBPort5], 4, [1,1], 2, 6>;
281 defm : X86WriteRes<WriteCvtPD2IY, [SBPort1,SBPort5], 4, [1,1], 2>;
282 defm : X86WriteRes<WriteCvtPD2IZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1
283 defm : X86WriteRes<WriteCvtPD2IYLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>;
284 defm : X86WriteRes<WriteCvtPD2IZLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; // Unsupported = 1
286 defm : X86WriteRes<WriteCvtI2SS, [SBPort1,SBPort5], 5, [1,2], 3>;
287 defm : X86WriteRes<WriteCvtI2SSLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>;
288 defm : SBWriteResPair<WriteCvtI2PS, [SBPort1], 3, [1], 1, 6>;
289 defm : SBWriteResPair<WriteCvtI2PSY, [SBPort1], 3, [1], 1, 7>;
290 defm : SBWriteResPair<WriteCvtI2PSZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1
291 defm : X86WriteRes<WriteCvtI2SD, [SBPort1,SBPort5], 4, [1,1], 2>;
292 defm : X86WriteRes<WriteCvtI2PD, [SBPort1,SBPort5], 4, [1,1], 2>;
293 defm : X86WriteRes<WriteCvtI2PDY, [SBPort1,SBPort5], 4, [1,1], 2>;
294 defm : X86WriteRes<WriteCvtI2PDZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1
295 defm : X86WriteRes<WriteCvtI2SDLd, [SBPort1,SBPort23], 9, [1,1], 2>;
296 defm : X86WriteRes<WriteCvtI2PDLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>;
297 defm : X86WriteRes<WriteCvtI2PDYLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>;
298 defm : X86WriteRes<WriteCvtI2PDZLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; // Unsupported = 1
300 defm : SBWriteResPair<WriteCvtSS2SD, [SBPort0], 1, [1], 1, 6>;
301 defm : X86WriteRes<WriteCvtPS2PD, [SBPort0,SBPort5], 2, [1,1], 2>;
302 defm : X86WriteRes<WriteCvtPS2PDY, [SBPort0,SBPort5], 2, [1,1], 2>;
303 defm : X86WriteRes<WriteCvtPS2PDZ, [SBPort0,SBPort5], 2, [1,1], 2>; // Unsupported = 1
304 defm : X86WriteRes<WriteCvtPS2PDLd, [SBPort0,SBPort23], 7, [1,1], 2>;
305 defm : X86WriteRes<WriteCvtPS2PDYLd, [SBPort0,SBPort23], 7, [1,1], 2>;
306 defm : X86WriteRes<WriteCvtPS2PDZLd, [SBPort0,SBPort23], 7, [1,1], 2>; // Unsupported = 1
307 defm : SBWriteResPair<WriteCvtSD2SS, [SBPort1,SBPort5], 4, [1,1], 2, 6>;
308 defm : SBWriteResPair<WriteCvtPD2PS, [SBPort1,SBPort5], 4, [1,1], 2, 6>;
309 defm : SBWriteResPair<WriteCvtPD2PSY, [SBPort1,SBPort5], 4, [1,1], 2, 7>;
310 defm : SBWriteResPair<WriteCvtPD2PSZ, [SBPort1,SBPort5], 4, [1,1], 2, 7>; // Unsupported = 1
312 defm : SBWriteResPair<WriteCvtPH2PS, [SBPort1], 3>;
313 defm : SBWriteResPair<WriteCvtPH2PSY, [SBPort1], 3>;
314 defm : SBWriteResPair<WriteCvtPH2PSZ, [SBPort1], 3>; // Unsupported = 1
316 defm : X86WriteRes<WriteCvtPS2PH, [SBPort1], 3, [1], 1>;
317 defm : X86WriteRes<WriteCvtPS2PHY, [SBPort1], 3, [1], 1>;
318 defm : X86WriteRes<WriteCvtPS2PHZ, [SBPort1], 3, [1], 1>; // Unsupported = 1
319 defm : X86WriteRes<WriteCvtPS2PHSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>;
320 defm : X86WriteRes<WriteCvtPS2PHYSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>;
321 defm : X86WriteRes<WriteCvtPS2PHZSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; // Unsupported = 1
323 // Vector integer operations.
324 defm : X86WriteRes<WriteVecLoad, [SBPort23], 5, [1], 1>;
325 defm : X86WriteRes<WriteVecLoadX, [SBPort23], 6, [1], 1>;
326 defm : X86WriteRes<WriteVecLoadY, [SBPort23], 7, [1], 1>;
327 defm : X86WriteRes<WriteVecLoadNT, [SBPort23], 6, [1], 1>;
328 defm : X86WriteRes<WriteVecLoadNTY, [SBPort23], 7, [1], 1>;
329 defm : X86WriteRes<WriteVecMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>;
330 defm : X86WriteRes<WriteVecMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>;
331 defm : X86WriteRes<WriteVecStore, [SBPort23,SBPort4], 1, [1,1], 1>;
332 defm : X86WriteRes<WriteVecStoreX, [SBPort23,SBPort4], 1, [1,1], 1>;
333 defm : X86WriteRes<WriteVecStoreY, [SBPort23,SBPort4], 1, [1,1], 1>;
334 defm : X86WriteRes<WriteVecStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>;
335 defm : X86WriteRes<WriteVecStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>;
336 defm : X86WriteRes<WriteVecMaskedStore, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
337 defm : X86WriteRes<WriteVecMaskedStoreY, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
338 defm : X86WriteRes<WriteVecMove, [SBPort05], 1, [1], 1>;
339 defm : X86WriteRes<WriteVecMoveX, [SBPort015], 1, [1], 1>;
340 defm : X86WriteRes<WriteVecMoveY, [SBPort05], 1, [1], 1>;
341 defm : X86WriteRes<WriteVecMoveToGpr, [SBPort0], 2, [1], 1>;
342 defm : X86WriteRes<WriteVecMoveFromGpr, [SBPort5], 1, [1], 1>;
344 defm : SBWriteResPair<WriteVecLogic, [SBPort015], 1, [1], 1, 5>;
345 defm : SBWriteResPair<WriteVecLogicX,[SBPort015], 1, [1], 1, 6>;
346 defm : SBWriteResPair<WriteVecLogicY,[SBPort015], 1, [1], 1, 7>;
347 defm : SBWriteResPair<WriteVecLogicZ,[SBPort015], 1, [1], 1, 7>; // Unsupported = 1
348 defm : SBWriteResPair<WriteVecTest, [SBPort0,SBPort5], 2, [1,1], 2, 6>;
349 defm : SBWriteResPair<WriteVecTestY, [SBPort0,SBPort5], 2, [1,1], 2, 7>;
350 defm : SBWriteResPair<WriteVecTestZ, [SBPort0,SBPort5], 2, [1,1], 2, 7>; // Unsupported = 1
351 defm : SBWriteResPair<WriteVecALU, [SBPort1], 3, [1], 1, 5>;
352 defm : SBWriteResPair<WriteVecALUX, [SBPort15], 1, [1], 1, 6>;
353 defm : SBWriteResPair<WriteVecALUY, [SBPort15], 1, [1], 1, 7>;
354 defm : SBWriteResPair<WriteVecALUZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1
355 defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5, [1], 1, 5>;
356 defm : SBWriteResPair<WriteVecIMulX, [SBPort0], 5, [1], 1, 6>;
357 defm : SBWriteResPair<WriteVecIMulY, [SBPort0], 5, [1], 1, 7>;
358 defm : SBWriteResPair<WriteVecIMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1
359 defm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>;
360 defm : SBWriteResPair<WritePMULLDY, [SBPort0], 5, [1], 1, 7>; // TODO this is probably wrong for 256/512-bit for the "generic" model
361 defm : SBWriteResPair<WritePMULLDZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1
362 defm : SBWriteResPair<WriteShuffle, [SBPort5], 1, [1], 1, 5>;
363 defm : SBWriteResPair<WriteShuffleX, [SBPort15], 1, [1], 1, 6>;
364 defm : SBWriteResPair<WriteShuffleY, [SBPort5], 1, [1], 1, 7>;
365 defm : SBWriteResPair<WriteShuffleZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1
366 defm : SBWriteResPair<WriteVarShuffle, [SBPort15], 1, [1], 1, 5>;
367 defm : SBWriteResPair<WriteVarShuffleX, [SBPort15], 1, [1], 1, 6>;
368 defm : SBWriteResPair<WriteVarShuffleY, [SBPort15], 1, [1], 1, 7>;
369 defm : SBWriteResPair<WriteVarShuffleZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1
370 defm : SBWriteResPair<WriteBlend, [SBPort15], 1, [1], 1, 6>;
371 defm : SBWriteResPair<WriteBlendY, [SBPort15], 1, [1], 1, 7>;
372 defm : SBWriteResPair<WriteBlendZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1
373 defm : SBWriteResPair<WriteVarBlend, [SBPort15], 2, [2], 2, 6>;
374 defm : SBWriteResPair<WriteVarBlendY,[SBPort15], 2, [2], 2, 7>;
375 defm : SBWriteResPair<WriteVarBlendZ,[SBPort15], 2, [2], 2, 7>; // Unsupported = 1
376 defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 7, [1,2], 3, 6>;
377 defm : SBWriteResPair<WriteMPSADY, [SBPort0, SBPort15], 7, [1,2], 3, 7>;
378 defm : SBWriteResPair<WriteMPSADZ, [SBPort0, SBPort15], 7, [1,2], 3, 7>; // Unsupported = 1
379 defm : SBWriteResPair<WritePSADBW, [SBPort0], 5, [1], 1, 5>;
380 defm : SBWriteResPair<WritePSADBWX, [SBPort0], 5, [1], 1, 6>;
381 defm : SBWriteResPair<WritePSADBWY, [SBPort0], 5, [1], 1, 7>;
382 defm : SBWriteResPair<WritePSADBWZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1
383 defm : SBWriteResPair<WritePHMINPOS, [SBPort0], 5, [1], 1, 6>;
385 // Vector integer shifts.
386 defm : SBWriteResPair<WriteVecShift, [SBPort5], 1, [1], 1, 5>;
387 defm : SBWriteResPair<WriteVecShiftX, [SBPort0,SBPort15], 2, [1,1], 2, 6>;
388 defm : SBWriteResPair<WriteVecShiftY, [SBPort0,SBPort15], 4, [1,1], 2, 7>;
389 defm : SBWriteResPair<WriteVecShiftZ, [SBPort0,SBPort15], 4, [1,1], 2, 7>; // Unsupported = 1
390 defm : SBWriteResPair<WriteVecShiftImm, [SBPort5], 1, [1], 1, 5>;
391 defm : SBWriteResPair<WriteVecShiftImmX, [SBPort0], 1, [1], 1, 6>;
392 defm : SBWriteResPair<WriteVecShiftImmY, [SBPort0], 1, [1], 1, 7>;
393 defm : SBWriteResPair<WriteVecShiftImmZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1
394 defm : SBWriteResPair<WriteVarVecShift, [SBPort0], 1, [1], 1, 6>;
395 defm : SBWriteResPair<WriteVarVecShiftY, [SBPort0], 1, [1], 1, 7>;
396 defm : SBWriteResPair<WriteVarVecShiftZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1
398 // Vector insert/extract operations.
399 def : WriteRes<WriteVecInsert, [SBPort5,SBPort15]> {
403 def : WriteRes<WriteVecInsertLd, [SBPort23,SBPort15]> {
408 def : WriteRes<WriteVecExtract, [SBPort0,SBPort15]> {
412 def : WriteRes<WriteVecExtractSt, [SBPort4,SBPort23,SBPort15]> {
417 ////////////////////////////////////////////////////////////////////////////////
418 // Horizontal add/sub instructions.
419 ////////////////////////////////////////////////////////////////////////////////
421 defm : SBWriteResPair<WriteFHAdd, [SBPort1,SBPort5], 5, [1,2], 3, 6>;
422 defm : SBWriteResPair<WriteFHAddY, [SBPort1,SBPort5], 5, [1,2], 3, 7>;
423 defm : SBWriteResPair<WriteFHAddZ, [SBPort1,SBPort5], 5, [1,2], 3, 7>; // Unsupported = 1
424 defm : SBWriteResPair<WritePHAdd, [SBPort15], 3, [3], 3, 5>;
425 defm : SBWriteResPair<WritePHAddX, [SBPort15], 3, [3], 3, 6>;
426 defm : SBWriteResPair<WritePHAddY, [SBPort15], 3, [3], 3, 7>;
427 defm : SBWriteResPair<WritePHAddZ, [SBPort15], 3, [3], 3, 7>; // Unsupported = 1
429 ////////////////////////////////////////////////////////////////////////////////
430 // String instructions.
431 ////////////////////////////////////////////////////////////////////////////////
433 // Packed Compare Implicit Length Strings, Return Mask
434 def : WriteRes<WritePCmpIStrM, [SBPort0]> {
437 let ResourceCycles = [3];
439 def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> {
442 let ResourceCycles = [3,1];
445 // Packed Compare Explicit Length Strings, Return Mask
446 def : WriteRes<WritePCmpEStrM, [SBPort015]> {
448 let ResourceCycles = [8];
450 def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
452 let ResourceCycles = [7, 1];
455 // Packed Compare Implicit Length Strings, Return Index
456 def : WriteRes<WritePCmpIStrI, [SBPort0]> {
459 let ResourceCycles = [3];
461 def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> {
464 let ResourceCycles = [3,1];
467 // Packed Compare Explicit Length Strings, Return Index
468 def : WriteRes<WritePCmpEStrI, [SBPort015]> {
470 let ResourceCycles = [8];
472 def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
474 let ResourceCycles = [7, 1];
477 // MOVMSK Instructions.
478 def : WriteRes<WriteFMOVMSK, [SBPort0]> { let Latency = 2; }
479 def : WriteRes<WriteVecMOVMSK, [SBPort0]> { let Latency = 2; }
480 def : WriteRes<WriteVecMOVMSKY, [SBPort0]> { let Latency = 2; }
481 def : WriteRes<WriteMMXMOVMSK, [SBPort0]> { let Latency = 1; }
484 def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> {
487 let ResourceCycles = [1,1];
489 def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> {
492 let ResourceCycles = [1,1,1];
495 def : WriteRes<WriteAESIMC, [SBPort5]> {
498 let ResourceCycles = [2];
500 def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> {
503 let ResourceCycles = [2,1];
506 def : WriteRes<WriteAESKeyGen, [SBPort015]> {
508 let ResourceCycles = [11];
510 def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
512 let ResourceCycles = [10, 1];
515 // Carry-less multiplication instructions.
516 def : WriteRes<WriteCLMul, [SBPort015]> {
518 let ResourceCycles = [18];
520 def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
522 let ResourceCycles = [17, 1];
526 // FIXME: This is probably wrong. Only STMXCSR should require Port4.
527 def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
528 def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
530 def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
531 def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
532 def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
533 def : WriteRes<WriteNop, []>;
535 // AVX2/FMA is not supported on that architecture, but we should define the basic
536 // scheduling resources anyway.
537 defm : SBWriteResPair<WriteFShuffle256, [SBPort5], 1, [1], 1, 7>;
538 defm : SBWriteResPair<WriteFVarShuffle256, [SBPort5], 1, [1], 1, 7>;
539 defm : SBWriteResPair<WriteShuffle256, [SBPort5], 1, [1], 1, 7>;
540 defm : SBWriteResPair<WriteVarShuffle256, [SBPort5], 1, [1], 1, 7>;
541 defm : SBWriteResPair<WriteFMA, [SBPort01], 5>;
542 defm : SBWriteResPair<WriteFMAX, [SBPort01], 5>;
543 defm : SBWriteResPair<WriteFMAY, [SBPort01], 5>;
544 defm : SBWriteResPair<WriteFMAZ, [SBPort01], 5>; // Unsupported = 1
546 // Remaining SNB instrs.
548 def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> {
551 let ResourceCycles = [1];
553 def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r,
558 def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
561 let ResourceCycles = [1];
563 def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
564 LD_Frr, ST_Frr, ST_FPrr)>;
565 def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs.
566 def: InstRW<[SBWriteResGroup2], (instrs RETQ)>;
568 def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
571 let ResourceCycles = [1];
573 def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
575 def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
578 let ResourceCycles = [1];
580 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABS(B|D|W)rr",
583 "MMX_PSIGN(B|D|W)rr")>;
585 def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> {
588 let ResourceCycles = [2];
590 def: InstRW<[SBWriteResGroup9], (instregex "ROL(8|16|32|64)r1",
596 def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
599 let ResourceCycles = [2];
601 def: InstRW<[SBWriteResGroup11], (instrs SCASB,
606 def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> {
609 let ResourceCycles = [1,1];
611 def: InstRW<[SBWriteResGroup12], (instregex "(V?)COMISDrr",
616 def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
619 let ResourceCycles = [1,1];
621 def: InstRW<[SBWriteResGroup15], (instrs CWD,
624 def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
627 let ResourceCycles = [1,1];
629 def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ)>;
630 def: InstRW<[SBWriteResGroup18], (instregex "MMX_MOVDQ2Qrr")>;
632 def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
635 let ResourceCycles = [1];
637 def: InstRW<[SBWriteResGroup21], (instregex "PUSHFS64")>;
639 def SBWriteResGroup21_16i : SchedWriteRes<[SBPort1, SBPort015]> {
642 let ResourceCycles = [1,1];
644 def: InstRW<[SBWriteResGroup21_16i], (instrs IMUL16rri, IMUL16rri8)>;
646 def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
649 let ResourceCycles = [1,1];
651 def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>;
653 def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> {
656 let ResourceCycles = [3];
658 def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(8|16|32|64)rCL",
659 "ROR(8|16|32|64)rCL",
660 "SAR(8|16|32|64)rCL",
661 "SHL(8|16|32|64)rCL",
662 "SHR(8|16|32|64)rCL")>;
664 def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> {
667 let ResourceCycles = [3];
669 def: InstRW<[SBWriteResGroup25], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr,
670 XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr,
671 XCHG16ar, XCHG32ar, XCHG64ar)>;
673 def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> {
676 let ResourceCycles = [1,2];
678 def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>;
680 def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
683 let ResourceCycles = [1,1,1];
685 def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
687 def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> {
690 let ResourceCycles = [1,1];
692 def: InstRW<[SBWriteResGroup27], (instrs IMUL64r, MUL64r)>;
694 def SBWriteResGroup27_1 : SchedWriteRes<[SBPort1,SBPort05,SBPort015]> {
697 let ResourceCycles = [1,1,1];
699 def: InstRW<[SBWriteResGroup27_1], (instrs IMUL32r, MUL32r)>;
701 def SBWriteResGroup27_2 : SchedWriteRes<[SBPort1,SBPort05,SBPort015]> {
704 let ResourceCycles = [1,1,2];
706 def: InstRW<[SBWriteResGroup27_2], (instrs IMUL16r, MUL16r)>;
708 def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
711 let ResourceCycles = [1,1];
713 def: InstRW<[SBWriteResGroup29], (instregex "MOV64sr")>;
715 def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> {
718 let ResourceCycles = [1,3];
720 def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>;
722 def SBWriteResGroup30 : SchedWriteRes<[SBPort0]> {
725 let ResourceCycles = [1];
727 def: InstRW<[SBWriteResGroup30], (instregex "(V?)PCMPGTQrr")>;
729 def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
732 let ResourceCycles = [1];
734 def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm(8|16|32)",
735 "MOVZX(16|32|64)rm(8|16)")>;
737 def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
740 let ResourceCycles = [1,1];
742 def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>;
744 def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
747 let ResourceCycles = [1,2];
749 def: InstRW<[SBWriteResGroup35], (instrs CLI)>;
751 def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
754 let ResourceCycles = [1,1,1];
756 def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m",
759 def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
762 let ResourceCycles = [1,1,1];
764 def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>;
765 def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r",
768 def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
771 let ResourceCycles = [1,1,1];
773 def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>;
775 def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> {
778 let ResourceCycles = [1,3];
780 def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>;
782 def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> {
785 let ResourceCycles = [1,3];
787 def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG(8|16|32|64)rr")>;
789 def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
792 let ResourceCycles = [1,1,2];
794 def: InstRW<[SBWriteResGroup43], (instregex "SET(A|BE)m")>;
796 def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
799 let ResourceCycles = [1,1,1,1];
801 def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr",
804 def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
807 let ResourceCycles = [1,1,1,1];
809 def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>;
811 def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
814 let ResourceCycles = [1,2,1,1];
816 def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;
818 def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> {
821 let ResourceCycles = [1];
823 def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm",
835 def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
838 let ResourceCycles = [1,1];
840 def: InstRW<[SBWriteResGroup49], (instregex "MOV16sm")>;
842 def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> {
845 let ResourceCycles = [1,1];
847 def: InstRW<[SBWriteResGroup50], (instregex "BT(16|32|64)mi8")>;
849 def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
852 let ResourceCycles = [1,1];
854 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABS(B|D|W)rm",
856 "MMX_PSIGN(B|D|W)rm")>;
858 def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
861 let ResourceCycles = [1,1];
863 def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>;
865 def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> {
868 let ResourceCycles = [1,2];
870 def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m",
871 "ST_FP(32|64|80)m")>;
873 def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> {
876 let ResourceCycles = [1];
878 def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSDYrm",
884 def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> {
887 let ResourceCycles = [1,1];
889 def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>;
891 def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> {
894 let ResourceCycles = [1,1];
896 def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm")>;
898 def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> {
901 let ResourceCycles = [2,1];
903 def: InstRW<[SBWriteResGroup62], (instregex "VER(R|W)m")>;
905 def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> {
908 let ResourceCycles = [1,2];
910 def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>;
912 def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
915 let ResourceCycles = [1,1,1];
917 def: InstRW<[SBWriteResGroup64], (instrs FARJMP64)>;
919 def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
922 let ResourceCycles = [1,1,2];
924 def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>;
926 def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
929 let ResourceCycles = [1,2,1];
931 def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r",
934 def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
937 let ResourceCycles = [1,1,2];
939 def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>;
940 def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>;
942 def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
945 let ResourceCycles = [1,2,1];
947 def: InstRW<[SBWriteResGroup69], (instregex "BTC(16|32|64)mi8",
955 "SHR(8|16|32|64)mi")>;
957 def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
960 let ResourceCycles = [1,1,1];
962 def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>;
964 def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> {
967 let ResourceCycles = [1,3];
969 def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16|32|64)rm")>;
971 def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> {
974 let ResourceCycles = [2,3];
976 def: InstRW<[SBWriteResGroup83], (instrs CMPSB,
981 def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
984 let ResourceCycles = [1,2,2];
986 def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>;
988 def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
991 let ResourceCycles = [1,2,2];
993 def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m1",
996 "ROR(8|16|32|64)mi")>;
998 def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
1000 let NumMicroOps = 5;
1001 let ResourceCycles = [1,2,2];
1003 def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
1004 def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>;
1006 def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
1008 let NumMicroOps = 5;
1009 let ResourceCycles = [1,1,1,2];
1011 def: InstRW<[SBWriteResGroup87], (instrs FARCALL64)>;
1013 def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
1015 let NumMicroOps = 3;
1016 let ResourceCycles = [1,1,1];
1018 def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)SD2SI(64)?rm",
1019 "CVT(T?)SS2SI(64)?rm")>;
1021 def SBWriteResGroup93_1 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
1023 let NumMicroOps = 3;
1024 let ResourceCycles = [1,1,1];
1026 def: InstRW<[SBWriteResGroup93_1], (instrs IMUL64m, MUL64m)>;
1028 def SBWriteResGroup93_2 : SchedWriteRes<[SBPort1,SBPort23,SBPort05,SBPort015]> {
1030 let NumMicroOps = 4;
1031 let ResourceCycles = [1,1,1,1];
1033 def: InstRW<[SBWriteResGroup93_2], (instrs IMUL32m, MUL32m)>;
1035 def SBWriteResGroup93_3 : SchedWriteRes<[SBPort1,SBPort05,SBPort015,SBPort23]> {
1037 let NumMicroOps = 5;
1038 let ResourceCycles = [1,1,2,1];
1040 def: InstRW<[SBWriteResGroup93_3], (instrs IMUL16m, MUL16m)>;
1042 def SBWriteResGroup93_4 : SchedWriteRes<[SBPort1,SBPort015,SBPort23]> {
1044 let NumMicroOps = 3;
1045 let ResourceCycles = [1,1,1];
1047 def: InstRW<[SBWriteResGroup93_4], (instrs IMUL16rmi, IMUL16rmi8)>;
1049 def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
1051 let NumMicroOps = 3;
1052 let ResourceCycles = [1,1,1];
1054 def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>;
1056 def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
1058 let NumMicroOps = 4;
1059 let ResourceCycles = [1,1,2];
1061 def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m",
1062 "IST_FP(16|32|64)m")>;
1064 def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
1066 let NumMicroOps = 6;
1067 let ResourceCycles = [1,2,3];
1069 def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL",
1070 "ROR(8|16|32|64)mCL",
1071 "SAR(8|16|32|64)mCL",
1072 "SHL(8|16|32|64)mCL",
1073 "SHR(8|16|32|64)mCL")>;
1075 def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
1077 let NumMicroOps = 6;
1078 let ResourceCycles = [1,2,3];
1080 def: SchedAlias<WriteADCRMW, SBWriteResGroup98>;
1082 def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
1084 let NumMicroOps = 6;
1085 let ResourceCycles = [1,2,2,1];
1087 def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
1088 SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
1090 def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> {
1092 let NumMicroOps = 6;
1093 let ResourceCycles = [1,1,2,1,1];
1095 def: InstRW<[SBWriteResGroup100], (instregex "BT(16|32|64)mr",
1098 "BTS(16|32|64)mr")>;
1100 def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
1102 let NumMicroOps = 2;
1103 let ResourceCycles = [1,1];
1105 def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1106 "ILD_F(16|32|64)m")>;
1108 def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> {
1110 let NumMicroOps = 2;
1111 let ResourceCycles = [1,1];
1113 def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>;
1115 def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
1117 let NumMicroOps = 3;
1118 let ResourceCycles = [2,1];
1120 def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>;
1122 def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
1124 let NumMicroOps = 2;
1125 let ResourceCycles = [1,1];
1127 def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>;
1129 def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> {
1131 let NumMicroOps = 3;
1132 let ResourceCycles = [2,1];
1134 def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1136 def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
1138 let NumMicroOps = 3;
1139 let ResourceCycles = [1,1,1];
1141 def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>;
1143 def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> {
1145 let NumMicroOps = 2;
1146 let ResourceCycles = [1,1];
1148 def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>;
1150 def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
1152 let NumMicroOps = 3;
1153 let ResourceCycles = [1,1,1];
1155 def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>;
1157 def: InstRW<[WriteZero], (instrs CLC)>;