contrib/llvm/lib/Target/X86/X86SchedSandyBridge.td

   1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for Sandy Bridge to support instruction
  11 // scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 def SandyBridgeModel : SchedMachineModel {
  16   // All x86 instructions are modeled as a single micro-op, and SB can decode 4
  17   // instructions per cycle.
  18   // FIXME: Identify instructions that aren't a single fused micro-op.
  19   let IssueWidth = 4;
  20   let MicroOpBufferSize = 168; // Based on the reorder buffer.
  21   let LoadLatency = 4;
  22   let MispredictPenalty = 16;
  23
  24   // Based on the LSD (loop-stream detector) queue size.
  25   let LoopMicroOpBufferSize = 28;
  26
  27   // This flag is set to allow the scheduler to assign
  28   // a default model to unrecognized opcodes.
  29   let CompleteModel = 0;
  30 }
  31
  32 let SchedModel = SandyBridgeModel in {
  33
  34 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
  35
  36 // Ports 0, 1, and 5 handle all computation.
  37 def SBPort0 : ProcResource<1>;
  38 def SBPort1 : ProcResource<1>;
  39 def SBPort5 : ProcResource<1>;
  40
  41 // Ports 2 and 3 are identical. They handle loads and the address half of
  42 // stores.
  43 def SBPort23 : ProcResource<2>;
  44
  45 // Port 4 gets the data half of stores. Store data can be available later than
  46 // the store address, but since we don't model the latency of stores, we can
  47 // ignore that.
  48 def SBPort4 : ProcResource<1>;
  49
  50 // Many micro-ops are capable of issuing on multiple ports.
  51 def SBPort01  : ProcResGroup<[SBPort0, SBPort1]>;
  52 def SBPort05  : ProcResGroup<[SBPort0, SBPort5]>;
  53 def SBPort15  : ProcResGroup<[SBPort1, SBPort5]>;
  54 def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
  55
  56 // 54 Entry Unified Scheduler
  57 def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> {
  58   let BufferSize=54;
  59 }
  60
  61 // Integer division issued on port 0.
  62 def SBDivider : ProcResource<1>;
  63
  64 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
  65 // cycles after the memory operand.
  66 def : ReadAdvance<ReadAfterLd, 4>;
  67
  68 // Many SchedWrites are defined in pairs with and without a folded load.
  69 // Instructions with folded loads are usually micro-fused, so they only appear
  70 // as two micro-ops when queued in the reservation station.
  71 // This multiclass defines the resource usage for variants with and without
  72 // folded loads.
  73 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
  74                           ProcResourceKind ExePort,
  75                           int Lat> {
  76   // Register variant is using a single cycle on ExePort.
  77   def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
  78
  79   // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
  80   // latency.
  81   def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
  82      let Latency = !add(Lat, 4);
  83   }
  84 }
  85
  86 // A folded store needs a cycle on port 4 for the store data, but it does not
  87 // need an extra port 2/3 cycle to recompute the address.
  88 def : WriteRes<WriteRMW, [SBPort4]>;
  89
  90 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
  91 def : WriteRes<WriteLoad,  [SBPort23]> { let Latency = 4; }
  92 def : WriteRes<WriteMove,  [SBPort015]>;
  93 def : WriteRes<WriteZero,  []>;
  94
  95 defm : SBWriteResPair<WriteALU,   SBPort015, 1>;
  96 defm : SBWriteResPair<WriteIMul,  SBPort1,   3>;
  97 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
  98 defm : SBWriteResPair<WriteShift, SBPort05,  1>;
  99 defm : SBWriteResPair<WriteJump,  SBPort5,   1>;
 100
 101 // This is for simple LEAs with one or two input operands.
 102 // The complex ones can only execute on port 1, and they require two cycles on
 103 // the port to read all inputs. We don't model that.
 104 def : WriteRes<WriteLEA, [SBPort15]>;
 105
 106 // This is quite rough, latency depends on the dividend.
 107 def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> {
 108   let Latency = 25;
 109   let ResourceCycles = [1, 10];
 110 }
 111 def : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> {
 112   let Latency = 29;
 113   let ResourceCycles = [1, 1, 10];
 114 }
 115
 116 // Scalar and vector floating point.
 117 defm : SBWriteResPair<WriteFAdd,   SBPort1, 3>;
 118 defm : SBWriteResPair<WriteFMul,   SBPort0, 5>;
 119 defm : SBWriteResPair<WriteFDiv,   SBPort0, 24>;
 120 defm : SBWriteResPair<WriteFRcp,   SBPort0, 5>;
 121 defm : SBWriteResPair<WriteFRsqrt, SBPort0, 5>;
 122 defm : SBWriteResPair<WriteFSqrt,  SBPort0, 14>;
 123 defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>;
 124 defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>;
 125 defm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>;
 126 defm : SBWriteResPair<WriteFShuffle,  SBPort5,  1>;
 127 defm : SBWriteResPair<WriteFBlend,  SBPort05,  1>;
 128 def : WriteRes<WriteFVarBlend, [SBPort0, SBPort5]> {
 129   let Latency = 2;
 130   let ResourceCycles = [1, 1];
 131 }
 132 def : WriteRes<WriteFVarBlendLd, [SBPort0, SBPort5, SBPort23]> {
 133   let Latency = 6;
 134   let ResourceCycles = [1, 1, 1];
 135 }
 136
 137 // Vector integer operations.
 138 defm : SBWriteResPair<WriteVecShift, SBPort5,  1>;
 139 defm : SBWriteResPair<WriteVecLogic, SBPort5, 1>;
 140 defm : SBWriteResPair<WriteVecALU,   SBPort1,  3>;
 141 defm : SBWriteResPair<WriteVecIMul,  SBPort0,   5>;
 142 defm : SBWriteResPair<WriteShuffle,  SBPort5,  1>;
 143 defm : SBWriteResPair<WriteBlend,  SBPort15,  1>;
 144 def : WriteRes<WriteVarBlend, [SBPort1, SBPort5]> {
 145   let Latency = 2;
 146   let ResourceCycles = [1, 1];
 147 }
 148 def : WriteRes<WriteVarBlendLd, [SBPort1, SBPort5, SBPort23]> {
 149   let Latency = 6;
 150   let ResourceCycles = [1, 1, 1];
 151 }
 152 def : WriteRes<WriteMPSAD, [SBPort0,SBPort15]> {
 153   let Latency = 5;
 154   let NumMicroOps = 3;
 155   let ResourceCycles = [1,2];
 156 }
 157 def : WriteRes<WriteMPSADLd, [SBPort0,SBPort23,SBPort15]> {
 158   let Latency = 11;
 159   let NumMicroOps = 4;
 160   let ResourceCycles = [1,1,2];
 161 }
 162
 163 ////////////////////////////////////////////////////////////////////////////////
 164 // Horizontal add/sub  instructions.
 165 ////////////////////////////////////////////////////////////////////////////////
 166 // HADD, HSUB PS/PD
 167 // x,x / v,v,v.
 168 def : WriteRes<WriteFHAdd, [SBPort1]> {
 169   let Latency = 3;
 170 }
 171
 172 // x,m / v,v,m.
 173 def : WriteRes<WriteFHAddLd, [SBPort1, SBPort23]> {
 174   let Latency = 7;
 175   let ResourceCycles = [1, 1];
 176 }
 177
 178 // PHADD|PHSUB (S) W/D.
 179 // v <- v,v.
 180 def : WriteRes<WritePHAdd, [SBPort15]>;
 181
 182 // v <- v,m.
 183 def : WriteRes<WritePHAddLd, [SBPort15, SBPort23]> {
 184   let Latency = 5;
 185   let ResourceCycles = [1, 1];
 186 }
 187
 188 // String instructions.
 189 // Packed Compare Implicit Length Strings, Return Mask
 190 def : WriteRes<WritePCmpIStrM, [SBPort015]> {
 191   let Latency = 11;
 192   let ResourceCycles = [3];
 193 }
 194 def : WriteRes<WritePCmpIStrMLd, [SBPort015, SBPort23]> {
 195   let Latency = 11;
 196   let ResourceCycles = [3, 1];
 197 }
 198
 199 // Packed Compare Explicit Length Strings, Return Mask
 200 def : WriteRes<WritePCmpEStrM, [SBPort015]> {
 201   let Latency = 11;
 202   let ResourceCycles = [8];
 203 }
 204 def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
 205   let Latency = 11;
 206   let ResourceCycles = [7, 1];
 207 }
 208
 209 // Packed Compare Implicit Length Strings, Return Index
 210 def : WriteRes<WritePCmpIStrI, [SBPort0]> {
 211   let Latency = 11;
 212   let NumMicroOps = 3;
 213   let ResourceCycles = [3];
 214 }
 215 def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> {
 216   let Latency = 17;
 217   let NumMicroOps = 4;
 218   let ResourceCycles = [3,1];
 219 }
 220
 221 // Packed Compare Explicit Length Strings, Return Index
 222 def : WriteRes<WritePCmpEStrI, [SBPort015]> {
 223   let Latency = 4;
 224   let ResourceCycles = [8];
 225 }
 226 def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
 227   let Latency = 4;
 228   let ResourceCycles = [7, 1];
 229 }
 230
 231 // AES Instructions.
 232 def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> {
 233   let Latency = 7;
 234   let NumMicroOps = 2;
 235   let ResourceCycles = [1,1];
 236 }
 237 def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> {
 238   let Latency = 13;
 239   let NumMicroOps = 3;
 240   let ResourceCycles = [1,1,1];
 241 }
 242
 243 def : WriteRes<WriteAESIMC, [SBPort5]> {
 244   let Latency = 12;
 245   let NumMicroOps = 2;
 246   let ResourceCycles = [2];
 247 }
 248 def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> {
 249   let Latency = 18;
 250   let NumMicroOps = 3;
 251   let ResourceCycles = [2,1];
 252 }
 253
 254 def : WriteRes<WriteAESKeyGen, [SBPort015]> {
 255   let Latency = 8;
 256   let ResourceCycles = [11];
 257 }
 258 def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
 259   let Latency = 8;
 260   let ResourceCycles = [10, 1];
 261 }
 262
 263 // Carry-less multiplication instructions.
 264 def : WriteRes<WriteCLMul, [SBPort015]> {
 265   let Latency = 14;
 266   let ResourceCycles = [18];
 267 }
 268 def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
 269   let Latency = 14;
 270   let ResourceCycles = [17, 1];
 271 }
 272
 273
 274 def : WriteRes<WriteSystem,     [SBPort015]> { let Latency = 100; }
 275 def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
 276 def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
 277 def : WriteRes<WriteNop, []>;
 278
 279 // AVX2 is not supported on that architecture, but we should define the basic
 280 // scheduling resources anyway.
 281 defm : SBWriteResPair<WriteFShuffle256, SBPort0,  1>;
 282 defm : SBWriteResPair<WriteShuffle256, SBPort0,  1>;
 283 defm : SBWriteResPair<WriteVarVecShift, SBPort0,  1>;
 284
 285 // Remaining SNB instrs.
 286
 287 def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> {
 288   let Latency = 1;
 289   let NumMicroOps = 1;
 290   let ResourceCycles = [1];
 291 }
 292 def: InstRW<[SBWriteResGroup0], (instregex "CVTSS2SDrr")>;
 293 def: InstRW<[SBWriteResGroup0], (instregex "PSLLDri")>;
 294 def: InstRW<[SBWriteResGroup0], (instregex "PSLLQri")>;
 295 def: InstRW<[SBWriteResGroup0], (instregex "PSLLWri")>;
 296 def: InstRW<[SBWriteResGroup0], (instregex "PSRADri")>;
 297 def: InstRW<[SBWriteResGroup0], (instregex "PSRAWri")>;
 298 def: InstRW<[SBWriteResGroup0], (instregex "PSRLDri")>;
 299 def: InstRW<[SBWriteResGroup0], (instregex "PSRLQri")>;
 300 def: InstRW<[SBWriteResGroup0], (instregex "PSRLWri")>;
 301 def: InstRW<[SBWriteResGroup0], (instregex "VCVTSS2SDrr")>;
 302 def: InstRW<[SBWriteResGroup0], (instregex "VPMOVMSKBrr")>;
 303 def: InstRW<[SBWriteResGroup0], (instregex "VPSLLDri")>;
 304 def: InstRW<[SBWriteResGroup0], (instregex "VPSLLQri")>;
 305 def: InstRW<[SBWriteResGroup0], (instregex "VPSLLWri")>;
 306 def: InstRW<[SBWriteResGroup0], (instregex "VPSRADri")>;
 307 def: InstRW<[SBWriteResGroup0], (instregex "VPSRAWri")>;
 308 def: InstRW<[SBWriteResGroup0], (instregex "VPSRLDri")>;
 309 def: InstRW<[SBWriteResGroup0], (instregex "VPSRLQri")>;
 310 def: InstRW<[SBWriteResGroup0], (instregex "VPSRLWri")>;
 311 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDYrr")>;
 312 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDrr")>;
 313 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSYrr")>;
 314 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSrr")>;
 315
 316 def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> {
 317   let Latency = 1;
 318   let NumMicroOps = 1;
 319   let ResourceCycles = [1];
 320 }
 321 def: InstRW<[SBWriteResGroup1], (instregex "COMP_FST0r")>;
 322 def: InstRW<[SBWriteResGroup1], (instregex "COM_FST0r")>;
 323 def: InstRW<[SBWriteResGroup1], (instregex "UCOM_FPr")>;
 324 def: InstRW<[SBWriteResGroup1], (instregex "UCOM_Fr")>;
 325
 326 def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
 327   let Latency = 1;
 328   let NumMicroOps = 1;
 329   let ResourceCycles = [1];
 330 }
 331 def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr")>;
 332 def: InstRW<[SBWriteResGroup2], (instregex "ANDNPSrr")>;
 333 def: InstRW<[SBWriteResGroup2], (instregex "ANDPDrr")>;
 334 def: InstRW<[SBWriteResGroup2], (instregex "ANDPSrr")>;
 335 def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP")>;
 336 def: InstRW<[SBWriteResGroup2], (instregex "FFREE")>;
 337 def: InstRW<[SBWriteResGroup2], (instregex "FINCSTP")>;
 338 def: InstRW<[SBWriteResGroup2], (instregex "FNOP")>;
 339 def: InstRW<[SBWriteResGroup2], (instregex "INSERTPSrr")>;
 340 def: InstRW<[SBWriteResGroup2], (instregex "JMP64r")>;
 341 def: InstRW<[SBWriteResGroup2], (instregex "LD_Frr")>;
 342 def: InstRW<[SBWriteResGroup2], (instregex "MOV64toPQIrr")>;
 343 def: InstRW<[SBWriteResGroup2], (instregex "MOVAPDrr")>;
 344 def: InstRW<[SBWriteResGroup2], (instregex "MOVAPSrr")>;
 345 def: InstRW<[SBWriteResGroup2], (instregex "MOVDDUPrr")>;
 346 def: InstRW<[SBWriteResGroup2], (instregex "MOVDI2PDIrr")>;
 347 def: InstRW<[SBWriteResGroup2], (instregex "MOVHLPSrr")>;
 348 def: InstRW<[SBWriteResGroup2], (instregex "MOVLHPSrr")>;
 349 def: InstRW<[SBWriteResGroup2], (instregex "MOVSDrr")>;
 350 def: InstRW<[SBWriteResGroup2], (instregex "MOVSHDUPrr")>;
 351 def: InstRW<[SBWriteResGroup2], (instregex "MOVSLDUPrr")>;
 352 def: InstRW<[SBWriteResGroup2], (instregex "MOVSSrr")>;
 353 def: InstRW<[SBWriteResGroup2], (instregex "MOVUPDrr")>;
 354 def: InstRW<[SBWriteResGroup2], (instregex "MOVUPSrr")>;
 355 def: InstRW<[SBWriteResGroup2], (instregex "ORPDrr")>;
 356 def: InstRW<[SBWriteResGroup2], (instregex "ORPSrr")>;
 357 def: InstRW<[SBWriteResGroup2], (instregex "RETQ")>;
 358 def: InstRW<[SBWriteResGroup2], (instregex "SHUFPDrri")>;
 359 def: InstRW<[SBWriteResGroup2], (instregex "SHUFPSrri")>;
 360 def: InstRW<[SBWriteResGroup2], (instregex "ST_FPrr")>;
 361 def: InstRW<[SBWriteResGroup2], (instregex "ST_Frr")>;
 362 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKHPDrr")>;
 363 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKHPSrr")>;
 364 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKLPDrr")>;
 365 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKLPSrr")>;
 366 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPDYrr")>;
 367 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPDrr")>;
 368 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPSYrr")>;
 369 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPSrr")>;
 370 def: InstRW<[SBWriteResGroup2], (instregex "VANDPDrr")>;
 371 def: InstRW<[SBWriteResGroup2], (instregex "VANDPDrr")>;
 372 def: InstRW<[SBWriteResGroup2], (instregex "VANDPSrr")>;
 373 def: InstRW<[SBWriteResGroup2], (instregex "VEXTRACTF128rr")>;
 374 def: InstRW<[SBWriteResGroup2], (instregex "VINSERTF128rr")>;
 375 def: InstRW<[SBWriteResGroup2], (instregex "VINSERTPSrr")>;
 376 def: InstRW<[SBWriteResGroup2], (instregex "VMOV64toPQIrr")>;
 377 def: InstRW<[SBWriteResGroup2], (instregex "VMOV64toPQIrr")>;
 378 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPDYrr")>;
 379 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPDrr")>;
 380 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPSYrr")>;
 381 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPSrr")>;
 382 def: InstRW<[SBWriteResGroup2], (instregex "VMOVDDUPYrr")>;
 383 def: InstRW<[SBWriteResGroup2], (instregex "VMOVDDUPrr")>;
 384 def: InstRW<[SBWriteResGroup2], (instregex "VMOVHLPSrr")>;
 385 def: InstRW<[SBWriteResGroup2], (instregex "VMOVHLPSrr")>;
 386 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSDrr")>;
 387 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSHDUPYrr")>;
 388 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSHDUPrr")>;
 389 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSLDUPYrr")>;
 390 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSLDUPrr")>;
 391 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSSrr")>;
 392 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPDYrr")>;
 393 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPDrr")>;
 394 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPSYrr")>;
 395 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPSrr")>;
 396 def: InstRW<[SBWriteResGroup2], (instregex "VORPDYrr")>;
 397 def: InstRW<[SBWriteResGroup2], (instregex "VORPDrr")>;
 398 def: InstRW<[SBWriteResGroup2], (instregex "VORPSYrr")>;
 399 def: InstRW<[SBWriteResGroup2], (instregex "VORPSrr")>;
 400 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDri")>;
 401 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDrm")>;
 402 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDrr")>;
 403 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSri")>;
 404 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrm")>;
 405 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrr")>;
 406 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrr")>;
 407 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPDYrri")>;
 408 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPDrri")>;
 409 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPSYrri")>;
 410 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPSrri")>;
 411 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPDrr")>;
 412 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPSrr")>;
 413 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPDYrr")>;
 414 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPDrr")>;
 415 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPSYrr")>;
 416 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPSrr")>;
 417 def: InstRW<[SBWriteResGroup2], (instregex "VXORPDrr")>;
 418 def: InstRW<[SBWriteResGroup2], (instregex "VXORPSrr")>;
 419 def: InstRW<[SBWriteResGroup2], (instregex "XORPDrr")>;
 420 def: InstRW<[SBWriteResGroup2], (instregex "XORPSrr")>;
 421
 422 def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {
 423   let Latency = 1;
 424   let NumMicroOps = 1;
 425   let ResourceCycles = [1];
 426 }
 427 def: InstRW<[SBWriteResGroup3], (instregex "LEA64_32r")>;
 428
 429 def SBWriteResGroup4 : SchedWriteRes<[SBPort0]> {
 430   let Latency = 1;
 431   let NumMicroOps = 1;
 432   let ResourceCycles = [1];
 433 }
 434 def: InstRW<[SBWriteResGroup4], (instregex "BLENDPDrri")>;
 435 def: InstRW<[SBWriteResGroup4], (instregex "BLENDPSrri")>;
 436 def: InstRW<[SBWriteResGroup4], (instregex "BT32ri8")>;
 437 def: InstRW<[SBWriteResGroup4], (instregex "BT32rr")>;
 438 def: InstRW<[SBWriteResGroup4], (instregex "BTC32ri8")>;
 439 def: InstRW<[SBWriteResGroup4], (instregex "BTC32rr")>;
 440 def: InstRW<[SBWriteResGroup4], (instregex "BTR32ri8")>;
 441 def: InstRW<[SBWriteResGroup4], (instregex "BTR32rr")>;
 442 def: InstRW<[SBWriteResGroup4], (instregex "BTS32ri8")>;
 443 def: InstRW<[SBWriteResGroup4], (instregex "BTS32rr")>;
 444 def: InstRW<[SBWriteResGroup4], (instregex "CDQ")>;
 445 def: InstRW<[SBWriteResGroup4], (instregex "CQO")>;
 446 def: InstRW<[SBWriteResGroup4], (instregex "LAHF")>;
 447 def: InstRW<[SBWriteResGroup4], (instregex "SAHF")>;
 448 def: InstRW<[SBWriteResGroup4], (instregex "SAR32ri")>;
 449 def: InstRW<[SBWriteResGroup4], (instregex "SAR8ri")>;
 450 def: InstRW<[SBWriteResGroup4], (instregex "SETAEr")>;
 451 def: InstRW<[SBWriteResGroup4], (instregex "SETBr")>;
 452 def: InstRW<[SBWriteResGroup4], (instregex "SETEr")>;
 453 def: InstRW<[SBWriteResGroup4], (instregex "SETGEr")>;
 454 def: InstRW<[SBWriteResGroup4], (instregex "SETGr")>;
 455 def: InstRW<[SBWriteResGroup4], (instregex "SETLEr")>;
 456 def: InstRW<[SBWriteResGroup4], (instregex "SETLr")>;
 457 def: InstRW<[SBWriteResGroup4], (instregex "SETNEr")>;
 458 def: InstRW<[SBWriteResGroup4], (instregex "SETNOr")>;
 459 def: InstRW<[SBWriteResGroup4], (instregex "SETNPr")>;
 460 def: InstRW<[SBWriteResGroup4], (instregex "SETNSr")>;
 461 def: InstRW<[SBWriteResGroup4], (instregex "SETOr")>;
 462 def: InstRW<[SBWriteResGroup4], (instregex "SETPr")>;
 463 def: InstRW<[SBWriteResGroup4], (instregex "SETSr")>;
 464 def: InstRW<[SBWriteResGroup4], (instregex "SHL32ri")>;
 465 def: InstRW<[SBWriteResGroup4], (instregex "SHL64r1")>;
 466 def: InstRW<[SBWriteResGroup4], (instregex "SHL8r1")>;
 467 def: InstRW<[SBWriteResGroup4], (instregex "SHL8ri")>;
 468 def: InstRW<[SBWriteResGroup4], (instregex "SHR32ri")>;
 469 def: InstRW<[SBWriteResGroup4], (instregex "SHR8ri")>;
 470 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDYrri")>;
 471 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDrri")>;
 472 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSYrri")>;
 473 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSrri")>;
 474 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQAYrr")>;
 475 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQArr")>;
 476 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQUYrr")>;
 477 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQUrr")>;
 478
 479 def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
 480   let Latency = 1;
 481   let NumMicroOps = 1;
 482   let ResourceCycles = [1];
 483 }
 484 def: InstRW<[SBWriteResGroup5], (instregex "KORTESTBrr")>;
 485 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr64")>;
 486 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSDrr64")>;
 487 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSWrr64")>;
 488 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PADDQirr")>;
 489 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PALIGNR64irr")>;
 490 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSHUFBrr64")>;
 491 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNBrr64")>;
 492 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNDrr64")>;
 493 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNWrr64")>;
 494 def: InstRW<[SBWriteResGroup5], (instregex "PABSBrr")>;
 495 def: InstRW<[SBWriteResGroup5], (instregex "PABSDrr")>;
 496 def: InstRW<[SBWriteResGroup5], (instregex "PABSWrr")>;
 497 def: InstRW<[SBWriteResGroup5], (instregex "PACKSSDWrr")>;
 498 def: InstRW<[SBWriteResGroup5], (instregex "PACKSSWBrr")>;
 499 def: InstRW<[SBWriteResGroup5], (instregex "PACKUSDWrr")>;
 500 def: InstRW<[SBWriteResGroup5], (instregex "PACKUSWBrr")>;
 501 def: InstRW<[SBWriteResGroup5], (instregex "PADDBrr")>;
 502 def: InstRW<[SBWriteResGroup5], (instregex "PADDDrr")>;
 503 def: InstRW<[SBWriteResGroup5], (instregex "PADDQrr")>;
 504 def: InstRW<[SBWriteResGroup5], (instregex "PADDSBrr")>;
 505 def: InstRW<[SBWriteResGroup5], (instregex "PADDSWrr")>;
 506 def: InstRW<[SBWriteResGroup5], (instregex "PADDUSBrr")>;
 507 def: InstRW<[SBWriteResGroup5], (instregex "PADDUSWrr")>;
 508 def: InstRW<[SBWriteResGroup5], (instregex "PADDWrr")>;
 509 def: InstRW<[SBWriteResGroup5], (instregex "PALIGNRrri")>;
 510 def: InstRW<[SBWriteResGroup5], (instregex "PAVGBrr")>;
 511 def: InstRW<[SBWriteResGroup5], (instregex "PAVGWrr")>;
 512 def: InstRW<[SBWriteResGroup5], (instregex "PBLENDWrri")>;
 513 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQBrr")>;
 514 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQDrr")>;
 515 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQQrr")>;
 516 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQWrr")>;
 517 def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTBrr")>;
 518 def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTDrr")>;
 519 def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTWrr")>;
 520 def: InstRW<[SBWriteResGroup5], (instregex "PMAXSBrr")>;
 521 def: InstRW<[SBWriteResGroup5], (instregex "PMAXSDrr")>;
 522 def: InstRW<[SBWriteResGroup5], (instregex "PMAXSWrr")>;
 523 def: InstRW<[SBWriteResGroup5], (instregex "PMAXUBrr")>;
 524 def: InstRW<[SBWriteResGroup5], (instregex "PMAXUDrr")>;
 525 def: InstRW<[SBWriteResGroup5], (instregex "PMAXUWrr")>;
 526 def: InstRW<[SBWriteResGroup5], (instregex "PMINSBrr")>;
 527 def: InstRW<[SBWriteResGroup5], (instregex "PMINSDrr")>;
 528 def: InstRW<[SBWriteResGroup5], (instregex "PMINSWrr")>;
 529 def: InstRW<[SBWriteResGroup5], (instregex "PMINUBrr")>;
 530 def: InstRW<[SBWriteResGroup5], (instregex "PMINUDrr")>;
 531 def: InstRW<[SBWriteResGroup5], (instregex "PMINUWrr")>;
 532 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBDrr")>;
 533 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBQrr")>;
 534 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBWrr")>;
 535 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXDQrr")>;
 536 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXWDrr")>;
 537 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXWQrr")>;
 538 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBDrr")>;
 539 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBQrr")>;
 540 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBWrr")>;
 541 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXDQrr")>;
 542 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXWDrr")>;
 543 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXWQrr")>;
 544 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFBrr")>;
 545 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFDri")>;
 546 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFHWri")>;
 547 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFLWri")>;
 548 def: InstRW<[SBWriteResGroup5], (instregex "PSIGNBrr128")>;
 549 def: InstRW<[SBWriteResGroup5], (instregex "PSIGNDrr128")>;
 550 def: InstRW<[SBWriteResGroup5], (instregex "PSIGNWrr128")>;
 551 def: InstRW<[SBWriteResGroup5], (instregex "PSLLDQri")>;
 552 def: InstRW<[SBWriteResGroup5], (instregex "PSRLDQri")>;
 553 def: InstRW<[SBWriteResGroup5], (instregex "PSUBBrr")>;
 554 def: InstRW<[SBWriteResGroup5], (instregex "PSUBDrr")>;
 555 def: InstRW<[SBWriteResGroup5], (instregex "PSUBQrr")>;
 556 def: InstRW<[SBWriteResGroup5], (instregex "PSUBSBrr")>;
 557 def: InstRW<[SBWriteResGroup5], (instregex "PSUBSWrr")>;
 558 def: InstRW<[SBWriteResGroup5], (instregex "PSUBUSBrr")>;
 559 def: InstRW<[SBWriteResGroup5], (instregex "PSUBUSWrr")>;
 560 def: InstRW<[SBWriteResGroup5], (instregex "PSUBWrr")>;
 561 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHBWrr")>;
 562 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHDQrr")>;
 563 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHQDQrr")>;
 564 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHWDrr")>;
 565 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLBWrr")>;
 566 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLDQrr")>;
 567 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLQDQrr")>;
 568 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLWDrr")>;
 569 def: InstRW<[SBWriteResGroup5], (instregex "VMASKMOVPSYrm")>;
 570 def: InstRW<[SBWriteResGroup5], (instregex "VPABSBrr")>;
 571 def: InstRW<[SBWriteResGroup5], (instregex "VPABSDrr")>;
 572 def: InstRW<[SBWriteResGroup5], (instregex "VPABSWrr")>;
 573 def: InstRW<[SBWriteResGroup5], (instregex "VPACKSSDWrr")>;
 574 def: InstRW<[SBWriteResGroup5], (instregex "VPACKSSWBrr")>;
 575 def: InstRW<[SBWriteResGroup5], (instregex "VPACKUSDWrr")>;
 576 def: InstRW<[SBWriteResGroup5], (instregex "VPACKUSWBrr")>;
 577 def: InstRW<[SBWriteResGroup5], (instregex "VPADDBrr")>;
 578 def: InstRW<[SBWriteResGroup5], (instregex "VPADDDrr")>;
 579 def: InstRW<[SBWriteResGroup5], (instregex "VPADDQrr")>;
 580 def: InstRW<[SBWriteResGroup5], (instregex "VPADDUSBrr")>;
 581 def: InstRW<[SBWriteResGroup5], (instregex "VPADDUSWrr")>;
 582 def: InstRW<[SBWriteResGroup5], (instregex "VPALIGNRrri")>;
 583 def: InstRW<[SBWriteResGroup5], (instregex "VPAVGBrr")>;
 584 def: InstRW<[SBWriteResGroup5], (instregex "VPAVGWrr")>;
 585 def: InstRW<[SBWriteResGroup5], (instregex "VPBLENDWrri")>;
 586 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQBrr")>;
 587 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQDrr")>;
 588 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQWrr")>;
 589 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTBrr")>;
 590 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTDrr")>;
 591 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTWrr")>;
 592 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSBrr")>;
 593 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSDrr")>;
 594 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSWrr")>;
 595 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUBrr")>;
 596 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUDrr")>;
 597 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUWrr")>;
 598 def: InstRW<[SBWriteResGroup5], (instregex "VPMINSBrr")>;
 599 def: InstRW<[SBWriteResGroup5], (instregex "VPMINSDrr")>;
 600 def: InstRW<[SBWriteResGroup5], (instregex "VPMINSWrr")>;
 601 def: InstRW<[SBWriteResGroup5], (instregex "VPMINUBrr")>;
 602 def: InstRW<[SBWriteResGroup5], (instregex "VPMINUDrr")>;
 603 def: InstRW<[SBWriteResGroup5], (instregex "VPMINUWrr")>;
 604 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBDrr")>;
 605 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBQrr")>;
 606 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBWrr")>;
 607 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXDQrr")>;
 608 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXWDrr")>;
 609 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXWQrr")>;
 610 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBDrr")>;
 611 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBQrr")>;
 612 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBWrr")>;
 613 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXDQrr")>;
 614 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXWDrr")>;
 615 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXWQrr")>;
 616 def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFBrr")>;
 617 def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFDri")>;
 618 def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFLWri")>;
 619 def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNBrr128")>;
 620 def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNDrr128")>;
 621 def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNWrr128")>;
 622 def: InstRW<[SBWriteResGroup5], (instregex "VPSLLDQri")>;
 623 def: InstRW<[SBWriteResGroup5], (instregex "VPSRLDQri")>;
 624 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBBrr")>;
 625 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBDrr")>;
 626 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBQrr")>;
 627 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBSBrr")>;
 628 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBSWrr")>;
 629 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBUSBrr")>;
 630 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBUSWrr")>;
 631 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBWrr")>;
 632 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHBWrr")>;
 633 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHDQrr")>;
 634 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHWDrr")>;
 635 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLDQrr")>;
 636 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLQDQrr")>;
 637 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLWDrr")>;
 638
 639 def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
 640   let Latency = 1;
 641   let NumMicroOps = 1;
 642   let ResourceCycles = [1];
 643 }
 644 def: InstRW<[SBWriteResGroup6], (instregex "ADD32ri8")>;
 645 def: InstRW<[SBWriteResGroup6], (instregex "ADD32rr")>;
 646 def: InstRW<[SBWriteResGroup6], (instregex "ADD8ri")>;
 647 def: InstRW<[SBWriteResGroup6], (instregex "ADD8rr")>;
 648 def: InstRW<[SBWriteResGroup6], (instregex "AND32ri")>;
 649 def: InstRW<[SBWriteResGroup6], (instregex "AND64ri8")>;
 650 def: InstRW<[SBWriteResGroup6], (instregex "AND64rr")>;
 651 def: InstRW<[SBWriteResGroup6], (instregex "AND8ri")>;
 652 def: InstRW<[SBWriteResGroup6], (instregex "AND8rr")>;
 653 def: InstRW<[SBWriteResGroup6], (instregex "CBW")>;
 654 def: InstRW<[SBWriteResGroup6], (instregex "CMC")>;
 655 def: InstRW<[SBWriteResGroup6], (instregex "CMP16ri8")>;
 656 def: InstRW<[SBWriteResGroup6], (instregex "CMP32i32")>;
 657 def: InstRW<[SBWriteResGroup6], (instregex "CMP64rr")>;
 658 def: InstRW<[SBWriteResGroup6], (instregex "CMP8ri")>;
 659 def: InstRW<[SBWriteResGroup6], (instregex "CMP8rr")>;
 660 def: InstRW<[SBWriteResGroup6], (instregex "CWDE")>;
 661 def: InstRW<[SBWriteResGroup6], (instregex "DEC64r")>;
 662 def: InstRW<[SBWriteResGroup6], (instregex "DEC8r")>;
 663 def: InstRW<[SBWriteResGroup6], (instregex "INC64r")>;
 664 def: InstRW<[SBWriteResGroup6], (instregex "INC8r")>;
 665 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVD64from64rr")>;
 666 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr")>;
 667 def: InstRW<[SBWriteResGroup6], (instregex "MOV32rr")>;
 668 def: InstRW<[SBWriteResGroup6], (instregex "MOV8ri")>;
 669 def: InstRW<[SBWriteResGroup6], (instregex "MOV8rr")>;
 670 def: InstRW<[SBWriteResGroup6], (instregex "MOVDQArr")>;
 671 def: InstRW<[SBWriteResGroup6], (instregex "MOVDQUrr")>;
 672 def: InstRW<[SBWriteResGroup6], (instregex "MOVPQI2QIrr")>;
 673 def: InstRW<[SBWriteResGroup6], (instregex "MOVSX32rr16")>;
 674 def: InstRW<[SBWriteResGroup6], (instregex "MOVSX32rr8")>;
 675 def: InstRW<[SBWriteResGroup6], (instregex "MOVZX32rr16")>;
 676 def: InstRW<[SBWriteResGroup6], (instregex "MOVZX32rr8")>;
 677 def: InstRW<[SBWriteResGroup6], (instregex "NEG64r")>;
 678 def: InstRW<[SBWriteResGroup6], (instregex "NEG8r")>;
 679 def: InstRW<[SBWriteResGroup6], (instregex "NOT64r")>;
 680 def: InstRW<[SBWriteResGroup6], (instregex "NOT8r")>;
 681 def: InstRW<[SBWriteResGroup6], (instregex "OR64ri8")>;
 682 def: InstRW<[SBWriteResGroup6], (instregex "OR64rr")>;
 683 def: InstRW<[SBWriteResGroup6], (instregex "OR8ri")>;
 684 def: InstRW<[SBWriteResGroup6], (instregex "OR8rr")>;
 685 def: InstRW<[SBWriteResGroup6], (instregex "PANDNrr")>;
 686 def: InstRW<[SBWriteResGroup6], (instregex "PANDrr")>;
 687 def: InstRW<[SBWriteResGroup6], (instregex "PORrr")>;
 688 def: InstRW<[SBWriteResGroup6], (instregex "PXORrr")>;
 689 def: InstRW<[SBWriteResGroup6], (instregex "STC")>;
 690 def: InstRW<[SBWriteResGroup6], (instregex "SUB64ri8")>;
 691 def: InstRW<[SBWriteResGroup6], (instregex "SUB64rr")>;
 692 def: InstRW<[SBWriteResGroup6], (instregex "SUB8ri")>;
 693 def: InstRW<[SBWriteResGroup6], (instregex "SUB8rr")>;
 694 def: InstRW<[SBWriteResGroup6], (instregex "TEST64rr")>;
 695 def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>;
 696 def: InstRW<[SBWriteResGroup6], (instregex "TEST8rr")>;
 697 def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQI2QIrr")>;
 698 def: InstRW<[SBWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>;
 699 def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>;
 700 def: InstRW<[SBWriteResGroup6], (instregex "VPANDrr")>;
 701 def: InstRW<[SBWriteResGroup6], (instregex "VPORrr")>;
 702 def: InstRW<[SBWriteResGroup6], (instregex "VPXORrr")>;
 703 def: InstRW<[SBWriteResGroup6], (instregex "XOR32rr")>;
 704 def: InstRW<[SBWriteResGroup6], (instregex "XOR64ri8")>;
 705 def: InstRW<[SBWriteResGroup6], (instregex "XOR8ri")>;
 706 def: InstRW<[SBWriteResGroup6], (instregex "XOR8rr")>;
 707
 708 def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
 709   let Latency = 2;
 710   let NumMicroOps = 1;
 711   let ResourceCycles = [1];
 712 }
 713 def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPDrr")>;
 714 def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPSrr")>;
 715 def: InstRW<[SBWriteResGroup7], (instregex "MOVPDI2DIrr")>;
 716 def: InstRW<[SBWriteResGroup7], (instregex "MOVPQIto64rr")>;
 717 def: InstRW<[SBWriteResGroup7], (instregex "PMOVMSKBrr")>;
 718 def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPDYrr")>;
 719 def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPDrr")>;
 720 def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPSrr")>;
 721 def: InstRW<[SBWriteResGroup7], (instregex "VMOVPDI2DIrr")>;
 722 def: InstRW<[SBWriteResGroup7], (instregex "VMOVPQIto64rr")>;
 723
 724 def SBWriteResGroup9 : SchedWriteRes<[SBPort0]> {
 725   let Latency = 2;
 726   let NumMicroOps = 2;
 727   let ResourceCycles = [2];
 728 }
 729 def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPDrr0")>;
 730 def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPSrr0")>;
 731 def: InstRW<[SBWriteResGroup9], (instregex "ROL32ri")>;
 732 def: InstRW<[SBWriteResGroup9], (instregex "ROL8ri")>;
 733 def: InstRW<[SBWriteResGroup9], (instregex "ROR32ri")>;
 734 def: InstRW<[SBWriteResGroup9], (instregex "ROR8ri")>;
 735 def: InstRW<[SBWriteResGroup9], (instregex "SETAr")>;
 736 def: InstRW<[SBWriteResGroup9], (instregex "SETBEr")>;
 737 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDYrr")>;
 738 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDrr")>;
 739 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPSYrr")>;
 740 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPSrr")>;
 741
 742 def SBWriteResGroup10 : SchedWriteRes<[SBPort15]> {
 743   let Latency = 2;
 744   let NumMicroOps = 2;
 745   let ResourceCycles = [2];
 746 }
 747 def: InstRW<[SBWriteResGroup10], (instregex "VPBLENDVBrr")>;
 748
 749 def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
 750   let Latency = 2;
 751   let NumMicroOps = 2;
 752   let ResourceCycles = [2];
 753 }
 754 def: InstRW<[SBWriteResGroup11], (instregex "SCASB")>;
 755 def: InstRW<[SBWriteResGroup11], (instregex "SCASL")>;
 756 def: InstRW<[SBWriteResGroup11], (instregex "SCASQ")>;
 757 def: InstRW<[SBWriteResGroup11], (instregex "SCASW")>;
 758
 759 def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> {
 760   let Latency = 2;
 761   let NumMicroOps = 2;
 762   let ResourceCycles = [1,1];
 763 }
 764 def: InstRW<[SBWriteResGroup12], (instregex "COMISDrr")>;
 765 def: InstRW<[SBWriteResGroup12], (instregex "COMISSrr")>;
 766 def: InstRW<[SBWriteResGroup12], (instregex "UCOMISDrr")>;
 767 def: InstRW<[SBWriteResGroup12], (instregex "UCOMISSrr")>;
 768 def: InstRW<[SBWriteResGroup12], (instregex "VCOMISDrr")>;
 769 def: InstRW<[SBWriteResGroup12], (instregex "VCOMISSrr")>;
 770 def: InstRW<[SBWriteResGroup12], (instregex "VUCOMISDrr")>;
 771 def: InstRW<[SBWriteResGroup12], (instregex "VUCOMISSrr")>;
 772
 773 def SBWriteResGroup13 : SchedWriteRes<[SBPort0,SBPort5]> {
 774   let Latency = 2;
 775   let NumMicroOps = 2;
 776   let ResourceCycles = [1,1];
 777 }
 778 def: InstRW<[SBWriteResGroup13], (instregex "CVTPS2PDrr")>;
 779 def: InstRW<[SBWriteResGroup13], (instregex "PTESTrr")>;
 780 def: InstRW<[SBWriteResGroup13], (instregex "VCVTPS2PDYrr")>;
 781 def: InstRW<[SBWriteResGroup13], (instregex "VCVTPS2PDrr")>;
 782 def: InstRW<[SBWriteResGroup13], (instregex "VPTESTYrr")>;
 783 def: InstRW<[SBWriteResGroup13], (instregex "VPTESTrr")>;
 784
 785 def SBWriteResGroup14 : SchedWriteRes<[SBPort0,SBPort15]> {
 786   let Latency = 2;
 787   let NumMicroOps = 2;
 788   let ResourceCycles = [1,1];
 789 }
 790 def: InstRW<[SBWriteResGroup14], (instregex "PSLLDrr")>;
 791 def: InstRW<[SBWriteResGroup14], (instregex "PSLLQrr")>;
 792 def: InstRW<[SBWriteResGroup14], (instregex "PSLLWrr")>;
 793 def: InstRW<[SBWriteResGroup14], (instregex "PSRADrr")>;
 794 def: InstRW<[SBWriteResGroup14], (instregex "PSRAWrr")>;
 795 def: InstRW<[SBWriteResGroup14], (instregex "PSRLDrr")>;
 796 def: InstRW<[SBWriteResGroup14], (instregex "PSRLQrr")>;
 797 def: InstRW<[SBWriteResGroup14], (instregex "PSRLWrr")>;
 798 def: InstRW<[SBWriteResGroup14], (instregex "VPSRADrr")>;
 799 def: InstRW<[SBWriteResGroup14], (instregex "VPSRAWrr")>;
 800 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLDrr")>;
 801 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLQrr")>;
 802 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLWrr")>;
 803
 804 def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
 805   let Latency = 2;
 806   let NumMicroOps = 2;
 807   let ResourceCycles = [1,1];
 808 }
 809 def: InstRW<[SBWriteResGroup15], (instregex "FNSTSW16r")>;
 810
 811 def SBWriteResGroup16 : SchedWriteRes<[SBPort1,SBPort0]> {
 812   let Latency = 2;
 813   let NumMicroOps = 2;
 814   let ResourceCycles = [1,1];
 815 }
 816 def: InstRW<[SBWriteResGroup16], (instregex "BSWAP32r")>;
 817
 818 def SBWriteResGroup17 : SchedWriteRes<[SBPort5,SBPort15]> {
 819   let Latency = 2;
 820   let NumMicroOps = 2;
 821   let ResourceCycles = [1,1];
 822 }
 823 def: InstRW<[SBWriteResGroup17], (instregex "PINSRBrr")>;
 824 def: InstRW<[SBWriteResGroup17], (instregex "PINSRDrr")>;
 825 def: InstRW<[SBWriteResGroup17], (instregex "PINSRQrr")>;
 826 def: InstRW<[SBWriteResGroup17], (instregex "PINSRWrri")>;
 827 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRBrr")>;
 828 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRDrr")>;
 829 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRQrr")>;
 830 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRWrri")>;
 831
 832 def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
 833   let Latency = 2;
 834   let NumMicroOps = 2;
 835   let ResourceCycles = [1,1];
 836 }
 837 def: InstRW<[SBWriteResGroup18], (instregex "MMX_MOVDQ2Qrr")>;
 838
 839 def SBWriteResGroup19 : SchedWriteRes<[SBPort0,SBPort015]> {
 840   let Latency = 2;
 841   let NumMicroOps = 2;
 842   let ResourceCycles = [1,1];
 843 }
 844 def: InstRW<[SBWriteResGroup19], (instregex "ADC64ri8")>;
 845 def: InstRW<[SBWriteResGroup19], (instregex "ADC64rr")>;
 846 def: InstRW<[SBWriteResGroup19], (instregex "ADC8ri")>;
 847 def: InstRW<[SBWriteResGroup19], (instregex "ADC8rr")>;
 848 def: InstRW<[SBWriteResGroup19], (instregex "CMOVAE32rr")>;
 849 def: InstRW<[SBWriteResGroup19], (instregex "CMOVB32rr")>;
 850 def: InstRW<[SBWriteResGroup19], (instregex "CMOVE32rr")>;
 851 def: InstRW<[SBWriteResGroup19], (instregex "CMOVG32rr")>;
 852 def: InstRW<[SBWriteResGroup19], (instregex "CMOVGE32rr")>;
 853 def: InstRW<[SBWriteResGroup19], (instregex "CMOVL32rr")>;
 854 def: InstRW<[SBWriteResGroup19], (instregex "CMOVLE32rr")>;
 855 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNE32rr")>;
 856 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNO32rr")>;
 857 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNP32rr")>;
 858 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNS32rr")>;
 859 def: InstRW<[SBWriteResGroup19], (instregex "CMOVO32rr")>;
 860 def: InstRW<[SBWriteResGroup19], (instregex "CMOVP32rr")>;
 861 def: InstRW<[SBWriteResGroup19], (instregex "CMOVS32rr")>;
 862 def: InstRW<[SBWriteResGroup19], (instregex "SBB32rr")>;
 863 def: InstRW<[SBWriteResGroup19], (instregex "SBB64ri8")>;
 864 def: InstRW<[SBWriteResGroup19], (instregex "SBB8ri")>;
 865 def: InstRW<[SBWriteResGroup19], (instregex "SBB8rr")>;
 866 def: InstRW<[SBWriteResGroup19], (instregex "SHLD32rri8")>;
 867 def: InstRW<[SBWriteResGroup19], (instregex "SHRD32rri8")>;
 868
 869 def SBWriteResGroup20 : SchedWriteRes<[SBPort0]> {
 870   let Latency = 3;
 871   let NumMicroOps = 1;
 872   let ResourceCycles = [1];
 873 }
 874 def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr64")>;
 875 def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULHRSWrr64")>;
 876 def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULUDQirr")>;
 877 def: InstRW<[SBWriteResGroup20], (instregex "PMADDUBSWrr")>;
 878 def: InstRW<[SBWriteResGroup20], (instregex "PMADDWDrr")>;
 879 def: InstRW<[SBWriteResGroup20], (instregex "PMULDQrr")>;
 880 def: InstRW<[SBWriteResGroup20], (instregex "PMULHRSWrr")>;
 881 def: InstRW<[SBWriteResGroup20], (instregex "PMULHUWrr")>;
 882 def: InstRW<[SBWriteResGroup20], (instregex "PMULHWrr")>;
 883 def: InstRW<[SBWriteResGroup20], (instregex "PMULLDrr")>;
 884 def: InstRW<[SBWriteResGroup20], (instregex "PMULLWrr")>;
 885 def: InstRW<[SBWriteResGroup20], (instregex "PMULUDQrr")>;
 886 def: InstRW<[SBWriteResGroup20], (instregex "PSADBWrr")>;
 887 def: InstRW<[SBWriteResGroup20], (instregex "VMOVMSKPSYrr")>;
 888 def: InstRW<[SBWriteResGroup20], (instregex "VPMADDUBSWrr")>;
 889 def: InstRW<[SBWriteResGroup20], (instregex "VPMADDWDrr")>;
 890 def: InstRW<[SBWriteResGroup20], (instregex "VPMULDQrr")>;
 891 def: InstRW<[SBWriteResGroup20], (instregex "VPMULHRSWrr")>;
 892 def: InstRW<[SBWriteResGroup20], (instregex "VPMULHWrr")>;
 893 def: InstRW<[SBWriteResGroup20], (instregex "VPMULLDrr")>;
 894 def: InstRW<[SBWriteResGroup20], (instregex "VPMULLWrr")>;
 895 def: InstRW<[SBWriteResGroup20], (instregex "VPSADBWrr")>;
 896
 897 def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
 898   let Latency = 3;
 899   let NumMicroOps = 1;
 900   let ResourceCycles = [1];
 901 }
 902 def: InstRW<[SBWriteResGroup21], (instregex "ADDPDrr")>;
 903 def: InstRW<[SBWriteResGroup21], (instregex "ADDPSrr")>;
 904 def: InstRW<[SBWriteResGroup21], (instregex "ADDSDrr")>;
 905 def: InstRW<[SBWriteResGroup21], (instregex "ADDSSrr")>;
 906 def: InstRW<[SBWriteResGroup21], (instregex "ADDSUBPDrr")>;
 907 def: InstRW<[SBWriteResGroup21], (instregex "ADDSUBPSrr")>;
 908 def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0")>;
 909 def: InstRW<[SBWriteResGroup21], (instregex "ADD_FST0r")>;
 910 def: InstRW<[SBWriteResGroup21], (instregex "ADD_FrST0")>;
 911 def: InstRW<[SBWriteResGroup21], (instregex "BSF32rr")>;
 912 def: InstRW<[SBWriteResGroup21], (instregex "BSR32rr")>;
 913 def: InstRW<[SBWriteResGroup21], (instregex "CMPPDrri")>;
 914 def: InstRW<[SBWriteResGroup21], (instregex "CMPPSrri")>;
 915 def: InstRW<[SBWriteResGroup21], (instregex "CMPSDrr")>;
 916 def: InstRW<[SBWriteResGroup21], (instregex "CMPSSrr")>;
 917 def: InstRW<[SBWriteResGroup21], (instregex "CRC32r32r32")>;
 918 def: InstRW<[SBWriteResGroup21], (instregex "CRC32r32r8")>;
 919 def: InstRW<[SBWriteResGroup21], (instregex "CVTDQ2PSrr")>;
 920 def: InstRW<[SBWriteResGroup21], (instregex "CVTPS2DQrr")>;
 921 def: InstRW<[SBWriteResGroup21], (instregex "CVTTPS2DQrr")>;
 922 def: InstRW<[SBWriteResGroup21], (instregex "MAXPDrr")>;
 923 def: InstRW<[SBWriteResGroup21], (instregex "MAXPSrr")>;
 924 def: InstRW<[SBWriteResGroup21], (instregex "MAXSDrr")>;
 925 def: InstRW<[SBWriteResGroup21], (instregex "MAXSSrr")>;
 926 def: InstRW<[SBWriteResGroup21], (instregex "MINPDrr")>;
 927 def: InstRW<[SBWriteResGroup21], (instregex "MINPSrr")>;
 928 def: InstRW<[SBWriteResGroup21], (instregex "MINSDrr")>;
 929 def: InstRW<[SBWriteResGroup21], (instregex "MINSSrr")>;
 930 def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPI2PSirr")>;
 931 def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPS2PIirr")>;
 932 def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTTPS2PIirr")>;
 933 def: InstRW<[SBWriteResGroup21], (instregex "MUL8r")>;
 934 def: InstRW<[SBWriteResGroup21], (instregex "POPCNT32rr")>;
 935 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDPDr")>;
 936 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDPSr")>;
 937 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDSDr")>;
 938 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDSSr")>;
 939 def: InstRW<[SBWriteResGroup21], (instregex "SUBPDrr")>;
 940 def: InstRW<[SBWriteResGroup21], (instregex "SUBPSrr")>;
 941 def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FPrST0")>;
 942 def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FST0r")>;
 943 def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FrST0")>;
 944 def: InstRW<[SBWriteResGroup21], (instregex "SUBSDrr")>;
 945 def: InstRW<[SBWriteResGroup21], (instregex "SUBSSrr")>;
 946 def: InstRW<[SBWriteResGroup21], (instregex "SUB_FPrST0")>;
 947 def: InstRW<[SBWriteResGroup21], (instregex "SUB_FST0r")>;
 948 def: InstRW<[SBWriteResGroup21], (instregex "SUB_FrST0")>;
 949 def: InstRW<[SBWriteResGroup21], (instregex "VADDPDYrr")>;
 950 def: InstRW<[SBWriteResGroup21], (instregex "VADDPDrr")>;
 951 def: InstRW<[SBWriteResGroup21], (instregex "VADDPSYrr")>;
 952 def: InstRW<[SBWriteResGroup21], (instregex "VADDPSrr")>;
 953 def: InstRW<[SBWriteResGroup21], (instregex "VADDSDrr")>;
 954 def: InstRW<[SBWriteResGroup21], (instregex "VADDSSrr")>;
 955 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPDYrr")>;
 956 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPDrr")>;
 957 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPSYrr")>;
 958 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPSrr")>;
 959 def: InstRW<[SBWriteResGroup21], (instregex "VBROADCASTF128")>;
 960 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPDYrri")>;
 961 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPDrri")>;
 962 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPSYrri")>;
 963 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPSrri")>;
 964 def: InstRW<[SBWriteResGroup21], (instregex "VCMPSDrr")>;
 965 def: InstRW<[SBWriteResGroup21], (instregex "VCMPSSrr")>;
 966 def: InstRW<[SBWriteResGroup21], (instregex "VCVTDQ2PSYrr")>;
 967 def: InstRW<[SBWriteResGroup21], (instregex "VCVTDQ2PSrr")>;
 968 def: InstRW<[SBWriteResGroup21], (instregex "VCVTPS2DQYrr")>;
 969 def: InstRW<[SBWriteResGroup21], (instregex "VCVTPS2DQrr")>;
 970 def: InstRW<[SBWriteResGroup21], (instregex "VCVTTPS2DQrr")>;
 971 def: InstRW<[SBWriteResGroup21], (instregex "VMAXPDYrr")>;
 972 def: InstRW<[SBWriteResGroup21], (instregex "VMAXPDrr")>;
 973 def: InstRW<[SBWriteResGroup21], (instregex "VMAXPSYrr")>;
 974 def: InstRW<[SBWriteResGroup21], (instregex "VMAXPSrr")>;
 975 def: InstRW<[SBWriteResGroup21], (instregex "VMAXSDrr")>;
 976 def: InstRW<[SBWriteResGroup21], (instregex "VMAXSSrr")>;
 977 def: InstRW<[SBWriteResGroup21], (instregex "VMINPDrr")>;
 978 def: InstRW<[SBWriteResGroup21], (instregex "VMINPSrr")>;
 979 def: InstRW<[SBWriteResGroup21], (instregex "VMINSDrr")>;
 980 def: InstRW<[SBWriteResGroup21], (instregex "VMINSSrr")>;
 981 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDPDr")>;
 982 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDPSr")>;
 983 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDSDr")>;
 984 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPDYrr")>;
 985 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPDrr")>;
 986 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPSYrr")>;
 987 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPSrr")>;
 988
 989 def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
 990   let Latency = 3;
 991   let NumMicroOps = 2;
 992   let ResourceCycles = [1,1];
 993 }
 994 def: InstRW<[SBWriteResGroup22], (instregex "EXTRACTPSrr")>;
 995 def: InstRW<[SBWriteResGroup22], (instregex "VEXTRACTPSrr")>;
 996
 997 def SBWriteResGroup23 : SchedWriteRes<[SBPort0,SBPort15]> {
 998   let Latency = 3;
 999   let NumMicroOps = 2;
1000   let ResourceCycles = [1,1];
1001 }
1002 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRBrr")>;
1003 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRDrr")>;
1004 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRQrr")>;
1005 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRWri")>;
1006 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRBrr")>;
1007 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRDrr")>;
1008 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRQrr")>;
1009 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRWri")>;
1010 def: InstRW<[SBWriteResGroup23], (instregex "SHL64rCL")>;
1011 def: InstRW<[SBWriteResGroup23], (instregex "SHL8rCL")>;
1012
1013 def SBWriteResGroup24 : SchedWriteRes<[SBPort15]> {
1014   let Latency = 3;
1015   let NumMicroOps = 3;
1016   let ResourceCycles = [3];
1017 }
1018 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDSWrr64")>;
1019 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDWrr64")>;
1020 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDrr64")>;
1021 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBDrr64")>;
1022 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBSWrr64")>;
1023 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBWrr64")>;
1024 def: InstRW<[SBWriteResGroup24], (instregex "PHADDDrr")>;
1025 def: InstRW<[SBWriteResGroup24], (instregex "PHADDSWrr128")>;
1026 def: InstRW<[SBWriteResGroup24], (instregex "PHADDWrr")>;
1027 def: InstRW<[SBWriteResGroup24], (instregex "PHSUBDrr")>;
1028 def: InstRW<[SBWriteResGroup24], (instregex "PHSUBSWrr128")>;
1029 def: InstRW<[SBWriteResGroup24], (instregex "PHSUBWrr")>;
1030 def: InstRW<[SBWriteResGroup24], (instregex "VPHADDDrr")>;
1031 def: InstRW<[SBWriteResGroup24], (instregex "VPHADDSWrr128")>;
1032 def: InstRW<[SBWriteResGroup24], (instregex "VPHADDWrr")>;
1033 def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBDrr")>;
1034 def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBSWrr128")>;
1035 def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBWrr")>;
1036
1037 def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> {
1038   let Latency = 3;
1039   let NumMicroOps = 3;
1040   let ResourceCycles = [3];
1041 }
1042 def: InstRW<[SBWriteResGroup25], (instregex "LEAVE64")>;
1043 def: InstRW<[SBWriteResGroup25], (instregex "XADD32rr")>;
1044 def: InstRW<[SBWriteResGroup25], (instregex "XADD8rr")>;
1045
1046 def SBWriteResGroup26 : SchedWriteRes<[SBPort0,SBPort015]> {
1047   let Latency = 3;
1048   let NumMicroOps = 3;
1049   let ResourceCycles = [2,1];
1050 }
1051 def: InstRW<[SBWriteResGroup26], (instregex "CMOVA32rr")>;
1052 def: InstRW<[SBWriteResGroup26], (instregex "CMOVBE32rr")>;
1053
1054 def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> {
1055   let Latency = 4;
1056   let NumMicroOps = 2;
1057   let ResourceCycles = [1,1];
1058 }
1059 def: InstRW<[SBWriteResGroup27], (instregex "MUL64r")>;
1060
1061 def SBWriteResGroup28 : SchedWriteRes<[SBPort1,SBPort5]> {
1062   let Latency = 4;
1063   let NumMicroOps = 2;
1064   let ResourceCycles = [1,1];
1065 }
1066 def: InstRW<[SBWriteResGroup28], (instregex "CVTDQ2PDrr")>;
1067 def: InstRW<[SBWriteResGroup28], (instregex "CVTPD2DQrr")>;
1068 def: InstRW<[SBWriteResGroup28], (instregex "CVTPD2PSrr")>;
1069 def: InstRW<[SBWriteResGroup28], (instregex "CVTSD2SSrr")>;
1070 def: InstRW<[SBWriteResGroup28], (instregex "CVTSI2SD64rr")>;
1071 def: InstRW<[SBWriteResGroup28], (instregex "CVTSI2SDrr")>;
1072 def: InstRW<[SBWriteResGroup28], (instregex "CVTTPD2DQrr")>;
1073 def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPD2PIirr")>;
1074 def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPI2PDirr")>;
1075 def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTTPD2PIirr")>;
1076 def: InstRW<[SBWriteResGroup28], (instregex "VCVTDQ2PDYrr")>;
1077 def: InstRW<[SBWriteResGroup28], (instregex "VCVTDQ2PDrr")>;
1078 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2DQYrr")>;
1079 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2DQrr")>;
1080 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2PSYrr")>;
1081 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2PSrr")>;
1082 def: InstRW<[SBWriteResGroup28], (instregex "VCVTSI2SD64rr")>;
1083 def: InstRW<[SBWriteResGroup28], (instregex "VCVTSI2SDrr")>;
1084 def: InstRW<[SBWriteResGroup28], (instregex "VCVTTPD2DQYrr")>;
1085 def: InstRW<[SBWriteResGroup28], (instregex "VCVTTPD2DQrr")>;
1086
1087 def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
1088   let Latency = 4;
1089   let NumMicroOps = 2;
1090   let ResourceCycles = [1,1];
1091 }
1092 def: InstRW<[SBWriteResGroup29], (instregex "MOV64sr")>;
1093 def: InstRW<[SBWriteResGroup29], (instregex "PAUSE")>;
1094
1095 def SBWriteResGroup30 : SchedWriteRes<[SBPort0]> {
1096   let Latency = 5;
1097   let NumMicroOps = 1;
1098   let ResourceCycles = [1];
1099 }
1100 def: InstRW<[SBWriteResGroup30], (instregex "MULPDrr")>;
1101 def: InstRW<[SBWriteResGroup30], (instregex "MULPSrr")>;
1102 def: InstRW<[SBWriteResGroup30], (instregex "MULSDrr")>;
1103 def: InstRW<[SBWriteResGroup30], (instregex "MULSSrr")>;
1104 def: InstRW<[SBWriteResGroup30], (instregex "MUL_FPrST0")>;
1105 def: InstRW<[SBWriteResGroup30], (instregex "MUL_FST0r")>;
1106 def: InstRW<[SBWriteResGroup30], (instregex "MUL_FrST0")>;
1107 def: InstRW<[SBWriteResGroup30], (instregex "PCMPGTQrr")>;
1108 def: InstRW<[SBWriteResGroup30], (instregex "PHMINPOSUWrr128")>;
1109 def: InstRW<[SBWriteResGroup30], (instregex "RCPPSr")>;
1110 def: InstRW<[SBWriteResGroup30], (instregex "RCPSSr")>;
1111 def: InstRW<[SBWriteResGroup30], (instregex "RSQRTPSr")>;
1112 def: InstRW<[SBWriteResGroup30], (instregex "RSQRTSSr")>;
1113 def: InstRW<[SBWriteResGroup30], (instregex "VMULPDYrr")>;
1114 def: InstRW<[SBWriteResGroup30], (instregex "VMULPDrr")>;
1115 def: InstRW<[SBWriteResGroup30], (instregex "VMULPSYrr")>;
1116 def: InstRW<[SBWriteResGroup30], (instregex "VMULPSrr")>;
1117 def: InstRW<[SBWriteResGroup30], (instregex "VMULSDrr")>;
1118 def: InstRW<[SBWriteResGroup30], (instregex "VMULSSrr")>;
1119 def: InstRW<[SBWriteResGroup30], (instregex "VPCMPGTQrr")>;
1120 def: InstRW<[SBWriteResGroup30], (instregex "VPHMINPOSUWrr128")>;
1121 def: InstRW<[SBWriteResGroup30], (instregex "VRSQRTPSr")>;
1122 def: InstRW<[SBWriteResGroup30], (instregex "VRSQRTSSr")>;
1123
1124 def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
1125   let Latency = 5;
1126   let NumMicroOps = 1;
1127   let ResourceCycles = [1];
1128 }
1129 def: InstRW<[SBWriteResGroup31], (instregex "MOV32rm")>;
1130 def: InstRW<[SBWriteResGroup31], (instregex "MOV8rm")>;
1131 def: InstRW<[SBWriteResGroup31], (instregex "MOVSX32rm16")>;
1132 def: InstRW<[SBWriteResGroup31], (instregex "MOVSX32rm8")>;
1133 def: InstRW<[SBWriteResGroup31], (instregex "MOVZX32rm16")>;
1134 def: InstRW<[SBWriteResGroup31], (instregex "MOVZX32rm8")>;
1135 def: InstRW<[SBWriteResGroup31], (instregex "PREFETCH")>;
1136
1137 def SBWriteResGroup32 : SchedWriteRes<[SBPort0,SBPort1]> {
1138   let Latency = 5;
1139   let NumMicroOps = 2;
1140   let ResourceCycles = [1,1];
1141 }
1142 def: InstRW<[SBWriteResGroup32], (instregex "CVTSD2SI64rr")>;
1143 def: InstRW<[SBWriteResGroup32], (instregex "CVTSD2SIrr")>;
1144 def: InstRW<[SBWriteResGroup32], (instregex "CVTSS2SI64rr")>;
1145 def: InstRW<[SBWriteResGroup32], (instregex "CVTSS2SIrr")>;
1146 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSD2SI64rr")>;
1147 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSD2SIrr")>;
1148 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSS2SI64rr")>;
1149 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSS2SIrr")>;
1150 def: InstRW<[SBWriteResGroup32], (instregex "VCVTSD2SI64rr")>;
1151 def: InstRW<[SBWriteResGroup32], (instregex "VCVTSS2SI64rr")>;
1152 def: InstRW<[SBWriteResGroup32], (instregex "VCVTSS2SIrr")>;
1153 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSD2SI64rr")>;
1154 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSD2SIrr")>;
1155 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSS2SI64rr")>;
1156 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSS2SIrr")>;
1157
1158 def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
1159   let Latency = 5;
1160   let NumMicroOps = 2;
1161   let ResourceCycles = [1,1];
1162 }
1163 def: InstRW<[SBWriteResGroup33], (instregex "MOV64mr")>;
1164 def: InstRW<[SBWriteResGroup33], (instregex "MOV8mr")>;
1165 def: InstRW<[SBWriteResGroup33], (instregex "MOVAPDmr")>;
1166 def: InstRW<[SBWriteResGroup33], (instregex "MOVAPSmr")>;
1167 def: InstRW<[SBWriteResGroup33], (instregex "MOVDQAmr")>;
1168 def: InstRW<[SBWriteResGroup33], (instregex "MOVDQUmr")>;
1169 def: InstRW<[SBWriteResGroup33], (instregex "MOVHPDmr")>;
1170 def: InstRW<[SBWriteResGroup33], (instregex "MOVHPSmr")>;
1171 def: InstRW<[SBWriteResGroup33], (instregex "MOVLPDmr")>;
1172 def: InstRW<[SBWriteResGroup33], (instregex "MOVLPSmr")>;
1173 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTDQmr")>;
1174 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTI_64mr")>;
1175 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTImr")>;
1176 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTPDmr")>;
1177 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTPSmr")>;
1178 def: InstRW<[SBWriteResGroup33], (instregex "MOVPDI2DImr")>;
1179 def: InstRW<[SBWriteResGroup33], (instregex "MOVPQI2QImr")>;
1180 def: InstRW<[SBWriteResGroup33], (instregex "MOVPQIto64mr")>;
1181 def: InstRW<[SBWriteResGroup33], (instregex "MOVSSmr")>;
1182 def: InstRW<[SBWriteResGroup33], (instregex "MOVUPDmr")>;
1183 def: InstRW<[SBWriteResGroup33], (instregex "MOVUPSmr")>;
1184 def: InstRW<[SBWriteResGroup33], (instregex "PUSH64i8")>;
1185 def: InstRW<[SBWriteResGroup33], (instregex "PUSH64r")>;
1186 def: InstRW<[SBWriteResGroup33], (instregex "VEXTRACTF128mr")>;
1187 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPDYmr")>;
1188 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPDmr")>;
1189 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPSYmr")>;
1190 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPSmr")>;
1191 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQAYmr")>;
1192 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQAmr")>;
1193 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQUYmr")>;
1194 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQUmr")>;
1195 def: InstRW<[SBWriteResGroup33], (instregex "VMOVHPDmr")>;
1196 def: InstRW<[SBWriteResGroup33], (instregex "VMOVHPSmr")>;
1197 def: InstRW<[SBWriteResGroup33], (instregex "VMOVLPDmr")>;
1198 def: InstRW<[SBWriteResGroup33], (instregex "VMOVLPSmr")>;
1199 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTDQYmr")>;
1200 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTDQmr")>;
1201 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPDYmr")>;
1202 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPDmr")>;
1203 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPSYmr")>;
1204 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPSmr")>;
1205 def: InstRW<[SBWriteResGroup33], (instregex "VMOVPDI2DImr")>;
1206 def: InstRW<[SBWriteResGroup33], (instregex "VMOVPQI2QImr")>;
1207 def: InstRW<[SBWriteResGroup33], (instregex "VMOVPQIto64mr")>;
1208 def: InstRW<[SBWriteResGroup33], (instregex "VMOVSDmr")>;
1209 def: InstRW<[SBWriteResGroup33], (instregex "VMOVSSmr")>;
1210 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPDYmr")>;
1211 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPDmr")>;
1212 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPSYmr")>;
1213 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPSmr")>;
1214
1215 def SBWriteResGroup34 : SchedWriteRes<[SBPort0,SBPort15]> {
1216   let Latency = 5;
1217   let NumMicroOps = 3;
1218   let ResourceCycles = [1,2];
1219 }
1220 def: InstRW<[SBWriteResGroup34], (instregex "MPSADBWrri")>;
1221 def: InstRW<[SBWriteResGroup34], (instregex "VMPSADBWrri")>;
1222
1223 def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
1224   let Latency = 5;
1225   let NumMicroOps = 3;
1226   let ResourceCycles = [1,2];
1227 }
1228 def: InstRW<[SBWriteResGroup35], (instregex "CLI")>;
1229 def: InstRW<[SBWriteResGroup35], (instregex "CVTSI2SS64rr")>;
1230 def: InstRW<[SBWriteResGroup35], (instregex "CVTSI2SSrr")>;
1231 def: InstRW<[SBWriteResGroup35], (instregex "HADDPDrr")>;
1232 def: InstRW<[SBWriteResGroup35], (instregex "HADDPSrr")>;
1233 def: InstRW<[SBWriteResGroup35], (instregex "HSUBPDrr")>;
1234 def: InstRW<[SBWriteResGroup35], (instregex "HSUBPSrr")>;
1235 def: InstRW<[SBWriteResGroup35], (instregex "VCVTSI2SS64rr")>;
1236 def: InstRW<[SBWriteResGroup35], (instregex "VCVTSI2SSrr")>;
1237 def: InstRW<[SBWriteResGroup35], (instregex "VHADDPDrr")>;
1238 def: InstRW<[SBWriteResGroup35], (instregex "VHADDPSYrr")>;
1239 def: InstRW<[SBWriteResGroup35], (instregex "VHADDPSrr")>;
1240 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPDYrr")>;
1241 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPDrr")>;
1242 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPSYrr")>;
1243 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPSrr")>;
1244
1245 def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
1246   let Latency = 5;
1247   let NumMicroOps = 3;
1248   let ResourceCycles = [1,1,1];
1249 }
1250 def: InstRW<[SBWriteResGroup36], (instregex "CALL64r")>;
1251 def: InstRW<[SBWriteResGroup36], (instregex "EXTRACTPSmr")>;
1252 def: InstRW<[SBWriteResGroup36], (instregex "VEXTRACTPSmr")>;
1253
1254 def SBWriteResGroup37 : SchedWriteRes<[SBPort4,SBPort01,SBPort23]> {
1255   let Latency = 5;
1256   let NumMicroOps = 3;
1257   let ResourceCycles = [1,1,1];
1258 }
1259 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPDYrm")>;
1260 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPDmr")>;
1261 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPSmr")>;
1262
1263 def SBWriteResGroup38 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> {
1264   let Latency = 5;
1265   let NumMicroOps = 3;
1266   let ResourceCycles = [1,1,1];
1267 }
1268 def: InstRW<[SBWriteResGroup38], (instregex "SETAEm")>;
1269 def: InstRW<[SBWriteResGroup38], (instregex "SETBm")>;
1270 def: InstRW<[SBWriteResGroup38], (instregex "SETEm")>;
1271 def: InstRW<[SBWriteResGroup38], (instregex "SETGEm")>;
1272 def: InstRW<[SBWriteResGroup38], (instregex "SETGm")>;
1273 def: InstRW<[SBWriteResGroup38], (instregex "SETLEm")>;
1274 def: InstRW<[SBWriteResGroup38], (instregex "SETLm")>;
1275 def: InstRW<[SBWriteResGroup38], (instregex "SETNEm")>;
1276 def: InstRW<[SBWriteResGroup38], (instregex "SETNOm")>;
1277 def: InstRW<[SBWriteResGroup38], (instregex "SETNPm")>;
1278 def: InstRW<[SBWriteResGroup38], (instregex "SETNSm")>;
1279 def: InstRW<[SBWriteResGroup38], (instregex "SETOm")>;
1280 def: InstRW<[SBWriteResGroup38], (instregex "SETPm")>;
1281 def: InstRW<[SBWriteResGroup38], (instregex "SETSm")>;
1282
1283 def SBWriteResGroup39 : SchedWriteRes<[SBPort4,SBPort23,SBPort15]> {
1284   let Latency = 5;
1285   let NumMicroOps = 3;
1286   let ResourceCycles = [1,1,1];
1287 }
1288 def: InstRW<[SBWriteResGroup39], (instregex "PEXTRBmr")>;
1289 def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRBmr")>;
1290 def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRDmr")>;
1291 def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRWmr")>;
1292
1293 def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
1294   let Latency = 5;
1295   let NumMicroOps = 3;
1296   let ResourceCycles = [1,1,1];
1297 }
1298 def: InstRW<[SBWriteResGroup40], (instregex "MOV8mi")>;
1299 def: InstRW<[SBWriteResGroup40], (instregex "STOSB")>;
1300 def: InstRW<[SBWriteResGroup40], (instregex "STOSL")>;
1301 def: InstRW<[SBWriteResGroup40], (instregex "STOSQ")>;
1302 def: InstRW<[SBWriteResGroup40], (instregex "STOSW")>;
1303
1304 def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> {
1305   let Latency = 5;
1306   let NumMicroOps = 4;
1307   let ResourceCycles = [1,3];
1308 }
1309 def: InstRW<[SBWriteResGroup41], (instregex "FNINIT")>;
1310
1311 def SBWriteResGroup42 : SchedWriteRes<[SBPort0,SBPort015]> {
1312   let Latency = 5;
1313   let NumMicroOps = 4;
1314   let ResourceCycles = [1,3];
1315 }
1316 def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG32rr")>;
1317 def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG8rr")>;
1318
1319 def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> {
1320   let Latency = 5;
1321   let NumMicroOps = 4;
1322   let ResourceCycles = [1,1,2];
1323 }
1324 def: InstRW<[SBWriteResGroup43], (instregex "SETAm")>;
1325 def: InstRW<[SBWriteResGroup43], (instregex "SETBEm")>;
1326
1327 def SBWriteResGroup44 : SchedWriteRes<[SBPort0,SBPort4,SBPort5,SBPort23]> {
1328   let Latency = 5;
1329   let NumMicroOps = 4;
1330   let ResourceCycles = [1,1,1,1];
1331 }
1332 def: InstRW<[SBWriteResGroup44], (instregex "LDMXCSR")>;
1333 def: InstRW<[SBWriteResGroup44], (instregex "STMXCSR")>;
1334 def: InstRW<[SBWriteResGroup44], (instregex "VLDMXCSR")>;
1335 def: InstRW<[SBWriteResGroup44], (instregex "VSTMXCSR")>;
1336
1337 def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
1338   let Latency = 5;
1339   let NumMicroOps = 4;
1340   let ResourceCycles = [1,1,1,1];
1341 }
1342 def: InstRW<[SBWriteResGroup45], (instregex "PEXTRDmr")>;
1343 def: InstRW<[SBWriteResGroup45], (instregex "PEXTRQmr")>;
1344 def: InstRW<[SBWriteResGroup45], (instregex "VPEXTRQmr")>;
1345 def: InstRW<[SBWriteResGroup45], (instregex "PUSHF16")>;
1346 def: InstRW<[SBWriteResGroup45], (instregex "PUSHF64")>;
1347
1348 def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
1349   let Latency = 5;
1350   let NumMicroOps = 4;
1351   let ResourceCycles = [1,1,1,1];
1352 }
1353 def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>;
1354
1355 def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
1356   let Latency = 5;
1357   let NumMicroOps = 5;
1358   let ResourceCycles = [1,2,1,1];
1359 }
1360 def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;
1361
1362 def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> {
1363   let Latency = 6;
1364   let NumMicroOps = 1;
1365   let ResourceCycles = [1];
1366 }
1367 def: InstRW<[SBWriteResGroup48], (instregex "LDDQUrm")>;
1368 def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm")>;
1369 def: InstRW<[SBWriteResGroup48], (instregex "MOV64toPQIrm")>;
1370 def: InstRW<[SBWriteResGroup48], (instregex "MOVAPDrm")>;
1371 def: InstRW<[SBWriteResGroup48], (instregex "MOVAPSrm")>;
1372 def: InstRW<[SBWriteResGroup48], (instregex "MOVDDUPrm")>;
1373 def: InstRW<[SBWriteResGroup48], (instregex "MOVDI2PDIrm")>;
1374 def: InstRW<[SBWriteResGroup48], (instregex "MOVDQArm")>;
1375 def: InstRW<[SBWriteResGroup48], (instregex "MOVDQUrm")>;
1376 def: InstRW<[SBWriteResGroup48], (instregex "MOVNTDQArm")>;
1377 def: InstRW<[SBWriteResGroup48], (instregex "MOVSHDUPrm")>;
1378 def: InstRW<[SBWriteResGroup48], (instregex "MOVSLDUPrm")>;
1379 def: InstRW<[SBWriteResGroup48], (instregex "MOVSSrm")>;
1380 def: InstRW<[SBWriteResGroup48], (instregex "MOVUPDrm")>;
1381 def: InstRW<[SBWriteResGroup48], (instregex "MOVUPSrm")>;
1382 def: InstRW<[SBWriteResGroup48], (instregex "POP64r")>;
1383 def: InstRW<[SBWriteResGroup48], (instregex "VBROADCASTSSrm")>;
1384 def: InstRW<[SBWriteResGroup48], (instregex "VLDDQUYrm")>;
1385 def: InstRW<[SBWriteResGroup48], (instregex "VLDDQUrm")>;
1386 def: InstRW<[SBWriteResGroup48], (instregex "VMOV64toPQIrm")>;
1387 def: InstRW<[SBWriteResGroup48], (instregex "VMOVAPDrm")>;
1388 def: InstRW<[SBWriteResGroup48], (instregex "VMOVAPSrm")>;
1389 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDDUPrm")>;
1390 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDI2PDIrm")>;
1391 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDQArm")>;
1392 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDQUrm")>;
1393 def: InstRW<[SBWriteResGroup48], (instregex "VMOVNTDQArm")>;
1394 def: InstRW<[SBWriteResGroup48], (instregex "VMOVQI2PQIrm")>;
1395 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSDrm")>;
1396 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSHDUPrm")>;
1397 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSLDUPrm")>;
1398 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSSrm")>;
1399 def: InstRW<[SBWriteResGroup48], (instregex "VMOVUPDrm")>;
1400 def: InstRW<[SBWriteResGroup48], (instregex "VMOVUPSrm")>;
1401
1402 def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
1403   let Latency = 6;
1404   let NumMicroOps = 2;
1405   let ResourceCycles = [1,1];
1406 }
1407 def: InstRW<[SBWriteResGroup49], (instregex "JMP64m")>;
1408 def: InstRW<[SBWriteResGroup49], (instregex "MOV64sm")>;
1409
1410 def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort0]> {
1411   let Latency = 6;
1412   let NumMicroOps = 2;
1413   let ResourceCycles = [1,1];
1414 }
1415 def: InstRW<[SBWriteResGroup50], (instregex "BT64mi8")>;
1416
1417 def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
1418   let Latency = 6;
1419   let NumMicroOps = 2;
1420   let ResourceCycles = [1,1];
1421 }
1422 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSBrm64")>;
1423 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSDrm64")>;
1424 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSWrm64")>;
1425 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PALIGNR64irm")>;
1426 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSHUFBrm64")>;
1427 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNBrm64")>;
1428 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNDrm64")>;
1429 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNWrm64")>;
1430
1431 def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
1432   let Latency = 6;
1433   let NumMicroOps = 2;
1434   let ResourceCycles = [1,1];
1435 }
1436 def: InstRW<[SBWriteResGroup52], (instregex "ADD64rm")>;
1437 def: InstRW<[SBWriteResGroup52], (instregex "ADD8rm")>;
1438 def: InstRW<[SBWriteResGroup52], (instregex "AND64rm")>;
1439 def: InstRW<[SBWriteResGroup52], (instregex "AND8rm")>;
1440 def: InstRW<[SBWriteResGroup52], (instregex "CMP64mi8")>;
1441 def: InstRW<[SBWriteResGroup52], (instregex "CMP64mr")>;
1442 def: InstRW<[SBWriteResGroup52], (instregex "CMP64rm")>;
1443 def: InstRW<[SBWriteResGroup52], (instregex "CMP8mi")>;
1444 def: InstRW<[SBWriteResGroup52], (instregex "CMP8mr")>;
1445 def: InstRW<[SBWriteResGroup52], (instregex "CMP8rm")>;
1446 def: InstRW<[SBWriteResGroup52], (instregex "LODSL")>;
1447 def: InstRW<[SBWriteResGroup52], (instregex "LODSQ")>;
1448 def: InstRW<[SBWriteResGroup52], (instregex "OR64rm")>;
1449 def: InstRW<[SBWriteResGroup52], (instregex "OR8rm")>;
1450 def: InstRW<[SBWriteResGroup52], (instregex "SUB64rm")>;
1451 def: InstRW<[SBWriteResGroup52], (instregex "SUB8rm")>;
1452 def: InstRW<[SBWriteResGroup52], (instregex "XOR64rm")>;
1453 def: InstRW<[SBWriteResGroup52], (instregex "XOR8rm")>;
1454
1455 def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> {
1456   let Latency = 6;
1457   let NumMicroOps = 3;
1458   let ResourceCycles = [1,2];
1459 }
1460 def: InstRW<[SBWriteResGroup53], (instregex "POP64rmm")>;
1461 def: InstRW<[SBWriteResGroup53], (instregex "PUSH64rmm")>;
1462 def: InstRW<[SBWriteResGroup53], (instregex "ST_F32m")>;
1463 def: InstRW<[SBWriteResGroup53], (instregex "ST_F64m")>;
1464 def: InstRW<[SBWriteResGroup53], (instregex "ST_FP32m")>;
1465 def: InstRW<[SBWriteResGroup53], (instregex "ST_FP64m")>;
1466 def: InstRW<[SBWriteResGroup53], (instregex "ST_FP80m")>;
1467
1468 def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> {
1469   let Latency = 7;
1470   let NumMicroOps = 1;
1471   let ResourceCycles = [1];
1472 }
1473 def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSDYrm")>;
1474 def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSSrm")>;
1475 def: InstRW<[SBWriteResGroup54], (instregex "VMOVAPDYrm")>;
1476 def: InstRW<[SBWriteResGroup54], (instregex "VMOVAPSYrm")>;
1477 def: InstRW<[SBWriteResGroup54], (instregex "VMOVDDUPYrm")>;
1478 def: InstRW<[SBWriteResGroup54], (instregex "VMOVDQAYrm")>;
1479 def: InstRW<[SBWriteResGroup54], (instregex "VMOVDQUYrm")>;
1480 def: InstRW<[SBWriteResGroup54], (instregex "VMOVSHDUPYrm")>;
1481 def: InstRW<[SBWriteResGroup54], (instregex "VMOVSLDUPYrm")>;
1482 def: InstRW<[SBWriteResGroup54], (instregex "VMOVUPDYrm")>;
1483 def: InstRW<[SBWriteResGroup54], (instregex "VMOVUPSYrm")>;
1484
1485 def SBWriteResGroup55 : SchedWriteRes<[SBPort0,SBPort23]> {
1486   let Latency = 7;
1487   let NumMicroOps = 2;
1488   let ResourceCycles = [1,1];
1489 }
1490 def: InstRW<[SBWriteResGroup55], (instregex "CVTPS2PDrm")>;
1491 def: InstRW<[SBWriteResGroup55], (instregex "CVTSS2SDrm")>;
1492 def: InstRW<[SBWriteResGroup55], (instregex "VCVTPS2PDYrm")>;
1493 def: InstRW<[SBWriteResGroup55], (instregex "VCVTPS2PDrm")>;
1494 def: InstRW<[SBWriteResGroup55], (instregex "VCVTSS2SDrm")>;
1495 def: InstRW<[SBWriteResGroup55], (instregex "VTESTPDrm")>;
1496 def: InstRW<[SBWriteResGroup55], (instregex "VTESTPSrm")>;
1497
1498 def SBWriteResGroup56 : SchedWriteRes<[SBPort5,SBPort23]> {
1499   let Latency = 7;
1500   let NumMicroOps = 2;
1501   let ResourceCycles = [1,1];
1502 }
1503 def: InstRW<[SBWriteResGroup56], (instregex "ANDNPDrm")>;
1504 def: InstRW<[SBWriteResGroup56], (instregex "ANDNPSrm")>;
1505 def: InstRW<[SBWriteResGroup56], (instregex "ANDPDrm")>;
1506 def: InstRW<[SBWriteResGroup56], (instregex "ANDPSrm")>;
1507 def: InstRW<[SBWriteResGroup56], (instregex "INSERTPSrm")>;
1508 def: InstRW<[SBWriteResGroup56], (instregex "MOVHPDrm")>;
1509 def: InstRW<[SBWriteResGroup56], (instregex "MOVHPSrm")>;
1510 def: InstRW<[SBWriteResGroup56], (instregex "MOVLPDrm")>;
1511 def: InstRW<[SBWriteResGroup56], (instregex "MOVLPSrm")>;
1512 def: InstRW<[SBWriteResGroup56], (instregex "ORPDrm")>;
1513 def: InstRW<[SBWriteResGroup56], (instregex "ORPSrm")>;
1514 def: InstRW<[SBWriteResGroup56], (instregex "SHUFPDrmi")>;
1515 def: InstRW<[SBWriteResGroup56], (instregex "SHUFPSrmi")>;
1516 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKHPDrm")>;
1517 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKHPSrm")>;
1518 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKLPDrm")>;
1519 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKLPSrm")>;
1520 def: InstRW<[SBWriteResGroup56], (instregex "VANDNPDrm")>;
1521 def: InstRW<[SBWriteResGroup56], (instregex "VANDNPSrm")>;
1522 def: InstRW<[SBWriteResGroup56], (instregex "VANDPDrm")>;
1523 def: InstRW<[SBWriteResGroup56], (instregex "VANDPSrm")>;
1524 def: InstRW<[SBWriteResGroup56], (instregex "VBROADCASTF128")>;
1525 def: InstRW<[SBWriteResGroup56], (instregex "VINSERTPSrm")>;
1526 def: InstRW<[SBWriteResGroup56], (instregex "VMOVHPDrm")>;
1527 def: InstRW<[SBWriteResGroup56], (instregex "VMOVHPSrm")>;
1528 def: InstRW<[SBWriteResGroup56], (instregex "VMOVLPDrm")>;
1529 def: InstRW<[SBWriteResGroup56], (instregex "VMOVLPSrm")>;
1530 def: InstRW<[SBWriteResGroup56], (instregex "VORPDrm")>;
1531 def: InstRW<[SBWriteResGroup56], (instregex "VORPSrm")>;
1532 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPDmi")>;
1533 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPDri")>;
1534 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPSmi")>;
1535 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPSri")>;
1536 def: InstRW<[SBWriteResGroup56], (instregex "VSHUFPDrmi")>;
1537 def: InstRW<[SBWriteResGroup56], (instregex "VSHUFPSrmi")>;
1538 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKHPDrm")>;
1539 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKHPSrm")>;
1540 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKLPDrm")>;
1541 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKLPSrm")>;
1542 def: InstRW<[SBWriteResGroup56], (instregex "VXORPDrm")>;
1543 def: InstRW<[SBWriteResGroup56], (instregex "VXORPSrm")>;
1544 def: InstRW<[SBWriteResGroup56], (instregex "XORPDrm")>;
1545 def: InstRW<[SBWriteResGroup56], (instregex "XORPSrm")>;
1546
1547 def SBWriteResGroup57 : SchedWriteRes<[SBPort5,SBPort015]> {
1548   let Latency = 7;
1549   let NumMicroOps = 2;
1550   let ResourceCycles = [1,1];
1551 }
1552 def: InstRW<[SBWriteResGroup57], (instregex "AESDECLASTrr")>;
1553 def: InstRW<[SBWriteResGroup57], (instregex "AESDECrr")>;
1554 def: InstRW<[SBWriteResGroup57], (instregex "AESENCLASTrr")>;
1555 def: InstRW<[SBWriteResGroup57], (instregex "AESENCrr")>;
1556 def: InstRW<[SBWriteResGroup57], (instregex "KANDQrr")>;
1557 def: InstRW<[SBWriteResGroup57], (instregex "VAESDECLASTrr")>;
1558 def: InstRW<[SBWriteResGroup57], (instregex "VAESDECrr")>;
1559 def: InstRW<[SBWriteResGroup57], (instregex "VAESENCrr")>;
1560
1561 def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort0]> {
1562   let Latency = 7;
1563   let NumMicroOps = 2;
1564   let ResourceCycles = [1,1];
1565 }
1566 def: InstRW<[SBWriteResGroup58], (instregex "BLENDPDrmi")>;
1567 def: InstRW<[SBWriteResGroup58], (instregex "BLENDPSrmi")>;
1568 def: InstRW<[SBWriteResGroup58], (instregex "VBLENDPDrmi")>;
1569 def: InstRW<[SBWriteResGroup58], (instregex "VBLENDPSrmi")>;
1570 def: InstRW<[SBWriteResGroup58], (instregex "VINSERTF128rm")>;
1571
1572 def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> {
1573   let Latency = 7;
1574   let NumMicroOps = 2;
1575   let ResourceCycles = [1,1];
1576 }
1577 def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm")>;
1578 def: InstRW<[SBWriteResGroup59], (instregex "PABSBrm")>;
1579 def: InstRW<[SBWriteResGroup59], (instregex "PABSDrm")>;
1580 def: InstRW<[SBWriteResGroup59], (instregex "PABSWrm")>;
1581 def: InstRW<[SBWriteResGroup59], (instregex "PACKSSDWrm")>;
1582 def: InstRW<[SBWriteResGroup59], (instregex "PACKSSWBrm")>;
1583 def: InstRW<[SBWriteResGroup59], (instregex "PACKUSDWrm")>;
1584 def: InstRW<[SBWriteResGroup59], (instregex "PACKUSWBrm")>;
1585 def: InstRW<[SBWriteResGroup59], (instregex "PADDBrm")>;
1586 def: InstRW<[SBWriteResGroup59], (instregex "PADDDrm")>;
1587 def: InstRW<[SBWriteResGroup59], (instregex "PADDQrm")>;
1588 def: InstRW<[SBWriteResGroup59], (instregex "PADDSBrm")>;
1589 def: InstRW<[SBWriteResGroup59], (instregex "PADDSWrm")>;
1590 def: InstRW<[SBWriteResGroup59], (instregex "PADDUSBrm")>;
1591 def: InstRW<[SBWriteResGroup59], (instregex "PADDUSWrm")>;
1592 def: InstRW<[SBWriteResGroup59], (instregex "PADDWrm")>;
1593 def: InstRW<[SBWriteResGroup59], (instregex "PALIGNRrmi")>;
1594 def: InstRW<[SBWriteResGroup59], (instregex "PAVGBrm")>;
1595 def: InstRW<[SBWriteResGroup59], (instregex "PAVGWrm")>;
1596 def: InstRW<[SBWriteResGroup59], (instregex "PBLENDWrmi")>;
1597 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQBrm")>;
1598 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQDrm")>;
1599 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQQrm")>;
1600 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQWrm")>;
1601 def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTBrm")>;
1602 def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTDrm")>;
1603 def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTWrm")>;
1604 def: InstRW<[SBWriteResGroup59], (instregex "PINSRBrm")>;
1605 def: InstRW<[SBWriteResGroup59], (instregex "PINSRDrm")>;
1606 def: InstRW<[SBWriteResGroup59], (instregex "PINSRQrm")>;
1607 def: InstRW<[SBWriteResGroup59], (instregex "PINSRWrmi")>;
1608 def: InstRW<[SBWriteResGroup59], (instregex "PMAXSBrm")>;
1609 def: InstRW<[SBWriteResGroup59], (instregex "PMAXSDrm")>;
1610 def: InstRW<[SBWriteResGroup59], (instregex "PMAXSWrm")>;
1611 def: InstRW<[SBWriteResGroup59], (instregex "PMAXUBrm")>;
1612 def: InstRW<[SBWriteResGroup59], (instregex "PMAXUDrm")>;
1613 def: InstRW<[SBWriteResGroup59], (instregex "PMAXUWrm")>;
1614 def: InstRW<[SBWriteResGroup59], (instregex "PMINSBrm")>;
1615 def: InstRW<[SBWriteResGroup59], (instregex "PMINSDrm")>;
1616 def: InstRW<[SBWriteResGroup59], (instregex "PMINSWrm")>;
1617 def: InstRW<[SBWriteResGroup59], (instregex "PMINUBrm")>;
1618 def: InstRW<[SBWriteResGroup59], (instregex "PMINUDrm")>;
1619 def: InstRW<[SBWriteResGroup59], (instregex "PMINUWrm")>;
1620 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBDrm")>;
1621 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBQrm")>;
1622 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBWrm")>;
1623 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXDQrm")>;
1624 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXWDrm")>;
1625 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXWQrm")>;
1626 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBDrm")>;
1627 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBQrm")>;
1628 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBWrm")>;
1629 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXDQrm")>;
1630 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXWDrm")>;
1631 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXWQrm")>;
1632 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFBrm")>;
1633 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFDmi")>;
1634 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFHWmi")>;
1635 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFLWmi")>;
1636 def: InstRW<[SBWriteResGroup59], (instregex "PSIGNBrm128")>;
1637 def: InstRW<[SBWriteResGroup59], (instregex "PSIGNDrm128")>;
1638 def: InstRW<[SBWriteResGroup59], (instregex "PSIGNWrm128")>;
1639 def: InstRW<[SBWriteResGroup59], (instregex "PSUBBrm")>;
1640 def: InstRW<[SBWriteResGroup59], (instregex "PSUBDrm")>;
1641 def: InstRW<[SBWriteResGroup59], (instregex "PSUBQrm")>;
1642 def: InstRW<[SBWriteResGroup59], (instregex "PSUBSBrm")>;
1643 def: InstRW<[SBWriteResGroup59], (instregex "PSUBSWrm")>;
1644 def: InstRW<[SBWriteResGroup59], (instregex "PSUBUSBrm")>;
1645 def: InstRW<[SBWriteResGroup59], (instregex "PSUBUSWrm")>;
1646 def: InstRW<[SBWriteResGroup59], (instregex "PSUBWrm")>;
1647 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHBWrm")>;
1648 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHDQrm")>;
1649 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHQDQrm")>;
1650 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHWDrm")>;
1651 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLBWrm")>;
1652 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLDQrm")>;
1653 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLQDQrm")>;
1654 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLWDrm")>;
1655 def: InstRW<[SBWriteResGroup59], (instregex "VPABSBrm")>;
1656 def: InstRW<[SBWriteResGroup59], (instregex "VPABSDrm")>;
1657 def: InstRW<[SBWriteResGroup59], (instregex "VPABSWrm")>;
1658 def: InstRW<[SBWriteResGroup59], (instregex "VPACKSSDWrm")>;
1659 def: InstRW<[SBWriteResGroup59], (instregex "VPACKSSWBrm")>;
1660 def: InstRW<[SBWriteResGroup59], (instregex "VPACKUSDWrm")>;
1661 def: InstRW<[SBWriteResGroup59], (instregex "VPACKUSWBrm")>;
1662 def: InstRW<[SBWriteResGroup59], (instregex "VPADDBrm")>;
1663 def: InstRW<[SBWriteResGroup59], (instregex "VPADDDrm")>;
1664 def: InstRW<[SBWriteResGroup59], (instregex "VPADDQrm")>;
1665 def: InstRW<[SBWriteResGroup59], (instregex "VPADDSBrm")>;
1666 def: InstRW<[SBWriteResGroup59], (instregex "VPADDSWrm")>;
1667 def: InstRW<[SBWriteResGroup59], (instregex "VPADDUSBrm")>;
1668 def: InstRW<[SBWriteResGroup59], (instregex "VPADDUSWrm")>;
1669 def: InstRW<[SBWriteResGroup59], (instregex "VPADDWrm")>;
1670 def: InstRW<[SBWriteResGroup59], (instregex "VPALIGNRrmi")>;
1671 def: InstRW<[SBWriteResGroup59], (instregex "VPAVGBrm")>;
1672 def: InstRW<[SBWriteResGroup59], (instregex "VPAVGWrm")>;
1673 def: InstRW<[SBWriteResGroup59], (instregex "VPBLENDWrmi")>;
1674 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQBrm")>;
1675 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQDrm")>;
1676 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQQrm")>;
1677 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQWrm")>;
1678 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTBrm")>;
1679 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTDrm")>;
1680 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTWrm")>;
1681 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRBrm")>;
1682 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRDrm")>;
1683 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRQrm")>;
1684 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRWrmi")>;
1685 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSBrm")>;
1686 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSDrm")>;
1687 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSWrm")>;
1688 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUBrm")>;
1689 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUDrm")>;
1690 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUWrm")>;
1691 def: InstRW<[SBWriteResGroup59], (instregex "VPMINSBrm")>;
1692 def: InstRW<[SBWriteResGroup59], (instregex "VPMINSDrm")>;
1693 def: InstRW<[SBWriteResGroup59], (instregex "VPMINSWrm")>;
1694 def: InstRW<[SBWriteResGroup59], (instregex "VPMINUBrm")>;
1695 def: InstRW<[SBWriteResGroup59], (instregex "VPMINUDrm")>;
1696 def: InstRW<[SBWriteResGroup59], (instregex "VPMINUWrm")>;
1697 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBDrm")>;
1698 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBQrm")>;
1699 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBWrm")>;
1700 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXDQrm")>;
1701 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXWDrm")>;
1702 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXWQrm")>;
1703 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBDrm")>;
1704 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBQrm")>;
1705 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBWrm")>;
1706 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXDQrm")>;
1707 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXWDrm")>;
1708 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXWQrm")>;
1709 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFBrm")>;
1710 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFDmi")>;
1711 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFHWmi")>;
1712 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFLWmi")>;
1713 def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNBrm128")>;
1714 def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNDrm128")>;
1715 def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNWrm128")>;
1716 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBBrm")>;
1717 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBDrm")>;
1718 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBQrm")>;
1719 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBSBrm")>;
1720 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBSWrm")>;
1721 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBUSBrm")>;
1722 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBUSWrm")>;
1723 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBWrm")>;
1724 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHBWrm")>;
1725 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHDQrm")>;
1726 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHQDQrm")>;
1727 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHWDrm")>;
1728 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLBWrm")>;
1729 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLDQrm")>;
1730 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLQDQrm")>;
1731 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLWDrm")>;
1732
1733 def SBWriteResGroup60 : SchedWriteRes<[SBPort23,SBPort015]> {
1734   let Latency = 7;
1735   let NumMicroOps = 2;
1736   let ResourceCycles = [1,1];
1737 }
1738 def: InstRW<[SBWriteResGroup60], (instregex "PANDNrm")>;
1739 def: InstRW<[SBWriteResGroup60], (instregex "PANDrm")>;
1740 def: InstRW<[SBWriteResGroup60], (instregex "PORrm")>;
1741 def: InstRW<[SBWriteResGroup60], (instregex "PXORrm")>;
1742 def: InstRW<[SBWriteResGroup60], (instregex "VPANDNrm")>;
1743 def: InstRW<[SBWriteResGroup60], (instregex "VPANDrm")>;
1744 def: InstRW<[SBWriteResGroup60], (instregex "VPORrm")>;
1745 def: InstRW<[SBWriteResGroup60], (instregex "VPXORrm")>;
1746
1747 def SBWriteResGroup61 : SchedWriteRes<[SBPort0,SBPort0]> {
1748   let Latency = 7;
1749   let NumMicroOps = 3;
1750   let ResourceCycles = [2,1];
1751 }
1752 def: InstRW<[SBWriteResGroup61], (instregex "VRCPPSr")>;
1753 def: InstRW<[SBWriteResGroup61], (instregex "VRSQRTPSYr")>;
1754
1755 def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> {
1756   let Latency = 7;
1757   let NumMicroOps = 3;
1758   let ResourceCycles = [2,1];
1759 }
1760 def: InstRW<[SBWriteResGroup62], (instregex "VERRm")>;
1761 def: InstRW<[SBWriteResGroup62], (instregex "VERWm")>;
1762
1763 def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> {
1764   let Latency = 7;
1765   let NumMicroOps = 3;
1766   let ResourceCycles = [1,2];
1767 }
1768 def: InstRW<[SBWriteResGroup63], (instregex "LODSB")>;
1769 def: InstRW<[SBWriteResGroup63], (instregex "LODSW")>;
1770
1771 def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
1772   let Latency = 7;
1773   let NumMicroOps = 3;
1774   let ResourceCycles = [1,1,1];
1775 }
1776 def: InstRW<[SBWriteResGroup64], (instregex "FARJMP64")>;
1777
1778 def SBWriteResGroup65 : SchedWriteRes<[SBPort23,SBPort0,SBPort015]> {
1779   let Latency = 7;
1780   let NumMicroOps = 3;
1781   let ResourceCycles = [1,1,1];
1782 }
1783 def: InstRW<[SBWriteResGroup65], (instregex "ADC64rm")>;
1784 def: InstRW<[SBWriteResGroup65], (instregex "ADC8rm")>;
1785 def: InstRW<[SBWriteResGroup65], (instregex "CMOVAE64rm")>;
1786 def: InstRW<[SBWriteResGroup65], (instregex "CMOVB64rm")>;
1787 def: InstRW<[SBWriteResGroup65], (instregex "CMOVE64rm")>;
1788 def: InstRW<[SBWriteResGroup65], (instregex "CMOVG64rm")>;
1789 def: InstRW<[SBWriteResGroup65], (instregex "CMOVGE64rm")>;
1790 def: InstRW<[SBWriteResGroup65], (instregex "CMOVL64rm")>;
1791 def: InstRW<[SBWriteResGroup65], (instregex "CMOVLE64rm")>;
1792 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNE64rm")>;
1793 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNO64rm")>;
1794 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNP64rm")>;
1795 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNS64rm")>;
1796 def: InstRW<[SBWriteResGroup65], (instregex "CMOVO64rm")>;
1797 def: InstRW<[SBWriteResGroup65], (instregex "CMOVP64rm")>;
1798 def: InstRW<[SBWriteResGroup65], (instregex "CMOVS64rm")>;
1799 def: InstRW<[SBWriteResGroup65], (instregex "SBB64rm")>;
1800 def: InstRW<[SBWriteResGroup65], (instregex "SBB8rm")>;
1801
1802 def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
1803   let Latency = 7;
1804   let NumMicroOps = 4;
1805   let ResourceCycles = [1,1,2];
1806 }
1807 def: InstRW<[SBWriteResGroup66], (instregex "FNSTSWm")>;
1808
1809 def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
1810   let Latency = 7;
1811   let NumMicroOps = 4;
1812   let ResourceCycles = [1,2,1];
1813 }
1814 def: InstRW<[SBWriteResGroup67], (instregex "SLDT32r")>;
1815 def: InstRW<[SBWriteResGroup67], (instregex "STR32r")>;
1816
1817 def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
1818   let Latency = 7;
1819   let NumMicroOps = 4;
1820   let ResourceCycles = [1,1,2];
1821 }
1822 def: InstRW<[SBWriteResGroup68], (instregex "CALL64m")>;
1823 def: InstRW<[SBWriteResGroup68], (instregex "FNSTCW16m")>;
1824
1825 def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> {
1826   let Latency = 7;
1827   let NumMicroOps = 4;
1828   let ResourceCycles = [1,2,1];
1829 }
1830 def: InstRW<[SBWriteResGroup69], (instregex "BTC64mi8")>;
1831 def: InstRW<[SBWriteResGroup69], (instregex "BTR64mi8")>;
1832 def: InstRW<[SBWriteResGroup69], (instregex "BTS64mi8")>;
1833 def: InstRW<[SBWriteResGroup69], (instregex "SAR64mi")>;
1834 def: InstRW<[SBWriteResGroup69], (instregex "SAR8mi")>;
1835 def: InstRW<[SBWriteResGroup69], (instregex "SHL64m1")>;
1836 def: InstRW<[SBWriteResGroup69], (instregex "SHL64mi")>;
1837 def: InstRW<[SBWriteResGroup69], (instregex "SHL8m1")>;
1838 def: InstRW<[SBWriteResGroup69], (instregex "SHL8mi")>;
1839 def: InstRW<[SBWriteResGroup69], (instregex "SHR64mi")>;
1840 def: InstRW<[SBWriteResGroup69], (instregex "SHR8mi")>;
1841
1842 def SBWriteResGroup70 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
1843   let Latency = 7;
1844   let NumMicroOps = 4;
1845   let ResourceCycles = [1,2,1];
1846 }
1847 def: InstRW<[SBWriteResGroup70], (instregex "ADD64mi8")>;
1848 def: InstRW<[SBWriteResGroup70], (instregex "ADD64mr")>;
1849 def: InstRW<[SBWriteResGroup70], (instregex "ADD8mi")>;
1850 def: InstRW<[SBWriteResGroup70], (instregex "ADD8mr")>;
1851 def: InstRW<[SBWriteResGroup70], (instregex "AND64mi8")>;
1852 def: InstRW<[SBWriteResGroup70], (instregex "AND64mr")>;
1853 def: InstRW<[SBWriteResGroup70], (instregex "AND8mi")>;
1854 def: InstRW<[SBWriteResGroup70], (instregex "AND8mr")>;
1855 def: InstRW<[SBWriteResGroup70], (instregex "DEC64m")>;
1856 def: InstRW<[SBWriteResGroup70], (instregex "DEC8m")>;
1857 def: InstRW<[SBWriteResGroup70], (instregex "INC64m")>;
1858 def: InstRW<[SBWriteResGroup70], (instregex "INC8m")>;
1859 def: InstRW<[SBWriteResGroup70], (instregex "NEG64m")>;
1860 def: InstRW<[SBWriteResGroup70], (instregex "NEG8m")>;
1861 def: InstRW<[SBWriteResGroup70], (instregex "NOT64m")>;
1862 def: InstRW<[SBWriteResGroup70], (instregex "NOT8m")>;
1863 def: InstRW<[SBWriteResGroup70], (instregex "OR64mi8")>;
1864 def: InstRW<[SBWriteResGroup70], (instregex "OR64mr")>;
1865 def: InstRW<[SBWriteResGroup70], (instregex "OR8mi")>;
1866 def: InstRW<[SBWriteResGroup70], (instregex "OR8mr")>;
1867 def: InstRW<[SBWriteResGroup70], (instregex "SUB64mi8")>;
1868 def: InstRW<[SBWriteResGroup70], (instregex "SUB64mr")>;
1869 def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>;
1870 def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>;
1871 def: InstRW<[SBWriteResGroup70], (instregex "TEST64rm")>;
1872 def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>;
1873 def: InstRW<[SBWriteResGroup70], (instregex "TEST8rm")>;
1874 def: InstRW<[SBWriteResGroup70], (instregex "XOR64mi8")>;
1875 def: InstRW<[SBWriteResGroup70], (instregex "XOR64mr")>;
1876 def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>;
1877 def: InstRW<[SBWriteResGroup70], (instregex "XOR8mr")>;
1878
1879 def SBWriteResGroup71 : SchedWriteRes<[SBPort0,SBPort23]> {
1880   let Latency = 8;
1881   let NumMicroOps = 2;
1882   let ResourceCycles = [1,1];
1883 }
1884 def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMADDUBSWrm64")>;
1885 def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMULHRSWrm64")>;
1886 def: InstRW<[SBWriteResGroup71], (instregex "VTESTPDYrm")>;
1887 def: InstRW<[SBWriteResGroup71], (instregex "VTESTPSYrm")>;
1888
1889 def SBWriteResGroup72 : SchedWriteRes<[SBPort1,SBPort23]> {
1890   let Latency = 8;
1891   let NumMicroOps = 2;
1892   let ResourceCycles = [1,1];
1893 }
1894 def: InstRW<[SBWriteResGroup72], (instregex "BSF64rm")>;
1895 def: InstRW<[SBWriteResGroup72], (instregex "BSR64rm")>;
1896 def: InstRW<[SBWriteResGroup72], (instregex "CRC32r32m16")>;
1897 def: InstRW<[SBWriteResGroup72], (instregex "CRC32r32m8")>;
1898 def: InstRW<[SBWriteResGroup72], (instregex "FCOM32m")>;
1899 def: InstRW<[SBWriteResGroup72], (instregex "FCOM64m")>;
1900 def: InstRW<[SBWriteResGroup72], (instregex "FCOMP32m")>;
1901 def: InstRW<[SBWriteResGroup72], (instregex "FCOMP64m")>;
1902 def: InstRW<[SBWriteResGroup72], (instregex "MUL8m")>;
1903
1904 def SBWriteResGroup73 : SchedWriteRes<[SBPort5,SBPort23]> {
1905   let Latency = 8;
1906   let NumMicroOps = 2;
1907   let ResourceCycles = [1,1];
1908 }
1909 def: InstRW<[SBWriteResGroup73], (instregex "VANDNPDYrm")>;
1910 def: InstRW<[SBWriteResGroup73], (instregex "VANDNPSYrm")>;
1911 def: InstRW<[SBWriteResGroup73], (instregex "VANDPDrm")>;
1912 def: InstRW<[SBWriteResGroup73], (instregex "VANDPSrm")>;
1913 def: InstRW<[SBWriteResGroup73], (instregex "VORPDYrm")>;
1914 def: InstRW<[SBWriteResGroup73], (instregex "VORPSYrm")>;
1915 def: InstRW<[SBWriteResGroup73], (instregex "VPERM2F128rm")>;
1916 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPDYri")>;
1917 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPDmi")>;
1918 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPSYri")>;
1919 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPSmi")>;
1920 def: InstRW<[SBWriteResGroup73], (instregex "VSHUFPDYrmi")>;
1921 def: InstRW<[SBWriteResGroup73], (instregex "VSHUFPSYrmi")>;
1922 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKHPDrm")>;
1923 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKHPSrm")>;
1924 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKLPDYrm")>;
1925 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKLPSYrm")>;
1926 def: InstRW<[SBWriteResGroup73], (instregex "VXORPDrm")>;
1927 def: InstRW<[SBWriteResGroup73], (instregex "VXORPSrm")>;
1928
1929 def SBWriteResGroup74 : SchedWriteRes<[SBPort23,SBPort0]> {
1930   let Latency = 8;
1931   let NumMicroOps = 2;
1932   let ResourceCycles = [1,1];
1933 }
1934 def: InstRW<[SBWriteResGroup74], (instregex "VBLENDPDYrmi")>;
1935 def: InstRW<[SBWriteResGroup74], (instregex "VBLENDPSYrmi")>;
1936
1937 def SBWriteResGroup75 : SchedWriteRes<[SBPort23,SBPort0]> {
1938   let Latency = 8;
1939   let NumMicroOps = 3;
1940   let ResourceCycles = [1,2];
1941 }
1942 def: InstRW<[SBWriteResGroup75], (instregex "BLENDVPDrm0")>;
1943 def: InstRW<[SBWriteResGroup75], (instregex "BLENDVPSrm0")>;
1944 def: InstRW<[SBWriteResGroup75], (instregex "VBLENDVPDrm")>;
1945 def: InstRW<[SBWriteResGroup75], (instregex "VBLENDVPSrm")>;
1946 def: InstRW<[SBWriteResGroup75], (instregex "VMASKMOVPDrm")>;
1947 def: InstRW<[SBWriteResGroup75], (instregex "VMASKMOVPSrm")>;
1948
1949 def SBWriteResGroup76 : SchedWriteRes<[SBPort23,SBPort15]> {
1950   let Latency = 8;
1951   let NumMicroOps = 3;
1952   let ResourceCycles = [1,2];
1953 }
1954 def: InstRW<[SBWriteResGroup76], (instregex "PBLENDVBrr0")>;
1955 def: InstRW<[SBWriteResGroup76], (instregex "VPBLENDVBrm")>;
1956
1957 def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
1958   let Latency = 8;
1959   let NumMicroOps = 3;
1960   let ResourceCycles = [1,1,1];
1961 }
1962 def: InstRW<[SBWriteResGroup77], (instregex "COMISDrm")>;
1963 def: InstRW<[SBWriteResGroup77], (instregex "COMISSrm")>;
1964 def: InstRW<[SBWriteResGroup77], (instregex "UCOMISDrm")>;
1965 def: InstRW<[SBWriteResGroup77], (instregex "UCOMISSrm")>;
1966 def: InstRW<[SBWriteResGroup77], (instregex "VCOMISDrm")>;
1967 def: InstRW<[SBWriteResGroup77], (instregex "VCOMISSrm")>;
1968 def: InstRW<[SBWriteResGroup77], (instregex "VUCOMISDrm")>;
1969 def: InstRW<[SBWriteResGroup77], (instregex "VUCOMISSrm")>;
1970
1971 def SBWriteResGroup78 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> {
1972   let Latency = 8;
1973   let NumMicroOps = 3;
1974   let ResourceCycles = [1,1,1];
1975 }
1976 def: InstRW<[SBWriteResGroup78], (instregex "PTESTrm")>;
1977 def: InstRW<[SBWriteResGroup78], (instregex "VPTESTrm")>;
1978
1979 def SBWriteResGroup79 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> {
1980   let Latency = 8;
1981   let NumMicroOps = 3;
1982   let ResourceCycles = [1,1,1];
1983 }
1984 def: InstRW<[SBWriteResGroup79], (instregex "PSLLDrm")>;
1985 def: InstRW<[SBWriteResGroup79], (instregex "PSLLQrm")>;
1986 def: InstRW<[SBWriteResGroup79], (instregex "PSLLWrm")>;
1987 def: InstRW<[SBWriteResGroup79], (instregex "PSRADrm")>;
1988 def: InstRW<[SBWriteResGroup79], (instregex "PSRAWrm")>;
1989 def: InstRW<[SBWriteResGroup79], (instregex "PSRLDrm")>;
1990 def: InstRW<[SBWriteResGroup79], (instregex "PSRLQrm")>;
1991 def: InstRW<[SBWriteResGroup79], (instregex "PSRLWrm")>;
1992 def: InstRW<[SBWriteResGroup79], (instregex "VPSLLDri")>;
1993 def: InstRW<[SBWriteResGroup79], (instregex "VPSLLQri")>;
1994 def: InstRW<[SBWriteResGroup79], (instregex "VPSLLWri")>;
1995 def: InstRW<[SBWriteResGroup79], (instregex "VPSRADrm")>;
1996 def: InstRW<[SBWriteResGroup79], (instregex "VPSRAWrm")>;
1997 def: InstRW<[SBWriteResGroup79], (instregex "VPSRLDrm")>;
1998 def: InstRW<[SBWriteResGroup79], (instregex "VPSRLQrm")>;
1999 def: InstRW<[SBWriteResGroup79], (instregex "VPSRLWrm")>;
2000
2001 def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort15]> {
2002   let Latency = 8;
2003   let NumMicroOps = 4;
2004   let ResourceCycles = [1,3];
2005 }
2006 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDSWrm64")>;
2007 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDWrm64")>;
2008 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDrm64")>;
2009 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBDrm64")>;
2010 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBSWrm64")>;
2011 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBWrm64")>;
2012
2013 def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> {
2014   let Latency = 8;
2015   let NumMicroOps = 4;
2016   let ResourceCycles = [1,3];
2017 }
2018 def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG64rm")>;
2019 def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG8rm")>;
2020
2021 def SBWriteResGroup82 : SchedWriteRes<[SBPort23,SBPort0,SBPort015]> {
2022   let Latency = 8;
2023   let NumMicroOps = 4;
2024   let ResourceCycles = [1,2,1];
2025 }
2026 def: InstRW<[SBWriteResGroup82], (instregex "CMOVA64rm")>;
2027 def: InstRW<[SBWriteResGroup82], (instregex "CMOVBE64rm")>;
2028
2029 def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> {
2030   let Latency = 8;
2031   let NumMicroOps = 5;
2032   let ResourceCycles = [2,3];
2033 }
2034 def: InstRW<[SBWriteResGroup83], (instregex "CMPSB")>;
2035 def: InstRW<[SBWriteResGroup83], (instregex "CMPSL")>;
2036 def: InstRW<[SBWriteResGroup83], (instregex "CMPSQ")>;
2037 def: InstRW<[SBWriteResGroup83], (instregex "CMPSW")>;
2038
2039 def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
2040   let Latency = 8;
2041   let NumMicroOps = 5;
2042   let ResourceCycles = [1,2,2];
2043 }
2044 def: InstRW<[SBWriteResGroup84], (instregex "FLDCW16m")>;
2045
2046 def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> {
2047   let Latency = 8;
2048   let NumMicroOps = 5;
2049   let ResourceCycles = [1,2,2];
2050 }
2051 def: InstRW<[SBWriteResGroup85], (instregex "ROL64mi")>;
2052 def: InstRW<[SBWriteResGroup85], (instregex "ROL8mi")>;
2053 def: InstRW<[SBWriteResGroup85], (instregex "ROR64mi")>;
2054 def: InstRW<[SBWriteResGroup85], (instregex "ROR8mi")>;
2055
2056 def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
2057   let Latency = 8;
2058   let NumMicroOps = 5;
2059   let ResourceCycles = [1,2,2];
2060 }
2061 def: InstRW<[SBWriteResGroup86], (instregex "MOVSB")>;
2062 def: InstRW<[SBWriteResGroup86], (instregex "MOVSL")>;
2063 def: InstRW<[SBWriteResGroup86], (instregex "MOVSQ")>;
2064 def: InstRW<[SBWriteResGroup86], (instregex "MOVSW")>;
2065 def: InstRW<[SBWriteResGroup86], (instregex "XADD64rm")>;
2066 def: InstRW<[SBWriteResGroup86], (instregex "XADD8rm")>;
2067
2068 def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
2069   let Latency = 8;
2070   let NumMicroOps = 5;
2071   let ResourceCycles = [1,1,1,2];
2072 }
2073 def: InstRW<[SBWriteResGroup87], (instregex "FARCALL64")>;
2074
2075 def SBWriteResGroup88 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
2076   let Latency = 8;
2077   let NumMicroOps = 5;
2078   let ResourceCycles = [1,2,1,1];
2079 }
2080 def: InstRW<[SBWriteResGroup88], (instregex "SHLD64mri8")>;
2081 def: InstRW<[SBWriteResGroup88], (instregex "SHRD64mri8")>;
2082
2083 def SBWriteResGroup89 : SchedWriteRes<[SBPort0,SBPort23]> {
2084   let Latency = 9;
2085   let NumMicroOps = 2;
2086   let ResourceCycles = [1,1];
2087 }
2088 def: InstRW<[SBWriteResGroup89], (instregex "MMX_PMULUDQirm")>;
2089 def: InstRW<[SBWriteResGroup89], (instregex "PMADDUBSWrm")>;
2090 def: InstRW<[SBWriteResGroup89], (instregex "PMADDWDrm")>;
2091 def: InstRW<[SBWriteResGroup89], (instregex "PMULDQrm")>;
2092 def: InstRW<[SBWriteResGroup89], (instregex "PMULHRSWrm")>;
2093 def: InstRW<[SBWriteResGroup89], (instregex "PMULHUWrm")>;
2094 def: InstRW<[SBWriteResGroup89], (instregex "PMULHWrm")>;
2095 def: InstRW<[SBWriteResGroup89], (instregex "PMULLDrm")>;
2096 def: InstRW<[SBWriteResGroup89], (instregex "PMULLWrm")>;
2097 def: InstRW<[SBWriteResGroup89], (instregex "PMULUDQrm")>;
2098 def: InstRW<[SBWriteResGroup89], (instregex "PSADBWrm")>;
2099 def: InstRW<[SBWriteResGroup89], (instregex "VPMADDUBSWrm")>;
2100 def: InstRW<[SBWriteResGroup89], (instregex "VPMADDWDrm")>;
2101 def: InstRW<[SBWriteResGroup89], (instregex "VPMULDQrm")>;
2102 def: InstRW<[SBWriteResGroup89], (instregex "VPMULHRSWrm")>;
2103 def: InstRW<[SBWriteResGroup89], (instregex "VPMULHUWrm")>;
2104 def: InstRW<[SBWriteResGroup89], (instregex "VPMULHWrm")>;
2105 def: InstRW<[SBWriteResGroup89], (instregex "VPMULLDrm")>;
2106 def: InstRW<[SBWriteResGroup89], (instregex "VPMULLWrm")>;
2107 def: InstRW<[SBWriteResGroup89], (instregex "VPMULUDQrm")>;
2108 def: InstRW<[SBWriteResGroup89], (instregex "VPSADBWrm")>;
2109
2110 def SBWriteResGroup90 : SchedWriteRes<[SBPort1,SBPort23]> {
2111   let Latency = 9;
2112   let NumMicroOps = 2;
2113   let ResourceCycles = [1,1];
2114 }
2115 def: InstRW<[SBWriteResGroup90], (instregex "ADDPDrm")>;
2116 def: InstRW<[SBWriteResGroup90], (instregex "ADDPSrm")>;
2117 def: InstRW<[SBWriteResGroup90], (instregex "ADDSDrm")>;
2118 def: InstRW<[SBWriteResGroup90], (instregex "ADDSSrm")>;
2119 def: InstRW<[SBWriteResGroup90], (instregex "ADDSUBPDrm")>;
2120 def: InstRW<[SBWriteResGroup90], (instregex "ADDSUBPSrm")>;
2121 def: InstRW<[SBWriteResGroup90], (instregex "CMPPDrmi")>;
2122 def: InstRW<[SBWriteResGroup90], (instregex "CMPPSrmi")>;
2123 def: InstRW<[SBWriteResGroup90], (instregex "CMPSSrm")>;
2124 def: InstRW<[SBWriteResGroup90], (instregex "CVTDQ2PSrm")>;
2125 def: InstRW<[SBWriteResGroup90], (instregex "CVTPS2DQrm")>;
2126 def: InstRW<[SBWriteResGroup90], (instregex "CVTSI2SD64rm")>;
2127 def: InstRW<[SBWriteResGroup90], (instregex "CVTSI2SDrm")>;
2128 def: InstRW<[SBWriteResGroup90], (instregex "CVTTPS2DQrm")>;
2129 def: InstRW<[SBWriteResGroup90], (instregex "MAXPDrm")>;
2130 def: InstRW<[SBWriteResGroup90], (instregex "MAXPSrm")>;
2131 def: InstRW<[SBWriteResGroup90], (instregex "MAXSDrm")>;
2132 def: InstRW<[SBWriteResGroup90], (instregex "MAXSSrm")>;
2133 def: InstRW<[SBWriteResGroup90], (instregex "MINPDrm")>;
2134 def: InstRW<[SBWriteResGroup90], (instregex "MINPSrm")>;
2135 def: InstRW<[SBWriteResGroup90], (instregex "MINSDrm")>;
2136 def: InstRW<[SBWriteResGroup90], (instregex "MINSSrm")>;
2137 def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPI2PSirm")>;
2138 def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPS2PIirm")>;
2139 def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTTPS2PIirm")>;
2140 def: InstRW<[SBWriteResGroup90], (instregex "POPCNT64rm")>;
2141 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDPDm")>;
2142 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDPSm")>;
2143 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDSDm")>;
2144 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDSSm")>;
2145 def: InstRW<[SBWriteResGroup90], (instregex "SUBPDrm")>;
2146 def: InstRW<[SBWriteResGroup90], (instregex "SUBPSrm")>;
2147 def: InstRW<[SBWriteResGroup90], (instregex "SUBSDrm")>;
2148 def: InstRW<[SBWriteResGroup90], (instregex "SUBSSrm")>;
2149 def: InstRW<[SBWriteResGroup90], (instregex "VADDPDrm")>;
2150 def: InstRW<[SBWriteResGroup90], (instregex "VADDPSrm")>;
2151 def: InstRW<[SBWriteResGroup90], (instregex "VADDSDrm")>;
2152 def: InstRW<[SBWriteResGroup90], (instregex "VADDSSrm")>;
2153 def: InstRW<[SBWriteResGroup90], (instregex "VADDSUBPDrm")>;
2154 def: InstRW<[SBWriteResGroup90], (instregex "VADDSUBPSrm")>;
2155 def: InstRW<[SBWriteResGroup90], (instregex "VCMPPDrmi")>;
2156 def: InstRW<[SBWriteResGroup90], (instregex "VCMPPSrmi")>;
2157 def: InstRW<[SBWriteResGroup90], (instregex "VCMPSDrm")>;
2158 def: InstRW<[SBWriteResGroup90], (instregex "VCMPSSrm")>;
2159 def: InstRW<[SBWriteResGroup90], (instregex "VCVTDQ2PSrm")>;
2160 def: InstRW<[SBWriteResGroup90], (instregex "VCVTPS2DQrm")>;
2161 def: InstRW<[SBWriteResGroup90], (instregex "VCVTSI2SD64rm")>;
2162 def: InstRW<[SBWriteResGroup90], (instregex "VCVTSI2SDrm")>;
2163 def: InstRW<[SBWriteResGroup90], (instregex "VCVTTPS2DQrm")>;
2164 def: InstRW<[SBWriteResGroup90], (instregex "VMAXPDrm")>;
2165 def: InstRW<[SBWriteResGroup90], (instregex "VMAXPSrm")>;
2166 def: InstRW<[SBWriteResGroup90], (instregex "VMAXSDrm")>;
2167 def: InstRW<[SBWriteResGroup90], (instregex "VMAXSSrm")>;
2168 def: InstRW<[SBWriteResGroup90], (instregex "VMINPDrm")>;
2169 def: InstRW<[SBWriteResGroup90], (instregex "VMINPSrm")>;
2170 def: InstRW<[SBWriteResGroup90], (instregex "VMINSDrm")>;
2171 def: InstRW<[SBWriteResGroup90], (instregex "VMINSSrm")>;
2172 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDPDm")>;
2173 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDPSm")>;
2174 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDSDm")>;
2175 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDSSm")>;
2176 def: InstRW<[SBWriteResGroup90], (instregex "VSUBPDrm")>;
2177 def: InstRW<[SBWriteResGroup90], (instregex "VSUBPSrm")>;
2178 def: InstRW<[SBWriteResGroup90], (instregex "VSUBSDrm")>;
2179 def: InstRW<[SBWriteResGroup90], (instregex "VSUBSSrm")>;
2180
2181 def SBWriteResGroup91 : SchedWriteRes<[SBPort23,SBPort0]> {
2182   let Latency = 9;
2183   let NumMicroOps = 3;
2184   let ResourceCycles = [1,2];
2185 }
2186 def: InstRW<[SBWriteResGroup91], (instregex "VBLENDVPDYrm")>;
2187 def: InstRW<[SBWriteResGroup91], (instregex "VBLENDVPSYrm")>;
2188 def: InstRW<[SBWriteResGroup91], (instregex "VMASKMOVPDrm")>;
2189 def: InstRW<[SBWriteResGroup91], (instregex "VMASKMOVPSrm")>;
2190
2191 def SBWriteResGroup92 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
2192   let Latency = 9;
2193   let NumMicroOps = 3;
2194   let ResourceCycles = [1,1,1];
2195 }
2196 def: InstRW<[SBWriteResGroup92], (instregex "DPPDrri")>;
2197 def: InstRW<[SBWriteResGroup92], (instregex "VDPPDrri")>;
2198
2199 def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2200   let Latency = 9;
2201   let NumMicroOps = 3;
2202   let ResourceCycles = [1,1,1];
2203 }
2204 def: InstRW<[SBWriteResGroup93], (instregex "CVTSD2SI64rm")>;
2205 def: InstRW<[SBWriteResGroup93], (instregex "CVTSD2SIrm")>;
2206 def: InstRW<[SBWriteResGroup93], (instregex "CVTSS2SI64rm")>;
2207 def: InstRW<[SBWriteResGroup93], (instregex "CVTSS2SIrm")>;
2208 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSD2SI64rm")>;
2209 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSD2SIrm")>;
2210 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSS2SI64rm")>;
2211 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSS2SIrm")>;
2212 def: InstRW<[SBWriteResGroup93], (instregex "MUL64m")>;
2213
2214 def SBWriteResGroup94 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> {
2215   let Latency = 9;
2216   let NumMicroOps = 3;
2217   let ResourceCycles = [1,1,1];
2218 }
2219 def: InstRW<[SBWriteResGroup94], (instregex "VPTESTYrm")>;
2220
2221 def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
2222   let Latency = 9;
2223   let NumMicroOps = 3;
2224   let ResourceCycles = [1,1,1];
2225 }
2226 def: InstRW<[SBWriteResGroup95], (instregex "LD_F32m")>;
2227 def: InstRW<[SBWriteResGroup95], (instregex "LD_F64m")>;
2228 def: InstRW<[SBWriteResGroup95], (instregex "LD_F80m")>;
2229
2230 def SBWriteResGroup96 : SchedWriteRes<[SBPort23,SBPort15]> {
2231   let Latency = 9;
2232   let NumMicroOps = 4;
2233   let ResourceCycles = [1,3];
2234 }
2235 def: InstRW<[SBWriteResGroup96], (instregex "PHADDDrm")>;
2236 def: InstRW<[SBWriteResGroup96], (instregex "PHADDSWrm128")>;
2237 def: InstRW<[SBWriteResGroup96], (instregex "PHADDWrm")>;
2238 def: InstRW<[SBWriteResGroup96], (instregex "PHSUBDrm")>;
2239 def: InstRW<[SBWriteResGroup96], (instregex "PHSUBSWrm128")>;
2240 def: InstRW<[SBWriteResGroup96], (instregex "PHSUBWrm")>;
2241 def: InstRW<[SBWriteResGroup96], (instregex "VPHADDDrm")>;
2242 def: InstRW<[SBWriteResGroup96], (instregex "VPHADDSWrm128")>;
2243 def: InstRW<[SBWriteResGroup96], (instregex "VPHADDWrm")>;
2244 def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBDrm")>;
2245 def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBSWrm128")>;
2246 def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBWrm")>;
2247
2248 def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
2249   let Latency = 9;
2250   let NumMicroOps = 4;
2251   let ResourceCycles = [1,1,2];
2252 }
2253 def: InstRW<[SBWriteResGroup97], (instregex "IST_F16m")>;
2254 def: InstRW<[SBWriteResGroup97], (instregex "IST_F32m")>;
2255 def: InstRW<[SBWriteResGroup97], (instregex "IST_FP16m")>;
2256 def: InstRW<[SBWriteResGroup97], (instregex "IST_FP32m")>;
2257 def: InstRW<[SBWriteResGroup97], (instregex "IST_FP64m")>;
2258 def: InstRW<[SBWriteResGroup97], (instregex "SHL64mCL")>;
2259 def: InstRW<[SBWriteResGroup97], (instregex "SHL8mCL")>;
2260
2261 def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
2262   let Latency = 9;
2263   let NumMicroOps = 6;
2264   let ResourceCycles = [1,2,3];
2265 }
2266 def: InstRW<[SBWriteResGroup98], (instregex "ADC64mi8")>;
2267 def: InstRW<[SBWriteResGroup98], (instregex "ADC8mi")>;
2268 def: InstRW<[SBWriteResGroup98], (instregex "SBB64mi8")>;
2269 def: InstRW<[SBWriteResGroup98], (instregex "SBB8mi")>;
2270
2271 def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
2272   let Latency = 9;
2273   let NumMicroOps = 6;
2274   let ResourceCycles = [1,2,2,1];
2275 }
2276 def: InstRW<[SBWriteResGroup99], (instregex "ADC64mr")>;
2277 def: InstRW<[SBWriteResGroup99], (instregex "ADC8mr")>;
2278 def: InstRW<[SBWriteResGroup99], (instregex "SBB64mr")>;
2279 def: InstRW<[SBWriteResGroup99], (instregex "SBB8mr")>;
2280
2281 def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort0,SBPort015]> {
2282   let Latency = 9;
2283   let NumMicroOps = 6;
2284   let ResourceCycles = [1,1,2,1,1];
2285 }
2286 def: InstRW<[SBWriteResGroup100], (instregex "BT64mr")>;
2287 def: InstRW<[SBWriteResGroup100], (instregex "BTC64mr")>;
2288 def: InstRW<[SBWriteResGroup100], (instregex "BTR64mr")>;
2289 def: InstRW<[SBWriteResGroup100], (instregex "BTS64mr")>;
2290
2291 def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
2292   let Latency = 10;
2293   let NumMicroOps = 2;
2294   let ResourceCycles = [1,1];
2295 }
2296 def: InstRW<[SBWriteResGroup101], (instregex "ADD_F32m")>;
2297 def: InstRW<[SBWriteResGroup101], (instregex "ADD_F64m")>;
2298 def: InstRW<[SBWriteResGroup101], (instregex "ILD_F16m")>;
2299 def: InstRW<[SBWriteResGroup101], (instregex "ILD_F32m")>;
2300 def: InstRW<[SBWriteResGroup101], (instregex "ILD_F64m")>;
2301 def: InstRW<[SBWriteResGroup101], (instregex "SUBR_F32m")>;
2302 def: InstRW<[SBWriteResGroup101], (instregex "SUBR_F64m")>;
2303 def: InstRW<[SBWriteResGroup101], (instregex "SUB_F32m")>;
2304 def: InstRW<[SBWriteResGroup101], (instregex "SUB_F64m")>;
2305 def: InstRW<[SBWriteResGroup101], (instregex "VADDPDYrm")>;
2306 def: InstRW<[SBWriteResGroup101], (instregex "VADDPSYrm")>;
2307 def: InstRW<[SBWriteResGroup101], (instregex "VADDSUBPDYrm")>;
2308 def: InstRW<[SBWriteResGroup101], (instregex "VADDSUBPSYrm")>;
2309 def: InstRW<[SBWriteResGroup101], (instregex "VCMPPDYrmi")>;
2310 def: InstRW<[SBWriteResGroup101], (instregex "VCMPPSYrmi")>;
2311 def: InstRW<[SBWriteResGroup101], (instregex "VCVTDQ2PSYrm")>;
2312 def: InstRW<[SBWriteResGroup101], (instregex "VCVTPS2DQYrm")>;
2313 def: InstRW<[SBWriteResGroup101], (instregex "VCVTTPS2DQrm")>;
2314 def: InstRW<[SBWriteResGroup101], (instregex "VMAXPDYrm")>;
2315 def: InstRW<[SBWriteResGroup101], (instregex "VMAXPSYrm")>;
2316 def: InstRW<[SBWriteResGroup101], (instregex "VMINPDrm")>;
2317 def: InstRW<[SBWriteResGroup101], (instregex "VMINPSrm")>;
2318 def: InstRW<[SBWriteResGroup101], (instregex "VROUNDPDm")>;
2319 def: InstRW<[SBWriteResGroup101], (instregex "VROUNDPSm")>;
2320 def: InstRW<[SBWriteResGroup101], (instregex "VSUBPDYrm")>;
2321 def: InstRW<[SBWriteResGroup101], (instregex "VSUBPSYrm")>;
2322
2323 def SBWriteResGroup102 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2324   let Latency = 10;
2325   let NumMicroOps = 3;
2326   let ResourceCycles = [1,1,1];
2327 }
2328 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSD2SI64rm")>;
2329 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSD2SI64rr")>;
2330 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSS2SI64rm")>;
2331 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSS2SIrm")>;
2332 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSD2SI64rm")>;
2333 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSD2SI64rr")>;
2334 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSS2SI64rm")>;
2335 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSS2SIrm")>;
2336
2337 def SBWriteResGroup103 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2338   let Latency = 10;
2339   let NumMicroOps = 3;
2340   let ResourceCycles = [1,1,1];
2341 }
2342 def: InstRW<[SBWriteResGroup103], (instregex "CVTDQ2PDrm")>;
2343 def: InstRW<[SBWriteResGroup103], (instregex "CVTPD2DQrm")>;
2344 def: InstRW<[SBWriteResGroup103], (instregex "CVTPD2PSrm")>;
2345 def: InstRW<[SBWriteResGroup103], (instregex "CVTSD2SSrm")>;
2346 def: InstRW<[SBWriteResGroup103], (instregex "CVTSI2SS64rm")>;
2347 def: InstRW<[SBWriteResGroup103], (instregex "CVTSI2SSrm")>;
2348 def: InstRW<[SBWriteResGroup103], (instregex "CVTTPD2DQrm")>;
2349 def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPD2PIirm")>;
2350 def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPI2PDirm")>;
2351 def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTTPD2PIirm")>;
2352 def: InstRW<[SBWriteResGroup103], (instregex "VCVTDQ2PDYrm")>;
2353 def: InstRW<[SBWriteResGroup103], (instregex "VCVTDQ2PDrm")>;
2354 def: InstRW<[SBWriteResGroup103], (instregex "VCVTPD2DQrm")>;
2355 def: InstRW<[SBWriteResGroup103], (instregex "VCVTPD2PSrm")>;
2356 def: InstRW<[SBWriteResGroup103], (instregex "VCVTSD2SSrm")>;
2357 def: InstRW<[SBWriteResGroup103], (instregex "VCVTSI2SS64rm")>;
2358 def: InstRW<[SBWriteResGroup103], (instregex "VCVTSI2SSrm")>;
2359 def: InstRW<[SBWriteResGroup103], (instregex "VCVTTPD2DQrm")>;
2360
2361 def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> {
2362   let Latency = 11;
2363   let NumMicroOps = 2;
2364   let ResourceCycles = [1,1];
2365 }
2366 def: InstRW<[SBWriteResGroup104], (instregex "MULPDrm")>;
2367 def: InstRW<[SBWriteResGroup104], (instregex "MULPSrm")>;
2368 def: InstRW<[SBWriteResGroup104], (instregex "MULSDrm")>;
2369 def: InstRW<[SBWriteResGroup104], (instregex "MULSSrm")>;
2370 def: InstRW<[SBWriteResGroup104], (instregex "PCMPGTQrm")>;
2371 def: InstRW<[SBWriteResGroup104], (instregex "PHMINPOSUWrm128")>;
2372 def: InstRW<[SBWriteResGroup104], (instregex "RCPPSm")>;
2373 def: InstRW<[SBWriteResGroup104], (instregex "RCPSSm")>;
2374 def: InstRW<[SBWriteResGroup104], (instregex "RSQRTPSm")>;
2375 def: InstRW<[SBWriteResGroup104], (instregex "RSQRTSSm")>;
2376 def: InstRW<[SBWriteResGroup104], (instregex "VMULPDrm")>;
2377 def: InstRW<[SBWriteResGroup104], (instregex "VMULPSrm")>;
2378 def: InstRW<[SBWriteResGroup104], (instregex "VMULSDrm")>;
2379 def: InstRW<[SBWriteResGroup104], (instregex "VMULSSrm")>;
2380 def: InstRW<[SBWriteResGroup104], (instregex "VPCMPGTQrm")>;
2381 def: InstRW<[SBWriteResGroup104], (instregex "VPHMINPOSUWrm128")>;
2382 def: InstRW<[SBWriteResGroup104], (instregex "VRCPPSm")>;
2383 def: InstRW<[SBWriteResGroup104], (instregex "VRCPSSm")>;
2384 def: InstRW<[SBWriteResGroup104], (instregex "VRSQRTPSm")>;
2385 def: InstRW<[SBWriteResGroup104], (instregex "VRSQRTSSm")>;
2386
2387 def SBWriteResGroup105 : SchedWriteRes<[SBPort0]> {
2388   let Latency = 11;
2389   let NumMicroOps = 3;
2390   let ResourceCycles = [3];
2391 }
2392 def: InstRW<[SBWriteResGroup105], (instregex "PCMPISTRIrr")>;
2393 def: InstRW<[SBWriteResGroup105], (instregex "PCMPISTRM128rr")>;
2394 def: InstRW<[SBWriteResGroup105], (instregex "VPCMPISTRIrr")>;
2395 def: InstRW<[SBWriteResGroup105], (instregex "VPCMPISTRM128rr")>;
2396
2397 def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
2398   let Latency = 11;
2399   let NumMicroOps = 3;
2400   let ResourceCycles = [2,1];
2401 }
2402 def: InstRW<[SBWriteResGroup106], (instregex "FICOM16m")>;
2403 def: InstRW<[SBWriteResGroup106], (instregex "FICOM32m")>;
2404 def: InstRW<[SBWriteResGroup106], (instregex "FICOMP16m")>;
2405 def: InstRW<[SBWriteResGroup106], (instregex "FICOMP32m")>;
2406
2407 def SBWriteResGroup107 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2408   let Latency = 11;
2409   let NumMicroOps = 3;
2410   let ResourceCycles = [1,1,1];
2411 }
2412 def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2DQYrm")>;
2413 def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2PSYrm")>;
2414 def: InstRW<[SBWriteResGroup107], (instregex "VCVTTPD2DQYrm")>;
2415
2416 def SBWriteResGroup108 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> {
2417   let Latency = 11;
2418   let NumMicroOps = 4;
2419   let ResourceCycles = [1,1,2];
2420 }
2421 def: InstRW<[SBWriteResGroup108], (instregex "MPSADBWrmi")>;
2422 def: InstRW<[SBWriteResGroup108], (instregex "VMPSADBWrmi")>;
2423
2424 def SBWriteResGroup109 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2425   let Latency = 11;
2426   let NumMicroOps = 4;
2427   let ResourceCycles = [1,2,1];
2428 }
2429 def: InstRW<[SBWriteResGroup109], (instregex "HADDPDrm")>;
2430 def: InstRW<[SBWriteResGroup109], (instregex "HADDPSrm")>;
2431 def: InstRW<[SBWriteResGroup109], (instregex "HSUBPDrm")>;
2432 def: InstRW<[SBWriteResGroup109], (instregex "HSUBPSrm")>;
2433 def: InstRW<[SBWriteResGroup109], (instregex "VHADDPDrm")>;
2434 def: InstRW<[SBWriteResGroup109], (instregex "VHADDPSrm")>;
2435 def: InstRW<[SBWriteResGroup109], (instregex "VHSUBPDrm")>;
2436 def: InstRW<[SBWriteResGroup109], (instregex "VHSUBPSrm")>;
2437
2438 def SBWriteResGroup110 : SchedWriteRes<[SBPort5]> {
2439   let Latency = 12;
2440   let NumMicroOps = 2;
2441   let ResourceCycles = [2];
2442 }
2443 def: InstRW<[SBWriteResGroup110], (instregex "AESIMCrr")>;
2444 def: InstRW<[SBWriteResGroup110], (instregex "VAESIMCrr")>;
2445
2446 def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
2447   let Latency = 12;
2448   let NumMicroOps = 2;
2449   let ResourceCycles = [1,1];
2450 }
2451 def: InstRW<[SBWriteResGroup111], (instregex "MUL_F32m")>;
2452 def: InstRW<[SBWriteResGroup111], (instregex "MUL_F64m")>;
2453 def: InstRW<[SBWriteResGroup111], (instregex "VMULPDYrm")>;
2454 def: InstRW<[SBWriteResGroup111], (instregex "VMULPSYrm")>;
2455
2456 def SBWriteResGroup112 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
2457   let Latency = 12;
2458   let NumMicroOps = 4;
2459   let ResourceCycles = [1,2,1];
2460 }
2461 def: InstRW<[SBWriteResGroup112], (instregex "DPPSrri")>;
2462 def: InstRW<[SBWriteResGroup112], (instregex "VDPPSYrri")>;
2463 def: InstRW<[SBWriteResGroup112], (instregex "VDPPSrri")>;
2464
2465 def SBWriteResGroup113 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2466   let Latency = 12;
2467   let NumMicroOps = 4;
2468   let ResourceCycles = [1,2,1];
2469 }
2470 def: InstRW<[SBWriteResGroup113], (instregex "VHADDPDrm")>;
2471 def: InstRW<[SBWriteResGroup113], (instregex "VHADDPSYrm")>;
2472 def: InstRW<[SBWriteResGroup113], (instregex "VHSUBPDYrm")>;
2473 def: InstRW<[SBWriteResGroup113], (instregex "VHSUBPSYrm")>;
2474
2475 def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> {
2476   let Latency = 13;
2477   let NumMicroOps = 3;
2478   let ResourceCycles = [2,1];
2479 }
2480 def: InstRW<[SBWriteResGroup114], (instregex "ADD_FI16m")>;
2481 def: InstRW<[SBWriteResGroup114], (instregex "ADD_FI32m")>;
2482 def: InstRW<[SBWriteResGroup114], (instregex "SUBR_FI16m")>;
2483 def: InstRW<[SBWriteResGroup114], (instregex "SUBR_FI32m")>;
2484 def: InstRW<[SBWriteResGroup114], (instregex "SUB_FI16m")>;
2485 def: InstRW<[SBWriteResGroup114], (instregex "SUB_FI32m")>;
2486
2487 def SBWriteResGroup115 : SchedWriteRes<[SBPort5,SBPort23,SBPort015]> {
2488   let Latency = 13;
2489   let NumMicroOps = 3;
2490   let ResourceCycles = [1,1,1];
2491 }
2492 def: InstRW<[SBWriteResGroup115], (instregex "AESDECLASTrm")>;
2493 def: InstRW<[SBWriteResGroup115], (instregex "AESDECrm")>;
2494 def: InstRW<[SBWriteResGroup115], (instregex "AESENCLASTrm")>;
2495 def: InstRW<[SBWriteResGroup115], (instregex "AESENCrm")>;
2496 def: InstRW<[SBWriteResGroup115], (instregex "VAESDECLASTrm")>;
2497 def: InstRW<[SBWriteResGroup115], (instregex "VAESDECrm")>;
2498 def: InstRW<[SBWriteResGroup115], (instregex "VAESENCLASTrm")>;
2499 def: InstRW<[SBWriteResGroup115], (instregex "VAESENCrm")>;
2500
2501 def SBWriteResGroup116 : SchedWriteRes<[SBPort0]> {
2502   let Latency = 14;
2503   let NumMicroOps = 1;
2504   let ResourceCycles = [1];
2505 }
2506 def: InstRW<[SBWriteResGroup116], (instregex "DIVPSrr")>;
2507 def: InstRW<[SBWriteResGroup116], (instregex "DIVSSrr")>;
2508 def: InstRW<[SBWriteResGroup116], (instregex "SQRTPSr")>;
2509 def: InstRW<[SBWriteResGroup116], (instregex "SQRTSSr")>;
2510 def: InstRW<[SBWriteResGroup116], (instregex "VDIVPSrr")>;
2511 def: InstRW<[SBWriteResGroup116], (instregex "VDIVSSrr")>;
2512 def: InstRW<[SBWriteResGroup116], (instregex "VSQRTPSr")>;
2513
2514 def SBWriteResGroup117 : SchedWriteRes<[SBPort0,SBPort23]> {
2515   let Latency = 14;
2516   let NumMicroOps = 2;
2517   let ResourceCycles = [1,1];
2518 }
2519 def: InstRW<[SBWriteResGroup117], (instregex "VSQRTSSm")>;
2520
2521 def SBWriteResGroup118 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> {
2522   let Latency = 14;
2523   let NumMicroOps = 4;
2524   let ResourceCycles = [2,1,1];
2525 }
2526 def: InstRW<[SBWriteResGroup118], (instregex "VRCPPSm")>;
2527 def: InstRW<[SBWriteResGroup118], (instregex "VRSQRTPSYm")>;
2528
2529 def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2530   let Latency = 15;
2531   let NumMicroOps = 3;
2532   let ResourceCycles = [1,1,1];
2533 }
2534 def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI16m")>;
2535 def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI32m")>;
2536
2537 def SBWriteResGroup120 : SchedWriteRes<[SBPort0,SBPort1,SBPort5,SBPort23]> {
2538   let Latency = 15;
2539   let NumMicroOps = 4;
2540   let ResourceCycles = [1,1,1,1];
2541 }
2542 def: InstRW<[SBWriteResGroup120], (instregex "DPPDrmi")>;
2543 def: InstRW<[SBWriteResGroup120], (instregex "VDPPDrmi")>;
2544
2545 def SBWriteResGroup121 : SchedWriteRes<[SBPort0,SBPort23]> {
2546   let Latency = 17;
2547   let NumMicroOps = 4;
2548   let ResourceCycles = [3,1];
2549 }
2550 def: InstRW<[SBWriteResGroup121], (instregex "PCMPISTRIrm")>;
2551 def: InstRW<[SBWriteResGroup121], (instregex "PCMPISTRM128rm")>;
2552 def: InstRW<[SBWriteResGroup121], (instregex "VPCMPISTRIrm")>;
2553 def: InstRW<[SBWriteResGroup121], (instregex "VPCMPISTRM128rm")>;
2554
2555 def SBWriteResGroup122 : SchedWriteRes<[SBPort5,SBPort23]> {
2556   let Latency = 18;
2557   let NumMicroOps = 3;
2558   let ResourceCycles = [2,1];
2559 }
2560 def: InstRW<[SBWriteResGroup122], (instregex "AESIMCrm")>;
2561 def: InstRW<[SBWriteResGroup122], (instregex "VAESIMCrm")>;
2562
2563 def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23]> {
2564   let Latency = 20;
2565   let NumMicroOps = 2;
2566   let ResourceCycles = [1,1];
2567 }
2568 def: InstRW<[SBWriteResGroup123], (instregex "DIVPSrm")>;
2569 def: InstRW<[SBWriteResGroup123], (instregex "DIVSSrm")>;
2570 def: InstRW<[SBWriteResGroup123], (instregex "SQRTPSm")>;
2571 def: InstRW<[SBWriteResGroup123], (instregex "SQRTSSm")>;
2572 def: InstRW<[SBWriteResGroup123], (instregex "VDIVPSrm")>;
2573 def: InstRW<[SBWriteResGroup123], (instregex "VDIVSSrm")>;
2574 def: InstRW<[SBWriteResGroup123], (instregex "VSQRTPSm")>;
2575
2576 def SBWriteResGroup124 : SchedWriteRes<[SBPort0]> {
2577   let Latency = 21;
2578   let NumMicroOps = 1;
2579   let ResourceCycles = [1];
2580 }
2581 def: InstRW<[SBWriteResGroup124], (instregex "VSQRTSDr")>;
2582
2583 def SBWriteResGroup125 : SchedWriteRes<[SBPort0,SBPort23]> {
2584   let Latency = 21;
2585   let NumMicroOps = 2;
2586   let ResourceCycles = [1,1];
2587 }
2588 def: InstRW<[SBWriteResGroup125], (instregex "VSQRTSDm")>;
2589
2590 def SBWriteResGroup126 : SchedWriteRes<[SBPort0]> {
2591   let Latency = 22;
2592   let NumMicroOps = 1;
2593   let ResourceCycles = [1];
2594 }
2595 def: InstRW<[SBWriteResGroup126], (instregex "DIVPDrr")>;
2596 def: InstRW<[SBWriteResGroup126], (instregex "DIVSDrr")>;
2597 def: InstRW<[SBWriteResGroup126], (instregex "SQRTPDr")>;
2598 def: InstRW<[SBWriteResGroup126], (instregex "SQRTSDr")>;
2599 def: InstRW<[SBWriteResGroup126], (instregex "VDIVPDrr")>;
2600 def: InstRW<[SBWriteResGroup126], (instregex "VDIVSDrr")>;
2601 def: InstRW<[SBWriteResGroup126], (instregex "VSQRTPDr")>;
2602
2603 def SBWriteResGroup127 : SchedWriteRes<[SBPort0]> {
2604   let Latency = 24;
2605   let NumMicroOps = 1;
2606   let ResourceCycles = [1];
2607 }
2608 def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FPrST0")>;
2609 def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FST0r")>;
2610 def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FrST0")>;
2611 def: InstRW<[SBWriteResGroup127], (instregex "DIV_FPrST0")>;
2612 def: InstRW<[SBWriteResGroup127], (instregex "DIV_FST0r")>;
2613 def: InstRW<[SBWriteResGroup127], (instregex "DIV_FrST0")>;
2614
2615 def SBWriteResGroup128 : SchedWriteRes<[SBPort0,SBPort23]> {
2616   let Latency = 28;
2617   let NumMicroOps = 2;
2618   let ResourceCycles = [1,1];
2619 }
2620 def: InstRW<[SBWriteResGroup128], (instregex "DIVPDrm")>;
2621 def: InstRW<[SBWriteResGroup128], (instregex "DIVSDrm")>;
2622 def: InstRW<[SBWriteResGroup128], (instregex "SQRTPDm")>;
2623 def: InstRW<[SBWriteResGroup128], (instregex "SQRTSDm")>;
2624 def: InstRW<[SBWriteResGroup128], (instregex "VDIVPDrm")>;
2625 def: InstRW<[SBWriteResGroup128], (instregex "VDIVSDrm")>;
2626 def: InstRW<[SBWriteResGroup128], (instregex "VSQRTPDm")>;
2627
2628 def SBWriteResGroup129 : SchedWriteRes<[SBPort0,SBPort0]> {
2629   let Latency = 29;
2630   let NumMicroOps = 3;
2631   let ResourceCycles = [2,1];
2632 }
2633 def: InstRW<[SBWriteResGroup129], (instregex "VDIVPSYrr")>;
2634 def: InstRW<[SBWriteResGroup129], (instregex "VSQRTPSYr")>;
2635
2636 def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> {
2637   let Latency = 31;
2638   let NumMicroOps = 2;
2639   let ResourceCycles = [1,1];
2640 }
2641 def: InstRW<[SBWriteResGroup130], (instregex "DIVR_F32m")>;
2642 def: InstRW<[SBWriteResGroup130], (instregex "DIVR_F64m")>;
2643 def: InstRW<[SBWriteResGroup130], (instregex "DIV_F32m")>;
2644 def: InstRW<[SBWriteResGroup130], (instregex "DIV_F64m")>;
2645
2646 def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2647   let Latency = 34;
2648   let NumMicroOps = 3;
2649   let ResourceCycles = [1,1,1];
2650 }
2651 def: InstRW<[SBWriteResGroup131], (instregex "DIVR_FI16m")>;
2652 def: InstRW<[SBWriteResGroup131], (instregex "DIVR_FI32m")>;
2653 def: InstRW<[SBWriteResGroup131], (instregex "DIV_FI16m")>;
2654 def: InstRW<[SBWriteResGroup131], (instregex "DIV_FI32m")>;
2655
2656 def SBWriteResGroup132 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> {
2657   let Latency = 36;
2658   let NumMicroOps = 4;
2659   let ResourceCycles = [2,1,1];
2660 }
2661 def: InstRW<[SBWriteResGroup132], (instregex "VDIVPSYrm")>;
2662 def: InstRW<[SBWriteResGroup132], (instregex "VSQRTPSYm")>;
2663
2664 def SBWriteResGroup133 : SchedWriteRes<[SBPort0,SBPort0]> {
2665   let Latency = 45;
2666   let NumMicroOps = 3;
2667   let ResourceCycles = [2,1];
2668 }
2669 def: InstRW<[SBWriteResGroup133], (instregex "VDIVPDYrr")>;
2670 def: InstRW<[SBWriteResGroup133], (instregex "VSQRTPDYr")>;
2671
2672 def SBWriteResGroup134 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> {
2673   let Latency = 52;
2674   let NumMicroOps = 4;
2675   let ResourceCycles = [2,1,1];
2676 }
2677 def: InstRW<[SBWriteResGroup134], (instregex "VDIVPDYrm")>;
2678 def: InstRW<[SBWriteResGroup134], (instregex "VSQRTPDYm")>;
2679
2680 def SBWriteResGroup135 : SchedWriteRes<[SBPort0]> {
2681   let Latency = 114;
2682   let NumMicroOps = 1;
2683   let ResourceCycles = [1];
2684 }
2685 def: InstRW<[SBWriteResGroup135], (instregex "VSQRTSSr")>;
2686
2687 } // SchedModel