contrib/llvm/lib/Target/X86/X86SchedSandyBridge.td

   1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for Sandy Bridge to support instruction
  11 // scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 def SandyBridgeModel : SchedMachineModel {
  16   // All x86 instructions are modeled as a single micro-op, and SB can decode 4
  17   // instructions per cycle.
  18   // FIXME: Identify instructions that aren't a single fused micro-op.
  19   let IssueWidth = 4;
  20   let MicroOpBufferSize = 168; // Based on the reorder buffer.
  21   let LoadLatency = 4;
  22   let MispredictPenalty = 16;
  23
  24   // Based on the LSD (loop-stream detector) queue size.
  25   let LoopMicroOpBufferSize = 28;
  26
  27   // This flag is set to allow the scheduler to assign
  28   // a default model to unrecognized opcodes.
  29   let CompleteModel = 0;
  30 }
  31
  32 let SchedModel = SandyBridgeModel in {
  33
  34 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
  35
  36 // Ports 0, 1, and 5 handle all computation.
  37 def SBPort0 : ProcResource<1>;
  38 def SBPort1 : ProcResource<1>;
  39 def SBPort5 : ProcResource<1>;
  40
  41 // Ports 2 and 3 are identical. They handle loads and the address half of
  42 // stores.
  43 def SBPort23 : ProcResource<2>;
  44
  45 // Port 4 gets the data half of stores. Store data can be available later than
  46 // the store address, but since we don't model the latency of stores, we can
  47 // ignore that.
  48 def SBPort4 : ProcResource<1>;
  49
  50 // Many micro-ops are capable of issuing on multiple ports.
  51 def SBPort01  : ProcResGroup<[SBPort0, SBPort1]>;
  52 def SBPort05  : ProcResGroup<[SBPort0, SBPort5]>;
  53 def SBPort15  : ProcResGroup<[SBPort1, SBPort5]>;
  54 def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
  55
  56 // 54 Entry Unified Scheduler
  57 def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> {
  58   let BufferSize=54;
  59 }
  60
  61 // Integer division issued on port 0.
  62 def SBDivider : ProcResource<1>;
  63
  64 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
  65 // cycles after the memory operand.
  66 def : ReadAdvance<ReadAfterLd, 4>;
  67
  68 // Many SchedWrites are defined in pairs with and without a folded load.
  69 // Instructions with folded loads are usually micro-fused, so they only appear
  70 // as two micro-ops when queued in the reservation station.
  71 // This multiclass defines the resource usage for variants with and without
  72 // folded loads.
  73 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
  74                           ProcResourceKind ExePort,
  75                           int Lat> {
  76   // Register variant is using a single cycle on ExePort.
  77   def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
  78
  79   // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
  80   // latency.
  81   def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
  82      let Latency = !add(Lat, 4);
  83   }
  84 }
  85
  86 // A folded store needs a cycle on port 4 for the store data, but it does not
  87 // need an extra port 2/3 cycle to recompute the address.
  88 def : WriteRes<WriteRMW, [SBPort4]>;
  89
  90 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
  91 def : WriteRes<WriteLoad,  [SBPort23]> { let Latency = 4; }
  92 def : WriteRes<WriteMove,  [SBPort015]>;
  93 def : WriteRes<WriteZero,  []>;
  94
  95 defm : SBWriteResPair<WriteALU,   SBPort015, 1>;
  96 defm : SBWriteResPair<WriteIMul,  SBPort1,   3>;
  97 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
  98 defm : SBWriteResPair<WriteShift, SBPort05,  1>;
  99 defm : SBWriteResPair<WriteJump,  SBPort5,   1>;
 100
 101 // This is for simple LEAs with one or two input operands.
 102 // The complex ones can only execute on port 1, and they require two cycles on
 103 // the port to read all inputs. We don't model that.
 104 def : WriteRes<WriteLEA, [SBPort15]>;
 105
 106 // This is quite rough, latency depends on the dividend.
 107 def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> {
 108   let Latency = 25;
 109   let ResourceCycles = [1, 10];
 110 }
 111 def : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> {
 112   let Latency = 29;
 113   let ResourceCycles = [1, 1, 10];
 114 }
 115
 116 // Scalar and vector floating point.
 117 defm : SBWriteResPair<WriteFAdd,   SBPort1, 3>;
 118 defm : SBWriteResPair<WriteFMul,   SBPort0, 5>;
 119 defm : SBWriteResPair<WriteFDiv,   SBPort0, 24>;
 120 defm : SBWriteResPair<WriteFRcp,   SBPort0, 5>;
 121 defm : SBWriteResPair<WriteFRsqrt, SBPort0, 5>;
 122 defm : SBWriteResPair<WriteFSqrt,  SBPort0, 14>;
 123 defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>;
 124 defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>;
 125 defm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>;
 126 defm : SBWriteResPair<WriteFShuffle,  SBPort5,  1>;
 127 defm : SBWriteResPair<WriteFBlend,  SBPort05,  1>;
 128 def : WriteRes<WriteFVarBlend, [SBPort0, SBPort5]> {
 129   let Latency = 2;
 130   let ResourceCycles = [1, 1];
 131 }
 132 def : WriteRes<WriteFVarBlendLd, [SBPort0, SBPort5, SBPort23]> {
 133   let Latency = 6;
 134   let ResourceCycles = [1, 1, 1];
 135 }
 136
 137 // Vector integer operations.
 138 defm : SBWriteResPair<WriteVecShift, SBPort5,  1>;
 139 defm : SBWriteResPair<WriteVecLogic, SBPort5, 1>;
 140 defm : SBWriteResPair<WriteVecALU,   SBPort1,  3>;
 141 defm : SBWriteResPair<WriteVecIMul,  SBPort0,   5>;
 142 defm : SBWriteResPair<WriteShuffle,  SBPort5,  1>;
 143 defm : SBWriteResPair<WriteBlend,  SBPort15,  1>;
 144 def : WriteRes<WriteVarBlend, [SBPort1, SBPort5]> {
 145   let Latency = 2;
 146   let ResourceCycles = [1, 1];
 147 }
 148 def : WriteRes<WriteVarBlendLd, [SBPort1, SBPort5, SBPort23]> {
 149   let Latency = 6;
 150   let ResourceCycles = [1, 1, 1];
 151 }
 152 def : WriteRes<WriteMPSAD, [SBPort0,SBPort15]> {
 153   let Latency = 5;
 154   let NumMicroOps = 3;
 155   let ResourceCycles = [1,2];
 156 }
 157 def : WriteRes<WriteMPSADLd, [SBPort0,SBPort23,SBPort15]> {
 158   let Latency = 11;
 159   let NumMicroOps = 4;
 160   let ResourceCycles = [1,1,2];
 161 }
 162
 163 ////////////////////////////////////////////////////////////////////////////////
 164 // Horizontal add/sub  instructions.
 165 ////////////////////////////////////////////////////////////////////////////////
 166 // HADD, HSUB PS/PD
 167 // x,x / v,v,v.
 168 def : WriteRes<WriteFHAdd, [SBPort1]> {
 169   let Latency = 3;
 170 }
 171
 172 // x,m / v,v,m.
 173 def : WriteRes<WriteFHAddLd, [SBPort1, SBPort23]> {
 174   let Latency = 7;
 175   let ResourceCycles = [1, 1];
 176 }
 177
 178 // PHADD|PHSUB (S) W/D.
 179 // v <- v,v.
 180 def : WriteRes<WritePHAdd, [SBPort15]>;
 181
 182 // v <- v,m.
 183 def : WriteRes<WritePHAddLd, [SBPort15, SBPort23]> {
 184   let Latency = 5;
 185   let ResourceCycles = [1, 1];
 186 }
 187
 188 // String instructions.
 189 // Packed Compare Implicit Length Strings, Return Mask
 190 def : WriteRes<WritePCmpIStrM, [SBPort015]> {
 191   let Latency = 11;
 192   let ResourceCycles = [3];
 193 }
 194 def : WriteRes<WritePCmpIStrMLd, [SBPort015, SBPort23]> {
 195   let Latency = 11;
 196   let ResourceCycles = [3, 1];
 197 }
 198
 199 // Packed Compare Explicit Length Strings, Return Mask
 200 def : WriteRes<WritePCmpEStrM, [SBPort015]> {
 201   let Latency = 11;
 202   let ResourceCycles = [8];
 203 }
 204 def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
 205   let Latency = 11;
 206   let ResourceCycles = [7, 1];
 207 }
 208
 209 // Packed Compare Implicit Length Strings, Return Index
 210 def : WriteRes<WritePCmpIStrI, [SBPort0]> {
 211   let Latency = 11;
 212   let NumMicroOps = 3;
 213   let ResourceCycles = [3];
 214 }
 215 def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> {
 216   let Latency = 17;
 217   let NumMicroOps = 4;
 218   let ResourceCycles = [3,1];
 219 }
 220
 221 // Packed Compare Explicit Length Strings, Return Index
 222 def : WriteRes<WritePCmpEStrI, [SBPort015]> {
 223   let Latency = 4;
 224   let ResourceCycles = [8];
 225 }
 226 def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
 227   let Latency = 4;
 228   let ResourceCycles = [7, 1];
 229 }
 230
 231 // AES Instructions.
 232 def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> {
 233   let Latency = 7;
 234   let NumMicroOps = 2;
 235   let ResourceCycles = [1,1];
 236 }
 237 def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> {
 238   let Latency = 13;
 239   let NumMicroOps = 3;
 240   let ResourceCycles = [1,1,1];
 241 }
 242
 243 def : WriteRes<WriteAESIMC, [SBPort5]> {
 244   let Latency = 12;
 245   let NumMicroOps = 2;
 246   let ResourceCycles = [2];
 247 }
 248 def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> {
 249   let Latency = 18;
 250   let NumMicroOps = 3;
 251   let ResourceCycles = [2,1];
 252 }
 253
 254 def : WriteRes<WriteAESKeyGen, [SBPort015]> {
 255   let Latency = 8;
 256   let ResourceCycles = [11];
 257 }
 258 def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
 259   let Latency = 8;
 260   let ResourceCycles = [10, 1];
 261 }
 262
 263 // Carry-less multiplication instructions.
 264 def : WriteRes<WriteCLMul, [SBPort015]> {
 265   let Latency = 14;
 266   let ResourceCycles = [18];
 267 }
 268 def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
 269   let Latency = 14;
 270   let ResourceCycles = [17, 1];
 271 }
 272
 273
 274 def : WriteRes<WriteSystem,     [SBPort015]> { let Latency = 100; }
 275 def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
 276 def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
 277 def : WriteRes<WriteNop, []>;
 278
 279 // AVX2/FMA is not supported on that architecture, but we should define the basic
 280 // scheduling resources anyway.
 281 defm : SBWriteResPair<WriteFShuffle256, SBPort0,  1>;
 282 defm : SBWriteResPair<WriteShuffle256, SBPort0,  1>;
 283 defm : SBWriteResPair<WriteVarVecShift, SBPort0,  1>;
 284 defm : SBWriteResPair<WriteFMA, SBPort01,  5>;
 285
 286 // Remaining SNB instrs.
 287
 288 def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> {
 289   let Latency = 1;
 290   let NumMicroOps = 1;
 291   let ResourceCycles = [1];
 292 }
 293 def: InstRW<[SBWriteResGroup0], (instregex "CVTSS2SDrr")>;
 294 def: InstRW<[SBWriteResGroup0], (instregex "PSLLDri")>;
 295 def: InstRW<[SBWriteResGroup0], (instregex "PSLLQri")>;
 296 def: InstRW<[SBWriteResGroup0], (instregex "PSLLWri")>;
 297 def: InstRW<[SBWriteResGroup0], (instregex "PSRADri")>;
 298 def: InstRW<[SBWriteResGroup0], (instregex "PSRAWri")>;
 299 def: InstRW<[SBWriteResGroup0], (instregex "PSRLDri")>;
 300 def: InstRW<[SBWriteResGroup0], (instregex "PSRLQri")>;
 301 def: InstRW<[SBWriteResGroup0], (instregex "PSRLWri")>;
 302 def: InstRW<[SBWriteResGroup0], (instregex "VCVTSS2SDrr")>;
 303 def: InstRW<[SBWriteResGroup0], (instregex "VPMOVMSKBrr")>;
 304 def: InstRW<[SBWriteResGroup0], (instregex "VPSLLDri")>;
 305 def: InstRW<[SBWriteResGroup0], (instregex "VPSLLQri")>;
 306 def: InstRW<[SBWriteResGroup0], (instregex "VPSLLWri")>;
 307 def: InstRW<[SBWriteResGroup0], (instregex "VPSRADri")>;
 308 def: InstRW<[SBWriteResGroup0], (instregex "VPSRAWri")>;
 309 def: InstRW<[SBWriteResGroup0], (instregex "VPSRLDri")>;
 310 def: InstRW<[SBWriteResGroup0], (instregex "VPSRLQri")>;
 311 def: InstRW<[SBWriteResGroup0], (instregex "VPSRLWri")>;
 312 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDYrr")>;
 313 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDrr")>;
 314 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSYrr")>;
 315 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSrr")>;
 316
 317 def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> {
 318   let Latency = 1;
 319   let NumMicroOps = 1;
 320   let ResourceCycles = [1];
 321 }
 322 def: InstRW<[SBWriteResGroup1], (instregex "COMP_FST0r")>;
 323 def: InstRW<[SBWriteResGroup1], (instregex "COM_FST0r")>;
 324 def: InstRW<[SBWriteResGroup1], (instregex "UCOM_FPr")>;
 325 def: InstRW<[SBWriteResGroup1], (instregex "UCOM_Fr")>;
 326
 327 def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
 328   let Latency = 1;
 329   let NumMicroOps = 1;
 330   let ResourceCycles = [1];
 331 }
 332 def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr")>;
 333 def: InstRW<[SBWriteResGroup2], (instregex "ANDNPSrr")>;
 334 def: InstRW<[SBWriteResGroup2], (instregex "ANDPDrr")>;
 335 def: InstRW<[SBWriteResGroup2], (instregex "ANDPSrr")>;
 336 def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP")>;
 337 def: InstRW<[SBWriteResGroup2], (instregex "FFREE")>;
 338 def: InstRW<[SBWriteResGroup2], (instregex "FINCSTP")>;
 339 def: InstRW<[SBWriteResGroup2], (instregex "FNOP")>;
 340 def: InstRW<[SBWriteResGroup2], (instregex "INSERTPSrr")>;
 341 def: InstRW<[SBWriteResGroup2], (instregex "JAE_1")>;
 342 def: InstRW<[SBWriteResGroup2], (instregex "JAE_4")>;
 343 def: InstRW<[SBWriteResGroup2], (instregex "JA_1")>;
 344 def: InstRW<[SBWriteResGroup2], (instregex "JA_4")>;
 345 def: InstRW<[SBWriteResGroup2], (instregex "JBE_1")>;
 346 def: InstRW<[SBWriteResGroup2], (instregex "JBE_4")>;
 347 def: InstRW<[SBWriteResGroup2], (instregex "JB_1")>;
 348 def: InstRW<[SBWriteResGroup2], (instregex "JB_4")>;
 349 def: InstRW<[SBWriteResGroup2], (instregex "JE_1")>;
 350 def: InstRW<[SBWriteResGroup2], (instregex "JE_4")>;
 351 def: InstRW<[SBWriteResGroup2], (instregex "JGE_1")>;
 352 def: InstRW<[SBWriteResGroup2], (instregex "JGE_4")>;
 353 def: InstRW<[SBWriteResGroup2], (instregex "JG_1")>;
 354 def: InstRW<[SBWriteResGroup2], (instregex "JG_4")>;
 355 def: InstRW<[SBWriteResGroup2], (instregex "JLE_1")>;
 356 def: InstRW<[SBWriteResGroup2], (instregex "JLE_4")>;
 357 def: InstRW<[SBWriteResGroup2], (instregex "JL_1")>;
 358 def: InstRW<[SBWriteResGroup2], (instregex "JL_4")>;
 359 def: InstRW<[SBWriteResGroup2], (instregex "JMP64r")>;
 360 def: InstRW<[SBWriteResGroup2], (instregex "JMP_1")>;
 361 def: InstRW<[SBWriteResGroup2], (instregex "JMP_4")>;
 362 def: InstRW<[SBWriteResGroup2], (instregex "JNE_1")>;
 363 def: InstRW<[SBWriteResGroup2], (instregex "JNE_4")>;
 364 def: InstRW<[SBWriteResGroup2], (instregex "JNO_1")>;
 365 def: InstRW<[SBWriteResGroup2], (instregex "JNO_4")>;
 366 def: InstRW<[SBWriteResGroup2], (instregex "JNP_1")>;
 367 def: InstRW<[SBWriteResGroup2], (instregex "JNP_4")>;
 368 def: InstRW<[SBWriteResGroup2], (instregex "JNS_1")>;
 369 def: InstRW<[SBWriteResGroup2], (instregex "JNS_4")>;
 370 def: InstRW<[SBWriteResGroup2], (instregex "JO_1")>;
 371 def: InstRW<[SBWriteResGroup2], (instregex "JO_4")>;
 372 def: InstRW<[SBWriteResGroup2], (instregex "JP_1")>;
 373 def: InstRW<[SBWriteResGroup2], (instregex "JP_4")>;
 374 def: InstRW<[SBWriteResGroup2], (instregex "JS_1")>;
 375 def: InstRW<[SBWriteResGroup2], (instregex "JS_4")>;
 376 def: InstRW<[SBWriteResGroup2], (instregex "LD_Frr")>;
 377 def: InstRW<[SBWriteResGroup2], (instregex "LOOP")>;
 378 def: InstRW<[SBWriteResGroup2], (instregex "LOOPE")>;
 379 def: InstRW<[SBWriteResGroup2], (instregex "LOOPNE")>;
 380 def: InstRW<[SBWriteResGroup2], (instregex "MOV64toPQIrr")>;
 381 def: InstRW<[SBWriteResGroup2], (instregex "MOVAPDrr")>;
 382 def: InstRW<[SBWriteResGroup2], (instregex "MOVAPSrr")>;
 383 def: InstRW<[SBWriteResGroup2], (instregex "MOVDDUPrr")>;
 384 def: InstRW<[SBWriteResGroup2], (instregex "MOVDI2PDIrr")>;
 385 def: InstRW<[SBWriteResGroup2], (instregex "MOVHLPSrr")>;
 386 def: InstRW<[SBWriteResGroup2], (instregex "MOVLHPSrr")>;
 387 def: InstRW<[SBWriteResGroup2], (instregex "MOVSDrr")>;
 388 def: InstRW<[SBWriteResGroup2], (instregex "MOVSHDUPrr")>;
 389 def: InstRW<[SBWriteResGroup2], (instregex "MOVSLDUPrr")>;
 390 def: InstRW<[SBWriteResGroup2], (instregex "MOVSSrr")>;
 391 def: InstRW<[SBWriteResGroup2], (instregex "MOVUPDrr")>;
 392 def: InstRW<[SBWriteResGroup2], (instregex "MOVUPSrr")>;
 393 def: InstRW<[SBWriteResGroup2], (instregex "ORPDrr")>;
 394 def: InstRW<[SBWriteResGroup2], (instregex "ORPSrr")>;
 395 def: InstRW<[SBWriteResGroup2], (instregex "RETQ")>;
 396 def: InstRW<[SBWriteResGroup2], (instregex "SHUFPDrri")>;
 397 def: InstRW<[SBWriteResGroup2], (instregex "SHUFPSrri")>;
 398 def: InstRW<[SBWriteResGroup2], (instregex "ST_FPrr")>;
 399 def: InstRW<[SBWriteResGroup2], (instregex "ST_Frr")>;
 400 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKHPDrr")>;
 401 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKHPSrr")>;
 402 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKLPDrr")>;
 403 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKLPSrr")>;
 404 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPDYrr")>;
 405 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPDrr")>;
 406 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPSYrr")>;
 407 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPSrr")>;
 408 def: InstRW<[SBWriteResGroup2], (instregex "VANDPDYrr")>;
 409 def: InstRW<[SBWriteResGroup2], (instregex "VANDPDrr")>;
 410 def: InstRW<[SBWriteResGroup2], (instregex "VANDPSYrr")>;
 411 def: InstRW<[SBWriteResGroup2], (instregex "VANDPSrr")>;
 412 def: InstRW<[SBWriteResGroup2], (instregex "VEXTRACTF128rr")>;
 413 def: InstRW<[SBWriteResGroup2], (instregex "VINSERTF128rr")>;
 414 def: InstRW<[SBWriteResGroup2], (instregex "VINSERTPSrr")>;
 415 def: InstRW<[SBWriteResGroup2], (instregex "VMOV64toPQIrr")>;
 416 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPDYrr")>;
 417 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPDrr")>;
 418 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPSYrr")>;
 419 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPSrr")>;
 420 def: InstRW<[SBWriteResGroup2], (instregex "VMOVDDUPYrr")>;
 421 def: InstRW<[SBWriteResGroup2], (instregex "VMOVDDUPrr")>;
 422 def: InstRW<[SBWriteResGroup2], (instregex "VMOVDI2PDIrr")>;
 423 def: InstRW<[SBWriteResGroup2], (instregex "VMOVHLPSrr")>;
 424 def: InstRW<[SBWriteResGroup2], (instregex "VMOVHLPSrr")>;
 425 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSDrr")>;
 426 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSHDUPYrr")>;
 427 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSHDUPrr")>;
 428 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSLDUPYrr")>;
 429 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSLDUPrr")>;
 430 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSSrr")>;
 431 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPDYrr")>;
 432 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPDrr")>;
 433 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPSYrr")>;
 434 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPSrr")>;
 435 def: InstRW<[SBWriteResGroup2], (instregex "VORPDYrr")>;
 436 def: InstRW<[SBWriteResGroup2], (instregex "VORPDrr")>;
 437 def: InstRW<[SBWriteResGroup2], (instregex "VORPSYrr")>;
 438 def: InstRW<[SBWriteResGroup2], (instregex "VORPSrr")>;
 439 def: InstRW<[SBWriteResGroup2], (instregex "VPERM2F128rr")>;
 440 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDYri")>;
 441 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDYrr")>;
 442 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDri")>;
 443 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDrr")>;
 444 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSYri")>;
 445 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSYrr")>;
 446 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSri")>;
 447 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrr")>;
 448 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPDYrri")>;
 449 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPDrri")>;
 450 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPSYrri")>;
 451 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPSrri")>;
 452 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPDYrr")>;
 453 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPDrr")>;
 454 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPSYrr")>;
 455 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPSrr")>;
 456 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPDYrr")>;
 457 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPDrr")>;
 458 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPSYrr")>;
 459 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPSrr")>;
 460 def: InstRW<[SBWriteResGroup2], (instregex "VXORPDYrr")>;
 461 def: InstRW<[SBWriteResGroup2], (instregex "VXORPDrr")>;
 462 def: InstRW<[SBWriteResGroup2], (instregex "VXORPSYrr")>;
 463 def: InstRW<[SBWriteResGroup2], (instregex "VXORPSrr")>;
 464 def: InstRW<[SBWriteResGroup2], (instregex "XORPDrr")>;
 465 def: InstRW<[SBWriteResGroup2], (instregex "XORPSrr")>;
 466
 467 def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {
 468   let Latency = 1;
 469   let NumMicroOps = 1;
 470   let ResourceCycles = [1];
 471 }
 472 def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>;
 473
 474 def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
 475   let Latency = 1;
 476   let NumMicroOps = 1;
 477   let ResourceCycles = [1];
 478 }
 479 def: InstRW<[SBWriteResGroup4], (instregex "BLENDPDrri")>;
 480 def: InstRW<[SBWriteResGroup4], (instregex "BLENDPSrri")>;
 481 def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8")>;
 482 def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)rr")>;
 483 def: InstRW<[SBWriteResGroup4], (instregex "BTC(16|32|64)ri8")>;
 484 def: InstRW<[SBWriteResGroup4], (instregex "BTC(16|32|64)rr")>;
 485 def: InstRW<[SBWriteResGroup4], (instregex "BTR(16|32|64)ri8")>;
 486 def: InstRW<[SBWriteResGroup4], (instregex "BTR(16|32|64)rr")>;
 487 def: InstRW<[SBWriteResGroup4], (instregex "BTS(16|32|64)ri8")>;
 488 def: InstRW<[SBWriteResGroup4], (instregex "BTS(16|32|64)rr")>;
 489 def: InstRW<[SBWriteResGroup4], (instregex "CDQ")>;
 490 def: InstRW<[SBWriteResGroup4], (instregex "CQO")>;
 491 def: InstRW<[SBWriteResGroup4], (instregex "LAHF")>;
 492 def: InstRW<[SBWriteResGroup4], (instregex "SAHF")>;
 493 def: InstRW<[SBWriteResGroup4], (instregex "SAR(16|32|64)ri")>;
 494 def: InstRW<[SBWriteResGroup4], (instregex "SAR8ri")>;
 495 def: InstRW<[SBWriteResGroup4], (instregex "SETAEr")>;
 496 def: InstRW<[SBWriteResGroup4], (instregex "SETBr")>;
 497 def: InstRW<[SBWriteResGroup4], (instregex "SETEr")>;
 498 def: InstRW<[SBWriteResGroup4], (instregex "SETGEr")>;
 499 def: InstRW<[SBWriteResGroup4], (instregex "SETGr")>;
 500 def: InstRW<[SBWriteResGroup4], (instregex "SETLEr")>;
 501 def: InstRW<[SBWriteResGroup4], (instregex "SETLr")>;
 502 def: InstRW<[SBWriteResGroup4], (instregex "SETNEr")>;
 503 def: InstRW<[SBWriteResGroup4], (instregex "SETNOr")>;
 504 def: InstRW<[SBWriteResGroup4], (instregex "SETNPr")>;
 505 def: InstRW<[SBWriteResGroup4], (instregex "SETNSr")>;
 506 def: InstRW<[SBWriteResGroup4], (instregex "SETOr")>;
 507 def: InstRW<[SBWriteResGroup4], (instregex "SETPr")>;
 508 def: InstRW<[SBWriteResGroup4], (instregex "SETSr")>;
 509 def: InstRW<[SBWriteResGroup4], (instregex "SHL(16|32|64)ri")>;
 510 def: InstRW<[SBWriteResGroup4], (instregex "SHL(16|32|64)r1")>;
 511 def: InstRW<[SBWriteResGroup4], (instregex "SHL8r1")>;
 512 def: InstRW<[SBWriteResGroup4], (instregex "SHL8ri")>;
 513 def: InstRW<[SBWriteResGroup4], (instregex "SHR(16|32|64)ri")>;
 514 def: InstRW<[SBWriteResGroup4], (instregex "SHR8ri")>;
 515 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDYrri")>;
 516 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDrri")>;
 517 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSYrri")>;
 518 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSrri")>;
 519 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQAYrr")>;
 520 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQArr")>;
 521 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQUYrr")>;
 522 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQUrr")>;
 523
 524 def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
 525   let Latency = 1;
 526   let NumMicroOps = 1;
 527   let ResourceCycles = [1];
 528 }
 529 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr64")>;
 530 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSDrr64")>;
 531 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSWrr64")>;
 532 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PADDQirr")>;
 533 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PALIGNR64irr")>;
 534 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSHUFBrr64")>;
 535 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNBrr64")>;
 536 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNDrr64")>;
 537 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNWrr64")>;
 538 def: InstRW<[SBWriteResGroup5], (instregex "PABSBrr")>;
 539 def: InstRW<[SBWriteResGroup5], (instregex "PABSDrr")>;
 540 def: InstRW<[SBWriteResGroup5], (instregex "PABSWrr")>;
 541 def: InstRW<[SBWriteResGroup5], (instregex "PACKSSDWrr")>;
 542 def: InstRW<[SBWriteResGroup5], (instregex "PACKSSWBrr")>;
 543 def: InstRW<[SBWriteResGroup5], (instregex "PACKUSDWrr")>;
 544 def: InstRW<[SBWriteResGroup5], (instregex "PACKUSWBrr")>;
 545 def: InstRW<[SBWriteResGroup5], (instregex "PADDBrr")>;
 546 def: InstRW<[SBWriteResGroup5], (instregex "PADDDrr")>;
 547 def: InstRW<[SBWriteResGroup5], (instregex "PADDQrr")>;
 548 def: InstRW<[SBWriteResGroup5], (instregex "PADDSBrr")>;
 549 def: InstRW<[SBWriteResGroup5], (instregex "PADDSWrr")>;
 550 def: InstRW<[SBWriteResGroup5], (instregex "PADDUSBrr")>;
 551 def: InstRW<[SBWriteResGroup5], (instregex "PADDUSWrr")>;
 552 def: InstRW<[SBWriteResGroup5], (instregex "PADDWrr")>;
 553 def: InstRW<[SBWriteResGroup5], (instregex "PALIGNRrri")>;
 554 def: InstRW<[SBWriteResGroup5], (instregex "PAVGBrr")>;
 555 def: InstRW<[SBWriteResGroup5], (instregex "PAVGWrr")>;
 556 def: InstRW<[SBWriteResGroup5], (instregex "PBLENDWrri")>;
 557 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQBrr")>;
 558 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQDrr")>;
 559 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQQrr")>;
 560 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQWrr")>;
 561 def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTBrr")>;
 562 def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTDrr")>;
 563 def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTWrr")>;
 564 def: InstRW<[SBWriteResGroup5], (instregex "PMAXSBrr")>;
 565 def: InstRW<[SBWriteResGroup5], (instregex "PMAXSDrr")>;
 566 def: InstRW<[SBWriteResGroup5], (instregex "PMAXSWrr")>;
 567 def: InstRW<[SBWriteResGroup5], (instregex "PMAXUBrr")>;
 568 def: InstRW<[SBWriteResGroup5], (instregex "PMAXUDrr")>;
 569 def: InstRW<[SBWriteResGroup5], (instregex "PMAXUWrr")>;
 570 def: InstRW<[SBWriteResGroup5], (instregex "PMINSBrr")>;
 571 def: InstRW<[SBWriteResGroup5], (instregex "PMINSDrr")>;
 572 def: InstRW<[SBWriteResGroup5], (instregex "PMINSWrr")>;
 573 def: InstRW<[SBWriteResGroup5], (instregex "PMINUBrr")>;
 574 def: InstRW<[SBWriteResGroup5], (instregex "PMINUDrr")>;
 575 def: InstRW<[SBWriteResGroup5], (instregex "PMINUWrr")>;
 576 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBDrr")>;
 577 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBQrr")>;
 578 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBWrr")>;
 579 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXDQrr")>;
 580 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXWDrr")>;
 581 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXWQrr")>;
 582 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBDrr")>;
 583 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBQrr")>;
 584 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBWrr")>;
 585 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXDQrr")>;
 586 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXWDrr")>;
 587 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXWQrr")>;
 588 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFBrr")>;
 589 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFDri")>;
 590 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFHWri")>;
 591 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFLWri")>;
 592 def: InstRW<[SBWriteResGroup5], (instregex "PSIGNBrr128")>;
 593 def: InstRW<[SBWriteResGroup5], (instregex "PSIGNDrr128")>;
 594 def: InstRW<[SBWriteResGroup5], (instregex "PSIGNWrr128")>;
 595 def: InstRW<[SBWriteResGroup5], (instregex "PSLLDQri")>;
 596 def: InstRW<[SBWriteResGroup5], (instregex "PSRLDQri")>;
 597 def: InstRW<[SBWriteResGroup5], (instregex "PSUBBrr")>;
 598 def: InstRW<[SBWriteResGroup5], (instregex "PSUBDrr")>;
 599 def: InstRW<[SBWriteResGroup5], (instregex "PSUBQrr")>;
 600 def: InstRW<[SBWriteResGroup5], (instregex "PSUBSBrr")>;
 601 def: InstRW<[SBWriteResGroup5], (instregex "PSUBSWrr")>;
 602 def: InstRW<[SBWriteResGroup5], (instregex "PSUBUSBrr")>;
 603 def: InstRW<[SBWriteResGroup5], (instregex "PSUBUSWrr")>;
 604 def: InstRW<[SBWriteResGroup5], (instregex "PSUBWrr")>;
 605 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHBWrr")>;
 606 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHDQrr")>;
 607 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHQDQrr")>;
 608 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHWDrr")>;
 609 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLBWrr")>;
 610 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLDQrr")>;
 611 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLQDQrr")>;
 612 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLWDrr")>;
 613 def: InstRW<[SBWriteResGroup5], (instregex "VPABSBrr")>;
 614 def: InstRW<[SBWriteResGroup5], (instregex "VPABSDrr")>;
 615 def: InstRW<[SBWriteResGroup5], (instregex "VPABSWrr")>;
 616 def: InstRW<[SBWriteResGroup5], (instregex "VPACKSSDWrr")>;
 617 def: InstRW<[SBWriteResGroup5], (instregex "VPACKSSWBrr")>;
 618 def: InstRW<[SBWriteResGroup5], (instregex "VPACKUSDWrr")>;
 619 def: InstRW<[SBWriteResGroup5], (instregex "VPACKUSWBrr")>;
 620 def: InstRW<[SBWriteResGroup5], (instregex "VPADDBrr")>;
 621 def: InstRW<[SBWriteResGroup5], (instregex "VPADDDrr")>;
 622 def: InstRW<[SBWriteResGroup5], (instregex "VPADDQrr")>;
 623 def: InstRW<[SBWriteResGroup5], (instregex "VPADDSBrr")>;
 624 def: InstRW<[SBWriteResGroup5], (instregex "VPADDSWrr")>;
 625 def: InstRW<[SBWriteResGroup5], (instregex "VPADDUSBrr")>;
 626 def: InstRW<[SBWriteResGroup5], (instregex "VPADDUSWrr")>;
 627 def: InstRW<[SBWriteResGroup5], (instregex "VPADDWrr")>;
 628 def: InstRW<[SBWriteResGroup5], (instregex "VPALIGNRrri")>;
 629 def: InstRW<[SBWriteResGroup5], (instregex "VPAVGBrr")>;
 630 def: InstRW<[SBWriteResGroup5], (instregex "VPAVGWrr")>;
 631 def: InstRW<[SBWriteResGroup5], (instregex "VPBLENDWrri")>;
 632 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQBrr")>;
 633 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQDrr")>;
 634 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQQrr")>;
 635 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQWrr")>;
 636 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTBrr")>;
 637 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTDrr")>;
 638 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTWrr")>;
 639 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSBrr")>;
 640 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSDrr")>;
 641 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSWrr")>;
 642 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUBrr")>;
 643 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUDrr")>;
 644 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUWrr")>;
 645 def: InstRW<[SBWriteResGroup5], (instregex "VPMINSBrr")>;
 646 def: InstRW<[SBWriteResGroup5], (instregex "VPMINSDrr")>;
 647 def: InstRW<[SBWriteResGroup5], (instregex "VPMINSWrr")>;
 648 def: InstRW<[SBWriteResGroup5], (instregex "VPMINUBrr")>;
 649 def: InstRW<[SBWriteResGroup5], (instregex "VPMINUDrr")>;
 650 def: InstRW<[SBWriteResGroup5], (instregex "VPMINUWrr")>;
 651 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBDrr")>;
 652 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBQrr")>;
 653 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBWrr")>;
 654 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXDQrr")>;
 655 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXWDrr")>;
 656 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXWQrr")>;
 657 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBDrr")>;
 658 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBQrr")>;
 659 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBWrr")>;
 660 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXDQrr")>;
 661 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXWDrr")>;
 662 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXWQrr")>;
 663 def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFBrr")>;
 664 def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFDri")>;
 665 def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFHWri")>;
 666 def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFLWri")>;
 667 def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNBrr128")>;
 668 def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNDrr128")>;
 669 def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNWrr128")>;
 670 def: InstRW<[SBWriteResGroup5], (instregex "VPSLLDQri")>;
 671 def: InstRW<[SBWriteResGroup5], (instregex "VPSRLDQri")>;
 672 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBBrr")>;
 673 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBDrr")>;
 674 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBQrr")>;
 675 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBSBrr")>;
 676 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBSWrr")>;
 677 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBUSBrr")>;
 678 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBUSWrr")>;
 679 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBWrr")>;
 680 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHBWrr")>;
 681 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHDQrr")>;
 682 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHQDQrr")>;
 683 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHWDrr")>;
 684 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLBWrr")>;
 685 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLDQrr")>;
 686 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLQDQrr")>;
 687 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLWDrr")>;
 688
 689 def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
 690   let Latency = 1;
 691   let NumMicroOps = 1;
 692   let ResourceCycles = [1];
 693 }
 694 def: InstRW<[SBWriteResGroup6], (instregex "ADD(16|32|64)ri")>;
 695 def: InstRW<[SBWriteResGroup6], (instregex "ADD(16|32|64)rr")>;
 696 def: InstRW<[SBWriteResGroup6], (instregex "ADD8i8")>;
 697 def: InstRW<[SBWriteResGroup6], (instregex "ADD8ri")>;
 698 def: InstRW<[SBWriteResGroup6], (instregex "ADD8rr")>;
 699 def: InstRW<[SBWriteResGroup6], (instregex "AND(16|32|64)ri")>;
 700 def: InstRW<[SBWriteResGroup6], (instregex "AND(16|32|64)rr")>;
 701 def: InstRW<[SBWriteResGroup6], (instregex "AND8i8")>;
 702 def: InstRW<[SBWriteResGroup6], (instregex "AND8ri")>;
 703 def: InstRW<[SBWriteResGroup6], (instregex "AND8rr")>;
 704 def: InstRW<[SBWriteResGroup6], (instregex "CBW")>;
 705 def: InstRW<[SBWriteResGroup6], (instregex "CMC")>;
 706 def: InstRW<[SBWriteResGroup6], (instregex "CMP(16|32|64)ri")>;
 707 def: InstRW<[SBWriteResGroup6], (instregex "CMP(16|32|64)rr")>;
 708 def: InstRW<[SBWriteResGroup6], (instregex "CMP8i8")>;
 709 def: InstRW<[SBWriteResGroup6], (instregex "CMP8ri")>;
 710 def: InstRW<[SBWriteResGroup6], (instregex "CMP8rr")>;
 711 def: InstRW<[SBWriteResGroup6], (instregex "CWDE")>;
 712 def: InstRW<[SBWriteResGroup6], (instregex "DEC(16|32|64)r")>;
 713 def: InstRW<[SBWriteResGroup6], (instregex "DEC8r")>;
 714 def: InstRW<[SBWriteResGroup6], (instregex "INC(16|32|64)r")>;
 715 def: InstRW<[SBWriteResGroup6], (instregex "INC8r")>;
 716 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVD64from64rr")>;
 717 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr")>;
 718 def: InstRW<[SBWriteResGroup6], (instregex "MOV(16|32|64)rr")>;
 719 def: InstRW<[SBWriteResGroup6], (instregex "MOV8ri")>;
 720 def: InstRW<[SBWriteResGroup6], (instregex "MOV8rr")>;
 721 def: InstRW<[SBWriteResGroup6], (instregex "MOVDQArr")>;
 722 def: InstRW<[SBWriteResGroup6], (instregex "MOVDQUrr")>;
 723 def: InstRW<[SBWriteResGroup6], (instregex "MOVPQI2QIrr")>;
 724 def: InstRW<[SBWriteResGroup6], (instregex "MOVSX(16|32|64)rr16")>;
 725 def: InstRW<[SBWriteResGroup6], (instregex "MOVSX(16|32|64)rr32")>;
 726 def: InstRW<[SBWriteResGroup6], (instregex "MOVSX(16|32|64)rr8")>;
 727 def: InstRW<[SBWriteResGroup6], (instregex "MOVZX(16|32|64)rr16")>;
 728 def: InstRW<[SBWriteResGroup6], (instregex "MOVZX(16|32|64)rr8")>;
 729 def: InstRW<[SBWriteResGroup6], (instregex "NEG(16|32|64)r")>;
 730 def: InstRW<[SBWriteResGroup6], (instregex "NEG8r")>;
 731 def: InstRW<[SBWriteResGroup6], (instregex "NOT(16|32|64)r")>;
 732 def: InstRW<[SBWriteResGroup6], (instregex "NOT8r")>;
 733 def: InstRW<[SBWriteResGroup6], (instregex "OR(16|32|64)ri")>;
 734 def: InstRW<[SBWriteResGroup6], (instregex "OR(16|32|64)rr")>;
 735 def: InstRW<[SBWriteResGroup6], (instregex "OR8i8")>;
 736 def: InstRW<[SBWriteResGroup6], (instregex "OR8ri")>;
 737 def: InstRW<[SBWriteResGroup6], (instregex "OR8rr")>;
 738 def: InstRW<[SBWriteResGroup6], (instregex "PANDNrr")>;
 739 def: InstRW<[SBWriteResGroup6], (instregex "PANDrr")>;
 740 def: InstRW<[SBWriteResGroup6], (instregex "PORrr")>;
 741 def: InstRW<[SBWriteResGroup6], (instregex "PXORrr")>;
 742 def: InstRW<[SBWriteResGroup6], (instregex "STC")>;
 743 def: InstRW<[SBWriteResGroup6], (instregex "SUB(16|32|64)ri")>;
 744 def: InstRW<[SBWriteResGroup6], (instregex "SUB(16|32|64)rr")>;
 745 def: InstRW<[SBWriteResGroup6], (instregex "SUB8i8")>;
 746 def: InstRW<[SBWriteResGroup6], (instregex "SUB8ri")>;
 747 def: InstRW<[SBWriteResGroup6], (instregex "SUB8rr")>;
 748 def: InstRW<[SBWriteResGroup6], (instregex "TEST(16|32|64)rr")>;
 749 def: InstRW<[SBWriteResGroup6], (instregex "TEST8i8")>;
 750 def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>;
 751 def: InstRW<[SBWriteResGroup6], (instregex "TEST8rr")>;
 752 def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQI2QIrr")>;
 753 def: InstRW<[SBWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>;
 754 def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>;
 755 def: InstRW<[SBWriteResGroup6], (instregex "VPANDrr")>;
 756 def: InstRW<[SBWriteResGroup6], (instregex "VPORrr")>;
 757 def: InstRW<[SBWriteResGroup6], (instregex "VPXORrr")>;
 758 def: InstRW<[SBWriteResGroup6], (instregex "XOR(16|32|64)ri")>;
 759 def: InstRW<[SBWriteResGroup6], (instregex "XOR(16|32|64)rr")>;
 760 def: InstRW<[SBWriteResGroup6], (instregex "XOR8i8")>;
 761 def: InstRW<[SBWriteResGroup6], (instregex "XOR8ri")>;
 762 def: InstRW<[SBWriteResGroup6], (instregex "XOR8rr")>;
 763
 764 def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
 765   let Latency = 2;
 766   let NumMicroOps = 1;
 767   let ResourceCycles = [1];
 768 }
 769 def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPDrr")>;
 770 def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPSrr")>;
 771 def: InstRW<[SBWriteResGroup7], (instregex "MOVPDI2DIrr")>;
 772 def: InstRW<[SBWriteResGroup7], (instregex "MOVPQIto64rr")>;
 773 def: InstRW<[SBWriteResGroup7], (instregex "PMOVMSKBrr")>;
 774 def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPDYrr")>;
 775 def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPDrr")>;
 776 def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPSYrr")>;
 777 def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPSrr")>;
 778 def: InstRW<[SBWriteResGroup7], (instregex "VMOVPDI2DIrr")>;
 779 def: InstRW<[SBWriteResGroup7], (instregex "VMOVPQIto64rr")>;
 780
 781 def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> {
 782   let Latency = 2;
 783   let NumMicroOps = 2;
 784   let ResourceCycles = [2];
 785 }
 786 def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPDrr0")>;
 787 def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPSrr0")>;
 788 def: InstRW<[SBWriteResGroup9], (instregex "ROL(16|32|64)ri")>;
 789 def: InstRW<[SBWriteResGroup9], (instregex "ROL8ri")>;
 790 def: InstRW<[SBWriteResGroup9], (instregex "ROR(16|32|64)ri")>;
 791 def: InstRW<[SBWriteResGroup9], (instregex "ROR8ri")>;
 792 def: InstRW<[SBWriteResGroup9], (instregex "SETAr")>;
 793 def: InstRW<[SBWriteResGroup9], (instregex "SETBEr")>;
 794 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDYrr")>;
 795 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDrr")>;
 796 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPSYrr")>;
 797 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPSrr")>;
 798
 799 def SBWriteResGroup10 : SchedWriteRes<[SBPort15]> {
 800   let Latency = 2;
 801   let NumMicroOps = 2;
 802   let ResourceCycles = [2];
 803 }
 804 def: InstRW<[SBWriteResGroup10], (instregex "VPBLENDVBrr")>;
 805
 806 def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
 807   let Latency = 2;
 808   let NumMicroOps = 2;
 809   let ResourceCycles = [2];
 810 }
 811 def: InstRW<[SBWriteResGroup11], (instregex "SCASB")>;
 812 def: InstRW<[SBWriteResGroup11], (instregex "SCASL")>;
 813 def: InstRW<[SBWriteResGroup11], (instregex "SCASQ")>;
 814 def: InstRW<[SBWriteResGroup11], (instregex "SCASW")>;
 815
 816 def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> {
 817   let Latency = 2;
 818   let NumMicroOps = 2;
 819   let ResourceCycles = [1,1];
 820 }
 821 def: InstRW<[SBWriteResGroup12], (instregex "COMISDrr")>;
 822 def: InstRW<[SBWriteResGroup12], (instregex "COMISSrr")>;
 823 def: InstRW<[SBWriteResGroup12], (instregex "UCOMISDrr")>;
 824 def: InstRW<[SBWriteResGroup12], (instregex "UCOMISSrr")>;
 825 def: InstRW<[SBWriteResGroup12], (instregex "VCOMISDrr")>;
 826 def: InstRW<[SBWriteResGroup12], (instregex "VCOMISSrr")>;
 827 def: InstRW<[SBWriteResGroup12], (instregex "VUCOMISDrr")>;
 828 def: InstRW<[SBWriteResGroup12], (instregex "VUCOMISSrr")>;
 829
 830 def SBWriteResGroup13 : SchedWriteRes<[SBPort0,SBPort5]> {
 831   let Latency = 2;
 832   let NumMicroOps = 2;
 833   let ResourceCycles = [1,1];
 834 }
 835 def: InstRW<[SBWriteResGroup13], (instregex "CVTPS2PDrr")>;
 836 def: InstRW<[SBWriteResGroup13], (instregex "PTESTrr")>;
 837 def: InstRW<[SBWriteResGroup13], (instregex "VCVTPS2PDYrr")>;
 838 def: InstRW<[SBWriteResGroup13], (instregex "VCVTPS2PDrr")>;
 839 def: InstRW<[SBWriteResGroup13], (instregex "VPTESTYrr")>;
 840 def: InstRW<[SBWriteResGroup13], (instregex "VPTESTrr")>;
 841
 842 def SBWriteResGroup14 : SchedWriteRes<[SBPort0,SBPort15]> {
 843   let Latency = 2;
 844   let NumMicroOps = 2;
 845   let ResourceCycles = [1,1];
 846 }
 847 def: InstRW<[SBWriteResGroup14], (instregex "PSLLDrr")>;
 848 def: InstRW<[SBWriteResGroup14], (instregex "PSLLQrr")>;
 849 def: InstRW<[SBWriteResGroup14], (instregex "PSLLWrr")>;
 850 def: InstRW<[SBWriteResGroup14], (instregex "PSRADrr")>;
 851 def: InstRW<[SBWriteResGroup14], (instregex "PSRAWrr")>;
 852 def: InstRW<[SBWriteResGroup14], (instregex "PSRLDrr")>;
 853 def: InstRW<[SBWriteResGroup14], (instregex "PSRLQrr")>;
 854 def: InstRW<[SBWriteResGroup14], (instregex "PSRLWrr")>;
 855 def: InstRW<[SBWriteResGroup14], (instregex "VPSLLDrr")>;
 856 def: InstRW<[SBWriteResGroup14], (instregex "VPSLLQrr")>;
 857 def: InstRW<[SBWriteResGroup14], (instregex "VPSLLWrr")>;
 858 def: InstRW<[SBWriteResGroup14], (instregex "VPSRADrr")>;
 859 def: InstRW<[SBWriteResGroup14], (instregex "VPSRAWrr")>;
 860 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLDrr")>;
 861 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLQrr")>;
 862 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLWrr")>;
 863
 864 def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
 865   let Latency = 2;
 866   let NumMicroOps = 2;
 867   let ResourceCycles = [1,1];
 868 }
 869 def: InstRW<[SBWriteResGroup15], (instregex "CWD")>;
 870 def: InstRW<[SBWriteResGroup15], (instregex "FNSTSW16r")>;
 871
 872 def SBWriteResGroup16 : SchedWriteRes<[SBPort1,SBPort05]> {
 873   let Latency = 2;
 874   let NumMicroOps = 2;
 875   let ResourceCycles = [1,1];
 876 }
 877 def: InstRW<[SBWriteResGroup16], (instregex "BSWAP(16|32|64)r")>;
 878
 879 def SBWriteResGroup17 : SchedWriteRes<[SBPort5,SBPort15]> {
 880   let Latency = 2;
 881   let NumMicroOps = 2;
 882   let ResourceCycles = [1,1];
 883 }
 884 def: InstRW<[SBWriteResGroup17], (instregex "PINSRBrr")>;
 885 def: InstRW<[SBWriteResGroup17], (instregex "PINSRDrr")>;
 886 def: InstRW<[SBWriteResGroup17], (instregex "PINSRQrr")>;
 887 def: InstRW<[SBWriteResGroup17], (instregex "PINSRWrri")>;
 888 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRBrr")>;
 889 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRDrr")>;
 890 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRQrr")>;
 891 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRWrri")>;
 892
 893 def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
 894   let Latency = 2;
 895   let NumMicroOps = 2;
 896   let ResourceCycles = [1,1];
 897 }
 898 def: InstRW<[SBWriteResGroup18], (instregex "JRCXZ")>;
 899 def: InstRW<[SBWriteResGroup18], (instregex "MMX_MOVDQ2Qrr")>;
 900
 901 def SBWriteResGroup19 : SchedWriteRes<[SBPort05,SBPort015]> {
 902   let Latency = 2;
 903   let NumMicroOps = 2;
 904   let ResourceCycles = [1,1];
 905 }
 906 def: InstRW<[SBWriteResGroup19], (instregex "ADC(16|32|64)ri")>;
 907 def: InstRW<[SBWriteResGroup19], (instregex "ADC(16|32|64)rr")>;
 908 def: InstRW<[SBWriteResGroup19], (instregex "ADC8ri")>;
 909 def: InstRW<[SBWriteResGroup19], (instregex "ADC8rr")>;
 910 def: InstRW<[SBWriteResGroup19], (instregex "CMOVAE(16|32|64)rr")>;
 911 def: InstRW<[SBWriteResGroup19], (instregex "CMOVB(16|32|64)rr")>;
 912 def: InstRW<[SBWriteResGroup19], (instregex "CMOVE(16|32|64)rr")>;
 913 def: InstRW<[SBWriteResGroup19], (instregex "CMOVG(16|32|64)rr")>;
 914 def: InstRW<[SBWriteResGroup19], (instregex "CMOVGE(16|32|64)rr")>;
 915 def: InstRW<[SBWriteResGroup19], (instregex "CMOVL(16|32|64)rr")>;
 916 def: InstRW<[SBWriteResGroup19], (instregex "CMOVLE(16|32|64)rr")>;
 917 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNE(16|32|64)rr")>;
 918 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNO(16|32|64)rr")>;
 919 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNP(16|32|64)rr")>;
 920 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNS(16|32|64)rr")>;
 921 def: InstRW<[SBWriteResGroup19], (instregex "CMOVO(16|32|64)rr")>;
 922 def: InstRW<[SBWriteResGroup19], (instregex "CMOVP(16|32|64)rr")>;
 923 def: InstRW<[SBWriteResGroup19], (instregex "CMOVS(16|32|64)rr")>;
 924 def: InstRW<[SBWriteResGroup19], (instregex "SBB(16|32|64)ri")>;
 925 def: InstRW<[SBWriteResGroup19], (instregex "SBB(16|32|64)rr")>;
 926 def: InstRW<[SBWriteResGroup19], (instregex "SBB8ri")>;
 927 def: InstRW<[SBWriteResGroup19], (instregex "SBB8rr")>;
 928 def: InstRW<[SBWriteResGroup19], (instregex "SHLD(16|32|64)rri8")>;
 929 def: InstRW<[SBWriteResGroup19], (instregex "SHRD(16|32|64)rri8")>;
 930
 931 def SBWriteResGroup20 : SchedWriteRes<[SBPort0]> {
 932   let Latency = 3;
 933   let NumMicroOps = 1;
 934   let ResourceCycles = [1];
 935 }
 936 def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr64")>;
 937 def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULHRSWrr64")>;
 938 def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULUDQirr")>;
 939 def: InstRW<[SBWriteResGroup20], (instregex "PMADDUBSWrr")>;
 940 def: InstRW<[SBWriteResGroup20], (instregex "PMADDWDrr")>;
 941 def: InstRW<[SBWriteResGroup20], (instregex "PMULDQrr")>;
 942 def: InstRW<[SBWriteResGroup20], (instregex "PMULHRSWrr")>;
 943 def: InstRW<[SBWriteResGroup20], (instregex "PMULHUWrr")>;
 944 def: InstRW<[SBWriteResGroup20], (instregex "PMULHWrr")>;
 945 def: InstRW<[SBWriteResGroup20], (instregex "PMULLDrr")>;
 946 def: InstRW<[SBWriteResGroup20], (instregex "PMULLWrr")>;
 947 def: InstRW<[SBWriteResGroup20], (instregex "PMULUDQrr")>;
 948 def: InstRW<[SBWriteResGroup20], (instregex "PSADBWrr")>;
 949 def: InstRW<[SBWriteResGroup20], (instregex "VPMADDUBSWrr")>;
 950 def: InstRW<[SBWriteResGroup20], (instregex "VPMADDWDrr")>;
 951 def: InstRW<[SBWriteResGroup20], (instregex "VPMULDQrr")>;
 952 def: InstRW<[SBWriteResGroup20], (instregex "VPMULHRSWrr")>;
 953 def: InstRW<[SBWriteResGroup20], (instregex "VPMULHUWrr")>;
 954 def: InstRW<[SBWriteResGroup20], (instregex "VPMULHWrr")>;
 955 def: InstRW<[SBWriteResGroup20], (instregex "VPMULLDrr")>;
 956 def: InstRW<[SBWriteResGroup20], (instregex "VPMULLWrr")>;
 957 def: InstRW<[SBWriteResGroup20], (instregex "VPMULUDQrr")>;
 958 def: InstRW<[SBWriteResGroup20], (instregex "VPSADBWrr")>;
 959
 960 def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
 961   let Latency = 3;
 962   let NumMicroOps = 1;
 963   let ResourceCycles = [1];
 964 }
 965 def: InstRW<[SBWriteResGroup21], (instregex "ADDPDrr")>;
 966 def: InstRW<[SBWriteResGroup21], (instregex "ADDPSrr")>;
 967 def: InstRW<[SBWriteResGroup21], (instregex "ADDSDrr")>;
 968 def: InstRW<[SBWriteResGroup21], (instregex "ADDSSrr")>;
 969 def: InstRW<[SBWriteResGroup21], (instregex "ADDSUBPDrr")>;
 970 def: InstRW<[SBWriteResGroup21], (instregex "ADDSUBPSrr")>;
 971 def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0")>;
 972 def: InstRW<[SBWriteResGroup21], (instregex "ADD_FST0r")>;
 973 def: InstRW<[SBWriteResGroup21], (instregex "ADD_FrST0")>;
 974 def: InstRW<[SBWriteResGroup21], (instregex "BSF(16|32|64)rr")>;
 975 def: InstRW<[SBWriteResGroup21], (instregex "BSR(16|32|64)rr")>;
 976 def: InstRW<[SBWriteResGroup21], (instregex "CMPPDrri")>;
 977 def: InstRW<[SBWriteResGroup21], (instregex "CMPPSrri")>;
 978 def: InstRW<[SBWriteResGroup21], (instregex "CMPSDrr")>;
 979 def: InstRW<[SBWriteResGroup21], (instregex "CMPSSrr")>;
 980 def: InstRW<[SBWriteResGroup21], (instregex "CRC32r(16|32|64)r8")>;
 981 def: InstRW<[SBWriteResGroup21], (instregex "CRC32r(16|32|64)r64")>;
 982 def: InstRW<[SBWriteResGroup21], (instregex "CVTDQ2PSrr")>;
 983 def: InstRW<[SBWriteResGroup21], (instregex "CVTPS2DQrr")>;
 984 def: InstRW<[SBWriteResGroup21], (instregex "CVTTPS2DQrr")>;
 985 def: InstRW<[SBWriteResGroup21], (instregex "MAX(C?)PDrr")>;
 986 def: InstRW<[SBWriteResGroup21], (instregex "MAX(C?)PSrr")>;
 987 def: InstRW<[SBWriteResGroup21], (instregex "MAX(C?)SDrr")>;
 988 def: InstRW<[SBWriteResGroup21], (instregex "MAX(C?)SSrr")>;
 989 def: InstRW<[SBWriteResGroup21], (instregex "MIN(C?)PDrr")>;
 990 def: InstRW<[SBWriteResGroup21], (instregex "MIN(C?)PSrr")>;
 991 def: InstRW<[SBWriteResGroup21], (instregex "MIN(C?)SDrr")>;
 992 def: InstRW<[SBWriteResGroup21], (instregex "MIN(C?)SSrr")>;
 993 def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPI2PSirr")>;
 994 def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPS2PIirr")>;
 995 def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTTPS2PIirr")>;
 996 def: InstRW<[SBWriteResGroup21], (instregex "MUL8r")>;
 997 def: InstRW<[SBWriteResGroup21], (instregex "POPCNT(16|32|64)rr")>;
 998 def: InstRW<[SBWriteResGroup21], (instregex "PUSHFS64")>;
 999 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDPDr")>;
1000 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDPSr")>;
1001 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDSDr")>;
1002 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDSSr")>;
1003 def: InstRW<[SBWriteResGroup21], (instregex "SUBPDrr")>;
1004 def: InstRW<[SBWriteResGroup21], (instregex "SUBPSrr")>;
1005 def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FPrST0")>;
1006 def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FST0r")>;
1007 def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FrST0")>;
1008 def: InstRW<[SBWriteResGroup21], (instregex "SUBSDrr")>;
1009 def: InstRW<[SBWriteResGroup21], (instregex "SUBSSrr")>;
1010 def: InstRW<[SBWriteResGroup21], (instregex "SUB_FPrST0")>;
1011 def: InstRW<[SBWriteResGroup21], (instregex "SUB_FST0r")>;
1012 def: InstRW<[SBWriteResGroup21], (instregex "SUB_FrST0")>;
1013 def: InstRW<[SBWriteResGroup21], (instregex "VADDPDYrr")>;
1014 def: InstRW<[SBWriteResGroup21], (instregex "VADDPDrr")>;
1015 def: InstRW<[SBWriteResGroup21], (instregex "VADDPSYrr")>;
1016 def: InstRW<[SBWriteResGroup21], (instregex "VADDPSrr")>;
1017 def: InstRW<[SBWriteResGroup21], (instregex "VADDSDrr")>;
1018 def: InstRW<[SBWriteResGroup21], (instregex "VADDSSrr")>;
1019 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPDYrr")>;
1020 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPDrr")>;
1021 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPSYrr")>;
1022 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPSrr")>;
1023 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPDYrri")>;
1024 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPDrri")>;
1025 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPSYrri")>;
1026 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPSrri")>;
1027 def: InstRW<[SBWriteResGroup21], (instregex "VCMPSDrr")>;
1028 def: InstRW<[SBWriteResGroup21], (instregex "VCMPSSrr")>;
1029 def: InstRW<[SBWriteResGroup21], (instregex "VCVTDQ2PSYrr")>;
1030 def: InstRW<[SBWriteResGroup21], (instregex "VCVTDQ2PSrr")>;
1031 def: InstRW<[SBWriteResGroup21], (instregex "VCVTPS2DQYrr")>;
1032 def: InstRW<[SBWriteResGroup21], (instregex "VCVTPS2DQrr")>;
1033 def: InstRW<[SBWriteResGroup21], (instregex "VCVTTPS2DQYrr")>;
1034 def: InstRW<[SBWriteResGroup21], (instregex "VCVTTPS2DQrr")>;
1035 def: InstRW<[SBWriteResGroup21], (instregex "VMAX(C?)PDYrr")>;
1036 def: InstRW<[SBWriteResGroup21], (instregex "VMAX(C?)PDrr")>;
1037 def: InstRW<[SBWriteResGroup21], (instregex "VMAX(C?)PSYrr")>;
1038 def: InstRW<[SBWriteResGroup21], (instregex "VMAX(C?)PSrr")>;
1039 def: InstRW<[SBWriteResGroup21], (instregex "VMAX(C?)SDrr")>;
1040 def: InstRW<[SBWriteResGroup21], (instregex "VMAX(C?)SSrr")>;
1041 def: InstRW<[SBWriteResGroup21], (instregex "VMIN(C?)PDYrr")>;
1042 def: InstRW<[SBWriteResGroup21], (instregex "VMIN(C?)PDrr")>;
1043 def: InstRW<[SBWriteResGroup21], (instregex "VMIN(C?)PSYrr")>;
1044 def: InstRW<[SBWriteResGroup21], (instregex "VMIN(C?)PSrr")>;
1045 def: InstRW<[SBWriteResGroup21], (instregex "VMIN(C?)SDrr")>;
1046 def: InstRW<[SBWriteResGroup21], (instregex "VMIN(C?)SSrr")>;
1047 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDPDr")>;
1048 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDPSr")>;
1049 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDSDr")>;
1050 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDSSr")>;
1051 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDYPDr")>;
1052 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDYPSr")>;
1053 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPDYrr")>;
1054 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPDrr")>;
1055 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPSYrr")>;
1056 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPSrr")>;
1057 def: InstRW<[SBWriteResGroup21], (instregex "VSUBSDrr")>;
1058 def: InstRW<[SBWriteResGroup21], (instregex "VSUBSSrr")>;
1059
1060 def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
1061   let Latency = 3;
1062   let NumMicroOps = 2;
1063   let ResourceCycles = [1,1];
1064 }
1065 def: InstRW<[SBWriteResGroup22], (instregex "EXTRACTPSrr")>;
1066 def: InstRW<[SBWriteResGroup22], (instregex "VEXTRACTPSrr")>;
1067
1068 def SBWriteResGroup23 : SchedWriteRes<[SBPort0,SBPort15]> {
1069   let Latency = 3;
1070   let NumMicroOps = 2;
1071   let ResourceCycles = [1,1];
1072 }
1073 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRBrr")>;
1074 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRDrr")>;
1075 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRQrr")>;
1076 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRWri")>;
1077 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRBrr")>;
1078 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRDrr")>;
1079 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRQrr")>;
1080 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRWri")>;
1081
1082 def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> {
1083   let Latency = 3;
1084   let NumMicroOps = 3;
1085   let ResourceCycles = [3];
1086 }
1087 def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(16|32|64)rCL")>;
1088 def: InstRW<[SBWriteResGroup23_2], (instregex "ROL8rCL")>;
1089 def: InstRW<[SBWriteResGroup23_2], (instregex "ROR(16|32|64)rCL")>;
1090 def: InstRW<[SBWriteResGroup23_2], (instregex "ROR8rCL")>;
1091 def: InstRW<[SBWriteResGroup23_2], (instregex "SAR(16|32|64)rCL")>;
1092 def: InstRW<[SBWriteResGroup23_2], (instregex "SAR8rCL")>;
1093 def: InstRW<[SBWriteResGroup23_2], (instregex "SHL(16|32|64)rCL")>;
1094 def: InstRW<[SBWriteResGroup23_2], (instregex "SHL8rCL")>;
1095 def: InstRW<[SBWriteResGroup23_2], (instregex "SHR(16|32|64)rCL")>;
1096 def: InstRW<[SBWriteResGroup23_2], (instregex "SHR8rCL")>;
1097
1098 def SBWriteResGroup24 : SchedWriteRes<[SBPort15]> {
1099   let Latency = 3;
1100   let NumMicroOps = 3;
1101   let ResourceCycles = [3];
1102 }
1103 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDSWrr64")>;
1104 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDWrr64")>;
1105 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDrr64")>;
1106 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBDrr64")>;
1107 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBSWrr64")>;
1108 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBWrr64")>;
1109 def: InstRW<[SBWriteResGroup24], (instregex "PHADDDrr")>;
1110 def: InstRW<[SBWriteResGroup24], (instregex "PHADDSWrr128")>;
1111 def: InstRW<[SBWriteResGroup24], (instregex "PHADDWrr")>;
1112 def: InstRW<[SBWriteResGroup24], (instregex "PHSUBDrr")>;
1113 def: InstRW<[SBWriteResGroup24], (instregex "PHSUBSWrr128")>;
1114 def: InstRW<[SBWriteResGroup24], (instregex "PHSUBWrr")>;
1115 def: InstRW<[SBWriteResGroup24], (instregex "VPHADDDrr")>;
1116 def: InstRW<[SBWriteResGroup24], (instregex "VPHADDSWrr128")>;
1117 def: InstRW<[SBWriteResGroup24], (instregex "VPHADDWrr")>;
1118 def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBDrr")>;
1119 def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBSWrr128")>;
1120 def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBWrr")>;
1121
1122 def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> {
1123   let Latency = 3;
1124   let NumMicroOps = 3;
1125   let ResourceCycles = [3];
1126 }
1127 def: InstRW<[SBWriteResGroup25], (instregex "ADC8i8")>;
1128 def: InstRW<[SBWriteResGroup25], (instregex "LEAVE64")>;
1129 def: InstRW<[SBWriteResGroup25], (instregex "OUT32rr")>;
1130 def: InstRW<[SBWriteResGroup25], (instregex "OUT8rr")>;
1131 def: InstRW<[SBWriteResGroup25], (instregex "SBB8i8")>;
1132 def: InstRW<[SBWriteResGroup25], (instregex "XADD(16|32|64)rr")>;
1133 def: InstRW<[SBWriteResGroup25], (instregex "XADD8rr")>;
1134
1135 def SBWriteResGroup25_2 : SchedWriteRes<[SBPort5,SBPort05]> {
1136   let Latency = 3;
1137   let NumMicroOps = 3;
1138   let ResourceCycles = [2,1];
1139 }
1140 def: InstRW<[SBWriteResGroup25_2], (instregex "CMOVBE_F")>;
1141 def: InstRW<[SBWriteResGroup25_2], (instregex "CMOVB_F")>;
1142 def: InstRW<[SBWriteResGroup25_2], (instregex "CMOVE_F")>;
1143 def: InstRW<[SBWriteResGroup25_2], (instregex "CMOVNBE_F")>;
1144 def: InstRW<[SBWriteResGroup25_2], (instregex "CMOVNB_F")>;
1145 def: InstRW<[SBWriteResGroup25_2], (instregex "CMOVNE_F")>;
1146 def: InstRW<[SBWriteResGroup25_2], (instregex "CMOVNP_F")>;
1147 def: InstRW<[SBWriteResGroup25_2], (instregex "CMOVP_F")>;
1148
1149 def SBWriteResGroup26 : SchedWriteRes<[SBPort05,SBPort015]> {
1150   let Latency = 3;
1151   let NumMicroOps = 3;
1152   let ResourceCycles = [2,1];
1153 }
1154 def: InstRW<[SBWriteResGroup26], (instregex "CMOVA(16|32|64)rr")>;
1155 def: InstRW<[SBWriteResGroup26], (instregex "CMOVBE(16|32|64)rr")>;
1156
1157 def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
1158   let Latency = 3;
1159   let NumMicroOps = 3;
1160   let ResourceCycles = [1,1,1];
1161 }
1162 def: InstRW<[SBWriteResGroup26_2], (instregex "COM_FIPr")>;
1163 def: InstRW<[SBWriteResGroup26_2], (instregex "COM_FIr")>;
1164 def: InstRW<[SBWriteResGroup26_2], (instregex "UCOM_FIPr")>;
1165 def: InstRW<[SBWriteResGroup26_2], (instregex "UCOM_FIr")>;
1166
1167 def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> {
1168   let Latency = 4;
1169   let NumMicroOps = 2;
1170   let ResourceCycles = [1,1];
1171 }
1172 def: InstRW<[SBWriteResGroup27], (instregex "MUL(16|32|64)r")>;
1173
1174 def SBWriteResGroup28 : SchedWriteRes<[SBPort1,SBPort5]> {
1175   let Latency = 4;
1176   let NumMicroOps = 2;
1177   let ResourceCycles = [1,1];
1178 }
1179 def: InstRW<[SBWriteResGroup28], (instregex "CVTDQ2PDrr")>;
1180 def: InstRW<[SBWriteResGroup28], (instregex "CVTPD2DQrr")>;
1181 def: InstRW<[SBWriteResGroup28], (instregex "CVTPD2PSrr")>;
1182 def: InstRW<[SBWriteResGroup28], (instregex "CVTSD2SSrr")>;
1183 def: InstRW<[SBWriteResGroup28], (instregex "CVTSI642SDrr")>;
1184 def: InstRW<[SBWriteResGroup28], (instregex "CVTSI2SDrr")>;
1185 def: InstRW<[SBWriteResGroup28], (instregex "CVTTPD2DQrr")>;
1186 def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPD2PIirr")>;
1187 def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPI2PDirr")>;
1188 def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTTPD2PIirr")>;
1189 def: InstRW<[SBWriteResGroup28], (instregex "VCVTDQ2PDYrr")>;
1190 def: InstRW<[SBWriteResGroup28], (instregex "VCVTDQ2PDrr")>;
1191 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2DQYrr")>;
1192 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2DQrr")>;
1193 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2PSYrr")>;
1194 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2PSrr")>;
1195 def: InstRW<[SBWriteResGroup28], (instregex "VCVTSD2SSrr")>;
1196 def: InstRW<[SBWriteResGroup28], (instregex "VCVTSI642SDrr")>;
1197 def: InstRW<[SBWriteResGroup28], (instregex "VCVTSI2SDrr")>;
1198 def: InstRW<[SBWriteResGroup28], (instregex "VCVTTPD2DQYrr")>;
1199 def: InstRW<[SBWriteResGroup28], (instregex "VCVTTPD2DQrr")>;
1200
1201 def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
1202   let Latency = 4;
1203   let NumMicroOps = 2;
1204   let ResourceCycles = [1,1];
1205 }
1206 def: InstRW<[SBWriteResGroup29], (instregex "MOV64sr")>;
1207
1208 def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> {
1209   let Latency = 4;
1210   let NumMicroOps = 4;
1211   let ResourceCycles = [1,3];
1212 }
1213 def: InstRW<[SBWriteResGroup29_2], (instregex "OUT32ir")>;
1214 def: InstRW<[SBWriteResGroup29_2], (instregex "OUT8ir")>;
1215 def: InstRW<[SBWriteResGroup29_2], (instregex "PAUSE")>;
1216
1217 def SBWriteResGroup29_3 : SchedWriteRes<[SBPort05,SBPort015]> {
1218   let Latency = 4;
1219   let NumMicroOps = 4;
1220   let ResourceCycles = [3,1];
1221 }
1222 def: InstRW<[SBWriteResGroup29_3], (instregex "SHLD(16|32|64)rrCL")>;
1223 def: InstRW<[SBWriteResGroup29_3], (instregex "SHRD(16|32|64)rrCL")>;
1224
1225 def SBWriteResGroup30 : SchedWriteRes<[SBPort0]> {
1226   let Latency = 5;
1227   let NumMicroOps = 1;
1228   let ResourceCycles = [1];
1229 }
1230 def: InstRW<[SBWriteResGroup30], (instregex "MULPDrr")>;
1231 def: InstRW<[SBWriteResGroup30], (instregex "MULPSrr")>;
1232 def: InstRW<[SBWriteResGroup30], (instregex "MULSDrr")>;
1233 def: InstRW<[SBWriteResGroup30], (instregex "MULSSrr")>;
1234 def: InstRW<[SBWriteResGroup30], (instregex "MUL_FPrST0")>;
1235 def: InstRW<[SBWriteResGroup30], (instregex "MUL_FST0r")>;
1236 def: InstRW<[SBWriteResGroup30], (instregex "MUL_FrST0")>;
1237 def: InstRW<[SBWriteResGroup30], (instregex "PCMPGTQrr")>;
1238 def: InstRW<[SBWriteResGroup30], (instregex "PHMINPOSUWrr128")>;
1239 def: InstRW<[SBWriteResGroup30], (instregex "RCPPSr")>;
1240 def: InstRW<[SBWriteResGroup30], (instregex "RCPSSr")>;
1241 def: InstRW<[SBWriteResGroup30], (instregex "RSQRTPSr")>;
1242 def: InstRW<[SBWriteResGroup30], (instregex "RSQRTSSr")>;
1243 def: InstRW<[SBWriteResGroup30], (instregex "VMULPDYrr")>;
1244 def: InstRW<[SBWriteResGroup30], (instregex "VMULPDrr")>;
1245 def: InstRW<[SBWriteResGroup30], (instregex "VMULPSYrr")>;
1246 def: InstRW<[SBWriteResGroup30], (instregex "VMULPSrr")>;
1247 def: InstRW<[SBWriteResGroup30], (instregex "VMULSDrr")>;
1248 def: InstRW<[SBWriteResGroup30], (instregex "VMULSSrr")>;
1249 def: InstRW<[SBWriteResGroup30], (instregex "VPCMPGTQrr")>;
1250 def: InstRW<[SBWriteResGroup30], (instregex "VPHMINPOSUWrr128")>;
1251 def: InstRW<[SBWriteResGroup30], (instregex "VRCPPSr")>;
1252 def: InstRW<[SBWriteResGroup30], (instregex "VRCPSSr")>;
1253 def: InstRW<[SBWriteResGroup30], (instregex "VRSQRTPSr")>;
1254 def: InstRW<[SBWriteResGroup30], (instregex "VRSQRTSSr")>;
1255
1256 def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
1257   let Latency = 5;
1258   let NumMicroOps = 1;
1259   let ResourceCycles = [1];
1260 }
1261 def: InstRW<[SBWriteResGroup31], (instregex "MOV(16|32|64)rm")>;
1262 def: InstRW<[SBWriteResGroup31], (instregex "MOV8rm")>;
1263 def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm16")>;
1264 def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm32")>;
1265 def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm8")>;
1266 def: InstRW<[SBWriteResGroup31], (instregex "MOVZX(16|32|64)rm16")>;
1267 def: InstRW<[SBWriteResGroup31], (instregex "MOVZX(16|32|64)rm8")>;
1268 def: InstRW<[SBWriteResGroup31], (instregex "PREFETCH")>;
1269
1270 def SBWriteResGroup32 : SchedWriteRes<[SBPort0,SBPort1]> {
1271   let Latency = 5;
1272   let NumMicroOps = 2;
1273   let ResourceCycles = [1,1];
1274 }
1275 def: InstRW<[SBWriteResGroup32], (instregex "CVTSD2SI64rr")>;
1276 def: InstRW<[SBWriteResGroup32], (instregex "CVTSD2SIrr")>;
1277 def: InstRW<[SBWriteResGroup32], (instregex "CVTSS2SI64rr")>;
1278 def: InstRW<[SBWriteResGroup32], (instregex "CVTSS2SIrr")>;
1279 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSD2SI64rr")>;
1280 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSD2SIrr")>;
1281 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSS2SI64rr")>;
1282 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSS2SIrr")>;
1283 def: InstRW<[SBWriteResGroup32], (instregex "VCVTSD2SI64rr")>;
1284 def: InstRW<[SBWriteResGroup32], (instregex "VCVTSD2SIrr")>;
1285 def: InstRW<[SBWriteResGroup32], (instregex "VCVTSS2SI64rr")>;
1286 def: InstRW<[SBWriteResGroup32], (instregex "VCVTSS2SIrr")>;
1287 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSD2SI64rr")>;
1288 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSD2SIrr")>;
1289 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSS2SI64rr")>;
1290 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSS2SIrr")>;
1291
1292 def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
1293   let Latency = 5;
1294   let NumMicroOps = 2;
1295   let ResourceCycles = [1,1];
1296 }
1297 def: InstRW<[SBWriteResGroup33], (instregex "MOV(16|32|64)mr")>;
1298 def: InstRW<[SBWriteResGroup33], (instregex "MOV8mr")>;
1299 def: InstRW<[SBWriteResGroup33], (instregex "MOVAPDmr")>;
1300 def: InstRW<[SBWriteResGroup33], (instregex "MOVAPSmr")>;
1301 def: InstRW<[SBWriteResGroup33], (instregex "MOVDQAmr")>;
1302 def: InstRW<[SBWriteResGroup33], (instregex "MOVDQUmr")>;
1303 def: InstRW<[SBWriteResGroup33], (instregex "MOVHPDmr")>;
1304 def: InstRW<[SBWriteResGroup33], (instregex "MOVHPSmr")>;
1305 def: InstRW<[SBWriteResGroup33], (instregex "MOVLPDmr")>;
1306 def: InstRW<[SBWriteResGroup33], (instregex "MOVLPSmr")>;
1307 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTDQmr")>;
1308 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTI_64mr")>;
1309 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTImr")>;
1310 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTPDmr")>;
1311 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTPSmr")>;
1312 def: InstRW<[SBWriteResGroup33], (instregex "MOVPDI2DImr")>;
1313 def: InstRW<[SBWriteResGroup33], (instregex "MOVPQI2QImr")>;
1314 def: InstRW<[SBWriteResGroup33], (instregex "MOVPQIto64mr")>;
1315 def: InstRW<[SBWriteResGroup33], (instregex "MOVSDmr")>;
1316 def: InstRW<[SBWriteResGroup33], (instregex "MOVSSmr")>;
1317 def: InstRW<[SBWriteResGroup33], (instregex "MOVUPDmr")>;
1318 def: InstRW<[SBWriteResGroup33], (instregex "MOVUPSmr")>;
1319 def: InstRW<[SBWriteResGroup33], (instregex "PUSH64i8")>;
1320 def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16|32|64)r")>;
1321 def: InstRW<[SBWriteResGroup33], (instregex "VEXTRACTF128mr")>;
1322 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPDYmr")>;
1323 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPDmr")>;
1324 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPSYmr")>;
1325 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPSmr")>;
1326 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQAYmr")>;
1327 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQAmr")>;
1328 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQUYmr")>;
1329 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQUmr")>;
1330 def: InstRW<[SBWriteResGroup33], (instregex "VMOVHPDmr")>;
1331 def: InstRW<[SBWriteResGroup33], (instregex "VMOVHPSmr")>;
1332 def: InstRW<[SBWriteResGroup33], (instregex "VMOVLPDmr")>;
1333 def: InstRW<[SBWriteResGroup33], (instregex "VMOVLPSmr")>;
1334 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTDQYmr")>;
1335 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTDQmr")>;
1336 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPDYmr")>;
1337 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPDmr")>;
1338 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPSYmr")>;
1339 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPSmr")>;
1340 def: InstRW<[SBWriteResGroup33], (instregex "VMOVPDI2DImr")>;
1341 def: InstRW<[SBWriteResGroup33], (instregex "VMOVPQI2QImr")>;
1342 def: InstRW<[SBWriteResGroup33], (instregex "VMOVPQIto64mr")>;
1343 def: InstRW<[SBWriteResGroup33], (instregex "VMOVSDmr")>;
1344 def: InstRW<[SBWriteResGroup33], (instregex "VMOVSSmr")>;
1345 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPDYmr")>;
1346 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPDmr")>;
1347 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPSYmr")>;
1348 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPSmr")>;
1349
1350 def SBWriteResGroup34 : SchedWriteRes<[SBPort0,SBPort15]> {
1351   let Latency = 5;
1352   let NumMicroOps = 3;
1353   let ResourceCycles = [1,2];
1354 }
1355 def: InstRW<[SBWriteResGroup34], (instregex "MPSADBWrri")>;
1356 def: InstRW<[SBWriteResGroup34], (instregex "VMPSADBWrri")>;
1357
1358 def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
1359   let Latency = 5;
1360   let NumMicroOps = 3;
1361   let ResourceCycles = [1,2];
1362 }
1363 def: InstRW<[SBWriteResGroup35], (instregex "CLI")>;
1364 def: InstRW<[SBWriteResGroup35], (instregex "CVTSI642SSrr")>;
1365 def: InstRW<[SBWriteResGroup35], (instregex "CVTSI2SSrr")>;
1366 def: InstRW<[SBWriteResGroup35], (instregex "HADDPDrr")>;
1367 def: InstRW<[SBWriteResGroup35], (instregex "HADDPSrr")>;
1368 def: InstRW<[SBWriteResGroup35], (instregex "HSUBPDrr")>;
1369 def: InstRW<[SBWriteResGroup35], (instregex "HSUBPSrr")>;
1370 def: InstRW<[SBWriteResGroup35], (instregex "VCVTSI642SSrr")>;
1371 def: InstRW<[SBWriteResGroup35], (instregex "VCVTSI2SSrr")>;
1372 def: InstRW<[SBWriteResGroup35], (instregex "VHADDPDYrr")>;
1373 def: InstRW<[SBWriteResGroup35], (instregex "VHADDPDrr")>;
1374 def: InstRW<[SBWriteResGroup35], (instregex "VHADDPSYrr")>;
1375 def: InstRW<[SBWriteResGroup35], (instregex "VHADDPSrr")>;
1376 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPDYrr")>;
1377 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPDrr")>;
1378 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPSYrr")>;
1379 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPSrr")>;
1380
1381 def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
1382   let Latency = 5;
1383   let NumMicroOps = 3;
1384   let ResourceCycles = [1,1,1];
1385 }
1386 def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP16m")>;
1387 def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP32m")>;
1388 def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP64m")>;
1389 def: InstRW<[SBWriteResGroup35_2], (instregex "PUSHGS64")>;
1390
1391 def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
1392   let Latency = 5;
1393   let NumMicroOps = 3;
1394   let ResourceCycles = [1,1,1];
1395 }
1396 def: InstRW<[SBWriteResGroup36], (instregex "CALL64pcrel32")>;
1397 def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r")>;
1398 def: InstRW<[SBWriteResGroup36], (instregex "EXTRACTPSmr")>;
1399 def: InstRW<[SBWriteResGroup36], (instregex "VEXTRACTPSmr")>;
1400
1401 def SBWriteResGroup37 : SchedWriteRes<[SBPort4,SBPort01,SBPort23]> {
1402   let Latency = 5;
1403   let NumMicroOps = 3;
1404   let ResourceCycles = [1,1,1];
1405 }
1406 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPDYmr")>;
1407 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPDmr")>;
1408 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPSYmr")>;
1409 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPSmr")>;
1410
1411 def SBWriteResGroup38 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
1412   let Latency = 5;
1413   let NumMicroOps = 3;
1414   let ResourceCycles = [1,1,1];
1415 }
1416 def: InstRW<[SBWriteResGroup38], (instregex "SETAEm")>;
1417 def: InstRW<[SBWriteResGroup38], (instregex "SETBm")>;
1418 def: InstRW<[SBWriteResGroup38], (instregex "SETEm")>;
1419 def: InstRW<[SBWriteResGroup38], (instregex "SETGEm")>;
1420 def: InstRW<[SBWriteResGroup38], (instregex "SETGm")>;
1421 def: InstRW<[SBWriteResGroup38], (instregex "SETLEm")>;
1422 def: InstRW<[SBWriteResGroup38], (instregex "SETLm")>;
1423 def: InstRW<[SBWriteResGroup38], (instregex "SETNEm")>;
1424 def: InstRW<[SBWriteResGroup38], (instregex "SETNOm")>;
1425 def: InstRW<[SBWriteResGroup38], (instregex "SETNPm")>;
1426 def: InstRW<[SBWriteResGroup38], (instregex "SETNSm")>;
1427 def: InstRW<[SBWriteResGroup38], (instregex "SETOm")>;
1428 def: InstRW<[SBWriteResGroup38], (instregex "SETPm")>;
1429 def: InstRW<[SBWriteResGroup38], (instregex "SETSm")>;
1430
1431 def SBWriteResGroup39 : SchedWriteRes<[SBPort4,SBPort23,SBPort15]> {
1432   let Latency = 5;
1433   let NumMicroOps = 3;
1434   let ResourceCycles = [1,1,1];
1435 }
1436 def: InstRW<[SBWriteResGroup39], (instregex "PEXTRBmr")>;
1437 def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRBmr")>;
1438 def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRDmr")>;
1439 def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRWmr")>;
1440
1441 def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
1442   let Latency = 5;
1443   let NumMicroOps = 3;
1444   let ResourceCycles = [1,1,1];
1445 }
1446 def: InstRW<[SBWriteResGroup40], (instregex "MOV8mi")>;
1447 def: InstRW<[SBWriteResGroup40], (instregex "STOSB")>;
1448 def: InstRW<[SBWriteResGroup40], (instregex "STOSL")>;
1449 def: InstRW<[SBWriteResGroup40], (instregex "STOSQ")>;
1450 def: InstRW<[SBWriteResGroup40], (instregex "STOSW")>;
1451
1452 def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> {
1453   let Latency = 5;
1454   let NumMicroOps = 4;
1455   let ResourceCycles = [1,3];
1456 }
1457 def: InstRW<[SBWriteResGroup41], (instregex "FNINIT")>;
1458
1459 def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> {
1460   let Latency = 5;
1461   let NumMicroOps = 4;
1462   let ResourceCycles = [1,3];
1463 }
1464 def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG(16|32|64)rr")>;
1465 def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG8rr")>;
1466
1467 def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
1468   let Latency = 5;
1469   let NumMicroOps = 4;
1470   let ResourceCycles = [1,1,2];
1471 }
1472 def: InstRW<[SBWriteResGroup43], (instregex "SETAm")>;
1473 def: InstRW<[SBWriteResGroup43], (instregex "SETBEm")>;
1474
1475 def SBWriteResGroup44 : SchedWriteRes<[SBPort0,SBPort4,SBPort5,SBPort23]> {
1476   let Latency = 5;
1477   let NumMicroOps = 4;
1478   let ResourceCycles = [1,1,1,1];
1479 }
1480 def: InstRW<[SBWriteResGroup44], (instregex "LDMXCSR")>;
1481 def: InstRW<[SBWriteResGroup44], (instregex "STMXCSR")>;
1482 def: InstRW<[SBWriteResGroup44], (instregex "VLDMXCSR")>;
1483 def: InstRW<[SBWriteResGroup44], (instregex "VSTMXCSR")>;
1484
1485 def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
1486   let Latency = 5;
1487   let NumMicroOps = 4;
1488   let ResourceCycles = [1,1,1,1];
1489 }
1490 def: InstRW<[SBWriteResGroup45], (instregex "PEXTRDmr")>;
1491 def: InstRW<[SBWriteResGroup45], (instregex "PEXTRQmr")>;
1492 def: InstRW<[SBWriteResGroup45], (instregex "VPEXTRQmr")>;
1493 def: InstRW<[SBWriteResGroup45], (instregex "PUSHF16")>;
1494 def: InstRW<[SBWriteResGroup45], (instregex "PUSHF64")>;
1495
1496 def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
1497   let Latency = 5;
1498   let NumMicroOps = 4;
1499   let ResourceCycles = [1,1,1,1];
1500 }
1501 def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>;
1502
1503 def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
1504   let Latency = 5;
1505   let NumMicroOps = 5;
1506   let ResourceCycles = [1,2,1,1];
1507 }
1508 def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;
1509
1510 def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> {
1511   let Latency = 6;
1512   let NumMicroOps = 1;
1513   let ResourceCycles = [1];
1514 }
1515 def: InstRW<[SBWriteResGroup48], (instregex "LDDQUrm")>;
1516 def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm")>;
1517 def: InstRW<[SBWriteResGroup48], (instregex "MOV64toPQIrm")>;
1518 def: InstRW<[SBWriteResGroup48], (instregex "MOVAPDrm")>;
1519 def: InstRW<[SBWriteResGroup48], (instregex "MOVAPSrm")>;
1520 def: InstRW<[SBWriteResGroup48], (instregex "MOVDDUPrm")>;
1521 def: InstRW<[SBWriteResGroup48], (instregex "MOVDI2PDIrm")>;
1522 def: InstRW<[SBWriteResGroup48], (instregex "MOVDQArm")>;
1523 def: InstRW<[SBWriteResGroup48], (instregex "MOVDQUrm")>;
1524 def: InstRW<[SBWriteResGroup48], (instregex "MOVNTDQArm")>;
1525 def: InstRW<[SBWriteResGroup48], (instregex "MOVQI2PQIrm")>;
1526 def: InstRW<[SBWriteResGroup48], (instregex "MOVSDrm")>;
1527 def: InstRW<[SBWriteResGroup48], (instregex "MOVSHDUPrm")>;
1528 def: InstRW<[SBWriteResGroup48], (instregex "MOVSLDUPrm")>;
1529 def: InstRW<[SBWriteResGroup48], (instregex "MOVSSrm")>;
1530 def: InstRW<[SBWriteResGroup48], (instregex "MOVUPDrm")>;
1531 def: InstRW<[SBWriteResGroup48], (instregex "MOVUPSrm")>;
1532 def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r")>;
1533 def: InstRW<[SBWriteResGroup48], (instregex "VBROADCASTSSrm")>;
1534 def: InstRW<[SBWriteResGroup48], (instregex "VLDDQUYrm")>;
1535 def: InstRW<[SBWriteResGroup48], (instregex "VLDDQUrm")>;
1536 def: InstRW<[SBWriteResGroup48], (instregex "VMOV64toPQIrm")>;
1537 def: InstRW<[SBWriteResGroup48], (instregex "VMOVAPDrm")>;
1538 def: InstRW<[SBWriteResGroup48], (instregex "VMOVAPSrm")>;
1539 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDDUPrm")>;
1540 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDI2PDIrm")>;
1541 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDQArm")>;
1542 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDQUrm")>;
1543 def: InstRW<[SBWriteResGroup48], (instregex "VMOVNTDQArm")>;
1544 def: InstRW<[SBWriteResGroup48], (instregex "VMOVQI2PQIrm")>;
1545 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSDrm")>;
1546 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSHDUPrm")>;
1547 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSLDUPrm")>;
1548 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSSrm")>;
1549 def: InstRW<[SBWriteResGroup48], (instregex "VMOVUPDrm")>;
1550 def: InstRW<[SBWriteResGroup48], (instregex "VMOVUPSrm")>;
1551
1552 def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
1553   let Latency = 6;
1554   let NumMicroOps = 2;
1555   let ResourceCycles = [1,1];
1556 }
1557 def: InstRW<[SBWriteResGroup49], (instregex "JMP(16|32|64)m")>;
1558 def: InstRW<[SBWriteResGroup49], (instregex "MOV16sm")>;
1559
1560 def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> {
1561   let Latency = 6;
1562   let NumMicroOps = 2;
1563   let ResourceCycles = [1,1];
1564 }
1565 def: InstRW<[SBWriteResGroup50], (instregex "BT(16|32|64)mi8")>;
1566
1567 def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
1568   let Latency = 6;
1569   let NumMicroOps = 2;
1570   let ResourceCycles = [1,1];
1571 }
1572 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSBrm64")>;
1573 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSDrm64")>;
1574 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSWrm64")>;
1575 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PALIGNR64irm")>;
1576 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSHUFBrm64")>;
1577 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNBrm64")>;
1578 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNDrm64")>;
1579 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNWrm64")>;
1580
1581 def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
1582   let Latency = 6;
1583   let NumMicroOps = 2;
1584   let ResourceCycles = [1,1];
1585 }
1586 def: InstRW<[SBWriteResGroup52], (instregex "ADD(16|32|64)rm")>;
1587 def: InstRW<[SBWriteResGroup52], (instregex "ADD8rm")>;
1588 def: InstRW<[SBWriteResGroup52], (instregex "AND(16|32|64)rm")>;
1589 def: InstRW<[SBWriteResGroup52], (instregex "AND8rm")>;
1590 def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)mi")>;
1591 def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)mr")>;
1592 def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)rm")>;
1593 def: InstRW<[SBWriteResGroup52], (instregex "CMP8mi")>;
1594 def: InstRW<[SBWriteResGroup52], (instregex "CMP8mr")>;
1595 def: InstRW<[SBWriteResGroup52], (instregex "CMP8rm")>;
1596 def: InstRW<[SBWriteResGroup52], (instregex "LODSL")>;
1597 def: InstRW<[SBWriteResGroup52], (instregex "LODSQ")>;
1598 def: InstRW<[SBWriteResGroup52], (instregex "OR(16|32|64)rm")>;
1599 def: InstRW<[SBWriteResGroup52], (instregex "OR8rm")>;
1600 def: InstRW<[SBWriteResGroup52], (instregex "SUB(16|32|64)rm")>;
1601 def: InstRW<[SBWriteResGroup52], (instregex "SUB8rm")>;
1602 def: InstRW<[SBWriteResGroup52], (instregex "XOR(16|32|64)rm")>;
1603 def: InstRW<[SBWriteResGroup52], (instregex "XOR8rm")>;
1604
1605 def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> {
1606   let Latency = 6;
1607   let NumMicroOps = 3;
1608   let ResourceCycles = [1,2];
1609 }
1610 def: InstRW<[SBWriteResGroup53], (instregex "ST_F32m")>;
1611 def: InstRW<[SBWriteResGroup53], (instregex "ST_F64m")>;
1612 def: InstRW<[SBWriteResGroup53], (instregex "ST_FP32m")>;
1613 def: InstRW<[SBWriteResGroup53], (instregex "ST_FP64m")>;
1614 def: InstRW<[SBWriteResGroup53], (instregex "ST_FP80m")>;
1615
1616 def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> {
1617   let Latency = 7;
1618   let NumMicroOps = 1;
1619   let ResourceCycles = [1];
1620 }
1621 def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSDYrm")>;
1622 def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSSYrm")>;
1623 def: InstRW<[SBWriteResGroup54], (instregex "VMOVAPDYrm")>;
1624 def: InstRW<[SBWriteResGroup54], (instregex "VMOVAPSYrm")>;
1625 def: InstRW<[SBWriteResGroup54], (instregex "VMOVDDUPYrm")>;
1626 def: InstRW<[SBWriteResGroup54], (instregex "VMOVDQAYrm")>;
1627 def: InstRW<[SBWriteResGroup54], (instregex "VMOVDQUYrm")>;
1628 def: InstRW<[SBWriteResGroup54], (instregex "VMOVSHDUPYrm")>;
1629 def: InstRW<[SBWriteResGroup54], (instregex "VMOVSLDUPYrm")>;
1630 def: InstRW<[SBWriteResGroup54], (instregex "VMOVUPDYrm")>;
1631 def: InstRW<[SBWriteResGroup54], (instregex "VMOVUPSYrm")>;
1632
1633 def SBWriteResGroup55 : SchedWriteRes<[SBPort0,SBPort23]> {
1634   let Latency = 7;
1635   let NumMicroOps = 2;
1636   let ResourceCycles = [1,1];
1637 }
1638 def: InstRW<[SBWriteResGroup55], (instregex "CVTPS2PDrm")>;
1639 def: InstRW<[SBWriteResGroup55], (instregex "CVTSS2SDrm")>;
1640 def: InstRW<[SBWriteResGroup55], (instregex "VCVTPS2PDYrm")>;
1641 def: InstRW<[SBWriteResGroup55], (instregex "VCVTPS2PDrm")>;
1642 def: InstRW<[SBWriteResGroup55], (instregex "VCVTSS2SDrm")>;
1643 def: InstRW<[SBWriteResGroup55], (instregex "VTESTPDrm")>;
1644 def: InstRW<[SBWriteResGroup55], (instregex "VTESTPSrm")>;
1645
1646 def SBWriteResGroup56 : SchedWriteRes<[SBPort5,SBPort23]> {
1647   let Latency = 7;
1648   let NumMicroOps = 2;
1649   let ResourceCycles = [1,1];
1650 }
1651 def: InstRW<[SBWriteResGroup56], (instregex "ANDNPDrm")>;
1652 def: InstRW<[SBWriteResGroup56], (instregex "ANDNPSrm")>;
1653 def: InstRW<[SBWriteResGroup56], (instregex "ANDPDrm")>;
1654 def: InstRW<[SBWriteResGroup56], (instregex "ANDPSrm")>;
1655 def: InstRW<[SBWriteResGroup56], (instregex "INSERTPSrm")>;
1656 def: InstRW<[SBWriteResGroup56], (instregex "MOVHPDrm")>;
1657 def: InstRW<[SBWriteResGroup56], (instregex "MOVHPSrm")>;
1658 def: InstRW<[SBWriteResGroup56], (instregex "MOVLPDrm")>;
1659 def: InstRW<[SBWriteResGroup56], (instregex "MOVLPSrm")>;
1660 def: InstRW<[SBWriteResGroup56], (instregex "ORPDrm")>;
1661 def: InstRW<[SBWriteResGroup56], (instregex "ORPSrm")>;
1662 def: InstRW<[SBWriteResGroup56], (instregex "SHUFPDrmi")>;
1663 def: InstRW<[SBWriteResGroup56], (instregex "SHUFPSrmi")>;
1664 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKHPDrm")>;
1665 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKHPSrm")>;
1666 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKLPDrm")>;
1667 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKLPSrm")>;
1668 def: InstRW<[SBWriteResGroup56], (instregex "VANDNPDrm")>;
1669 def: InstRW<[SBWriteResGroup56], (instregex "VANDNPSrm")>;
1670 def: InstRW<[SBWriteResGroup56], (instregex "VANDPDrm")>;
1671 def: InstRW<[SBWriteResGroup56], (instregex "VANDPSrm")>;
1672 def: InstRW<[SBWriteResGroup56], (instregex "VBROADCASTF128")>;
1673 def: InstRW<[SBWriteResGroup56], (instregex "VINSERTPSrm")>;
1674 def: InstRW<[SBWriteResGroup56], (instregex "VMOVHPDrm")>;
1675 def: InstRW<[SBWriteResGroup56], (instregex "VMOVHPSrm")>;
1676 def: InstRW<[SBWriteResGroup56], (instregex "VMOVLPDrm")>;
1677 def: InstRW<[SBWriteResGroup56], (instregex "VMOVLPSrm")>;
1678 def: InstRW<[SBWriteResGroup56], (instregex "VORPDrm")>;
1679 def: InstRW<[SBWriteResGroup56], (instregex "VORPSrm")>;
1680 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPDmi")>;
1681 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPDrm")>;
1682 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPSmi")>;
1683 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPSrm")>;
1684 def: InstRW<[SBWriteResGroup56], (instregex "VSHUFPDrmi")>;
1685 def: InstRW<[SBWriteResGroup56], (instregex "VSHUFPSrmi")>;
1686 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKHPDrm")>;
1687 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKHPSrm")>;
1688 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKLPDrm")>;
1689 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKLPSrm")>;
1690 def: InstRW<[SBWriteResGroup56], (instregex "VXORPDrm")>;
1691 def: InstRW<[SBWriteResGroup56], (instregex "VXORPSrm")>;
1692 def: InstRW<[SBWriteResGroup56], (instregex "XORPDrm")>;
1693 def: InstRW<[SBWriteResGroup56], (instregex "XORPSrm")>;
1694
1695 def SBWriteResGroup57 : SchedWriteRes<[SBPort5,SBPort015]> {
1696   let Latency = 7;
1697   let NumMicroOps = 2;
1698   let ResourceCycles = [1,1];
1699 }
1700 def: InstRW<[SBWriteResGroup57], (instregex "AESDECLASTrr")>;
1701 def: InstRW<[SBWriteResGroup57], (instregex "AESDECrr")>;
1702 def: InstRW<[SBWriteResGroup57], (instregex "AESENCLASTrr")>;
1703 def: InstRW<[SBWriteResGroup57], (instregex "AESENCrr")>;
1704 def: InstRW<[SBWriteResGroup57], (instregex "VAESDECLASTrr")>;
1705 def: InstRW<[SBWriteResGroup57], (instregex "VAESDECrr")>;
1706 def: InstRW<[SBWriteResGroup57], (instregex "VAESENCLASTrr")>;
1707 def: InstRW<[SBWriteResGroup57], (instregex "VAESENCrr")>;
1708
1709 def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> {
1710   let Latency = 7;
1711   let NumMicroOps = 2;
1712   let ResourceCycles = [1,1];
1713 }
1714 def: InstRW<[SBWriteResGroup58], (instregex "BLENDPDrmi")>;
1715 def: InstRW<[SBWriteResGroup58], (instregex "BLENDPSrmi")>;
1716 def: InstRW<[SBWriteResGroup58], (instregex "VBLENDPDrmi")>;
1717 def: InstRW<[SBWriteResGroup58], (instregex "VBLENDPSrmi")>;
1718 def: InstRW<[SBWriteResGroup58], (instregex "VINSERTF128rm")>;
1719
1720 def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> {
1721   let Latency = 7;
1722   let NumMicroOps = 2;
1723   let ResourceCycles = [1,1];
1724 }
1725 def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm")>;
1726 def: InstRW<[SBWriteResGroup59], (instregex "PABSBrm")>;
1727 def: InstRW<[SBWriteResGroup59], (instregex "PABSDrm")>;
1728 def: InstRW<[SBWriteResGroup59], (instregex "PABSWrm")>;
1729 def: InstRW<[SBWriteResGroup59], (instregex "PACKSSDWrm")>;
1730 def: InstRW<[SBWriteResGroup59], (instregex "PACKSSWBrm")>;
1731 def: InstRW<[SBWriteResGroup59], (instregex "PACKUSDWrm")>;
1732 def: InstRW<[SBWriteResGroup59], (instregex "PACKUSWBrm")>;
1733 def: InstRW<[SBWriteResGroup59], (instregex "PADDBrm")>;
1734 def: InstRW<[SBWriteResGroup59], (instregex "PADDDrm")>;
1735 def: InstRW<[SBWriteResGroup59], (instregex "PADDQrm")>;
1736 def: InstRW<[SBWriteResGroup59], (instregex "PADDSBrm")>;
1737 def: InstRW<[SBWriteResGroup59], (instregex "PADDSWrm")>;
1738 def: InstRW<[SBWriteResGroup59], (instregex "PADDUSBrm")>;
1739 def: InstRW<[SBWriteResGroup59], (instregex "PADDUSWrm")>;
1740 def: InstRW<[SBWriteResGroup59], (instregex "PADDWrm")>;
1741 def: InstRW<[SBWriteResGroup59], (instregex "PALIGNRrmi")>;
1742 def: InstRW<[SBWriteResGroup59], (instregex "PAVGBrm")>;
1743 def: InstRW<[SBWriteResGroup59], (instregex "PAVGWrm")>;
1744 def: InstRW<[SBWriteResGroup59], (instregex "PBLENDWrmi")>;
1745 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQBrm")>;
1746 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQDrm")>;
1747 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQQrm")>;
1748 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQWrm")>;
1749 def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTBrm")>;
1750 def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTDrm")>;
1751 def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTWrm")>;
1752 def: InstRW<[SBWriteResGroup59], (instregex "PINSRBrm")>;
1753 def: InstRW<[SBWriteResGroup59], (instregex "PINSRDrm")>;
1754 def: InstRW<[SBWriteResGroup59], (instregex "PINSRQrm")>;
1755 def: InstRW<[SBWriteResGroup59], (instregex "PINSRWrmi")>;
1756 def: InstRW<[SBWriteResGroup59], (instregex "PMAXSBrm")>;
1757 def: InstRW<[SBWriteResGroup59], (instregex "PMAXSDrm")>;
1758 def: InstRW<[SBWriteResGroup59], (instregex "PMAXSWrm")>;
1759 def: InstRW<[SBWriteResGroup59], (instregex "PMAXUBrm")>;
1760 def: InstRW<[SBWriteResGroup59], (instregex "PMAXUDrm")>;
1761 def: InstRW<[SBWriteResGroup59], (instregex "PMAXUWrm")>;
1762 def: InstRW<[SBWriteResGroup59], (instregex "PMINSBrm")>;
1763 def: InstRW<[SBWriteResGroup59], (instregex "PMINSDrm")>;
1764 def: InstRW<[SBWriteResGroup59], (instregex "PMINSWrm")>;
1765 def: InstRW<[SBWriteResGroup59], (instregex "PMINUBrm")>;
1766 def: InstRW<[SBWriteResGroup59], (instregex "PMINUDrm")>;
1767 def: InstRW<[SBWriteResGroup59], (instregex "PMINUWrm")>;
1768 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBDrm")>;
1769 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBQrm")>;
1770 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBWrm")>;
1771 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXDQrm")>;
1772 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXWDrm")>;
1773 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXWQrm")>;
1774 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBDrm")>;
1775 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBQrm")>;
1776 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBWrm")>;
1777 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXDQrm")>;
1778 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXWDrm")>;
1779 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXWQrm")>;
1780 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFBrm")>;
1781 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFDmi")>;
1782 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFHWmi")>;
1783 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFLWmi")>;
1784 def: InstRW<[SBWriteResGroup59], (instregex "PSIGNBrm128")>;
1785 def: InstRW<[SBWriteResGroup59], (instregex "PSIGNDrm128")>;
1786 def: InstRW<[SBWriteResGroup59], (instregex "PSIGNWrm128")>;
1787 def: InstRW<[SBWriteResGroup59], (instregex "PSUBBrm")>;
1788 def: InstRW<[SBWriteResGroup59], (instregex "PSUBDrm")>;
1789 def: InstRW<[SBWriteResGroup59], (instregex "PSUBQrm")>;
1790 def: InstRW<[SBWriteResGroup59], (instregex "PSUBSBrm")>;
1791 def: InstRW<[SBWriteResGroup59], (instregex "PSUBSWrm")>;
1792 def: InstRW<[SBWriteResGroup59], (instregex "PSUBUSBrm")>;
1793 def: InstRW<[SBWriteResGroup59], (instregex "PSUBUSWrm")>;
1794 def: InstRW<[SBWriteResGroup59], (instregex "PSUBWrm")>;
1795 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHBWrm")>;
1796 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHDQrm")>;
1797 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHQDQrm")>;
1798 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHWDrm")>;
1799 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLBWrm")>;
1800 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLDQrm")>;
1801 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLQDQrm")>;
1802 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLWDrm")>;
1803 def: InstRW<[SBWriteResGroup59], (instregex "VPABSBrm")>;
1804 def: InstRW<[SBWriteResGroup59], (instregex "VPABSDrm")>;
1805 def: InstRW<[SBWriteResGroup59], (instregex "VPABSWrm")>;
1806 def: InstRW<[SBWriteResGroup59], (instregex "VPACKSSDWrm")>;
1807 def: InstRW<[SBWriteResGroup59], (instregex "VPACKSSWBrm")>;
1808 def: InstRW<[SBWriteResGroup59], (instregex "VPACKUSDWrm")>;
1809 def: InstRW<[SBWriteResGroup59], (instregex "VPACKUSWBrm")>;
1810 def: InstRW<[SBWriteResGroup59], (instregex "VPADDBrm")>;
1811 def: InstRW<[SBWriteResGroup59], (instregex "VPADDDrm")>;
1812 def: InstRW<[SBWriteResGroup59], (instregex "VPADDQrm")>;
1813 def: InstRW<[SBWriteResGroup59], (instregex "VPADDSBrm")>;
1814 def: InstRW<[SBWriteResGroup59], (instregex "VPADDSWrm")>;
1815 def: InstRW<[SBWriteResGroup59], (instregex "VPADDUSBrm")>;
1816 def: InstRW<[SBWriteResGroup59], (instregex "VPADDUSWrm")>;
1817 def: InstRW<[SBWriteResGroup59], (instregex "VPADDWrm")>;
1818 def: InstRW<[SBWriteResGroup59], (instregex "VPALIGNRrmi")>;
1819 def: InstRW<[SBWriteResGroup59], (instregex "VPAVGBrm")>;
1820 def: InstRW<[SBWriteResGroup59], (instregex "VPAVGWrm")>;
1821 def: InstRW<[SBWriteResGroup59], (instregex "VPBLENDWrmi")>;
1822 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQBrm")>;
1823 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQDrm")>;
1824 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQQrm")>;
1825 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQWrm")>;
1826 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTBrm")>;
1827 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTDrm")>;
1828 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTWrm")>;
1829 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRBrm")>;
1830 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRDrm")>;
1831 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRQrm")>;
1832 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRWrmi")>;
1833 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSBrm")>;
1834 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSDrm")>;
1835 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSWrm")>;
1836 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUBrm")>;
1837 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUDrm")>;
1838 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUWrm")>;
1839 def: InstRW<[SBWriteResGroup59], (instregex "VPMINSBrm")>;
1840 def: InstRW<[SBWriteResGroup59], (instregex "VPMINSDrm")>;
1841 def: InstRW<[SBWriteResGroup59], (instregex "VPMINSWrm")>;
1842 def: InstRW<[SBWriteResGroup59], (instregex "VPMINUBrm")>;
1843 def: InstRW<[SBWriteResGroup59], (instregex "VPMINUDrm")>;
1844 def: InstRW<[SBWriteResGroup59], (instregex "VPMINUWrm")>;
1845 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBDrm")>;
1846 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBQrm")>;
1847 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBWrm")>;
1848 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXDQrm")>;
1849 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXWDrm")>;
1850 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXWQrm")>;
1851 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBDrm")>;
1852 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBQrm")>;
1853 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBWrm")>;
1854 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXDQrm")>;
1855 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXWDrm")>;
1856 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXWQrm")>;
1857 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFBrm")>;
1858 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFDmi")>;
1859 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFHWmi")>;
1860 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFLWmi")>;
1861 def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNBrm128")>;
1862 def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNDrm128")>;
1863 def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNWrm128")>;
1864 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBBrm")>;
1865 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBDrm")>;
1866 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBQrm")>;
1867 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBSBrm")>;
1868 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBSWrm")>;
1869 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBUSBrm")>;
1870 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBUSWrm")>;
1871 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBWrm")>;
1872 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHBWrm")>;
1873 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHDQrm")>;
1874 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHQDQrm")>;
1875 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHWDrm")>;
1876 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLBWrm")>;
1877 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLDQrm")>;
1878 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLQDQrm")>;
1879 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLWDrm")>;
1880
1881 def SBWriteResGroup60 : SchedWriteRes<[SBPort23,SBPort015]> {
1882   let Latency = 7;
1883   let NumMicroOps = 2;
1884   let ResourceCycles = [1,1];
1885 }
1886 def: InstRW<[SBWriteResGroup60], (instregex "PANDNrm")>;
1887 def: InstRW<[SBWriteResGroup60], (instregex "PANDrm")>;
1888 def: InstRW<[SBWriteResGroup60], (instregex "PORrm")>;
1889 def: InstRW<[SBWriteResGroup60], (instregex "PXORrm")>;
1890 def: InstRW<[SBWriteResGroup60], (instregex "VPANDNrm")>;
1891 def: InstRW<[SBWriteResGroup60], (instregex "VPANDrm")>;
1892 def: InstRW<[SBWriteResGroup60], (instregex "VPORrm")>;
1893 def: InstRW<[SBWriteResGroup60], (instregex "VPXORrm")>;
1894
1895 def SBWriteResGroup61 : SchedWriteRes<[SBPort0,SBPort05]> {
1896   let Latency = 7;
1897   let NumMicroOps = 3;
1898   let ResourceCycles = [2,1];
1899 }
1900 def: InstRW<[SBWriteResGroup61], (instregex "VRCPPSYr")>;
1901 def: InstRW<[SBWriteResGroup61], (instregex "VRSQRTPSYr")>;
1902
1903 def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> {
1904   let Latency = 7;
1905   let NumMicroOps = 3;
1906   let ResourceCycles = [2,1];
1907 }
1908 def: InstRW<[SBWriteResGroup62], (instregex "VERRm")>;
1909 def: InstRW<[SBWriteResGroup62], (instregex "VERWm")>;
1910
1911 def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> {
1912   let Latency = 7;
1913   let NumMicroOps = 3;
1914   let ResourceCycles = [1,2];
1915 }
1916 def: InstRW<[SBWriteResGroup63], (instregex "LODSB")>;
1917 def: InstRW<[SBWriteResGroup63], (instregex "LODSW")>;
1918
1919 def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
1920   let Latency = 7;
1921   let NumMicroOps = 3;
1922   let ResourceCycles = [1,1,1];
1923 }
1924 def: InstRW<[SBWriteResGroup64], (instregex "FARJMP64")>;
1925
1926 def SBWriteResGroup65 : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
1927   let Latency = 7;
1928   let NumMicroOps = 3;
1929   let ResourceCycles = [1,1,1];
1930 }
1931 def: InstRW<[SBWriteResGroup65], (instregex "ADC(16|32|64)rm")>;
1932 def: InstRW<[SBWriteResGroup65], (instregex "ADC8rm")>;
1933 def: InstRW<[SBWriteResGroup65], (instregex "CMOVAE(16|32|64)rm")>;
1934 def: InstRW<[SBWriteResGroup65], (instregex "CMOVB(16|32|64)rm")>;
1935 def: InstRW<[SBWriteResGroup65], (instregex "CMOVE(16|32|64)rm")>;
1936 def: InstRW<[SBWriteResGroup65], (instregex "CMOVG(16|32|64)rm")>;
1937 def: InstRW<[SBWriteResGroup65], (instregex "CMOVGE(16|32|64)rm")>;
1938 def: InstRW<[SBWriteResGroup65], (instregex "CMOVL(16|32|64)rm")>;
1939 def: InstRW<[SBWriteResGroup65], (instregex "CMOVLE(16|32|64)rm")>;
1940 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNE(16|32|64)rm")>;
1941 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNO(16|32|64)rm")>;
1942 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNP(16|32|64)rm")>;
1943 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNS(16|32|64)rm")>;
1944 def: InstRW<[SBWriteResGroup65], (instregex "CMOVO(16|32|64)rm")>;
1945 def: InstRW<[SBWriteResGroup65], (instregex "CMOVP(16|32|64)rm")>;
1946 def: InstRW<[SBWriteResGroup65], (instregex "CMOVS(16|32|64)rm")>;
1947 def: InstRW<[SBWriteResGroup65], (instregex "SBB(16|32|64)rm")>;
1948 def: InstRW<[SBWriteResGroup65], (instregex "SBB8rm")>;
1949
1950 def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
1951   let Latency = 7;
1952   let NumMicroOps = 4;
1953   let ResourceCycles = [1,1,2];
1954 }
1955 def: InstRW<[SBWriteResGroup66], (instregex "FNSTSWm")>;
1956
1957 def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
1958   let Latency = 7;
1959   let NumMicroOps = 4;
1960   let ResourceCycles = [1,2,1];
1961 }
1962 def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r")>;
1963 def: InstRW<[SBWriteResGroup67], (instregex "STR(16|32|64)r")>;
1964
1965 def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
1966   let Latency = 7;
1967   let NumMicroOps = 4;
1968   let ResourceCycles = [1,1,2];
1969 }
1970 def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>;
1971 def: InstRW<[SBWriteResGroup68], (instregex "FNSTCW16m")>;
1972
1973 def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
1974   let Latency = 7;
1975   let NumMicroOps = 4;
1976   let ResourceCycles = [1,2,1];
1977 }
1978 def: InstRW<[SBWriteResGroup69], (instregex "BTC(16|32|64)mi8")>;
1979 def: InstRW<[SBWriteResGroup69], (instregex "BTR(16|32|64)mi8")>;
1980 def: InstRW<[SBWriteResGroup69], (instregex "BTS(16|32|64)mi8")>;
1981 def: InstRW<[SBWriteResGroup69], (instregex "SAR(16|32|64)mi")>;
1982 def: InstRW<[SBWriteResGroup69], (instregex "SAR8mi")>;
1983 def: InstRW<[SBWriteResGroup69], (instregex "SHL(16|32|64)m1")>;
1984 def: InstRW<[SBWriteResGroup69], (instregex "SHL(16|32|64)mi")>;
1985 def: InstRW<[SBWriteResGroup69], (instregex "SHL8m1")>;
1986 def: InstRW<[SBWriteResGroup69], (instregex "SHL8mi")>;
1987 def: InstRW<[SBWriteResGroup69], (instregex "SHR(16|32|64)mi")>;
1988 def: InstRW<[SBWriteResGroup69], (instregex "SHR8mi")>;
1989
1990 def SBWriteResGroup70 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
1991   let Latency = 7;
1992   let NumMicroOps = 4;
1993   let ResourceCycles = [1,2,1];
1994 }
1995 def: InstRW<[SBWriteResGroup70], (instregex "ADD(16|32|64)mi")>;
1996 def: InstRW<[SBWriteResGroup70], (instregex "ADD(16|32|64)mr")>;
1997 def: InstRW<[SBWriteResGroup70], (instregex "ADD8mi")>;
1998 def: InstRW<[SBWriteResGroup70], (instregex "ADD8mr")>;
1999 def: InstRW<[SBWriteResGroup70], (instregex "AND(16|32|64)mi")>;
2000 def: InstRW<[SBWriteResGroup70], (instregex "AND(16|32|64)mr")>;
2001 def: InstRW<[SBWriteResGroup70], (instregex "AND8mi")>;
2002 def: InstRW<[SBWriteResGroup70], (instregex "AND8mr")>;
2003 def: InstRW<[SBWriteResGroup70], (instregex "DEC(16|32|64)m")>;
2004 def: InstRW<[SBWriteResGroup70], (instregex "DEC8m")>;
2005 def: InstRW<[SBWriteResGroup70], (instregex "INC(16|32|64)m")>;
2006 def: InstRW<[SBWriteResGroup70], (instregex "INC8m")>;
2007 def: InstRW<[SBWriteResGroup70], (instregex "NEG(16|32|64)m")>;
2008 def: InstRW<[SBWriteResGroup70], (instregex "NEG8m")>;
2009 def: InstRW<[SBWriteResGroup70], (instregex "NOT(16|32|64)m")>;
2010 def: InstRW<[SBWriteResGroup70], (instregex "NOT8m")>;
2011 def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mi")>;
2012 def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mr")>;
2013 def: InstRW<[SBWriteResGroup70], (instregex "OR8mi")>;
2014 def: InstRW<[SBWriteResGroup70], (instregex "OR8mr")>;
2015 def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mi")>;
2016 def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mr")>;
2017 def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>;
2018 def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>;
2019 def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)mr")>;
2020 def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>;
2021 def: InstRW<[SBWriteResGroup70], (instregex "TEST8mr")>;
2022 def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mi")>;
2023 def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mr")>;
2024 def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>;
2025 def: InstRW<[SBWriteResGroup70], (instregex "XOR8mr")>;
2026
2027 def SBWriteResGroup71 : SchedWriteRes<[SBPort0,SBPort23]> {
2028   let Latency = 8;
2029   let NumMicroOps = 2;
2030   let ResourceCycles = [1,1];
2031 }
2032 def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMADDUBSWrm64")>;
2033 def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMULHRSWrm64")>;
2034 def: InstRW<[SBWriteResGroup71], (instregex "VTESTPDYrm")>;
2035 def: InstRW<[SBWriteResGroup71], (instregex "VTESTPSYrm")>;
2036
2037 def SBWriteResGroup72 : SchedWriteRes<[SBPort1,SBPort23]> {
2038   let Latency = 8;
2039   let NumMicroOps = 2;
2040   let ResourceCycles = [1,1];
2041 }
2042 def: InstRW<[SBWriteResGroup72], (instregex "BSF(16|32|64)rm")>;
2043 def: InstRW<[SBWriteResGroup72], (instregex "BSR(16|32|64)rm")>;
2044 def: InstRW<[SBWriteResGroup72], (instregex "CRC32r(16|32|64)m64")>;
2045 def: InstRW<[SBWriteResGroup72], (instregex "CRC32r(16|32|64)m8")>;
2046 def: InstRW<[SBWriteResGroup72], (instregex "FCOM32m")>;
2047 def: InstRW<[SBWriteResGroup72], (instregex "FCOM64m")>;
2048 def: InstRW<[SBWriteResGroup72], (instregex "FCOMP32m")>;
2049 def: InstRW<[SBWriteResGroup72], (instregex "FCOMP64m")>;
2050 def: InstRW<[SBWriteResGroup72], (instregex "MUL8m")>;
2051
2052 def SBWriteResGroup73 : SchedWriteRes<[SBPort5,SBPort23]> {
2053   let Latency = 8;
2054   let NumMicroOps = 2;
2055   let ResourceCycles = [1,1];
2056 }
2057 def: InstRW<[SBWriteResGroup73], (instregex "VANDNPDYrm")>;
2058 def: InstRW<[SBWriteResGroup73], (instregex "VANDNPSYrm")>;
2059 def: InstRW<[SBWriteResGroup73], (instregex "VANDPDYrm")>;
2060 def: InstRW<[SBWriteResGroup73], (instregex "VANDPSYrm")>;
2061 def: InstRW<[SBWriteResGroup73], (instregex "VORPDYrm")>;
2062 def: InstRW<[SBWriteResGroup73], (instregex "VORPSYrm")>;
2063 def: InstRW<[SBWriteResGroup73], (instregex "VPERM2F128rm")>;
2064 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPDYmi")>;
2065 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPDYrm")>;
2066 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPSYmi")>;
2067 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPSYrm")>;
2068 def: InstRW<[SBWriteResGroup73], (instregex "VSHUFPDYrmi")>;
2069 def: InstRW<[SBWriteResGroup73], (instregex "VSHUFPSYrmi")>;
2070 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKHPDYrm")>;
2071 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKHPSYrm")>;
2072 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKLPDYrm")>;
2073 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKLPSYrm")>;
2074 def: InstRW<[SBWriteResGroup73], (instregex "VXORPDYrm")>;
2075 def: InstRW<[SBWriteResGroup73], (instregex "VXORPSYrm")>;
2076
2077 def SBWriteResGroup74 : SchedWriteRes<[SBPort23,SBPort05]> {
2078   let Latency = 8;
2079   let NumMicroOps = 2;
2080   let ResourceCycles = [1,1];
2081 }
2082 def: InstRW<[SBWriteResGroup74], (instregex "VBLENDPDYrmi")>;
2083 def: InstRW<[SBWriteResGroup74], (instregex "VBLENDPSYrmi")>;
2084
2085 def SBWriteResGroup75 : SchedWriteRes<[SBPort23,SBPort05]> {
2086   let Latency = 8;
2087   let NumMicroOps = 3;
2088   let ResourceCycles = [1,2];
2089 }
2090 def: InstRW<[SBWriteResGroup75], (instregex "BLENDVPDrm0")>;
2091 def: InstRW<[SBWriteResGroup75], (instregex "BLENDVPSrm0")>;
2092 def: InstRW<[SBWriteResGroup75], (instregex "VBLENDVPDrm")>;
2093 def: InstRW<[SBWriteResGroup75], (instregex "VBLENDVPSrm")>;
2094 def: InstRW<[SBWriteResGroup75], (instregex "VMASKMOVPDrm")>;
2095 def: InstRW<[SBWriteResGroup75], (instregex "VMASKMOVPSrm")>;
2096
2097 def SBWriteResGroup76 : SchedWriteRes<[SBPort23,SBPort15]> {
2098   let Latency = 8;
2099   let NumMicroOps = 3;
2100   let ResourceCycles = [1,2];
2101 }
2102 def: InstRW<[SBWriteResGroup76], (instregex "PBLENDVBrr0")>;
2103 def: InstRW<[SBWriteResGroup76], (instregex "VPBLENDVBrm")>;
2104
2105 def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2106   let Latency = 8;
2107   let NumMicroOps = 3;
2108   let ResourceCycles = [1,1,1];
2109 }
2110 def: InstRW<[SBWriteResGroup77], (instregex "COMISDrm")>;
2111 def: InstRW<[SBWriteResGroup77], (instregex "COMISSrm")>;
2112 def: InstRW<[SBWriteResGroup77], (instregex "UCOMISDrm")>;
2113 def: InstRW<[SBWriteResGroup77], (instregex "UCOMISSrm")>;
2114 def: InstRW<[SBWriteResGroup77], (instregex "VCOMISDrm")>;
2115 def: InstRW<[SBWriteResGroup77], (instregex "VCOMISSrm")>;
2116 def: InstRW<[SBWriteResGroup77], (instregex "VUCOMISDrm")>;
2117 def: InstRW<[SBWriteResGroup77], (instregex "VUCOMISSrm")>;
2118
2119 def SBWriteResGroup78 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> {
2120   let Latency = 8;
2121   let NumMicroOps = 3;
2122   let ResourceCycles = [1,1,1];
2123 }
2124 def: InstRW<[SBWriteResGroup78], (instregex "PTESTrm")>;
2125 def: InstRW<[SBWriteResGroup78], (instregex "VPTESTrm")>;
2126
2127 def SBWriteResGroup79 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> {
2128   let Latency = 8;
2129   let NumMicroOps = 3;
2130   let ResourceCycles = [1,1,1];
2131 }
2132 def: InstRW<[SBWriteResGroup79], (instregex "PSLLDrm")>;
2133 def: InstRW<[SBWriteResGroup79], (instregex "PSLLQrm")>;
2134 def: InstRW<[SBWriteResGroup79], (instregex "PSLLWrm")>;
2135 def: InstRW<[SBWriteResGroup79], (instregex "PSRADrm")>;
2136 def: InstRW<[SBWriteResGroup79], (instregex "PSRAWrm")>;
2137 def: InstRW<[SBWriteResGroup79], (instregex "PSRLDrm")>;
2138 def: InstRW<[SBWriteResGroup79], (instregex "PSRLQrm")>;
2139 def: InstRW<[SBWriteResGroup79], (instregex "PSRLWrm")>;
2140 def: InstRW<[SBWriteResGroup79], (instregex "VPSLLDrm")>;
2141 def: InstRW<[SBWriteResGroup79], (instregex "VPSLLQrm")>;
2142 def: InstRW<[SBWriteResGroup79], (instregex "VPSLLWrm")>;
2143 def: InstRW<[SBWriteResGroup79], (instregex "VPSRADrm")>;
2144 def: InstRW<[SBWriteResGroup79], (instregex "VPSRAWrm")>;
2145 def: InstRW<[SBWriteResGroup79], (instregex "VPSRLDrm")>;
2146 def: InstRW<[SBWriteResGroup79], (instregex "VPSRLQrm")>;
2147 def: InstRW<[SBWriteResGroup79], (instregex "VPSRLWrm")>;
2148
2149 def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort15]> {
2150   let Latency = 8;
2151   let NumMicroOps = 4;
2152   let ResourceCycles = [1,3];
2153 }
2154 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDSWrm64")>;
2155 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDWrm64")>;
2156 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDrm64")>;
2157 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBDrm64")>;
2158 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBSWrm64")>;
2159 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBWrm64")>;
2160
2161 def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> {
2162   let Latency = 8;
2163   let NumMicroOps = 4;
2164   let ResourceCycles = [1,3];
2165 }
2166 def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(16|32|64)rm")>;
2167 def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG8rm")>;
2168
2169 def SBWriteResGroup82 : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
2170   let Latency = 8;
2171   let NumMicroOps = 4;
2172   let ResourceCycles = [1,2,1];
2173 }
2174 def: InstRW<[SBWriteResGroup82], (instregex "CMOVA(16|32|64)rm")>;
2175 def: InstRW<[SBWriteResGroup82], (instregex "CMOVBE(16|32|64)rm")>;
2176
2177 def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> {
2178   let Latency = 8;
2179   let NumMicroOps = 5;
2180   let ResourceCycles = [2,3];
2181 }
2182 def: InstRW<[SBWriteResGroup83], (instregex "CMPSB")>;
2183 def: InstRW<[SBWriteResGroup83], (instregex "CMPSL")>;
2184 def: InstRW<[SBWriteResGroup83], (instregex "CMPSQ")>;
2185 def: InstRW<[SBWriteResGroup83], (instregex "CMPSW")>;
2186
2187 def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
2188   let Latency = 8;
2189   let NumMicroOps = 5;
2190   let ResourceCycles = [1,2,2];
2191 }
2192 def: InstRW<[SBWriteResGroup84], (instregex "FLDCW16m")>;
2193
2194 def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
2195   let Latency = 8;
2196   let NumMicroOps = 5;
2197   let ResourceCycles = [1,2,2];
2198 }
2199 def: InstRW<[SBWriteResGroup85], (instregex "ROL(16|32|64)mi")>;
2200 def: InstRW<[SBWriteResGroup85], (instregex "ROL8mi")>;
2201 def: InstRW<[SBWriteResGroup85], (instregex "ROR(16|32|64)mi")>;
2202 def: InstRW<[SBWriteResGroup85], (instregex "ROR8mi")>;
2203
2204 def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
2205   let Latency = 8;
2206   let NumMicroOps = 5;
2207   let ResourceCycles = [1,2,2];
2208 }
2209 def: InstRW<[SBWriteResGroup86], (instregex "MOVSB")>;
2210 def: InstRW<[SBWriteResGroup86], (instregex "MOVSL")>;
2211 def: InstRW<[SBWriteResGroup86], (instregex "MOVSQ")>;
2212 def: InstRW<[SBWriteResGroup86], (instregex "MOVSW")>;
2213 def: InstRW<[SBWriteResGroup86], (instregex "XADD(16|32|64)rm")>;
2214 def: InstRW<[SBWriteResGroup86], (instregex "XADD8rm")>;
2215
2216 def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
2217   let Latency = 8;
2218   let NumMicroOps = 5;
2219   let ResourceCycles = [1,1,1,2];
2220 }
2221 def: InstRW<[SBWriteResGroup87], (instregex "FARCALL64")>;
2222
2223 def SBWriteResGroup88 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
2224   let Latency = 8;
2225   let NumMicroOps = 5;
2226   let ResourceCycles = [1,2,1,1];
2227 }
2228 def: InstRW<[SBWriteResGroup88], (instregex "SHLD(16|32|64)mri8")>;
2229 def: InstRW<[SBWriteResGroup88], (instregex "SHRD(16|32|64)mri8")>;
2230
2231 def SBWriteResGroup89 : SchedWriteRes<[SBPort0,SBPort23]> {
2232   let Latency = 9;
2233   let NumMicroOps = 2;
2234   let ResourceCycles = [1,1];
2235 }
2236 def: InstRW<[SBWriteResGroup89], (instregex "MMX_PMULUDQirm")>;
2237 def: InstRW<[SBWriteResGroup89], (instregex "PMADDUBSWrm")>;
2238 def: InstRW<[SBWriteResGroup89], (instregex "PMADDWDrm")>;
2239 def: InstRW<[SBWriteResGroup89], (instregex "PMULDQrm")>;
2240 def: InstRW<[SBWriteResGroup89], (instregex "PMULHRSWrm")>;
2241 def: InstRW<[SBWriteResGroup89], (instregex "PMULHUWrm")>;
2242 def: InstRW<[SBWriteResGroup89], (instregex "PMULHWrm")>;
2243 def: InstRW<[SBWriteResGroup89], (instregex "PMULLDrm")>;
2244 def: InstRW<[SBWriteResGroup89], (instregex "PMULLWrm")>;
2245 def: InstRW<[SBWriteResGroup89], (instregex "PMULUDQrm")>;
2246 def: InstRW<[SBWriteResGroup89], (instregex "PSADBWrm")>;
2247 def: InstRW<[SBWriteResGroup89], (instregex "VPMADDUBSWrm")>;
2248 def: InstRW<[SBWriteResGroup89], (instregex "VPMADDWDrm")>;
2249 def: InstRW<[SBWriteResGroup89], (instregex "VPMULDQrm")>;
2250 def: InstRW<[SBWriteResGroup89], (instregex "VPMULHRSWrm")>;
2251 def: InstRW<[SBWriteResGroup89], (instregex "VPMULHUWrm")>;
2252 def: InstRW<[SBWriteResGroup89], (instregex "VPMULHWrm")>;
2253 def: InstRW<[SBWriteResGroup89], (instregex "VPMULLDrm")>;
2254 def: InstRW<[SBWriteResGroup89], (instregex "VPMULLWrm")>;
2255 def: InstRW<[SBWriteResGroup89], (instregex "VPMULUDQrm")>;
2256 def: InstRW<[SBWriteResGroup89], (instregex "VPSADBWrm")>;
2257
2258 def SBWriteResGroup90 : SchedWriteRes<[SBPort1,SBPort23]> {
2259   let Latency = 9;
2260   let NumMicroOps = 2;
2261   let ResourceCycles = [1,1];
2262 }
2263 def: InstRW<[SBWriteResGroup90], (instregex "ADDPDrm")>;
2264 def: InstRW<[SBWriteResGroup90], (instregex "ADDPSrm")>;
2265 def: InstRW<[SBWriteResGroup90], (instregex "ADDSDrm")>;
2266 def: InstRW<[SBWriteResGroup90], (instregex "ADDSSrm")>;
2267 def: InstRW<[SBWriteResGroup90], (instregex "ADDSUBPDrm")>;
2268 def: InstRW<[SBWriteResGroup90], (instregex "ADDSUBPSrm")>;
2269 def: InstRW<[SBWriteResGroup90], (instregex "CMPPDrmi")>;
2270 def: InstRW<[SBWriteResGroup90], (instregex "CMPPSrmi")>;
2271 def: InstRW<[SBWriteResGroup90], (instregex "CMPSDrm")>;
2272 def: InstRW<[SBWriteResGroup90], (instregex "CMPSSrm")>;
2273 def: InstRW<[SBWriteResGroup90], (instregex "CVTDQ2PSrm")>;
2274 def: InstRW<[SBWriteResGroup90], (instregex "CVTPS2DQrm")>;
2275 def: InstRW<[SBWriteResGroup90], (instregex "CVTSI642SDrm")>;
2276 def: InstRW<[SBWriteResGroup90], (instregex "CVTSI2SDrm")>;
2277 def: InstRW<[SBWriteResGroup90], (instregex "CVTTPS2DQrm")>;
2278 def: InstRW<[SBWriteResGroup90], (instregex "MAX(C?)PDrm")>;
2279 def: InstRW<[SBWriteResGroup90], (instregex "MAX(C?)PSrm")>;
2280 def: InstRW<[SBWriteResGroup90], (instregex "MAX(C?)SDrm")>;
2281 def: InstRW<[SBWriteResGroup90], (instregex "MAX(C?)SSrm")>;
2282 def: InstRW<[SBWriteResGroup90], (instregex "MIN(C?)PDrm")>;
2283 def: InstRW<[SBWriteResGroup90], (instregex "MIN(C?)PSrm")>;
2284 def: InstRW<[SBWriteResGroup90], (instregex "MIN(C?)SDrm")>;
2285 def: InstRW<[SBWriteResGroup90], (instregex "MIN(C?)SSrm")>;
2286 def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPI2PSirm")>;
2287 def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPS2PIirm")>;
2288 def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTTPS2PIirm")>;
2289 def: InstRW<[SBWriteResGroup90], (instregex "POPCNT(16|32|64)rm")>;
2290 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDPDm")>;
2291 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDPSm")>;
2292 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDSDm")>;
2293 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDSSm")>;
2294 def: InstRW<[SBWriteResGroup90], (instregex "SUBPDrm")>;
2295 def: InstRW<[SBWriteResGroup90], (instregex "SUBPSrm")>;
2296 def: InstRW<[SBWriteResGroup90], (instregex "SUBSDrm")>;
2297 def: InstRW<[SBWriteResGroup90], (instregex "SUBSSrm")>;
2298 def: InstRW<[SBWriteResGroup90], (instregex "VADDPDrm")>;
2299 def: InstRW<[SBWriteResGroup90], (instregex "VADDPSrm")>;
2300 def: InstRW<[SBWriteResGroup90], (instregex "VADDSDrm")>;
2301 def: InstRW<[SBWriteResGroup90], (instregex "VADDSSrm")>;
2302 def: InstRW<[SBWriteResGroup90], (instregex "VADDSUBPDrm")>;
2303 def: InstRW<[SBWriteResGroup90], (instregex "VADDSUBPSrm")>;
2304 def: InstRW<[SBWriteResGroup90], (instregex "VCMPPDrmi")>;
2305 def: InstRW<[SBWriteResGroup90], (instregex "VCMPPSrmi")>;
2306 def: InstRW<[SBWriteResGroup90], (instregex "VCMPSDrm")>;
2307 def: InstRW<[SBWriteResGroup90], (instregex "VCMPSSrm")>;
2308 def: InstRW<[SBWriteResGroup90], (instregex "VCVTDQ2PSrm")>;
2309 def: InstRW<[SBWriteResGroup90], (instregex "VCVTPS2DQrm")>;
2310 def: InstRW<[SBWriteResGroup90], (instregex "VCVTSI642SDrm")>;
2311 def: InstRW<[SBWriteResGroup90], (instregex "VCVTSI2SDrm")>;
2312 def: InstRW<[SBWriteResGroup90], (instregex "VCVTTPS2DQrm")>;
2313 def: InstRW<[SBWriteResGroup90], (instregex "VMAX(C?)PDrm")>;
2314 def: InstRW<[SBWriteResGroup90], (instregex "VMAX(C?)PSrm")>;
2315 def: InstRW<[SBWriteResGroup90], (instregex "VMAX(C?)SDrm")>;
2316 def: InstRW<[SBWriteResGroup90], (instregex "VMAX(C?)SSrm")>;
2317 def: InstRW<[SBWriteResGroup90], (instregex "VMIN(C?)PDrm")>;
2318 def: InstRW<[SBWriteResGroup90], (instregex "VMIN(C?)PSrm")>;
2319 def: InstRW<[SBWriteResGroup90], (instregex "VMIN(C?)SDrm")>;
2320 def: InstRW<[SBWriteResGroup90], (instregex "VMIN(C?)SSrm")>;
2321 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDPDm")>;
2322 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDPSm")>;
2323 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDSDm")>;
2324 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDSSm")>;
2325 def: InstRW<[SBWriteResGroup90], (instregex "VSUBPDrm")>;
2326 def: InstRW<[SBWriteResGroup90], (instregex "VSUBPSrm")>;
2327 def: InstRW<[SBWriteResGroup90], (instregex "VSUBSDrm")>;
2328 def: InstRW<[SBWriteResGroup90], (instregex "VSUBSSrm")>;
2329
2330 def SBWriteResGroup91 : SchedWriteRes<[SBPort23,SBPort05]> {
2331   let Latency = 9;
2332   let NumMicroOps = 3;
2333   let ResourceCycles = [1,2];
2334 }
2335 def: InstRW<[SBWriteResGroup91], (instregex "VBLENDVPDYrm")>;
2336 def: InstRW<[SBWriteResGroup91], (instregex "VBLENDVPSYrm")>;
2337 def: InstRW<[SBWriteResGroup91], (instregex "VMASKMOVPDYrm")>;
2338 def: InstRW<[SBWriteResGroup91], (instregex "VMASKMOVPSYrm")>;
2339
2340 def SBWriteResGroup92 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
2341   let Latency = 9;
2342   let NumMicroOps = 3;
2343   let ResourceCycles = [1,1,1];
2344 }
2345 def: InstRW<[SBWriteResGroup92], (instregex "DPPDrri")>;
2346 def: InstRW<[SBWriteResGroup92], (instregex "VDPPDrri")>;
2347
2348 def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2349   let Latency = 9;
2350   let NumMicroOps = 3;
2351   let ResourceCycles = [1,1,1];
2352 }
2353 def: InstRW<[SBWriteResGroup93], (instregex "CVTSD2SI64rm")>;
2354 def: InstRW<[SBWriteResGroup93], (instregex "CVTSD2SIrm")>;
2355 def: InstRW<[SBWriteResGroup93], (instregex "CVTSS2SI64rm")>;
2356 def: InstRW<[SBWriteResGroup93], (instregex "CVTSS2SIrm")>;
2357 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSD2SI64rm")>;
2358 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSD2SIrm")>;
2359 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSS2SI64rm")>;
2360 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSS2SIrm")>;
2361 def: InstRW<[SBWriteResGroup93], (instregex "MUL(16|32|64)m")>;
2362
2363 def SBWriteResGroup94 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> {
2364   let Latency = 9;
2365   let NumMicroOps = 3;
2366   let ResourceCycles = [1,1,1];
2367 }
2368 def: InstRW<[SBWriteResGroup94], (instregex "VPTESTYrm")>;
2369
2370 def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
2371   let Latency = 9;
2372   let NumMicroOps = 3;
2373   let ResourceCycles = [1,1,1];
2374 }
2375 def: InstRW<[SBWriteResGroup95], (instregex "LD_F32m")>;
2376 def: InstRW<[SBWriteResGroup95], (instregex "LD_F64m")>;
2377 def: InstRW<[SBWriteResGroup95], (instregex "LD_F80m")>;
2378
2379 def SBWriteResGroup96 : SchedWriteRes<[SBPort23,SBPort15]> {
2380   let Latency = 9;
2381   let NumMicroOps = 4;
2382   let ResourceCycles = [1,3];
2383 }
2384 def: InstRW<[SBWriteResGroup96], (instregex "PHADDDrm")>;
2385 def: InstRW<[SBWriteResGroup96], (instregex "PHADDSWrm128")>;
2386 def: InstRW<[SBWriteResGroup96], (instregex "PHADDWrm")>;
2387 def: InstRW<[SBWriteResGroup96], (instregex "PHSUBDrm")>;
2388 def: InstRW<[SBWriteResGroup96], (instregex "PHSUBSWrm128")>;
2389 def: InstRW<[SBWriteResGroup96], (instregex "PHSUBWrm")>;
2390 def: InstRW<[SBWriteResGroup96], (instregex "VPHADDDrm")>;
2391 def: InstRW<[SBWriteResGroup96], (instregex "VPHADDSWrm128")>;
2392 def: InstRW<[SBWriteResGroup96], (instregex "VPHADDWrm")>;
2393 def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBDrm")>;
2394 def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBSWrm128")>;
2395 def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBWrm")>;
2396
2397 def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
2398   let Latency = 9;
2399   let NumMicroOps = 4;
2400   let ResourceCycles = [1,1,2];
2401 }
2402 def: InstRW<[SBWriteResGroup97], (instregex "IST_F16m")>;
2403 def: InstRW<[SBWriteResGroup97], (instregex "IST_F32m")>;
2404 def: InstRW<[SBWriteResGroup97], (instregex "IST_FP16m")>;
2405 def: InstRW<[SBWriteResGroup97], (instregex "IST_FP32m")>;
2406 def: InstRW<[SBWriteResGroup97], (instregex "IST_FP64m")>;
2407
2408 def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
2409   let Latency = 9;
2410   let NumMicroOps = 6;
2411   let ResourceCycles = [1,2,3];
2412 }
2413 def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(16|32|64)mCL")>;
2414 def: InstRW<[SBWriteResGroup97_2], (instregex "ROL8mCL")>;
2415 def: InstRW<[SBWriteResGroup97_2], (instregex "ROR(16|32|64)mCL")>;
2416 def: InstRW<[SBWriteResGroup97_2], (instregex "ROR8mCL")>;
2417 def: InstRW<[SBWriteResGroup97_2], (instregex "SAR(16|32|64)mCL")>;
2418 def: InstRW<[SBWriteResGroup97_2], (instregex "SAR8mCL")>;
2419 def: InstRW<[SBWriteResGroup97_2], (instregex "SHL(16|32|64)mCL")>;
2420 def: InstRW<[SBWriteResGroup97_2], (instregex "SHL8mCL")>;
2421 def: InstRW<[SBWriteResGroup97_2], (instregex "SHR(16|32|64)mCL")>;
2422 def: InstRW<[SBWriteResGroup97_2], (instregex "SHR8mCL")>;
2423
2424 def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
2425   let Latency = 9;
2426   let NumMicroOps = 6;
2427   let ResourceCycles = [1,2,3];
2428 }
2429 def: InstRW<[SBWriteResGroup98], (instregex "ADC(16|32|64)mi")>;
2430 def: InstRW<[SBWriteResGroup98], (instregex "ADC8mi")>;
2431 def: InstRW<[SBWriteResGroup98], (instregex "SBB(16|32|64)mi")>;
2432 def: InstRW<[SBWriteResGroup98], (instregex "SBB8mi")>;
2433
2434 def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
2435   let Latency = 9;
2436   let NumMicroOps = 6;
2437   let ResourceCycles = [1,2,2,1];
2438 }
2439 def: InstRW<[SBWriteResGroup99], (instregex "ADC(16|32|64)mr")>;
2440 def: InstRW<[SBWriteResGroup99], (instregex "ADC8mr")>;
2441 def: InstRW<[SBWriteResGroup99], (instregex "SBB(16|32|64)mr")>;
2442 def: InstRW<[SBWriteResGroup99], (instregex "SBB8mr")>;
2443
2444 def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> {
2445   let Latency = 9;
2446   let NumMicroOps = 6;
2447   let ResourceCycles = [1,1,2,1,1];
2448 }
2449 def: InstRW<[SBWriteResGroup100], (instregex "BT(16|32|64)mr")>;
2450 def: InstRW<[SBWriteResGroup100], (instregex "BTC(16|32|64)mr")>;
2451 def: InstRW<[SBWriteResGroup100], (instregex "BTR(16|32|64)mr")>;
2452 def: InstRW<[SBWriteResGroup100], (instregex "BTS(16|32|64)mr")>;
2453
2454 def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
2455   let Latency = 10;
2456   let NumMicroOps = 2;
2457   let ResourceCycles = [1,1];
2458 }
2459 def: InstRW<[SBWriteResGroup101], (instregex "ADD_F32m")>;
2460 def: InstRW<[SBWriteResGroup101], (instregex "ADD_F64m")>;
2461 def: InstRW<[SBWriteResGroup101], (instregex "ILD_F16m")>;
2462 def: InstRW<[SBWriteResGroup101], (instregex "ILD_F32m")>;
2463 def: InstRW<[SBWriteResGroup101], (instregex "ILD_F64m")>;
2464 def: InstRW<[SBWriteResGroup101], (instregex "SUBR_F32m")>;
2465 def: InstRW<[SBWriteResGroup101], (instregex "SUBR_F64m")>;
2466 def: InstRW<[SBWriteResGroup101], (instregex "SUB_F32m")>;
2467 def: InstRW<[SBWriteResGroup101], (instregex "SUB_F64m")>;
2468 def: InstRW<[SBWriteResGroup101], (instregex "VADDPDYrm")>;
2469 def: InstRW<[SBWriteResGroup101], (instregex "VADDPSYrm")>;
2470 def: InstRW<[SBWriteResGroup101], (instregex "VADDSUBPDYrm")>;
2471 def: InstRW<[SBWriteResGroup101], (instregex "VADDSUBPSYrm")>;
2472 def: InstRW<[SBWriteResGroup101], (instregex "VCMPPDYrmi")>;
2473 def: InstRW<[SBWriteResGroup101], (instregex "VCMPPSYrmi")>;
2474 def: InstRW<[SBWriteResGroup101], (instregex "VCVTDQ2PSYrm")>;
2475 def: InstRW<[SBWriteResGroup101], (instregex "VCVTPS2DQYrm")>;
2476 def: InstRW<[SBWriteResGroup101], (instregex "VCVTTPS2DQYrm")>;
2477 def: InstRW<[SBWriteResGroup101], (instregex "VMAX(C?)PDYrm")>;
2478 def: InstRW<[SBWriteResGroup101], (instregex "VMAX(C?)PSYrm")>;
2479 def: InstRW<[SBWriteResGroup101], (instregex "VMIN(C?)PDYrm")>;
2480 def: InstRW<[SBWriteResGroup101], (instregex "VMIN(C?)PSYrm")>;
2481 def: InstRW<[SBWriteResGroup101], (instregex "VROUNDYPDm")>;
2482 def: InstRW<[SBWriteResGroup101], (instregex "VROUNDYPSm")>;
2483 def: InstRW<[SBWriteResGroup101], (instregex "VSUBPDYrm")>;
2484 def: InstRW<[SBWriteResGroup101], (instregex "VSUBPSYrm")>;
2485
2486 def SBWriteResGroup102 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2487   let Latency = 10;
2488   let NumMicroOps = 3;
2489   let ResourceCycles = [1,1,1];
2490 }
2491 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSD2SI64rm")>;
2492 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSD2SIrm")>;
2493 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSS2SI64rm")>;
2494 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSS2SIrm")>;
2495 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSD2SI64rm")>;
2496 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSD2SIrm")>;
2497 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSS2SI64rm")>;
2498 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSS2SIrm")>;
2499
2500 def SBWriteResGroup103 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2501   let Latency = 10;
2502   let NumMicroOps = 3;
2503   let ResourceCycles = [1,1,1];
2504 }
2505 def: InstRW<[SBWriteResGroup103], (instregex "CVTDQ2PDrm")>;
2506 def: InstRW<[SBWriteResGroup103], (instregex "CVTPD2DQrm")>;
2507 def: InstRW<[SBWriteResGroup103], (instregex "CVTPD2PSrm")>;
2508 def: InstRW<[SBWriteResGroup103], (instregex "CVTSD2SSrm")>;
2509 def: InstRW<[SBWriteResGroup103], (instregex "CVTSI642SSrm")>;
2510 def: InstRW<[SBWriteResGroup103], (instregex "CVTSI2SSrm")>;
2511 def: InstRW<[SBWriteResGroup103], (instregex "CVTTPD2DQrm")>;
2512 def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPD2PIirm")>;
2513 def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPI2PDirm")>;
2514 def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTTPD2PIirm")>;
2515 def: InstRW<[SBWriteResGroup103], (instregex "VCVTDQ2PDYrm")>;
2516 def: InstRW<[SBWriteResGroup103], (instregex "VCVTDQ2PDrm")>;
2517 def: InstRW<[SBWriteResGroup103], (instregex "VCVTPD2DQrm")>;
2518 def: InstRW<[SBWriteResGroup103], (instregex "VCVTPD2PSrm")>;
2519 def: InstRW<[SBWriteResGroup103], (instregex "VCVTSD2SSrm")>;
2520 def: InstRW<[SBWriteResGroup103], (instregex "VCVTSI642SSrm")>;
2521 def: InstRW<[SBWriteResGroup103], (instregex "VCVTSI2SSrm")>;
2522 def: InstRW<[SBWriteResGroup103], (instregex "VCVTTPD2DQrm")>;
2523
2524 def SBWriteResGroup103_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
2525   let Latency = 10;
2526   let NumMicroOps = 7;
2527   let ResourceCycles = [1,2,3,1];
2528 }
2529 def: InstRW<[SBWriteResGroup103_2], (instregex "SHLD(16|32|64)mrCL")>;
2530 def: InstRW<[SBWriteResGroup103_2], (instregex "SHRD(16|32|64)mrCL")>;
2531
2532 def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> {
2533   let Latency = 11;
2534   let NumMicroOps = 2;
2535   let ResourceCycles = [1,1];
2536 }
2537 def: InstRW<[SBWriteResGroup104], (instregex "MULPDrm")>;
2538 def: InstRW<[SBWriteResGroup104], (instregex "MULPSrm")>;
2539 def: InstRW<[SBWriteResGroup104], (instregex "MULSDrm")>;
2540 def: InstRW<[SBWriteResGroup104], (instregex "MULSSrm")>;
2541 def: InstRW<[SBWriteResGroup104], (instregex "PCMPGTQrm")>;
2542 def: InstRW<[SBWriteResGroup104], (instregex "PHMINPOSUWrm128")>;
2543 def: InstRW<[SBWriteResGroup104], (instregex "RCPPSm")>;
2544 def: InstRW<[SBWriteResGroup104], (instregex "RCPSSm")>;
2545 def: InstRW<[SBWriteResGroup104], (instregex "RSQRTPSm")>;
2546 def: InstRW<[SBWriteResGroup104], (instregex "RSQRTSSm")>;
2547 def: InstRW<[SBWriteResGroup104], (instregex "VMULPDrm")>;
2548 def: InstRW<[SBWriteResGroup104], (instregex "VMULPSrm")>;
2549 def: InstRW<[SBWriteResGroup104], (instregex "VMULSDrm")>;
2550 def: InstRW<[SBWriteResGroup104], (instregex "VMULSSrm")>;
2551 def: InstRW<[SBWriteResGroup104], (instregex "VPCMPGTQrm")>;
2552 def: InstRW<[SBWriteResGroup104], (instregex "VPHMINPOSUWrm128")>;
2553 def: InstRW<[SBWriteResGroup104], (instregex "VRCPPSm")>;
2554 def: InstRW<[SBWriteResGroup104], (instregex "VRCPSSm")>;
2555 def: InstRW<[SBWriteResGroup104], (instregex "VRSQRTPSm")>;
2556 def: InstRW<[SBWriteResGroup104], (instregex "VRSQRTSSm")>;
2557
2558 def SBWriteResGroup105 : SchedWriteRes<[SBPort0]> {
2559   let Latency = 11;
2560   let NumMicroOps = 3;
2561   let ResourceCycles = [3];
2562 }
2563 def: InstRW<[SBWriteResGroup105], (instregex "PCMPISTRIrr")>;
2564 def: InstRW<[SBWriteResGroup105], (instregex "PCMPISTRM128rr")>;
2565 def: InstRW<[SBWriteResGroup105], (instregex "VPCMPISTRIrr")>;
2566 def: InstRW<[SBWriteResGroup105], (instregex "VPCMPISTRM128rr")>;
2567
2568 def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
2569   let Latency = 11;
2570   let NumMicroOps = 3;
2571   let ResourceCycles = [2,1];
2572 }
2573 def: InstRW<[SBWriteResGroup106], (instregex "FICOM16m")>;
2574 def: InstRW<[SBWriteResGroup106], (instregex "FICOM32m")>;
2575 def: InstRW<[SBWriteResGroup106], (instregex "FICOMP16m")>;
2576 def: InstRW<[SBWriteResGroup106], (instregex "FICOMP32m")>;
2577
2578 def SBWriteResGroup107 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2579   let Latency = 11;
2580   let NumMicroOps = 3;
2581   let ResourceCycles = [1,1,1];
2582 }
2583 def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2DQYrm")>;
2584 def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2PSYrm")>;
2585 def: InstRW<[SBWriteResGroup107], (instregex "VCVTTPD2DQYrm")>;
2586
2587 def SBWriteResGroup108 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> {
2588   let Latency = 11;
2589   let NumMicroOps = 4;
2590   let ResourceCycles = [1,1,2];
2591 }
2592 def: InstRW<[SBWriteResGroup108], (instregex "MPSADBWrmi")>;
2593 def: InstRW<[SBWriteResGroup108], (instregex "VMPSADBWrmi")>;
2594
2595 def SBWriteResGroup109 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2596   let Latency = 11;
2597   let NumMicroOps = 4;
2598   let ResourceCycles = [1,2,1];
2599 }
2600 def: InstRW<[SBWriteResGroup109], (instregex "HADDPDrm")>;
2601 def: InstRW<[SBWriteResGroup109], (instregex "HADDPSrm")>;
2602 def: InstRW<[SBWriteResGroup109], (instregex "HSUBPDrm")>;
2603 def: InstRW<[SBWriteResGroup109], (instregex "HSUBPSrm")>;
2604 def: InstRW<[SBWriteResGroup109], (instregex "VHADDPDrm")>;
2605 def: InstRW<[SBWriteResGroup109], (instregex "VHADDPSrm")>;
2606 def: InstRW<[SBWriteResGroup109], (instregex "VHSUBPDrm")>;
2607 def: InstRW<[SBWriteResGroup109], (instregex "VHSUBPSrm")>;
2608
2609 def SBWriteResGroup110 : SchedWriteRes<[SBPort5]> {
2610   let Latency = 12;
2611   let NumMicroOps = 2;
2612   let ResourceCycles = [2];
2613 }
2614 def: InstRW<[SBWriteResGroup110], (instregex "AESIMCrr")>;
2615 def: InstRW<[SBWriteResGroup110], (instregex "VAESIMCrr")>;
2616
2617 def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
2618   let Latency = 12;
2619   let NumMicroOps = 2;
2620   let ResourceCycles = [1,1];
2621 }
2622 def: InstRW<[SBWriteResGroup111], (instregex "MUL_F32m")>;
2623 def: InstRW<[SBWriteResGroup111], (instregex "MUL_F64m")>;
2624 def: InstRW<[SBWriteResGroup111], (instregex "VMULPDYrm")>;
2625 def: InstRW<[SBWriteResGroup111], (instregex "VMULPSYrm")>;
2626
2627 def SBWriteResGroup112 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
2628   let Latency = 12;
2629   let NumMicroOps = 4;
2630   let ResourceCycles = [1,2,1];
2631 }
2632 def: InstRW<[SBWriteResGroup112], (instregex "DPPSrri")>;
2633 def: InstRW<[SBWriteResGroup112], (instregex "VDPPSYrri")>;
2634 def: InstRW<[SBWriteResGroup112], (instregex "VDPPSrri")>;
2635
2636 def SBWriteResGroup113 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2637   let Latency = 12;
2638   let NumMicroOps = 4;
2639   let ResourceCycles = [1,2,1];
2640 }
2641 def: InstRW<[SBWriteResGroup113], (instregex "VHADDPDYrm")>;
2642 def: InstRW<[SBWriteResGroup113], (instregex "VHADDPSYrm")>;
2643 def: InstRW<[SBWriteResGroup113], (instregex "VHSUBPDYrm")>;
2644 def: InstRW<[SBWriteResGroup113], (instregex "VHSUBPSYrm")>;
2645
2646 def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> {
2647   let Latency = 13;
2648   let NumMicroOps = 3;
2649   let ResourceCycles = [2,1];
2650 }
2651 def: InstRW<[SBWriteResGroup114], (instregex "ADD_FI16m")>;
2652 def: InstRW<[SBWriteResGroup114], (instregex "ADD_FI32m")>;
2653 def: InstRW<[SBWriteResGroup114], (instregex "SUBR_FI16m")>;
2654 def: InstRW<[SBWriteResGroup114], (instregex "SUBR_FI32m")>;
2655 def: InstRW<[SBWriteResGroup114], (instregex "SUB_FI16m")>;
2656 def: InstRW<[SBWriteResGroup114], (instregex "SUB_FI32m")>;
2657
2658 def SBWriteResGroup115 : SchedWriteRes<[SBPort5,SBPort23,SBPort015]> {
2659   let Latency = 13;
2660   let NumMicroOps = 3;
2661   let ResourceCycles = [1,1,1];
2662 }
2663 def: InstRW<[SBWriteResGroup115], (instregex "AESDECLASTrm")>;
2664 def: InstRW<[SBWriteResGroup115], (instregex "AESDECrm")>;
2665 def: InstRW<[SBWriteResGroup115], (instregex "AESENCLASTrm")>;
2666 def: InstRW<[SBWriteResGroup115], (instregex "AESENCrm")>;
2667 def: InstRW<[SBWriteResGroup115], (instregex "VAESDECLASTrm")>;
2668 def: InstRW<[SBWriteResGroup115], (instregex "VAESDECrm")>;
2669 def: InstRW<[SBWriteResGroup115], (instregex "VAESENCLASTrm")>;
2670 def: InstRW<[SBWriteResGroup115], (instregex "VAESENCrm")>;
2671
2672 def SBWriteResGroup116 : SchedWriteRes<[SBPort0]> {
2673   let Latency = 14;
2674   let NumMicroOps = 1;
2675   let ResourceCycles = [1];
2676 }
2677 def: InstRW<[SBWriteResGroup116], (instregex "DIVPSrr")>;
2678 def: InstRW<[SBWriteResGroup116], (instregex "DIVSSrr")>;
2679 def: InstRW<[SBWriteResGroup116], (instregex "SQRTPSr")>;
2680 def: InstRW<[SBWriteResGroup116], (instregex "SQRTSSr")>;
2681 def: InstRW<[SBWriteResGroup116], (instregex "VDIVPSrr")>;
2682 def: InstRW<[SBWriteResGroup116], (instregex "VDIVSSrr")>;
2683 def: InstRW<[SBWriteResGroup116], (instregex "VSQRTPSr")>;
2684
2685 def SBWriteResGroup117 : SchedWriteRes<[SBPort0,SBPort23]> {
2686   let Latency = 14;
2687   let NumMicroOps = 2;
2688   let ResourceCycles = [1,1];
2689 }
2690 def: InstRW<[SBWriteResGroup117], (instregex "VSQRTSSm")>;
2691
2692 def SBWriteResGroup118 : SchedWriteRes<[SBPort0,SBPort23,SBPort05]> {
2693   let Latency = 14;
2694   let NumMicroOps = 4;
2695   let ResourceCycles = [2,1,1];
2696 }
2697 def: InstRW<[SBWriteResGroup118], (instregex "VRCPPSYm")>;
2698 def: InstRW<[SBWriteResGroup118], (instregex "VRSQRTPSYm")>;
2699
2700 def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2701   let Latency = 15;
2702   let NumMicroOps = 3;
2703   let ResourceCycles = [1,1,1];
2704 }
2705 def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI16m")>;
2706 def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI32m")>;
2707
2708 def SBWriteResGroup120 : SchedWriteRes<[SBPort0,SBPort1,SBPort5,SBPort23]> {
2709   let Latency = 15;
2710   let NumMicroOps = 4;
2711   let ResourceCycles = [1,1,1,1];
2712 }
2713 def: InstRW<[SBWriteResGroup120], (instregex "DPPDrmi")>;
2714 def: InstRW<[SBWriteResGroup120], (instregex "VDPPDrmi")>;
2715
2716 def SBWriteResGroup121 : SchedWriteRes<[SBPort0,SBPort23]> {
2717   let Latency = 17;
2718   let NumMicroOps = 4;
2719   let ResourceCycles = [3,1];
2720 }
2721 def: InstRW<[SBWriteResGroup121], (instregex "PCMPISTRIrm")>;
2722 def: InstRW<[SBWriteResGroup121], (instregex "PCMPISTRM128rm")>;
2723 def: InstRW<[SBWriteResGroup121], (instregex "VPCMPISTRIrm")>;
2724 def: InstRW<[SBWriteResGroup121], (instregex "VPCMPISTRM128rm")>;
2725
2726 def SBWriteResGroup122 : SchedWriteRes<[SBPort5,SBPort23]> {
2727   let Latency = 18;
2728   let NumMicroOps = 3;
2729   let ResourceCycles = [2,1];
2730 }
2731 def: InstRW<[SBWriteResGroup122], (instregex "AESIMCrm")>;
2732 def: InstRW<[SBWriteResGroup122], (instregex "VAESIMCrm")>;
2733
2734 def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23]> {
2735   let Latency = 20;
2736   let NumMicroOps = 2;
2737   let ResourceCycles = [1,1];
2738 }
2739 def: InstRW<[SBWriteResGroup123], (instregex "DIVPSrm")>;
2740 def: InstRW<[SBWriteResGroup123], (instregex "DIVSSrm")>;
2741 def: InstRW<[SBWriteResGroup123], (instregex "SQRTPSm")>;
2742 def: InstRW<[SBWriteResGroup123], (instregex "SQRTSSm")>;
2743 def: InstRW<[SBWriteResGroup123], (instregex "VDIVPSrm")>;
2744 def: InstRW<[SBWriteResGroup123], (instregex "VDIVSSrm")>;
2745 def: InstRW<[SBWriteResGroup123], (instregex "VSQRTPSm")>;
2746
2747 def SBWriteResGroup124 : SchedWriteRes<[SBPort0]> {
2748   let Latency = 21;
2749   let NumMicroOps = 1;
2750   let ResourceCycles = [1];
2751 }
2752 def: InstRW<[SBWriteResGroup124], (instregex "VSQRTSDr")>;
2753
2754 def SBWriteResGroup125 : SchedWriteRes<[SBPort0,SBPort23]> {
2755   let Latency = 21;
2756   let NumMicroOps = 2;
2757   let ResourceCycles = [1,1];
2758 }
2759 def: InstRW<[SBWriteResGroup125], (instregex "VSQRTSDm")>;
2760
2761 def SBWriteResGroup126 : SchedWriteRes<[SBPort0]> {
2762   let Latency = 22;
2763   let NumMicroOps = 1;
2764   let ResourceCycles = [1];
2765 }
2766 def: InstRW<[SBWriteResGroup126], (instregex "DIVPDrr")>;
2767 def: InstRW<[SBWriteResGroup126], (instregex "DIVSDrr")>;
2768 def: InstRW<[SBWriteResGroup126], (instregex "SQRTPDr")>;
2769 def: InstRW<[SBWriteResGroup126], (instregex "SQRTSDr")>;
2770 def: InstRW<[SBWriteResGroup126], (instregex "VDIVPDrr")>;
2771 def: InstRW<[SBWriteResGroup126], (instregex "VDIVSDrr")>;
2772 def: InstRW<[SBWriteResGroup126], (instregex "VSQRTPDr")>;
2773
2774 def SBWriteResGroup127 : SchedWriteRes<[SBPort0]> {
2775   let Latency = 24;
2776   let NumMicroOps = 1;
2777   let ResourceCycles = [1];
2778 }
2779 def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FPrST0")>;
2780 def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FST0r")>;
2781 def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FrST0")>;
2782 def: InstRW<[SBWriteResGroup127], (instregex "DIV_FPrST0")>;
2783 def: InstRW<[SBWriteResGroup127], (instregex "DIV_FST0r")>;
2784 def: InstRW<[SBWriteResGroup127], (instregex "DIV_FrST0")>;
2785
2786 def SBWriteResGroup128 : SchedWriteRes<[SBPort0,SBPort23]> {
2787   let Latency = 28;
2788   let NumMicroOps = 2;
2789   let ResourceCycles = [1,1];
2790 }
2791 def: InstRW<[SBWriteResGroup128], (instregex "DIVPDrm")>;
2792 def: InstRW<[SBWriteResGroup128], (instregex "DIVSDrm")>;
2793 def: InstRW<[SBWriteResGroup128], (instregex "SQRTPDm")>;
2794 def: InstRW<[SBWriteResGroup128], (instregex "SQRTSDm")>;
2795 def: InstRW<[SBWriteResGroup128], (instregex "VDIVPDrm")>;
2796 def: InstRW<[SBWriteResGroup128], (instregex "VDIVSDrm")>;
2797 def: InstRW<[SBWriteResGroup128], (instregex "VSQRTPDm")>;
2798
2799 def SBWriteResGroup129 : SchedWriteRes<[SBPort0,SBPort05]> {
2800   let Latency = 29;
2801   let NumMicroOps = 3;
2802   let ResourceCycles = [2,1];
2803 }
2804 def: InstRW<[SBWriteResGroup129], (instregex "VDIVPSYrr")>;
2805 def: InstRW<[SBWriteResGroup129], (instregex "VSQRTPSYr")>;
2806
2807 def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> {
2808   let Latency = 31;
2809   let NumMicroOps = 2;
2810   let ResourceCycles = [1,1];
2811 }
2812 def: InstRW<[SBWriteResGroup130], (instregex "DIVR_F32m")>;
2813 def: InstRW<[SBWriteResGroup130], (instregex "DIVR_F64m")>;
2814 def: InstRW<[SBWriteResGroup130], (instregex "DIV_F32m")>;
2815 def: InstRW<[SBWriteResGroup130], (instregex "DIV_F64m")>;
2816
2817 def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2818   let Latency = 34;
2819   let NumMicroOps = 3;
2820   let ResourceCycles = [1,1,1];
2821 }
2822 def: InstRW<[SBWriteResGroup131], (instregex "DIVR_FI16m")>;
2823 def: InstRW<[SBWriteResGroup131], (instregex "DIVR_FI32m")>;
2824 def: InstRW<[SBWriteResGroup131], (instregex "DIV_FI16m")>;
2825 def: InstRW<[SBWriteResGroup131], (instregex "DIV_FI32m")>;
2826
2827 def SBWriteResGroup132 : SchedWriteRes<[SBPort0,SBPort23,SBPort05]> {
2828   let Latency = 36;
2829   let NumMicroOps = 4;
2830   let ResourceCycles = [2,1,1];
2831 }
2832 def: InstRW<[SBWriteResGroup132], (instregex "VDIVPSYrm")>;
2833 def: InstRW<[SBWriteResGroup132], (instregex "VSQRTPSYm")>;
2834
2835 def SBWriteResGroup133 : SchedWriteRes<[SBPort0,SBPort05]> {
2836   let Latency = 45;
2837   let NumMicroOps = 3;
2838   let ResourceCycles = [2,1];
2839 }
2840 def: InstRW<[SBWriteResGroup133], (instregex "VDIVPDYrr")>;
2841 def: InstRW<[SBWriteResGroup133], (instregex "VSQRTPDYr")>;
2842
2843 def SBWriteResGroup134 : SchedWriteRes<[SBPort0,SBPort23,SBPort05]> {
2844   let Latency = 52;
2845   let NumMicroOps = 4;
2846   let ResourceCycles = [2,1,1];
2847 }
2848 def: InstRW<[SBWriteResGroup134], (instregex "VDIVPDYrm")>;
2849 def: InstRW<[SBWriteResGroup134], (instregex "VSQRTPDYm")>;
2850
2851 def SBWriteResGroup135 : SchedWriteRes<[SBPort0]> {
2852   let Latency = 114;
2853   let NumMicroOps = 1;
2854   let ResourceCycles = [1];
2855 }
2856 def: InstRW<[SBWriteResGroup135], (instregex "VSQRTSSr")>;
2857
2858 } // SchedModel