contrib/llvm/lib/Target/X86/X86SchedSkylakeClient.td

   1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for Skylake Client to support
  11 // instruction scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 def SkylakeClientModel : SchedMachineModel {
  16   // All x86 instructions are modeled as a single micro-op, and SKylake can
  17   // decode 6 instructions per cycle.
  18   let IssueWidth = 6;
  19   let MicroOpBufferSize = 224; // Based on the reorder buffer.
  20   let LoadLatency = 5;
  21   let MispredictPenalty = 14;
  22
  23   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  24   let LoopMicroOpBufferSize = 50;
  25
  26   // This flag is set to allow the scheduler to assign a default model to
  27   // unrecognized opcodes.
  28   let CompleteModel = 0;
  29 }
  30
  31 let SchedModel = SkylakeClientModel in {
  32
  33 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
  34
  35 // Ports 0, 1, 5, and 6 handle all computation.
  36 // Port 4 gets the data half of stores. Store data can be available later than
  37 // the store address, but since we don't model the latency of stores, we can
  38 // ignore that.
  39 // Ports 2 and 3 are identical. They handle loads and the address half of
  40 // stores. Port 7 can handle address calculations.
  41 def SKLPort0 : ProcResource<1>;
  42 def SKLPort1 : ProcResource<1>;
  43 def SKLPort2 : ProcResource<1>;
  44 def SKLPort3 : ProcResource<1>;
  45 def SKLPort4 : ProcResource<1>;
  46 def SKLPort5 : ProcResource<1>;
  47 def SKLPort6 : ProcResource<1>;
  48 def SKLPort7 : ProcResource<1>;
  49
  50 // Many micro-ops are capable of issuing on multiple ports.
  51 def SKLPort01  : ProcResGroup<[SKLPort0, SKLPort1]>;
  52 def SKLPort23  : ProcResGroup<[SKLPort2, SKLPort3]>;
  53 def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
  54 def SKLPort04  : ProcResGroup<[SKLPort0, SKLPort4]>;
  55 def SKLPort05  : ProcResGroup<[SKLPort0, SKLPort5]>;
  56 def SKLPort06  : ProcResGroup<[SKLPort0, SKLPort6]>;
  57 def SKLPort15  : ProcResGroup<[SKLPort1, SKLPort5]>;
  58 def SKLPort16  : ProcResGroup<[SKLPort1, SKLPort6]>;
  59 def SKLPort56  : ProcResGroup<[SKLPort5, SKLPort6]>;
  60 def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
  61 def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
  62 def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
  63
  64 def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
  65 // FP division and sqrt on port 0.
  66 def SKLFPDivider : ProcResource<1>;
  67
  68 // 60 Entry Unified Scheduler
  69 def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
  70                               SKLPort5, SKLPort6, SKLPort7]> {
  71   let BufferSize=60;
  72 }
  73
  74 // Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  75 // cycles after the memory operand.
  76 def : ReadAdvance<ReadAfterLd, 5>;
  77
  78 // Many SchedWrites are defined in pairs with and without a folded load.
  79 // Instructions with folded loads are usually micro-fused, so they only appear
  80 // as two micro-ops when queued in the reservation station.
  81 // This multiclass defines the resource usage for variants with and without
  82 // folded loads.
  83 multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
  84                           list<ProcResourceKind> ExePorts,
  85                           int Lat, list<int> Res = [1], int UOps = 1,
  86                           int LoadLat = 5> {
  87   // Register variant is using a single cycle on ExePort.
  88   def : WriteRes<SchedRW, ExePorts> {
  89     let Latency = Lat;
  90     let ResourceCycles = Res;
  91     let NumMicroOps = UOps;
  92   }
  93
  94   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
  95   // the latency (default = 5).
  96   def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
  97     let Latency = !add(Lat, LoadLat);
  98     let ResourceCycles = !listconcat([1], Res);
  99     let NumMicroOps = !add(UOps, 1);
 100   }
 101 }
 102
 103 // A folded store needs a cycle on port 4 for the store data, and an extra port
 104 // 2/3/7 cycle to recompute the address.
 105 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
 106
 107 // Arithmetic.
 108 defm : SKLWriteResPair<WriteALU,    [SKLPort0156], 1>; // Simple integer ALU op.
 109 defm : SKLWriteResPair<WriteADC,    [SKLPort06],   1>; // Integer ALU + flags op.
 110 defm : SKLWriteResPair<WriteIMul,   [SKLPort1],    3>; // Integer multiplication.
 111 defm : SKLWriteResPair<WriteIMul64, [SKLPort1],    3>; // Integer 64-bit multiplication.
 112
 113 defm : X86WriteRes<WriteBSWAP32,    [SKLPort15], 1, [1], 1>;
 114 defm : X86WriteRes<WriteBSWAP64,    [SKLPort06, SKLPort15], 2, [1,1], 2>;
 115
 116 defm : SKLWriteResPair<WriteDiv8,   [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 117 defm : SKLWriteResPair<WriteDiv16,  [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 118 defm : SKLWriteResPair<WriteDiv32,  [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 119 defm : SKLWriteResPair<WriteDiv64,  [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 120 defm : SKLWriteResPair<WriteIDiv8,  [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 121 defm : SKLWriteResPair<WriteIDiv16, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 122 defm : SKLWriteResPair<WriteIDiv32, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 123 defm : SKLWriteResPair<WriteIDiv64, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 124
 125 defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
 126
 127 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 128 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
 129
 130 defm : SKLWriteResPair<WriteCMOV,  [SKLPort06], 1, [1], 1>; // Conditional move.
 131 defm : SKLWriteResPair<WriteCMOV2, [SKLPort06], 2, [2], 2>; // Conditional (CF + ZF flag) move.
 132 defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move.
 133 def  : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
 134 def  : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
 135   let Latency = 2;
 136   let NumMicroOps = 3;
 137 }
 138 def  : WriteRes<WriteLAHFSAHF, [SKLPort06]>;
 139 def  : WriteRes<WriteBitTest,[SKLPort06]>; //
 140
 141 // Bit counts.
 142 defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
 143 defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;
 144 defm : SKLWriteResPair<WriteLZCNT,          [SKLPort1], 3>;
 145 defm : SKLWriteResPair<WriteTZCNT,          [SKLPort1], 3>;
 146 defm : SKLWriteResPair<WritePOPCNT,         [SKLPort1], 3>;
 147
 148 // Integer shifts and rotates.
 149 defm : SKLWriteResPair<WriteShift, [SKLPort06],  1>;
 150
 151 // SHLD/SHRD.
 152 defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;
 153 defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>;
 154 defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>;
 155 defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>;
 156
 157 // BMI1 BEXTR, BMI2 BZHI
 158 defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;
 159 defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>;
 160
 161 // Loads, stores, and moves, not folded with other operations.
 162 defm : X86WriteRes<WriteLoad,    [SKLPort23], 5, [1], 1>;
 163 defm : X86WriteRes<WriteStore,   [SKLPort237, SKLPort4], 1, [1,1], 1>;
 164 defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;
 165 defm : X86WriteRes<WriteMove,    [SKLPort0156], 1, [1], 1>;
 166
 167 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 168 // These can often bypass execution ports completely.
 169 def : WriteRes<WriteZero,  []>;
 170
 171 // Branches don't produce values, so they have no latency, but they still
 172 // consume resources. Indirect branches can fold loads.
 173 defm : SKLWriteResPair<WriteJump,  [SKLPort06],   1>;
 174
 175 // Floating point. This covers both scalar and vector operations.
 176 defm : X86WriteRes<WriteFLD0,          [SKLPort05], 1, [1], 1>;
 177 defm : X86WriteRes<WriteFLD1,          [SKLPort05], 1, [2], 2>;
 178 defm : X86WriteRes<WriteFLDC,          [SKLPort05], 1, [2], 2>;
 179 defm : X86WriteRes<WriteFLoad,         [SKLPort23], 5, [1], 1>;
 180 defm : X86WriteRes<WriteFLoadX,        [SKLPort23], 6, [1], 1>;
 181 defm : X86WriteRes<WriteFLoadY,        [SKLPort23], 7, [1], 1>;
 182 defm : X86WriteRes<WriteFMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 183 defm : X86WriteRes<WriteFMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 184 defm : X86WriteRes<WriteFStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 185 defm : X86WriteRes<WriteFStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 186 defm : X86WriteRes<WriteFStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 187 defm : X86WriteRes<WriteFStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 188 defm : X86WriteRes<WriteFStoreNTX,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 189 defm : X86WriteRes<WriteFStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 190 defm : X86WriteRes<WriteFMaskedStore,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
 191 defm : X86WriteRes<WriteFMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>;
 192 defm : X86WriteRes<WriteFMove,         [SKLPort015], 1, [1], 1>;
 193 defm : X86WriteRes<WriteFMoveX,        [SKLPort015], 1, [1], 1>;
 194 defm : X86WriteRes<WriteFMoveY,        [SKLPort015], 1, [1], 1>;
 195 defm : X86WriteRes<WriteEMMS,          [SKLPort05,SKLPort0156], 10, [9,1], 10>;
 196
 197 defm : SKLWriteResPair<WriteFAdd,     [SKLPort01],  4, [1], 1, 5>; // Floating point add/sub.
 198 defm : SKLWriteResPair<WriteFAddX,    [SKLPort01],  4, [1], 1, 6>;
 199 defm : SKLWriteResPair<WriteFAddY,    [SKLPort01],  4, [1], 1, 7>;
 200 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 201 defm : SKLWriteResPair<WriteFAdd64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double add/sub.
 202 defm : SKLWriteResPair<WriteFAdd64X,  [SKLPort01],  4, [1], 1, 6>;
 203 defm : SKLWriteResPair<WriteFAdd64Y,  [SKLPort01],  4, [1], 1, 7>;
 204 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 205
 206 defm : SKLWriteResPair<WriteFCmp,     [SKLPort01],  4, [1], 1, 5>; // Floating point compare.
 207 defm : SKLWriteResPair<WriteFCmpX,    [SKLPort01],  4, [1], 1, 6>;
 208 defm : SKLWriteResPair<WriteFCmpY,    [SKLPort01],  4, [1], 1, 7>;
 209 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 210 defm : SKLWriteResPair<WriteFCmp64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double compare.
 211 defm : SKLWriteResPair<WriteFCmp64X,  [SKLPort01],  4, [1], 1, 6>;
 212 defm : SKLWriteResPair<WriteFCmp64Y,  [SKLPort01],  4, [1], 1, 7>;
 213 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 214
 215 defm : SKLWriteResPair<WriteFCom,      [SKLPort0],  2>; // Floating point compare to flags.
 216
 217 defm : SKLWriteResPair<WriteFMul,     [SKLPort01],  4, [1], 1, 5>; // Floating point multiplication.
 218 defm : SKLWriteResPair<WriteFMulX,    [SKLPort01],  4, [1], 1, 6>;
 219 defm : SKLWriteResPair<WriteFMulY,    [SKLPort01],  4, [1], 1, 7>;
 220 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 221 defm : SKLWriteResPair<WriteFMul64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double multiplication.
 222 defm : SKLWriteResPair<WriteFMul64X,  [SKLPort01],  4, [1], 1, 6>;
 223 defm : SKLWriteResPair<WriteFMul64Y,  [SKLPort01],  4, [1], 1, 7>;
 224 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 225
 226 defm : SKLWriteResPair<WriteFDiv,     [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 227 //defm : SKLWriteResPair<WriteFDivX,    [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>;
 228 defm : SKLWriteResPair<WriteFDivY,    [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>;
 229 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 230 //defm : SKLWriteResPair<WriteFDiv64,   [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division.
 231 //defm : SKLWriteResPair<WriteFDiv64X,  [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>;
 232 //defm : SKLWriteResPair<WriteFDiv64Y,  [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>;
 233 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 234
 235 defm : SKLWriteResPair<WriteFSqrt,    [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
 236 defm : SKLWriteResPair<WriteFSqrtX,   [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>;
 237 defm : SKLWriteResPair<WriteFSqrtY,   [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>;
 238 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 239 defm : SKLWriteResPair<WriteFSqrt64,  [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
 240 defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>;
 241 defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>;
 242 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 243 defm : SKLWriteResPair<WriteFSqrt80,  [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root.
 244
 245 defm : SKLWriteResPair<WriteFRcp,   [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
 246 defm : SKLWriteResPair<WriteFRcpX,  [SKLPort0], 4, [1], 1, 6>;
 247 defm : SKLWriteResPair<WriteFRcpY,  [SKLPort0], 4, [1], 1, 7>;
 248 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 249
 250 defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
 251 defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>;
 252 defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>;
 253 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 254
 255 defm : SKLWriteResPair<WriteFMA,    [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add.
 256 defm : SKLWriteResPair<WriteFMAX,   [SKLPort01], 4, [1], 1, 6>;
 257 defm : SKLWriteResPair<WriteFMAY,   [SKLPort01], 4, [1], 1, 7>;
 258 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 259 defm : SKLWriteResPair<WriteDPPD,   [SKLPort5,SKLPort01],  9, [1,2], 3, 6>; // Floating point double dot product.
 260 defm : SKLWriteResPair<WriteDPPS,   [SKLPort5,SKLPort01], 13, [1,3], 4, 6>;
 261 defm : SKLWriteResPair<WriteDPPSY,  [SKLPort5,SKLPort01], 13, [1,3], 4, 7>;
 262 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
 263 defm : SKLWriteResPair<WriteFSign,   [SKLPort0], 1>; // Floating point fabs/fchs.
 264 defm : SKLWriteResPair<WriteFRnd,     [SKLPort01], 8, [2], 2, 6>; // Floating point rounding.
 265 defm : SKLWriteResPair<WriteFRndY,    [SKLPort01], 8, [2], 2, 7>;
 266 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 267 defm : SKLWriteResPair<WriteFLogic,  [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
 268 defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>;
 269 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 270 defm : SKLWriteResPair<WriteFTest,   [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
 271 defm : SKLWriteResPair<WriteFTestY,  [SKLPort0], 2, [1], 1, 7>;
 272 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 273 defm : SKLWriteResPair<WriteFShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 274 defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>;
 275 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 276 defm : SKLWriteResPair<WriteFVarShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 277 defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 278 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 279 defm : SKLWriteResPair<WriteFBlend,  [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends.
 280 defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>;
 281 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 282 defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends.
 283 defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>;
 284 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 285
 286 // FMA Scheduling helper class.
 287 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 288
 289 // Vector integer operations.
 290 defm : X86WriteRes<WriteVecLoad,         [SKLPort23], 5, [1], 1>;
 291 defm : X86WriteRes<WriteVecLoadX,        [SKLPort23], 6, [1], 1>;
 292 defm : X86WriteRes<WriteVecLoadY,        [SKLPort23], 7, [1], 1>;
 293 defm : X86WriteRes<WriteVecLoadNT,       [SKLPort23], 6, [1], 1>;
 294 defm : X86WriteRes<WriteVecLoadNTY,      [SKLPort23], 7, [1], 1>;
 295 defm : X86WriteRes<WriteVecMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 296 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 297 defm : X86WriteRes<WriteVecStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 298 defm : X86WriteRes<WriteVecStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 299 defm : X86WriteRes<WriteVecStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 300 defm : X86WriteRes<WriteVecStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 301 defm : X86WriteRes<WriteVecStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 302 defm : X86WriteRes<WriteVecMaskedStore,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
 303 defm : X86WriteRes<WriteVecMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>;
 304 defm : X86WriteRes<WriteVecMove,         [SKLPort05],  1, [1], 1>;
 305 defm : X86WriteRes<WriteVecMoveX,        [SKLPort015], 1, [1], 1>;
 306 defm : X86WriteRes<WriteVecMoveY,        [SKLPort015], 1, [1], 1>;
 307 defm : X86WriteRes<WriteVecMoveToGpr,    [SKLPort0], 2, [1], 1>;
 308 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKLPort5], 1, [1], 1>;
 309
 310 defm : SKLWriteResPair<WriteVecALU,   [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 311 defm : SKLWriteResPair<WriteVecALUX,  [SKLPort01], 1, [1], 1, 6>;
 312 defm : SKLWriteResPair<WriteVecALUY,  [SKLPort01], 1, [1], 1, 7>;
 313 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 314 defm : SKLWriteResPair<WriteVecLogic, [SKLPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
 315 defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>;
 316 defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>;
 317 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 318 defm : SKLWriteResPair<WriteVecTest,  [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
 319 defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>;
 320 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 321 defm : SKLWriteResPair<WriteVecIMul,  [SKLPort0] ,  4, [1], 1, 5>; // Vector integer multiply.
 322 defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01],  4, [1], 1, 6>;
 323 defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01],  4, [1], 1, 7>;
 324 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 325 defm : SKLWriteResPair<WritePMULLD,   [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD.
 326 defm : SKLWriteResPair<WritePMULLDY,  [SKLPort01], 10, [2], 2, 7>;
 327 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 328 defm : SKLWriteResPair<WriteShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 329 defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;
 330 defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;
 331 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 332 defm : SKLWriteResPair<WriteVarShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 333 defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;
 334 defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 335 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 336 defm : SKLWriteResPair<WriteBlend,  [SKLPort5], 1, [1], 1, 6>; // Vector blends.
 337 defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>;
 338 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 339 defm : SKLWriteResPair<WriteVarBlend,  [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
 340 defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>;
 341 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 342 defm : SKLWriteResPair<WriteMPSAD,  [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
 343 defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>;
 344 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 345 defm : SKLWriteResPair<WritePSADBW,  [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW.
 346 defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;
 347 defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;
 348 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 349 defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
 350
 351 // Vector integer shifts.
 352 defm : SKLWriteResPair<WriteVecShift,     [SKLPort0], 1, [1], 1, 5>;
 353 defm : X86WriteRes<WriteVecShiftX,        [SKLPort5,SKLPort01],  2, [1,1], 2>;
 354 defm : X86WriteRes<WriteVecShiftY,        [SKLPort5,SKLPort01],  4, [1,1], 2>;
 355 defm : X86WriteRes<WriteVecShiftXLd,      [SKLPort01,SKLPort23], 7, [1,1], 2>;
 356 defm : X86WriteRes<WriteVecShiftYLd,      [SKLPort01,SKLPort23], 8, [1,1], 2>;
 357 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 358
 359 defm : SKLWriteResPair<WriteVecShiftImm,  [SKLPort0],  1, [1], 1, 5>; // Vector integer immediate shifts.
 360 defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>;
 361 defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>;
 362 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 363 defm : SKLWriteResPair<WriteVarVecShift,  [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.
 364 defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;
 365 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 366
 367 // Vector insert/extract operations.
 368 def : WriteRes<WriteVecInsert, [SKLPort5]> {
 369   let Latency = 2;
 370   let NumMicroOps = 2;
 371   let ResourceCycles = [2];
 372 }
 373 def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
 374   let Latency = 6;
 375   let NumMicroOps = 2;
 376 }
 377 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 378
 379 def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {
 380   let Latency = 3;
 381   let NumMicroOps = 2;
 382 }
 383 def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> {
 384   let Latency = 2;
 385   let NumMicroOps = 3;
 386 }
 387
 388 // Conversion between integer and float.
 389 defm : SKLWriteResPair<WriteCvtSS2I,   [SKLPort1], 3>;
 390 defm : SKLWriteResPair<WriteCvtPS2I,   [SKLPort1], 3>;
 391 defm : SKLWriteResPair<WriteCvtPS2IY,  [SKLPort1], 3>;
 392 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 393 defm : SKLWriteResPair<WriteCvtSD2I,   [SKLPort1], 3>;
 394 defm : SKLWriteResPair<WriteCvtPD2I,   [SKLPort1], 3>;
 395 defm : SKLWriteResPair<WriteCvtPD2IY,  [SKLPort1], 3>;
 396 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 397
 398 defm : SKLWriteResPair<WriteCvtI2SS,   [SKLPort1], 4>;
 399 defm : SKLWriteResPair<WriteCvtI2PS,   [SKLPort1], 4>;
 400 defm : SKLWriteResPair<WriteCvtI2PSY,  [SKLPort1], 4>;
 401 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 402 defm : SKLWriteResPair<WriteCvtI2SD,   [SKLPort1], 4>;
 403 defm : SKLWriteResPair<WriteCvtI2PD,   [SKLPort1], 4>;
 404 defm : SKLWriteResPair<WriteCvtI2PDY,  [SKLPort1], 4>;
 405 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 406
 407 defm : SKLWriteResPair<WriteCvtSS2SD,  [SKLPort1], 3>;
 408 defm : SKLWriteResPair<WriteCvtPS2PD,  [SKLPort1], 3>;
 409 defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>;
 410 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 411 defm : SKLWriteResPair<WriteCvtSD2SS,  [SKLPort1], 3>;
 412 defm : SKLWriteResPair<WriteCvtPD2PS,  [SKLPort1], 3>;
 413 defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>;
 414 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 415
 416 defm : X86WriteRes<WriteCvtPH2PS,    [SKLPort5,SKLPort015],  5, [1,1], 2>;
 417 defm : X86WriteRes<WriteCvtPH2PSY,    [SKLPort5,SKLPort01],  7, [1,1], 2>;
 418 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 419 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKLPort23,SKLPort01],  9, [1,1], 2>;
 420 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
 421 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 422
 423 defm : X86WriteRes<WriteCvtPS2PH,                       [SKLPort5,SKLPort015], 5, [1,1], 2>;
 424 defm : X86WriteRes<WriteCvtPS2PHY,                       [SKLPort5,SKLPort01], 7, [1,1], 2>;
 425 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 426 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>;
 427 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>;
 428 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 429
 430 // Strings instructions.
 431
 432 // Packed Compare Implicit Length Strings, Return Mask
 433 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
 434   let Latency = 10;
 435   let NumMicroOps = 3;
 436   let ResourceCycles = [3];
 437 }
 438 def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
 439   let Latency = 16;
 440   let NumMicroOps = 4;
 441   let ResourceCycles = [3,1];
 442 }
 443
 444 // Packed Compare Explicit Length Strings, Return Mask
 445 def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
 446   let Latency = 19;
 447   let NumMicroOps = 9;
 448   let ResourceCycles = [4,3,1,1];
 449 }
 450 def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
 451   let Latency = 25;
 452   let NumMicroOps = 10;
 453   let ResourceCycles = [4,3,1,1,1];
 454 }
 455
 456 // Packed Compare Implicit Length Strings, Return Index
 457 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
 458   let Latency = 10;
 459   let NumMicroOps = 3;
 460   let ResourceCycles = [3];
 461 }
 462 def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
 463   let Latency = 16;
 464   let NumMicroOps = 4;
 465   let ResourceCycles = [3,1];
 466 }
 467
 468 // Packed Compare Explicit Length Strings, Return Index
 469 def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
 470   let Latency = 18;
 471   let NumMicroOps = 8;
 472   let ResourceCycles = [4,3,1];
 473 }
 474 def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
 475   let Latency = 24;
 476   let NumMicroOps = 9;
 477   let ResourceCycles = [4,3,1,1];
 478 }
 479
 480 // MOVMSK Instructions.
 481 def : WriteRes<WriteFMOVMSK,    [SKLPort0]> { let Latency = 2; }
 482 def : WriteRes<WriteVecMOVMSK,  [SKLPort0]> { let Latency = 2; }
 483 def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }
 484 def : WriteRes<WriteMMXMOVMSK,  [SKLPort0]> { let Latency = 2; }
 485
 486 // AES instructions.
 487 def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
 488   let Latency = 4;
 489   let NumMicroOps = 1;
 490   let ResourceCycles = [1];
 491 }
 492 def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
 493   let Latency = 10;
 494   let NumMicroOps = 2;
 495   let ResourceCycles = [1,1];
 496 }
 497
 498 def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
 499   let Latency = 8;
 500   let NumMicroOps = 2;
 501   let ResourceCycles = [2];
 502 }
 503 def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
 504   let Latency = 14;
 505   let NumMicroOps = 3;
 506   let ResourceCycles = [2,1];
 507 }
 508
 509 def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
 510   let Latency = 20;
 511   let NumMicroOps = 11;
 512   let ResourceCycles = [3,6,2];
 513 }
 514 def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
 515   let Latency = 25;
 516   let NumMicroOps = 11;
 517   let ResourceCycles = [3,6,1,1];
 518 }
 519
 520 // Carry-less multiplication instructions.
 521 def : WriteRes<WriteCLMul, [SKLPort5]> {
 522   let Latency = 6;
 523   let NumMicroOps = 1;
 524   let ResourceCycles = [1];
 525 }
 526 def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
 527   let Latency = 12;
 528   let NumMicroOps = 2;
 529   let ResourceCycles = [1,1];
 530 }
 531
 532 // Catch-all for expensive system instructions.
 533 def : WriteRes<WriteSystem,     [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 534
 535 // AVX2.
 536 defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 537 defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 538 defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 539 defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 540
 541 // Old microcoded instructions that nobody use.
 542 def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 543
 544 // Fence instructions.
 545 def : WriteRes<WriteFence,  [SKLPort23, SKLPort4]>;
 546
 547 // Load/store MXCSR.
 548 def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 549 def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 550
 551 // Nop, not very useful expect it provides a model for nops!
 552 def : WriteRes<WriteNop, []>;
 553
 554 ////////////////////////////////////////////////////////////////////////////////
 555 // Horizontal add/sub  instructions.
 556 ////////////////////////////////////////////////////////////////////////////////
 557
 558 defm : SKLWriteResPair<WriteFHAdd,  [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
 559 defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;
 560 defm : SKLWriteResPair<WritePHAdd,  [SKLPort5,SKLPort05],  3, [2,1], 3, 5>;
 561 defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;
 562 defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
 563
 564 // Remaining instrs.
 565
 566 def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
 567   let Latency = 1;
 568   let NumMicroOps = 1;
 569   let ResourceCycles = [1];
 570 }
 571 def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr",
 572                                             "MMX_PADDUS(B|W)irr",
 573                                             "MMX_PAVG(B|W)irr",
 574                                             "MMX_PCMPEQ(B|D|W)irr",
 575                                             "MMX_PCMPGT(B|D|W)irr",
 576                                             "MMX_P(MAX|MIN)SWirr",
 577                                             "MMX_P(MAX|MIN)UBirr",
 578                                             "MMX_PSUBS(B|W)irr",
 579                                             "MMX_PSUBUS(B|W)irr")>;
 580
 581 def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
 582   let Latency = 1;
 583   let NumMicroOps = 1;
 584   let ResourceCycles = [1];
 585 }
 586 def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
 587                                             "UCOM_F(P?)r")>;
 588
 589 def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
 590   let Latency = 1;
 591   let NumMicroOps = 1;
 592   let ResourceCycles = [1];
 593 }
 594 def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 595
 596 def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
 597   let Latency = 1;
 598   let NumMicroOps = 1;
 599   let ResourceCycles = [1];
 600 }
 601 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
 602
 603 def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
 604   let Latency = 1;
 605   let NumMicroOps = 1;
 606   let ResourceCycles = [1];
 607 }
 608 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 609
 610 def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
 611   let Latency = 1;
 612   let NumMicroOps = 1;
 613   let ResourceCycles = [1];
 614 }
 615 def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr",
 616                                             "BLSI(32|64)rr",
 617                                             "BLSMSK(32|64)rr",
 618                                             "BLSR(32|64)rr")>;
 619
 620 def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
 621   let Latency = 1;
 622   let NumMicroOps = 1;
 623   let ResourceCycles = [1];
 624 }
 625 def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
 626                                             "VPBLENDD(Y?)rri",
 627                                             "(V?)PSUB(B|D|Q|W)(Y?)rr")>;
 628
 629 def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
 630   let Latency = 1;
 631   let NumMicroOps = 1;
 632   let ResourceCycles = [1];
 633 }
 634 def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
 635                                           CMC, STC)>;
 636 def: InstRW<[SKLWriteResGroup10], (instregex "SGDT64m",
 637                                              "SIDT64m",
 638                                              "SMSW16m",
 639                                              "STRm",
 640                                              "SYSCALL")>;
 641
 642 def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
 643   let Latency = 1;
 644   let NumMicroOps = 2;
 645   let ResourceCycles = [1,1];
 646 }
 647 def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",
 648                                              "ST_FP(32|64|80)m",
 649                                              "VMPTRSTm")>;
 650
 651 def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
 652   let Latency = 2;
 653   let NumMicroOps = 2;
 654   let ResourceCycles = [2];
 655 }
 656 def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>;
 657
 658 def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
 659   let Latency = 2;
 660   let NumMicroOps = 2;
 661   let ResourceCycles = [2];
 662 }
 663 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP)>;
 664 def: InstRW<[SKLWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>;
 665
 666 def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {
 667   let Latency = 2;
 668   let NumMicroOps = 2;
 669   let ResourceCycles = [2];
 670 }
 671 def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)r1",
 672                                              "ROL(8|16|32|64)ri",
 673                                              "ROR(8|16|32|64)r1",
 674                                              "ROR(8|16|32|64)ri",
 675                                              "SET(A|BE)r")>;
 676
 677 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
 678   let Latency = 2;
 679   let NumMicroOps = 2;
 680   let ResourceCycles = [2];
 681 }
 682 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
 683                                           WAIT,
 684                                           XGETBV)>;
 685
 686 def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 687   let Latency = 2;
 688   let NumMicroOps = 2;
 689   let ResourceCycles = [1,1];
 690 }
 691 def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
 692
 693 def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
 694   let Latency = 2;
 695   let NumMicroOps = 2;
 696   let ResourceCycles = [1,1];
 697 }
 698 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
 699
 700 def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 701   let Latency = 2;
 702   let NumMicroOps = 2;
 703   let ResourceCycles = [1,1];
 704 }
 705 def: InstRW<[SKLWriteResGroup23], (instrs CWD)>;
 706 def: InstRW<[SKLWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>;
 707 def: InstRW<[SKLWriteResGroup23], (instregex "ADC8i8",
 708                                              "ADC8ri",
 709                                              "SBB8i8",
 710                                              "SBB8ri")>;
 711
 712 def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
 713   let Latency = 2;
 714   let NumMicroOps = 3;
 715   let ResourceCycles = [1,1,1];
 716 }
 717 def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
 718
 719 def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
 720   let Latency = 2;
 721   let NumMicroOps = 3;
 722   let ResourceCycles = [1,1,1];
 723 }
 724 def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 725
 726 def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 727   let Latency = 2;
 728   let NumMicroOps = 3;
 729   let ResourceCycles = [1,1,1];
 730 }
 731 def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r,
 732                                           STOSB, STOSL, STOSQ, STOSW)>;
 733 def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr",
 734                                              "PUSH64i8")>;
 735
 736 def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
 737   let Latency = 3;
 738   let NumMicroOps = 1;
 739   let ResourceCycles = [1];
 740 }
 741 def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
 742                                              "PEXT(32|64)rr")>;
 743
 744 def SKLWriteResGroup29_16i : SchedWriteRes<[SKLPort1, SKLPort0156]> {
 745   let Latency = 4;
 746   let NumMicroOps = 2;
 747   let ResourceCycles = [1,1];
 748 }
 749 def: InstRW<[SKLWriteResGroup29_16i], (instrs IMUL16rri, IMUL16rri8)>;
 750
 751 def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
 752   let Latency = 3;
 753   let NumMicroOps = 1;
 754   let ResourceCycles = [1];
 755 }
 756 def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
 757                                              "VPBROADCASTBrr",
 758                                              "VPBROADCASTWrr",
 759                                              "(V?)PCMPGTQ(Y?)rr")>;
 760
 761 def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
 762   let Latency = 3;
 763   let NumMicroOps = 2;
 764   let ResourceCycles = [1,1];
 765 }
 766 def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
 767
 768 def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> {
 769   let Latency = 3;
 770   let NumMicroOps = 3;
 771   let ResourceCycles = [3];
 772 }
 773 def: InstRW<[SKLWriteResGroup33], (instregex "ROL(8|16|32|64)rCL",
 774                                              "ROR(8|16|32|64)rCL",
 775                                              "SAR(8|16|32|64)rCL",
 776                                              "SHL(8|16|32|64)rCL",
 777                                              "SHR(8|16|32|64)rCL")>;
 778
 779 def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> {
 780   let Latency = 2;
 781   let NumMicroOps = 3;
 782   let ResourceCycles = [3];
 783 }
 784 def: InstRW<[SKLWriteResGroup34], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr,
 785                                           XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr,
 786                                           XCHG16ar, XCHG32ar, XCHG64ar)>;
 787
 788 def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
 789   let Latency = 3;
 790   let NumMicroOps = 3;
 791   let ResourceCycles = [1,2];
 792 }
 793 def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 794
 795 def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
 796   let Latency = 3;
 797   let NumMicroOps = 3;
 798   let ResourceCycles = [2,1];
 799 }
 800 def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
 801                                              "(V?)PHSUBSW(Y?)rr")>;
 802
 803 def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
 804   let Latency = 3;
 805   let NumMicroOps = 3;
 806   let ResourceCycles = [2,1];
 807 }
 808 def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSDWirr",
 809                                              "MMX_PACKSSWBirr",
 810                                              "MMX_PACKUSWBirr")>;
 811
 812 def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 813   let Latency = 3;
 814   let NumMicroOps = 3;
 815   let ResourceCycles = [1,2];
 816 }
 817 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
 818
 819 def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
 820   let Latency = 3;
 821   let NumMicroOps = 3;
 822   let ResourceCycles = [1,2];
 823 }
 824 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
 825
 826 def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 827   let Latency = 3;
 828   let NumMicroOps = 3;
 829   let ResourceCycles = [1,2];
 830 }
 831 def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r1",
 832                                              "RCL(8|16|32|64)ri",
 833                                              "RCR(8|16|32|64)r1",
 834                                              "RCR(8|16|32|64)ri")>;
 835
 836 def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
 837   let Latency = 3;
 838   let NumMicroOps = 3;
 839   let ResourceCycles = [1,1,1];
 840 }
 841 def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
 842
 843 def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
 844   let Latency = 3;
 845   let NumMicroOps = 4;
 846   let ResourceCycles = [1,1,2];
 847 }
 848 def: InstRW<[SKLWriteResGroup44], (instregex "SET(A|BE)m")>;
 849
 850 def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
 851   let Latency = 3;
 852   let NumMicroOps = 4;
 853   let ResourceCycles = [1,1,1,1];
 854 }
 855 def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
 856
 857 def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
 858   let Latency = 3;
 859   let NumMicroOps = 4;
 860   let ResourceCycles = [1,1,1,1];
 861 }
 862 def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
 863
 864 def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
 865   let Latency = 4;
 866   let NumMicroOps = 1;
 867   let ResourceCycles = [1];
 868 }
 869 def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 870
 871 def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
 872   let Latency = 4;
 873   let NumMicroOps = 1;
 874   let ResourceCycles = [1];
 875 }
 876 def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr",
 877                                              "(V?)CVT(T?)PS2DQ(Y?)rr")>;
 878
 879 def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> {
 880   let Latency = 4;
 881   let NumMicroOps = 2;
 882   let ResourceCycles = [1,1];
 883 }
 884 def: InstRW<[SKLWriteResGroup51], (instrs IMUL64r, MUL64r, MULX64rr)>;
 885
 886 def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
 887   let Latency = 4;
 888   let NumMicroOps = 4;
 889   let ResourceCycles = [1,1,2];
 890 }
 891 def: InstRW<[SKLWriteResGroup51_16], (instrs IMUL16r, MUL16r)>;
 892
 893 def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
 894   let Latency = 4;
 895   let NumMicroOps = 3;
 896   let ResourceCycles = [1,1,1];
 897 }
 898 def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
 899                                              "IST_F(16|32)m")>;
 900
 901 def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
 902   let Latency = 4;
 903   let NumMicroOps = 4;
 904   let ResourceCycles = [4];
 905 }
 906 def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
 907
 908 def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 909   let Latency = 4;
 910   let NumMicroOps = 4;
 911   let ResourceCycles = [1,3];
 912 }
 913 def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
 914
 915 def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> {
 916   let Latency = 4;
 917   let NumMicroOps = 4;
 918   let ResourceCycles = [1,3];
 919 }
 920 def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
 921
 922 def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
 923   let Latency = 4;
 924   let NumMicroOps = 4;
 925   let ResourceCycles = [1,1,2];
 926 }
 927 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
 928
 929 def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
 930   let Latency = 5;
 931   let NumMicroOps = 1;
 932   let ResourceCycles = [1];
 933 }
 934 def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm16",
 935                                              "MOVSX(16|32|64)rm32",
 936                                              "MOVSX(16|32|64)rm8",
 937                                              "MOVZX(16|32|64)rm16",
 938                                              "MOVZX(16|32|64)rm8",
 939                                              "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67?
 940
 941 def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
 942   let Latency = 5;
 943   let NumMicroOps = 2;
 944   let ResourceCycles = [1,1];
 945 }
 946 def: InstRW<[SKLWriteResGroup59], (instregex "MMX_CVTPI2PDirr",
 947                                              "(V?)CVTDQ2PDrr")>;
 948
 949 def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
 950   let Latency = 5;
 951   let NumMicroOps = 2;
 952   let ResourceCycles = [1,1];
 953 }
 954 def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr",
 955                                              "MMX_CVT(T?)PS2PIirr",
 956                                              "(V?)CVT(T?)PD2DQrr",
 957                                              "(V?)CVTPD2PSrr",
 958                                              "(V?)CVTPS2PDrr",
 959                                              "(V?)CVTSD2SSrr",
 960                                              "(V?)CVTSI642SDrr",
 961                                              "(V?)CVTSI2SDrr",
 962                                              "(V?)CVTSI2SSrr",
 963                                              "(V?)CVTSS2SDrr")>;
 964
 965 def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
 966   let Latency = 5;
 967   let NumMicroOps = 3;
 968   let ResourceCycles = [1,1,1];
 969 }
 970 def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
 971
 972 def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
 973   let Latency = 4;
 974   let NumMicroOps = 3;
 975   let ResourceCycles = [1,1,1];
 976 }
 977 def: InstRW<[SKLWriteResGroup62], (instrs IMUL32r, MUL32r, MULX32rr)>;
 978
 979 def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 980   let Latency = 5;
 981   let NumMicroOps = 5;
 982   let ResourceCycles = [1,4];
 983 }
 984 def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
 985
 986 def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 987   let Latency = 5;
 988   let NumMicroOps = 5;
 989   let ResourceCycles = [2,3];
 990 }
 991 def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>;
 992
 993 def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 994   let Latency = 5;
 995   let NumMicroOps = 6;
 996   let ResourceCycles = [1,1,4];
 997 }
 998 def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
 999
1000 def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
1001   let Latency = 6;
1002   let NumMicroOps = 1;
1003   let ResourceCycles = [1];
1004 }
1005 def: InstRW<[SKLWriteResGroup67], (instregex "VBROADCASTSSrm",
1006                                              "(V?)MOVSHDUPrm",
1007                                              "(V?)MOVSLDUPrm",
1008                                              "VPBROADCASTDrm",
1009                                              "VPBROADCASTQrm")>;
1010
1011 def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
1012   let Latency = 6;
1013   let NumMicroOps = 2;
1014   let ResourceCycles = [2];
1015 }
1016 def: InstRW<[SKLWriteResGroup68], (instregex "MMX_CVTPI2PSirr")>;
1017
1018 def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1019   let Latency = 6;
1020   let NumMicroOps = 2;
1021   let ResourceCycles = [1,1];
1022 }
1023 def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm",
1024                                              "MMX_PADDSWirm",
1025                                              "MMX_PADDUSBirm",
1026                                              "MMX_PADDUSWirm",
1027                                              "MMX_PAVGBirm",
1028                                              "MMX_PAVGWirm",
1029                                              "MMX_PCMPEQBirm",
1030                                              "MMX_PCMPEQDirm",
1031                                              "MMX_PCMPEQWirm",
1032                                              "MMX_PCMPGTBirm",
1033                                              "MMX_PCMPGTDirm",
1034                                              "MMX_PCMPGTWirm",
1035                                              "MMX_PMAXSWirm",
1036                                              "MMX_PMAXUBirm",
1037                                              "MMX_PMINSWirm",
1038                                              "MMX_PMINUBirm",
1039                                              "MMX_PSUBSBirm",
1040                                              "MMX_PSUBSWirm",
1041                                              "MMX_PSUBUSBirm",
1042                                              "MMX_PSUBUSWirm")>;
1043
1044 def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> {
1045   let Latency = 6;
1046   let NumMicroOps = 2;
1047   let ResourceCycles = [1,1];
1048 }
1049 def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr",
1050                                              "(V?)CVT(T?)SD2SI(64)?rr")>;
1051
1052 def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
1053   let Latency = 6;
1054   let NumMicroOps = 2;
1055   let ResourceCycles = [1,1];
1056 }
1057 def: InstRW<[SKLWriteResGroup72], (instregex "FARJMP64",
1058                                              "JMP(16|32|64)m")>;
1059
1060 def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
1061   let Latency = 6;
1062   let NumMicroOps = 2;
1063   let ResourceCycles = [1,1];
1064 }
1065 def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
1066
1067 def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
1068   let Latency = 6;
1069   let NumMicroOps = 2;
1070   let ResourceCycles = [1,1];
1071 }
1072 def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1073                                              "BLSI(32|64)rm",
1074                                              "BLSMSK(32|64)rm",
1075                                              "BLSR(32|64)rm",
1076                                              "MOVBE(16|32|64)rm")>;
1077
1078 def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1079   let Latency = 6;
1080   let NumMicroOps = 2;
1081   let ResourceCycles = [1,1];
1082 }
1083 def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
1084 def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
1085
1086 def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1087   let Latency = 6;
1088   let NumMicroOps = 3;
1089   let ResourceCycles = [2,1];
1090 }
1091 def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
1092
1093 def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
1094   let Latency = 6;
1095   let NumMicroOps = 4;
1096   let ResourceCycles = [1,1,1,1];
1097 }
1098 def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
1099
1100 def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1101   let Latency = 6;
1102   let NumMicroOps = 4;
1103   let ResourceCycles = [1,1,1,1];
1104 }
1105 def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8",
1106                                              "BTR(16|32|64)mi8",
1107                                              "BTS(16|32|64)mi8",
1108                                              "SAR(8|16|32|64)m1",
1109                                              "SAR(8|16|32|64)mi",
1110                                              "SHL(8|16|32|64)m1",
1111                                              "SHL(8|16|32|64)mi",
1112                                              "SHR(8|16|32|64)m1",
1113                                              "SHR(8|16|32|64)mi")>;
1114
1115 def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1116   let Latency = 6;
1117   let NumMicroOps = 4;
1118   let ResourceCycles = [1,1,1,1];
1119 }
1120 def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
1121                                              "PUSH(16|32|64)rmm")>;
1122
1123 def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1124   let Latency = 6;
1125   let NumMicroOps = 6;
1126   let ResourceCycles = [1,5];
1127 }
1128 def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
1129
1130 def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
1131   let Latency = 7;
1132   let NumMicroOps = 1;
1133   let ResourceCycles = [1];
1134 }
1135 def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m",
1136                                              "VBROADCASTF128",
1137                                              "VBROADCASTI128",
1138                                              "VBROADCASTSDYrm",
1139                                              "VBROADCASTSSYrm",
1140                                              "VMOVDDUPYrm",
1141                                              "VMOVSHDUPYrm",
1142                                              "VMOVSLDUPYrm",
1143                                              "VPBROADCASTDYrm",
1144                                              "VPBROADCASTQYrm")>;
1145
1146 def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1147   let Latency = 7;
1148   let NumMicroOps = 2;
1149   let ResourceCycles = [1,1];
1150 }
1151 def: InstRW<[SKLWriteResGroup86], (instregex "VCVTDQ2PDYrr")>;
1152
1153 def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1154   let Latency = 6;
1155   let NumMicroOps = 2;
1156   let ResourceCycles = [1,1];
1157 }
1158 def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
1159                                              "(V?)PMOV(SX|ZX)BQrm",
1160                                              "(V?)PMOV(SX|ZX)BWrm",
1161                                              "(V?)PMOV(SX|ZX)DQrm",
1162                                              "(V?)PMOV(SX|ZX)WDrm",
1163                                              "(V?)PMOV(SX|ZX)WQrm")>;
1164
1165 def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1166   let Latency = 7;
1167   let NumMicroOps = 2;
1168   let ResourceCycles = [1,1];
1169 }
1170 def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2PSYrr",
1171                                              "VCVTPS2PDYrr",
1172                                              "VCVT(T?)PD2DQYrr")>;
1173
1174 def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1175   let Latency = 7;
1176   let NumMicroOps = 2;
1177   let ResourceCycles = [1,1];
1178 }
1179 def: InstRW<[SKLWriteResGroup91], (instregex "(V?)INSERTF128rm",
1180                                              "(V?)INSERTI128rm",
1181                                              "(V?)PADD(B|D|Q|W)rm",
1182                                              "(V?)PBLENDDrmi",
1183                                              "(V?)PSUB(B|D|Q|W)rm")>;
1184
1185 def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1186   let Latency = 7;
1187   let NumMicroOps = 3;
1188   let ResourceCycles = [2,1];
1189 }
1190 def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm",
1191                                              "MMX_PACKSSWBirm",
1192                                              "MMX_PACKUSWBirm")>;
1193
1194 def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1195   let Latency = 7;
1196   let NumMicroOps = 3;
1197   let ResourceCycles = [1,2];
1198 }
1199 def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
1200                                           SCASB, SCASL, SCASQ, SCASW)>;
1201
1202 def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
1203   let Latency = 7;
1204   let NumMicroOps = 3;
1205   let ResourceCycles = [1,1,1];
1206 }
1207 def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>;
1208
1209 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
1210   let Latency = 7;
1211   let NumMicroOps = 3;
1212   let ResourceCycles = [1,1,1];
1213 }
1214 def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
1215
1216 def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
1217   let Latency = 7;
1218   let NumMicroOps = 3;
1219   let ResourceCycles = [1,1,1];
1220 }
1221 def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>;
1222
1223 def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1224   let Latency = 7;
1225   let NumMicroOps = 5;
1226   let ResourceCycles = [1,1,1,2];
1227 }
1228 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m1",
1229                                               "ROL(8|16|32|64)mi",
1230                                               "ROR(8|16|32|64)m1",
1231                                               "ROR(8|16|32|64)mi")>;
1232
1233 def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1234   let Latency = 7;
1235   let NumMicroOps = 5;
1236   let ResourceCycles = [1,1,1,2];
1237 }
1238 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
1239
1240 def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1241   let Latency = 7;
1242   let NumMicroOps = 5;
1243   let ResourceCycles = [1,1,1,1,1];
1244 }
1245 def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m",
1246                                               "FARCALL64")>;
1247
1248 def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
1249   let Latency = 7;
1250   let NumMicroOps = 7;
1251   let ResourceCycles = [1,3,1,2];
1252 }
1253 def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
1254
1255 def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
1256   let Latency = 8;
1257   let NumMicroOps = 2;
1258   let ResourceCycles = [1,1];
1259 }
1260 def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
1261                                               "PEXT(32|64)rm")>;
1262
1263 def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
1264   let Latency = 8;
1265   let NumMicroOps = 3;
1266   let ResourceCycles = [1,1,1];
1267 }
1268 def: InstRW<[SKLWriteResGroup107_16], (instrs IMUL16rmi, IMUL16rmi8)>;
1269
1270 def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort06, SKLPort0156, SKLPort23]> {
1271   let Latency = 9;
1272   let NumMicroOps = 5;
1273   let ResourceCycles = [1,1,2,1];
1274 }
1275 def: InstRW<[SKLWriteResGroup107_16_2], (instrs IMUL16m, MUL16m)>;
1276
1277 def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1278   let Latency = 8;
1279   let NumMicroOps = 2;
1280   let ResourceCycles = [1,1];
1281 }
1282 def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m",
1283                                               "VPBROADCASTBYrm",
1284                                               "VPBROADCASTWYrm",
1285                                               "VPMOVSXBDYrm",
1286                                               "VPMOVSXBQYrm",
1287                                               "VPMOVSXWQYrm")>;
1288
1289 def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1290   let Latency = 8;
1291   let NumMicroOps = 2;
1292   let ResourceCycles = [1,1];
1293 }
1294 def: InstRW<[SKLWriteResGroup110], (instregex "VPADD(B|D|Q|W)Yrm",
1295                                               "VPBLENDDYrmi",
1296                                               "VPSUB(B|D|Q|W)Yrm")>;
1297
1298 def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1299   let Latency = 8;
1300   let NumMicroOps = 4;
1301   let ResourceCycles = [1,2,1];
1302 }
1303 def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1304
1305 def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> {
1306   let Latency = 8;
1307   let NumMicroOps = 5;
1308   let ResourceCycles = [1,1,3];
1309 }
1310 def: InstRW<[SKLWriteResGroup115], (instregex "ROR(8|16|32|64)mCL")>;
1311
1312 def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1313   let Latency = 8;
1314   let NumMicroOps = 5;
1315   let ResourceCycles = [1,1,1,2];
1316 }
1317 def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m1",
1318                                               "RCL(8|16|32|64)mi",
1319                                               "RCR(8|16|32|64)m1",
1320                                               "RCR(8|16|32|64)mi")>;
1321
1322 def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1323   let Latency = 8;
1324   let NumMicroOps = 6;
1325   let ResourceCycles = [1,1,1,3];
1326 }
1327 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
1328                                               "SAR(8|16|32|64)mCL",
1329                                               "SHL(8|16|32|64)mCL",
1330                                               "SHR(8|16|32|64)mCL")>;
1331
1332 def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1333   let Latency = 8;
1334   let NumMicroOps = 6;
1335   let ResourceCycles = [1,1,1,2,1];
1336 }
1337 def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
1338 def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(8|16|32|64)rm")>;
1339
1340 def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1341   let Latency = 9;
1342   let NumMicroOps = 2;
1343   let ResourceCycles = [1,1];
1344 }
1345 def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm")>;
1346
1347 def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1348   let Latency = 9;
1349   let NumMicroOps = 2;
1350   let ResourceCycles = [1,1];
1351 }
1352 def: InstRW<[SKLWriteResGroup121], (instregex "(V?)PCMPGTQrm",
1353                                               "VPMOVSXBWYrm",
1354                                               "VPMOVSXDQYrm",
1355                                               "VPMOVSXWDYrm",
1356                                               "VPMOVZXWDYrm")>;
1357
1358 def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
1359   let Latency = 9;
1360   let NumMicroOps = 2;
1361   let ResourceCycles = [1,1];
1362 }
1363 def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm",
1364                                               "(V?)CVTPS2PDrm")>;
1365
1366 def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> {
1367   let Latency = 9;
1368   let NumMicroOps = 3;
1369   let ResourceCycles = [1,1,1];
1370 }
1371 def: InstRW<[SKLWriteResGroup127], (instrs IMUL64m, MUL64m, MULX64rm)>;
1372
1373 def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1374   let Latency = 9;
1375   let NumMicroOps = 4;
1376   let ResourceCycles = [2,1,1];
1377 }
1378 def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
1379                                               "(V?)PHSUBSWrm")>;
1380
1381 def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1382   let Latency = 9;
1383   let NumMicroOps = 5;
1384   let ResourceCycles = [1,2,1,1];
1385 }
1386 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
1387                                               "LSL(16|32|64)rm")>;
1388
1389 def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1390   let Latency = 10;
1391   let NumMicroOps = 2;
1392   let ResourceCycles = [1,1];
1393 }
1394 def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1395                                               "ILD_F(16|32|64)m",
1396                                               "VPCMPGTQYrm")>;
1397
1398 def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1399   let Latency = 10;
1400   let NumMicroOps = 2;
1401   let ResourceCycles = [1,1];
1402 }
1403 def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm",
1404                                               "(V?)CVTPS2DQrm",
1405                                               "(V?)CVTSS2SDrm",
1406                                               "(V?)CVTTPS2DQrm")>;
1407
1408 def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1409   let Latency = 10;
1410   let NumMicroOps = 3;
1411   let ResourceCycles = [1,1,1];
1412 }
1413 def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm")>;
1414
1415 def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1416   let Latency = 10;
1417   let NumMicroOps = 3;
1418   let ResourceCycles = [1,1,1];
1419 }
1420 def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>;
1421
1422 def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1423   let Latency = 10;
1424   let NumMicroOps = 4;
1425   let ResourceCycles = [2,1,1];
1426 }
1427 def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWYrm",
1428                                               "VPHSUBSWYrm")>;
1429
1430 def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> {
1431   let Latency = 9;
1432   let NumMicroOps = 4;
1433   let ResourceCycles = [1,1,1,1];
1434 }
1435 def: InstRW<[SKLWriteResGroup142], (instrs IMUL32m, MUL32m, MULX32rm)>;
1436
1437 def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1438   let Latency = 10;
1439   let NumMicroOps = 8;
1440   let ResourceCycles = [1,1,1,1,1,3];
1441 }
1442 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
1443
1444 def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1445   let Latency = 11;
1446   let NumMicroOps = 1;
1447   let ResourceCycles = [1,3];
1448 }
1449 def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair
1450
1451 def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1452   let Latency = 11;
1453   let NumMicroOps = 2;
1454   let ResourceCycles = [1,1];
1455 }
1456 def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
1457
1458 def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1459   let Latency = 11;
1460   let NumMicroOps = 2;
1461   let ResourceCycles = [1,1];
1462 }
1463 def: InstRW<[SKLWriteResGroup147], (instregex "VCVTDQ2PSYrm",
1464                                               "VCVTPS2PDYrm",
1465                                               "VCVT(T?)PS2DQYrm")>;
1466
1467 def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1468   let Latency = 11;
1469   let NumMicroOps = 3;
1470   let ResourceCycles = [2,1];
1471 }
1472 def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
1473
1474 def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1475   let Latency = 11;
1476   let NumMicroOps = 3;
1477   let ResourceCycles = [1,1,1];
1478 }
1479 def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
1480
1481 def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
1482   let Latency = 11;
1483   let NumMicroOps = 3;
1484   let ResourceCycles = [1,1,1];
1485 }
1486 def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm",
1487                                               "(V?)CVT(T?)SD2SI(64)?rm",
1488                                               "VCVTTSS2SI64rm",
1489                                               "(V?)CVT(T?)SS2SIrm")>;
1490
1491 def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1492   let Latency = 11;
1493   let NumMicroOps = 3;
1494   let ResourceCycles = [1,1,1];
1495 }
1496 def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2PSrm",
1497                                               "CVT(T?)PD2DQrm",
1498                                               "MMX_CVT(T?)PD2PIirm")>;
1499
1500 def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1501   let Latency = 11;
1502   let NumMicroOps = 7;
1503   let ResourceCycles = [2,3,2];
1504 }
1505 def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
1506                                               "RCR(16|32|64)rCL")>;
1507
1508 def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1509   let Latency = 11;
1510   let NumMicroOps = 9;
1511   let ResourceCycles = [1,5,1,2];
1512 }
1513 def: InstRW<[SKLWriteResGroup155], (instregex "RCL8rCL")>;
1514
1515 def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1516   let Latency = 11;
1517   let NumMicroOps = 11;
1518   let ResourceCycles = [2,9];
1519 }
1520 def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
1521
1522 def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
1523   let Latency = 12;
1524   let NumMicroOps = 4;
1525   let ResourceCycles = [1,1,1,1];
1526 }
1527 def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
1528
1529 def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1530   let Latency = 13;
1531   let NumMicroOps = 3;
1532   let ResourceCycles = [2,1];
1533 }
1534 def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1535
1536 def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1537   let Latency = 13;
1538   let NumMicroOps = 3;
1539   let ResourceCycles = [1,1,1];
1540 }
1541 def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>;
1542
1543 def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1544   let Latency = 14;
1545   let NumMicroOps = 1;
1546   let ResourceCycles = [1,3];
1547 }
1548 def : SchedAlias<WriteFDiv64,  SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1549 def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1550
1551 def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1552   let Latency = 14;
1553   let NumMicroOps = 1;
1554   let ResourceCycles = [1,5];
1555 }
1556 def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair
1557
1558 def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1559   let Latency = 14;
1560   let NumMicroOps = 3;
1561   let ResourceCycles = [1,1,1];
1562 }
1563 def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
1564
1565 def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1566   let Latency = 14;
1567   let NumMicroOps = 10;
1568   let ResourceCycles = [2,4,1,3];
1569 }
1570 def: InstRW<[SKLWriteResGroup170], (instregex "RCR8rCL")>;
1571
1572 def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
1573   let Latency = 15;
1574   let NumMicroOps = 1;
1575   let ResourceCycles = [1];
1576 }
1577 def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1578
1579 def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1580   let Latency = 15;
1581   let NumMicroOps = 10;
1582   let ResourceCycles = [1,1,1,5,1,1];
1583 }
1584 def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
1585
1586 def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1587   let Latency = 16;
1588   let NumMicroOps = 14;
1589   let ResourceCycles = [1,1,1,4,2,5];
1590 }
1591 def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
1592
1593 def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
1594   let Latency = 16;
1595   let NumMicroOps = 16;
1596   let ResourceCycles = [16];
1597 }
1598 def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
1599
1600 def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1601   let Latency = 17;
1602   let NumMicroOps = 2;
1603   let ResourceCycles = [1,1,5];
1604 }
1605 def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair
1606
1607 def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1608   let Latency = 17;
1609   let NumMicroOps = 15;
1610   let ResourceCycles = [2,1,2,4,2,4];
1611 }
1612 def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
1613
1614 def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1615   let Latency = 18;
1616   let NumMicroOps = 8;
1617   let ResourceCycles = [1,1,1,5];
1618 }
1619 def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
1620
1621 def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1622   let Latency = 18;
1623   let NumMicroOps = 11;
1624   let ResourceCycles = [2,1,1,4,1,2];
1625 }
1626 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
1627
1628 def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1629   let Latency = 19;
1630   let NumMicroOps = 2;
1631   let ResourceCycles = [1,1,4];
1632 }
1633 def : SchedAlias<WriteFDiv64Ld,  SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair
1634
1635 def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
1636   let Latency = 20;
1637   let NumMicroOps = 1;
1638   let ResourceCycles = [1];
1639 }
1640 def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1641
1642 def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1643   let Latency = 20;
1644   let NumMicroOps = 2;
1645   let ResourceCycles = [1,1,4];
1646 }
1647 def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair
1648
1649 def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1650   let Latency = 20;
1651   let NumMicroOps = 8;
1652   let ResourceCycles = [1,1,1,1,1,1,2];
1653 }
1654 def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
1655
1656 def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
1657   let Latency = 20;
1658   let NumMicroOps = 10;
1659   let ResourceCycles = [1,2,7];
1660 }
1661 def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
1662
1663 def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1664   let Latency = 21;
1665   let NumMicroOps = 2;
1666   let ResourceCycles = [1,1,8];
1667 }
1668 def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair
1669
1670 def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1671   let Latency = 22;
1672   let NumMicroOps = 2;
1673   let ResourceCycles = [1,1];
1674 }
1675 def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
1676
1677 def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1678   let Latency = 22;
1679   let NumMicroOps = 5;
1680   let ResourceCycles = [1,2,1,1];
1681 }
1682 def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm,
1683                                              VGATHERDPDrm,
1684                                              VGATHERQPDrm,
1685                                              VGATHERQPSrm,
1686                                              VPGATHERDDrm,
1687                                              VPGATHERDQrm,
1688                                              VPGATHERQDrm,
1689                                              VPGATHERQQrm)>;
1690
1691 def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1692   let Latency = 25;
1693   let NumMicroOps = 5;
1694   let ResourceCycles = [1,2,1,1];
1695 }
1696 def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm,
1697                                              VGATHERQPDYrm,
1698                                              VGATHERQPSYrm,
1699                                              VPGATHERDDYrm,
1700                                              VPGATHERDQYrm,
1701                                              VPGATHERQDYrm,
1702                                              VPGATHERQQYrm,
1703                                              VGATHERDPDYrm)>;
1704
1705 def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1706   let Latency = 23;
1707   let NumMicroOps = 19;
1708   let ResourceCycles = [2,1,4,1,1,4,6];
1709 }
1710 def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
1711
1712 def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1713   let Latency = 25;
1714   let NumMicroOps = 3;
1715   let ResourceCycles = [1,1,1];
1716 }
1717 def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
1718
1719 def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1720   let Latency = 27;
1721   let NumMicroOps = 2;
1722   let ResourceCycles = [1,1];
1723 }
1724 def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
1725
1726 def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
1727   let Latency = 28;
1728   let NumMicroOps = 8;
1729   let ResourceCycles = [2,4,1,1];
1730 }
1731 def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(8|16|32|64)m")>;
1732
1733 def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1734   let Latency = 30;
1735   let NumMicroOps = 3;
1736   let ResourceCycles = [1,1,1];
1737 }
1738 def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
1739
1740 def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
1741   let Latency = 35;
1742   let NumMicroOps = 23;
1743   let ResourceCycles = [1,5,3,4,10];
1744 }
1745 def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
1746                                               "IN(8|16|32)rr")>;
1747
1748 def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1749   let Latency = 35;
1750   let NumMicroOps = 23;
1751   let ResourceCycles = [1,5,2,1,4,10];
1752 }
1753 def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
1754                                               "OUT(8|16|32)rr")>;
1755
1756 def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1757   let Latency = 37;
1758   let NumMicroOps = 31;
1759   let ResourceCycles = [1,8,1,21];
1760 }
1761 def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
1762
1763 def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
1764   let Latency = 40;
1765   let NumMicroOps = 18;
1766   let ResourceCycles = [1,1,2,3,1,1,1,8];
1767 }
1768 def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
1769
1770 def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1771   let Latency = 41;
1772   let NumMicroOps = 39;
1773   let ResourceCycles = [1,10,1,1,26];
1774 }
1775 def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
1776
1777 def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1778   let Latency = 42;
1779   let NumMicroOps = 22;
1780   let ResourceCycles = [2,20];
1781 }
1782 def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
1783
1784 def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1785   let Latency = 42;
1786   let NumMicroOps = 40;
1787   let ResourceCycles = [1,11,1,1,26];
1788 }
1789 def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
1790 def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
1791
1792 def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1793   let Latency = 46;
1794   let NumMicroOps = 44;
1795   let ResourceCycles = [1,11,1,1,30];
1796 }
1797 def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
1798
1799 def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
1800   let Latency = 62;
1801   let NumMicroOps = 64;
1802   let ResourceCycles = [2,8,5,10,39];
1803 }
1804 def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
1805
1806 def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1807   let Latency = 63;
1808   let NumMicroOps = 88;
1809   let ResourceCycles = [4,4,31,1,2,1,45];
1810 }
1811 def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
1812
1813 def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1814   let Latency = 63;
1815   let NumMicroOps = 90;
1816   let ResourceCycles = [4,2,33,1,2,1,47];
1817 }
1818 def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
1819
1820 def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
1821   let Latency = 75;
1822   let NumMicroOps = 15;
1823   let ResourceCycles = [6,3,6];
1824 }
1825 def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
1826
1827 def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1828   let Latency = 76;
1829   let NumMicroOps = 32;
1830   let ResourceCycles = [7,2,8,3,1,11];
1831 }
1832 def: InstRW<[SKLWriteResGroup221], (instregex "DIV(16|32|64)r")>;
1833
1834 def SKLWriteResGroup222 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1835   let Latency = 102;
1836   let NumMicroOps = 66;
1837   let ResourceCycles = [4,2,4,8,14,34];
1838 }
1839 def: InstRW<[SKLWriteResGroup222], (instregex "IDIV(16|32|64)r")>;
1840
1841 def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
1842   let Latency = 106;
1843   let NumMicroOps = 100;
1844   let ResourceCycles = [9,1,11,16,1,11,21,30];
1845 }
1846 def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
1847
1848 def: InstRW<[WriteZero], (instrs CLC)>;
1849
1850 } // SchedModel