1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Skylake Client to support
11 // instruction scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def SkylakeClientModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and SKylake can
17 // decode 6 instructions per cycle.
19 let MicroOpBufferSize = 224; // Based on the reorder buffer.
21 let MispredictPenalty = 14;
23 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
26 // This flag is set to allow the scheduler to assign a default model to
27 // unrecognized opcodes.
28 let CompleteModel = 0;
31 let SchedModel = SkylakeClientModel in {
33 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
35 // Ports 0, 1, 5, and 6 handle all computation.
36 // Port 4 gets the data half of stores. Store data can be available later than
37 // the store address, but since we don't model the latency of stores, we can
39 // Ports 2 and 3 are identical. They handle loads and the address half of
40 // stores. Port 7 can handle address calculations.
41 def SKLPort0 : ProcResource<1>;
42 def SKLPort1 : ProcResource<1>;
43 def SKLPort2 : ProcResource<1>;
44 def SKLPort3 : ProcResource<1>;
45 def SKLPort4 : ProcResource<1>;
46 def SKLPort5 : ProcResource<1>;
47 def SKLPort6 : ProcResource<1>;
48 def SKLPort7 : ProcResource<1>;
50 // Many micro-ops are capable of issuing on multiple ports.
51 def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>;
52 def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>;
53 def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
54 def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>;
55 def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>;
56 def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>;
57 def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>;
58 def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>;
59 def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>;
60 def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
61 def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
62 def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
64 def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
65 // FP division and sqrt on port 0.
66 def SKLFPDivider : ProcResource<1>;
68 // 60 Entry Unified Scheduler
69 def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
70 SKLPort5, SKLPort6, SKLPort7]> {
74 // Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
75 // cycles after the memory operand.
76 def : ReadAdvance<ReadAfterLd, 5>;
78 // Many SchedWrites are defined in pairs with and without a folded load.
79 // Instructions with folded loads are usually micro-fused, so they only appear
80 // as two micro-ops when queued in the reservation station.
81 // This multiclass defines the resource usage for variants with and without
83 multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
84 list<ProcResourceKind> ExePorts,
85 int Lat, list<int> Res = [1], int UOps = 1,
87 // Register variant is using a single cycle on ExePort.
88 def : WriteRes<SchedRW, ExePorts> {
90 let ResourceCycles = Res;
91 let NumMicroOps = UOps;
94 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
95 // the latency (default = 5).
96 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
97 let Latency = !add(Lat, LoadLat);
98 let ResourceCycles = !listconcat([1], Res);
99 let NumMicroOps = !add(UOps, 1);
103 // A folded store needs a cycle on port 4 for the store data, and an extra port
104 // 2/3/7 cycle to recompute the address.
105 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
108 defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op.
109 defm : SKLWriteResPair<WriteADC, [SKLPort06], 1>; // Integer ALU + flags op.
110 defm : SKLWriteResPair<WriteIMul, [SKLPort1], 3>; // Integer multiplication.
111 defm : SKLWriteResPair<WriteIMul64, [SKLPort1], 3>; // Integer 64-bit multiplication.
113 defm : X86WriteRes<WriteBSWAP32, [SKLPort15], 1, [1], 1>;
114 defm : X86WriteRes<WriteBSWAP64, [SKLPort06, SKLPort15], 2, [1,1], 2>;
116 defm : SKLWriteResPair<WriteDiv8, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
117 defm : SKLWriteResPair<WriteDiv16, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
118 defm : SKLWriteResPair<WriteDiv32, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
119 defm : SKLWriteResPair<WriteDiv64, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
120 defm : SKLWriteResPair<WriteIDiv8, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
121 defm : SKLWriteResPair<WriteIDiv16, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
122 defm : SKLWriteResPair<WriteIDiv32, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
123 defm : SKLWriteResPair<WriteIDiv64, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
125 defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
127 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
128 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
130 defm : SKLWriteResPair<WriteCMOV, [SKLPort06], 1, [1], 1>; // Conditional move.
131 defm : SKLWriteResPair<WriteCMOV2, [SKLPort06], 2, [2], 2>; // Conditional (CF + ZF flag) move.
132 defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move.
133 def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
134 def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
138 def : WriteRes<WriteLAHFSAHF, [SKLPort06]>;
139 def : WriteRes<WriteBitTest,[SKLPort06]>; //
142 defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
143 defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;
144 defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>;
145 defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>;
146 defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>;
148 // Integer shifts and rotates.
149 defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>;
152 defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;
153 defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>;
154 defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>;
155 defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>;
157 // BMI1 BEXTR, BMI2 BZHI
158 defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;
159 defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>;
161 // Loads, stores, and moves, not folded with other operations.
162 defm : X86WriteRes<WriteLoad, [SKLPort23], 5, [1], 1>;
163 defm : X86WriteRes<WriteStore, [SKLPort237, SKLPort4], 1, [1,1], 1>;
164 defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;
165 defm : X86WriteRes<WriteMove, [SKLPort0156], 1, [1], 1>;
167 // Idioms that clear a register, like xorps %xmm0, %xmm0.
168 // These can often bypass execution ports completely.
169 def : WriteRes<WriteZero, []>;
171 // Branches don't produce values, so they have no latency, but they still
172 // consume resources. Indirect branches can fold loads.
173 defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>;
175 // Floating point. This covers both scalar and vector operations.
176 defm : X86WriteRes<WriteFLD0, [SKLPort05], 1, [1], 1>;
177 defm : X86WriteRes<WriteFLD1, [SKLPort05], 1, [2], 2>;
178 defm : X86WriteRes<WriteFLDC, [SKLPort05], 1, [2], 2>;
179 defm : X86WriteRes<WriteFLoad, [SKLPort23], 5, [1], 1>;
180 defm : X86WriteRes<WriteFLoadX, [SKLPort23], 6, [1], 1>;
181 defm : X86WriteRes<WriteFLoadY, [SKLPort23], 7, [1], 1>;
182 defm : X86WriteRes<WriteFMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>;
183 defm : X86WriteRes<WriteFMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>;
184 defm : X86WriteRes<WriteFStore, [SKLPort237,SKLPort4], 1, [1,1], 2>;
185 defm : X86WriteRes<WriteFStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>;
186 defm : X86WriteRes<WriteFStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>;
187 defm : X86WriteRes<WriteFStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>;
188 defm : X86WriteRes<WriteFStoreNTX, [SKLPort237,SKLPort4], 1, [1,1], 2>;
189 defm : X86WriteRes<WriteFStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>;
190 defm : X86WriteRes<WriteFMaskedStore, [SKLPort237,SKLPort0], 2, [1,1], 2>;
191 defm : X86WriteRes<WriteFMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>;
192 defm : X86WriteRes<WriteFMove, [SKLPort015], 1, [1], 1>;
193 defm : X86WriteRes<WriteFMoveX, [SKLPort015], 1, [1], 1>;
194 defm : X86WriteRes<WriteFMoveY, [SKLPort015], 1, [1], 1>;
195 defm : X86WriteRes<WriteEMMS, [SKLPort05,SKLPort0156], 10, [9,1], 10>;
197 defm : SKLWriteResPair<WriteFAdd, [SKLPort01], 4, [1], 1, 5>; // Floating point add/sub.
198 defm : SKLWriteResPair<WriteFAddX, [SKLPort01], 4, [1], 1, 6>;
199 defm : SKLWriteResPair<WriteFAddY, [SKLPort01], 4, [1], 1, 7>;
200 defm : X86WriteResPairUnsupported<WriteFAddZ>;
201 defm : SKLWriteResPair<WriteFAdd64, [SKLPort01], 4, [1], 1, 5>; // Floating point double add/sub.
202 defm : SKLWriteResPair<WriteFAdd64X, [SKLPort01], 4, [1], 1, 6>;
203 defm : SKLWriteResPair<WriteFAdd64Y, [SKLPort01], 4, [1], 1, 7>;
204 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
206 defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 5>; // Floating point compare.
207 defm : SKLWriteResPair<WriteFCmpX, [SKLPort01], 4, [1], 1, 6>;
208 defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>;
209 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
210 defm : SKLWriteResPair<WriteFCmp64, [SKLPort01], 4, [1], 1, 5>; // Floating point double compare.
211 defm : SKLWriteResPair<WriteFCmp64X, [SKLPort01], 4, [1], 1, 6>;
212 defm : SKLWriteResPair<WriteFCmp64Y, [SKLPort01], 4, [1], 1, 7>;
213 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
215 defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags.
217 defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 5>; // Floating point multiplication.
218 defm : SKLWriteResPair<WriteFMulX, [SKLPort01], 4, [1], 1, 6>;
219 defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>;
220 defm : X86WriteResPairUnsupported<WriteFMulZ>;
221 defm : SKLWriteResPair<WriteFMul64, [SKLPort01], 4, [1], 1, 5>; // Floating point double multiplication.
222 defm : SKLWriteResPair<WriteFMul64X, [SKLPort01], 4, [1], 1, 6>;
223 defm : SKLWriteResPair<WriteFMul64Y, [SKLPort01], 4, [1], 1, 7>;
224 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
226 defm : SKLWriteResPair<WriteFDiv, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.
227 //defm : SKLWriteResPair<WriteFDivX, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>;
228 defm : SKLWriteResPair<WriteFDivY, [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>;
229 defm : X86WriteResPairUnsupported<WriteFDivZ>;
230 //defm : SKLWriteResPair<WriteFDiv64, [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division.
231 //defm : SKLWriteResPair<WriteFDiv64X, [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>;
232 //defm : SKLWriteResPair<WriteFDiv64Y, [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>;
233 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
235 defm : SKLWriteResPair<WriteFSqrt, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
236 defm : SKLWriteResPair<WriteFSqrtX, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>;
237 defm : SKLWriteResPair<WriteFSqrtY, [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>;
238 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
239 defm : SKLWriteResPair<WriteFSqrt64, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
240 defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>;
241 defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>;
242 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
243 defm : SKLWriteResPair<WriteFSqrt80, [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root.
245 defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
246 defm : SKLWriteResPair<WriteFRcpX, [SKLPort0], 4, [1], 1, 6>;
247 defm : SKLWriteResPair<WriteFRcpY, [SKLPort0], 4, [1], 1, 7>;
248 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
250 defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
251 defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>;
252 defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>;
253 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
255 defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add.
256 defm : SKLWriteResPair<WriteFMAX, [SKLPort01], 4, [1], 1, 6>;
257 defm : SKLWriteResPair<WriteFMAY, [SKLPort01], 4, [1], 1, 7>;
258 defm : X86WriteResPairUnsupported<WriteFMAZ>;
259 defm : SKLWriteResPair<WriteDPPD, [SKLPort5,SKLPort01], 9, [1,2], 3, 6>; // Floating point double dot product.
260 defm : SKLWriteResPair<WriteDPPS, [SKLPort5,SKLPort01], 13, [1,3], 4, 6>;
261 defm : SKLWriteResPair<WriteDPPSY, [SKLPort5,SKLPort01], 13, [1,3], 4, 7>;
262 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
263 defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs.
264 defm : SKLWriteResPair<WriteFRnd, [SKLPort01], 8, [2], 2, 6>; // Floating point rounding.
265 defm : SKLWriteResPair<WriteFRndY, [SKLPort01], 8, [2], 2, 7>;
266 defm : X86WriteResPairUnsupported<WriteFRndZ>;
267 defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
268 defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>;
269 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
270 defm : SKLWriteResPair<WriteFTest, [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
271 defm : SKLWriteResPair<WriteFTestY, [SKLPort0], 2, [1], 1, 7>;
272 defm : X86WriteResPairUnsupported<WriteFTestZ>;
273 defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
274 defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>;
275 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
276 defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
277 defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
278 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
279 defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends.
280 defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>;
281 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
282 defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends.
283 defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>;
284 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
286 // FMA Scheduling helper class.
287 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
289 // Vector integer operations.
290 defm : X86WriteRes<WriteVecLoad, [SKLPort23], 5, [1], 1>;
291 defm : X86WriteRes<WriteVecLoadX, [SKLPort23], 6, [1], 1>;
292 defm : X86WriteRes<WriteVecLoadY, [SKLPort23], 7, [1], 1>;
293 defm : X86WriteRes<WriteVecLoadNT, [SKLPort23], 6, [1], 1>;
294 defm : X86WriteRes<WriteVecLoadNTY, [SKLPort23], 7, [1], 1>;
295 defm : X86WriteRes<WriteVecMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>;
296 defm : X86WriteRes<WriteVecMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>;
297 defm : X86WriteRes<WriteVecStore, [SKLPort237,SKLPort4], 1, [1,1], 2>;
298 defm : X86WriteRes<WriteVecStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>;
299 defm : X86WriteRes<WriteVecStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>;
300 defm : X86WriteRes<WriteVecStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>;
301 defm : X86WriteRes<WriteVecStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>;
302 defm : X86WriteRes<WriteVecMaskedStore, [SKLPort237,SKLPort0], 2, [1,1], 2>;
303 defm : X86WriteRes<WriteVecMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>;
304 defm : X86WriteRes<WriteVecMove, [SKLPort05], 1, [1], 1>;
305 defm : X86WriteRes<WriteVecMoveX, [SKLPort015], 1, [1], 1>;
306 defm : X86WriteRes<WriteVecMoveY, [SKLPort015], 1, [1], 1>;
307 defm : X86WriteRes<WriteVecMoveToGpr, [SKLPort0], 2, [1], 1>;
308 defm : X86WriteRes<WriteVecMoveFromGpr, [SKLPort5], 1, [1], 1>;
310 defm : SKLWriteResPair<WriteVecALU, [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
311 defm : SKLWriteResPair<WriteVecALUX, [SKLPort01], 1, [1], 1, 6>;
312 defm : SKLWriteResPair<WriteVecALUY, [SKLPort01], 1, [1], 1, 7>;
313 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
314 defm : SKLWriteResPair<WriteVecLogic, [SKLPort05], 1, [1], 1, 5>; // Vector integer and/or/xor.
315 defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>;
316 defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>;
317 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
318 defm : SKLWriteResPair<WriteVecTest, [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
319 defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>;
320 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
321 defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 4, [1], 1, 5>; // Vector integer multiply.
322 defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 4, [1], 1, 6>;
323 defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 4, [1], 1, 7>;
324 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
325 defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD.
326 defm : SKLWriteResPair<WritePMULLDY, [SKLPort01], 10, [2], 2, 7>;
327 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
328 defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
329 defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;
330 defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;
331 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
332 defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
333 defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;
334 defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
335 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
336 defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends.
337 defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>;
338 defm : X86WriteResPairUnsupported<WriteBlendZ>;
339 defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
340 defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>;
341 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
342 defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
343 defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>;
344 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
345 defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW.
346 defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;
347 defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;
348 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
349 defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
351 // Vector integer shifts.
352 defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1, [1], 1, 5>;
353 defm : X86WriteRes<WriteVecShiftX, [SKLPort5,SKLPort01], 2, [1,1], 2>;
354 defm : X86WriteRes<WriteVecShiftY, [SKLPort5,SKLPort01], 4, [1,1], 2>;
355 defm : X86WriteRes<WriteVecShiftXLd, [SKLPort01,SKLPort23], 7, [1,1], 2>;
356 defm : X86WriteRes<WriteVecShiftYLd, [SKLPort01,SKLPort23], 8, [1,1], 2>;
357 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
359 defm : SKLWriteResPair<WriteVecShiftImm, [SKLPort0], 1, [1], 1, 5>; // Vector integer immediate shifts.
360 defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>;
361 defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>;
362 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
363 defm : SKLWriteResPair<WriteVarVecShift, [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.
364 defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;
365 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
367 // Vector insert/extract operations.
368 def : WriteRes<WriteVecInsert, [SKLPort5]> {
371 let ResourceCycles = [2];
373 def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
377 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
379 def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {
383 def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> {
388 // Conversion between integer and float.
389 defm : SKLWriteResPair<WriteCvtSS2I, [SKLPort1], 3>;
390 defm : SKLWriteResPair<WriteCvtPS2I, [SKLPort1], 3>;
391 defm : SKLWriteResPair<WriteCvtPS2IY, [SKLPort1], 3>;
392 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
393 defm : SKLWriteResPair<WriteCvtSD2I, [SKLPort1], 3>;
394 defm : SKLWriteResPair<WriteCvtPD2I, [SKLPort1], 3>;
395 defm : SKLWriteResPair<WriteCvtPD2IY, [SKLPort1], 3>;
396 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
398 defm : SKLWriteResPair<WriteCvtI2SS, [SKLPort1], 4>;
399 defm : SKLWriteResPair<WriteCvtI2PS, [SKLPort1], 4>;
400 defm : SKLWriteResPair<WriteCvtI2PSY, [SKLPort1], 4>;
401 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
402 defm : SKLWriteResPair<WriteCvtI2SD, [SKLPort1], 4>;
403 defm : SKLWriteResPair<WriteCvtI2PD, [SKLPort1], 4>;
404 defm : SKLWriteResPair<WriteCvtI2PDY, [SKLPort1], 4>;
405 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
407 defm : SKLWriteResPair<WriteCvtSS2SD, [SKLPort1], 3>;
408 defm : SKLWriteResPair<WriteCvtPS2PD, [SKLPort1], 3>;
409 defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>;
410 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
411 defm : SKLWriteResPair<WriteCvtSD2SS, [SKLPort1], 3>;
412 defm : SKLWriteResPair<WriteCvtPD2PS, [SKLPort1], 3>;
413 defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>;
414 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
416 defm : X86WriteRes<WriteCvtPH2PS, [SKLPort5,SKLPort015], 5, [1,1], 2>;
417 defm : X86WriteRes<WriteCvtPH2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2>;
418 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
419 defm : X86WriteRes<WriteCvtPH2PSLd, [SKLPort23,SKLPort01], 9, [1,1], 2>;
420 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
421 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
423 defm : X86WriteRes<WriteCvtPS2PH, [SKLPort5,SKLPort015], 5, [1,1], 2>;
424 defm : X86WriteRes<WriteCvtPS2PHY, [SKLPort5,SKLPort01], 7, [1,1], 2>;
425 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
426 defm : X86WriteRes<WriteCvtPS2PHSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>;
427 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>;
428 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
430 // Strings instructions.
432 // Packed Compare Implicit Length Strings, Return Mask
433 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
436 let ResourceCycles = [3];
438 def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
441 let ResourceCycles = [3,1];
444 // Packed Compare Explicit Length Strings, Return Mask
445 def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
448 let ResourceCycles = [4,3,1,1];
450 def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
452 let NumMicroOps = 10;
453 let ResourceCycles = [4,3,1,1,1];
456 // Packed Compare Implicit Length Strings, Return Index
457 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
460 let ResourceCycles = [3];
462 def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
465 let ResourceCycles = [3,1];
468 // Packed Compare Explicit Length Strings, Return Index
469 def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
472 let ResourceCycles = [4,3,1];
474 def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
477 let ResourceCycles = [4,3,1,1];
480 // MOVMSK Instructions.
481 def : WriteRes<WriteFMOVMSK, [SKLPort0]> { let Latency = 2; }
482 def : WriteRes<WriteVecMOVMSK, [SKLPort0]> { let Latency = 2; }
483 def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }
484 def : WriteRes<WriteMMXMOVMSK, [SKLPort0]> { let Latency = 2; }
487 def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
490 let ResourceCycles = [1];
492 def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
495 let ResourceCycles = [1,1];
498 def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
501 let ResourceCycles = [2];
503 def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
506 let ResourceCycles = [2,1];
509 def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
511 let NumMicroOps = 11;
512 let ResourceCycles = [3,6,2];
514 def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
516 let NumMicroOps = 11;
517 let ResourceCycles = [3,6,1,1];
520 // Carry-less multiplication instructions.
521 def : WriteRes<WriteCLMul, [SKLPort5]> {
524 let ResourceCycles = [1];
526 def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
529 let ResourceCycles = [1,1];
532 // Catch-all for expensive system instructions.
533 def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
536 defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
537 defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
538 defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles.
539 defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles.
541 // Old microcoded instructions that nobody use.
542 def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
544 // Fence instructions.
545 def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
548 def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
549 def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
551 // Nop, not very useful expect it provides a model for nops!
552 def : WriteRes<WriteNop, []>;
554 ////////////////////////////////////////////////////////////////////////////////
555 // Horizontal add/sub instructions.
556 ////////////////////////////////////////////////////////////////////////////////
558 defm : SKLWriteResPair<WriteFHAdd, [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
559 defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;
560 defm : SKLWriteResPair<WritePHAdd, [SKLPort5,SKLPort05], 3, [2,1], 3, 5>;
561 defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;
562 defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
566 def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
569 let ResourceCycles = [1];
571 def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr",
572 "MMX_PADDUS(B|W)irr",
574 "MMX_PCMPEQ(B|D|W)irr",
575 "MMX_PCMPGT(B|D|W)irr",
576 "MMX_P(MAX|MIN)SWirr",
577 "MMX_P(MAX|MIN)UBirr",
579 "MMX_PSUBUS(B|W)irr")>;
581 def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
584 let ResourceCycles = [1];
586 def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
589 def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
592 let ResourceCycles = [1];
594 def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
596 def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
599 let ResourceCycles = [1];
601 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
603 def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
606 let ResourceCycles = [1];
608 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
610 def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
613 let ResourceCycles = [1];
615 def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr",
620 def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
623 let ResourceCycles = [1];
625 def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
627 "(V?)PSUB(B|D|Q|W)(Y?)rr")>;
629 def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
632 let ResourceCycles = [1];
634 def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
636 def: InstRW<[SKLWriteResGroup10], (instregex "SGDT64m",
642 def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
645 let ResourceCycles = [1,1];
647 def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",
651 def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
654 let ResourceCycles = [2];
656 def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>;
658 def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
661 let ResourceCycles = [2];
663 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP)>;
664 def: InstRW<[SKLWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>;
666 def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {
669 let ResourceCycles = [2];
671 def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)r1",
677 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
680 let ResourceCycles = [2];
682 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
686 def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
689 let ResourceCycles = [1,1];
691 def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
693 def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
696 let ResourceCycles = [1,1];
698 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
700 def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
703 let ResourceCycles = [1,1];
705 def: InstRW<[SKLWriteResGroup23], (instrs CWD)>;
706 def: InstRW<[SKLWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>;
707 def: InstRW<[SKLWriteResGroup23], (instregex "ADC8i8",
712 def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
715 let ResourceCycles = [1,1,1];
717 def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
719 def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
722 let ResourceCycles = [1,1,1];
724 def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
726 def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
729 let ResourceCycles = [1,1,1];
731 def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r,
732 STOSB, STOSL, STOSQ, STOSW)>;
733 def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr",
736 def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
739 let ResourceCycles = [1];
741 def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
744 def SKLWriteResGroup29_16i : SchedWriteRes<[SKLPort1, SKLPort0156]> {
747 let ResourceCycles = [1,1];
749 def: InstRW<[SKLWriteResGroup29_16i], (instrs IMUL16rri, IMUL16rri8)>;
751 def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
754 let ResourceCycles = [1];
756 def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
759 "(V?)PCMPGTQ(Y?)rr")>;
761 def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
764 let ResourceCycles = [1,1];
766 def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
768 def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> {
771 let ResourceCycles = [3];
773 def: InstRW<[SKLWriteResGroup33], (instregex "ROL(8|16|32|64)rCL",
774 "ROR(8|16|32|64)rCL",
775 "SAR(8|16|32|64)rCL",
776 "SHL(8|16|32|64)rCL",
777 "SHR(8|16|32|64)rCL")>;
779 def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> {
782 let ResourceCycles = [3];
784 def: InstRW<[SKLWriteResGroup34], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr,
785 XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr,
786 XCHG16ar, XCHG32ar, XCHG64ar)>;
788 def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
791 let ResourceCycles = [1,2];
793 def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
795 def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
798 let ResourceCycles = [2,1];
800 def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
801 "(V?)PHSUBSW(Y?)rr")>;
803 def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
806 let ResourceCycles = [2,1];
808 def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSDWirr",
812 def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
815 let ResourceCycles = [1,2];
817 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
819 def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
822 let ResourceCycles = [1,2];
824 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
826 def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
829 let ResourceCycles = [1,2];
831 def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r1",
834 "RCR(8|16|32|64)ri")>;
836 def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
839 let ResourceCycles = [1,1,1];
841 def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
843 def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
846 let ResourceCycles = [1,1,2];
848 def: InstRW<[SKLWriteResGroup44], (instregex "SET(A|BE)m")>;
850 def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
853 let ResourceCycles = [1,1,1,1];
855 def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
857 def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
860 let ResourceCycles = [1,1,1,1];
862 def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
864 def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
867 let ResourceCycles = [1];
869 def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
871 def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
874 let ResourceCycles = [1];
876 def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr",
877 "(V?)CVT(T?)PS2DQ(Y?)rr")>;
879 def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> {
882 let ResourceCycles = [1,1];
884 def: InstRW<[SKLWriteResGroup51], (instrs IMUL64r, MUL64r, MULX64rr)>;
886 def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
889 let ResourceCycles = [1,1,2];
891 def: InstRW<[SKLWriteResGroup51_16], (instrs IMUL16r, MUL16r)>;
893 def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
896 let ResourceCycles = [1,1,1];
898 def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
901 def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
904 let ResourceCycles = [4];
906 def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
908 def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
911 let ResourceCycles = [1,3];
913 def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
915 def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> {
918 let ResourceCycles = [1,3];
920 def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
922 def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
925 let ResourceCycles = [1,1,2];
927 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
929 def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
932 let ResourceCycles = [1];
934 def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm16",
935 "MOVSX(16|32|64)rm32",
936 "MOVSX(16|32|64)rm8",
937 "MOVZX(16|32|64)rm16",
938 "MOVZX(16|32|64)rm8",
939 "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67?
941 def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
944 let ResourceCycles = [1,1];
946 def: InstRW<[SKLWriteResGroup59], (instregex "MMX_CVTPI2PDirr",
949 def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
952 let ResourceCycles = [1,1];
954 def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr",
955 "MMX_CVT(T?)PS2PIirr",
956 "(V?)CVT(T?)PD2DQrr",
965 def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
968 let ResourceCycles = [1,1,1];
970 def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
972 def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
975 let ResourceCycles = [1,1,1];
977 def: InstRW<[SKLWriteResGroup62], (instrs IMUL32r, MUL32r, MULX32rr)>;
979 def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
982 let ResourceCycles = [1,4];
984 def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
986 def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
989 let ResourceCycles = [2,3];
991 def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>;
993 def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
996 let ResourceCycles = [1,1,4];
998 def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
1000 def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
1002 let NumMicroOps = 1;
1003 let ResourceCycles = [1];
1005 def: InstRW<[SKLWriteResGroup67], (instregex "VBROADCASTSSrm",
1011 def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
1013 let NumMicroOps = 2;
1014 let ResourceCycles = [2];
1016 def: InstRW<[SKLWriteResGroup68], (instregex "MMX_CVTPI2PSirr")>;
1018 def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1020 let NumMicroOps = 2;
1021 let ResourceCycles = [1,1];
1023 def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm",
1044 def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> {
1046 let NumMicroOps = 2;
1047 let ResourceCycles = [1,1];
1049 def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr",
1050 "(V?)CVT(T?)SD2SI(64)?rr")>;
1052 def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
1054 let NumMicroOps = 2;
1055 let ResourceCycles = [1,1];
1057 def: InstRW<[SKLWriteResGroup72], (instregex "FARJMP64",
1060 def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
1062 let NumMicroOps = 2;
1063 let ResourceCycles = [1,1];
1065 def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
1067 def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
1069 let NumMicroOps = 2;
1070 let ResourceCycles = [1,1];
1072 def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1076 "MOVBE(16|32|64)rm")>;
1078 def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1080 let NumMicroOps = 2;
1081 let ResourceCycles = [1,1];
1083 def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
1084 def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
1086 def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1088 let NumMicroOps = 3;
1089 let ResourceCycles = [2,1];
1091 def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
1093 def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
1095 let NumMicroOps = 4;
1096 let ResourceCycles = [1,1,1,1];
1098 def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
1100 def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1102 let NumMicroOps = 4;
1103 let ResourceCycles = [1,1,1,1];
1105 def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8",
1108 "SAR(8|16|32|64)m1",
1109 "SAR(8|16|32|64)mi",
1110 "SHL(8|16|32|64)m1",
1111 "SHL(8|16|32|64)mi",
1112 "SHR(8|16|32|64)m1",
1113 "SHR(8|16|32|64)mi")>;
1115 def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1117 let NumMicroOps = 4;
1118 let ResourceCycles = [1,1,1,1];
1120 def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
1121 "PUSH(16|32|64)rmm")>;
1123 def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1125 let NumMicroOps = 6;
1126 let ResourceCycles = [1,5];
1128 def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
1130 def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
1132 let NumMicroOps = 1;
1133 let ResourceCycles = [1];
1135 def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m",
1144 "VPBROADCASTQYrm")>;
1146 def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1148 let NumMicroOps = 2;
1149 let ResourceCycles = [1,1];
1151 def: InstRW<[SKLWriteResGroup86], (instregex "VCVTDQ2PDYrr")>;
1153 def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1155 let NumMicroOps = 2;
1156 let ResourceCycles = [1,1];
1158 def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
1159 "(V?)PMOV(SX|ZX)BQrm",
1160 "(V?)PMOV(SX|ZX)BWrm",
1161 "(V?)PMOV(SX|ZX)DQrm",
1162 "(V?)PMOV(SX|ZX)WDrm",
1163 "(V?)PMOV(SX|ZX)WQrm")>;
1165 def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1167 let NumMicroOps = 2;
1168 let ResourceCycles = [1,1];
1170 def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2PSYrr",
1172 "VCVT(T?)PD2DQYrr")>;
1174 def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1176 let NumMicroOps = 2;
1177 let ResourceCycles = [1,1];
1179 def: InstRW<[SKLWriteResGroup91], (instregex "(V?)INSERTF128rm",
1181 "(V?)PADD(B|D|Q|W)rm",
1183 "(V?)PSUB(B|D|Q|W)rm")>;
1185 def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1187 let NumMicroOps = 3;
1188 let ResourceCycles = [2,1];
1190 def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm",
1192 "MMX_PACKUSWBirm")>;
1194 def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1196 let NumMicroOps = 3;
1197 let ResourceCycles = [1,2];
1199 def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
1200 SCASB, SCASL, SCASQ, SCASW)>;
1202 def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
1204 let NumMicroOps = 3;
1205 let ResourceCycles = [1,1,1];
1207 def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>;
1209 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
1211 let NumMicroOps = 3;
1212 let ResourceCycles = [1,1,1];
1214 def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
1216 def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
1218 let NumMicroOps = 3;
1219 let ResourceCycles = [1,1,1];
1221 def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>;
1223 def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1225 let NumMicroOps = 5;
1226 let ResourceCycles = [1,1,1,2];
1228 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m1",
1229 "ROL(8|16|32|64)mi",
1230 "ROR(8|16|32|64)m1",
1231 "ROR(8|16|32|64)mi")>;
1233 def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1235 let NumMicroOps = 5;
1236 let ResourceCycles = [1,1,1,2];
1238 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
1240 def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1242 let NumMicroOps = 5;
1243 let ResourceCycles = [1,1,1,1,1];
1245 def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m",
1248 def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
1250 let NumMicroOps = 7;
1251 let ResourceCycles = [1,3,1,2];
1253 def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
1255 def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
1257 let NumMicroOps = 2;
1258 let ResourceCycles = [1,1];
1260 def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
1263 def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
1265 let NumMicroOps = 3;
1266 let ResourceCycles = [1,1,1];
1268 def: InstRW<[SKLWriteResGroup107_16], (instrs IMUL16rmi, IMUL16rmi8)>;
1270 def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort06, SKLPort0156, SKLPort23]> {
1272 let NumMicroOps = 5;
1273 let ResourceCycles = [1,1,2,1];
1275 def: InstRW<[SKLWriteResGroup107_16_2], (instrs IMUL16m, MUL16m)>;
1277 def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1279 let NumMicroOps = 2;
1280 let ResourceCycles = [1,1];
1282 def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m",
1289 def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1291 let NumMicroOps = 2;
1292 let ResourceCycles = [1,1];
1294 def: InstRW<[SKLWriteResGroup110], (instregex "VPADD(B|D|Q|W)Yrm",
1296 "VPSUB(B|D|Q|W)Yrm")>;
1298 def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1300 let NumMicroOps = 4;
1301 let ResourceCycles = [1,2,1];
1303 def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1305 def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> {
1307 let NumMicroOps = 5;
1308 let ResourceCycles = [1,1,3];
1310 def: InstRW<[SKLWriteResGroup115], (instregex "ROR(8|16|32|64)mCL")>;
1312 def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1314 let NumMicroOps = 5;
1315 let ResourceCycles = [1,1,1,2];
1317 def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m1",
1318 "RCL(8|16|32|64)mi",
1319 "RCR(8|16|32|64)m1",
1320 "RCR(8|16|32|64)mi")>;
1322 def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1324 let NumMicroOps = 6;
1325 let ResourceCycles = [1,1,1,3];
1327 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
1328 "SAR(8|16|32|64)mCL",
1329 "SHL(8|16|32|64)mCL",
1330 "SHR(8|16|32|64)mCL")>;
1332 def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1334 let NumMicroOps = 6;
1335 let ResourceCycles = [1,1,1,2,1];
1337 def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
1338 def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(8|16|32|64)rm")>;
1340 def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1342 let NumMicroOps = 2;
1343 let ResourceCycles = [1,1];
1345 def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm")>;
1347 def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1349 let NumMicroOps = 2;
1350 let ResourceCycles = [1,1];
1352 def: InstRW<[SKLWriteResGroup121], (instregex "(V?)PCMPGTQrm",
1358 def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
1360 let NumMicroOps = 2;
1361 let ResourceCycles = [1,1];
1363 def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm",
1366 def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> {
1368 let NumMicroOps = 3;
1369 let ResourceCycles = [1,1,1];
1371 def: InstRW<[SKLWriteResGroup127], (instrs IMUL64m, MUL64m, MULX64rm)>;
1373 def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1375 let NumMicroOps = 4;
1376 let ResourceCycles = [2,1,1];
1378 def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
1381 def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1383 let NumMicroOps = 5;
1384 let ResourceCycles = [1,2,1,1];
1386 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
1387 "LSL(16|32|64)rm")>;
1389 def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1391 let NumMicroOps = 2;
1392 let ResourceCycles = [1,1];
1394 def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1398 def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1400 let NumMicroOps = 2;
1401 let ResourceCycles = [1,1];
1403 def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm",
1406 "(V?)CVTTPS2DQrm")>;
1408 def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1410 let NumMicroOps = 3;
1411 let ResourceCycles = [1,1,1];
1413 def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm")>;
1415 def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1417 let NumMicroOps = 3;
1418 let ResourceCycles = [1,1,1];
1420 def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>;
1422 def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1424 let NumMicroOps = 4;
1425 let ResourceCycles = [2,1,1];
1427 def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWYrm",
1430 def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> {
1432 let NumMicroOps = 4;
1433 let ResourceCycles = [1,1,1,1];
1435 def: InstRW<[SKLWriteResGroup142], (instrs IMUL32m, MUL32m, MULX32rm)>;
1437 def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1439 let NumMicroOps = 8;
1440 let ResourceCycles = [1,1,1,1,1,3];
1442 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
1444 def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1446 let NumMicroOps = 1;
1447 let ResourceCycles = [1,3];
1449 def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair
1451 def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1453 let NumMicroOps = 2;
1454 let ResourceCycles = [1,1];
1456 def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
1458 def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1460 let NumMicroOps = 2;
1461 let ResourceCycles = [1,1];
1463 def: InstRW<[SKLWriteResGroup147], (instregex "VCVTDQ2PSYrm",
1465 "VCVT(T?)PS2DQYrm")>;
1467 def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1469 let NumMicroOps = 3;
1470 let ResourceCycles = [2,1];
1472 def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
1474 def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1476 let NumMicroOps = 3;
1477 let ResourceCycles = [1,1,1];
1479 def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
1481 def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
1483 let NumMicroOps = 3;
1484 let ResourceCycles = [1,1,1];
1486 def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm",
1487 "(V?)CVT(T?)SD2SI(64)?rm",
1489 "(V?)CVT(T?)SS2SIrm")>;
1491 def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1493 let NumMicroOps = 3;
1494 let ResourceCycles = [1,1,1];
1496 def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2PSrm",
1498 "MMX_CVT(T?)PD2PIirm")>;
1500 def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1502 let NumMicroOps = 7;
1503 let ResourceCycles = [2,3,2];
1505 def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
1506 "RCR(16|32|64)rCL")>;
1508 def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1510 let NumMicroOps = 9;
1511 let ResourceCycles = [1,5,1,2];
1513 def: InstRW<[SKLWriteResGroup155], (instregex "RCL8rCL")>;
1515 def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1517 let NumMicroOps = 11;
1518 let ResourceCycles = [2,9];
1520 def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
1522 def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
1524 let NumMicroOps = 4;
1525 let ResourceCycles = [1,1,1,1];
1527 def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
1529 def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1531 let NumMicroOps = 3;
1532 let ResourceCycles = [2,1];
1534 def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1536 def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1538 let NumMicroOps = 3;
1539 let ResourceCycles = [1,1,1];
1541 def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>;
1543 def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1545 let NumMicroOps = 1;
1546 let ResourceCycles = [1,3];
1548 def : SchedAlias<WriteFDiv64, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1549 def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1551 def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1553 let NumMicroOps = 1;
1554 let ResourceCycles = [1,5];
1556 def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair
1558 def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1560 let NumMicroOps = 3;
1561 let ResourceCycles = [1,1,1];
1563 def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
1565 def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1567 let NumMicroOps = 10;
1568 let ResourceCycles = [2,4,1,3];
1570 def: InstRW<[SKLWriteResGroup170], (instregex "RCR8rCL")>;
1572 def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
1574 let NumMicroOps = 1;
1575 let ResourceCycles = [1];
1577 def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1579 def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1581 let NumMicroOps = 10;
1582 let ResourceCycles = [1,1,1,5,1,1];
1584 def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
1586 def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1588 let NumMicroOps = 14;
1589 let ResourceCycles = [1,1,1,4,2,5];
1591 def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
1593 def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
1595 let NumMicroOps = 16;
1596 let ResourceCycles = [16];
1598 def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
1600 def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1602 let NumMicroOps = 2;
1603 let ResourceCycles = [1,1,5];
1605 def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair
1607 def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1609 let NumMicroOps = 15;
1610 let ResourceCycles = [2,1,2,4,2,4];
1612 def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
1614 def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1616 let NumMicroOps = 8;
1617 let ResourceCycles = [1,1,1,5];
1619 def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
1621 def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1623 let NumMicroOps = 11;
1624 let ResourceCycles = [2,1,1,4,1,2];
1626 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
1628 def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1630 let NumMicroOps = 2;
1631 let ResourceCycles = [1,1,4];
1633 def : SchedAlias<WriteFDiv64Ld, SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair
1635 def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
1637 let NumMicroOps = 1;
1638 let ResourceCycles = [1];
1640 def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1642 def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1644 let NumMicroOps = 2;
1645 let ResourceCycles = [1,1,4];
1647 def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair
1649 def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1651 let NumMicroOps = 8;
1652 let ResourceCycles = [1,1,1,1,1,1,2];
1654 def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
1656 def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
1658 let NumMicroOps = 10;
1659 let ResourceCycles = [1,2,7];
1661 def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
1663 def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1665 let NumMicroOps = 2;
1666 let ResourceCycles = [1,1,8];
1668 def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair
1670 def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1672 let NumMicroOps = 2;
1673 let ResourceCycles = [1,1];
1675 def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
1677 def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1679 let NumMicroOps = 5;
1680 let ResourceCycles = [1,2,1,1];
1682 def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm,
1691 def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1693 let NumMicroOps = 5;
1694 let ResourceCycles = [1,2,1,1];
1696 def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm,
1705 def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1707 let NumMicroOps = 19;
1708 let ResourceCycles = [2,1,4,1,1,4,6];
1710 def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
1712 def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1714 let NumMicroOps = 3;
1715 let ResourceCycles = [1,1,1];
1717 def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
1719 def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1721 let NumMicroOps = 2;
1722 let ResourceCycles = [1,1];
1724 def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
1726 def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
1728 let NumMicroOps = 8;
1729 let ResourceCycles = [2,4,1,1];
1731 def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(8|16|32|64)m")>;
1733 def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1735 let NumMicroOps = 3;
1736 let ResourceCycles = [1,1,1];
1738 def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
1740 def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
1742 let NumMicroOps = 23;
1743 let ResourceCycles = [1,5,3,4,10];
1745 def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
1748 def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1750 let NumMicroOps = 23;
1751 let ResourceCycles = [1,5,2,1,4,10];
1753 def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
1756 def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1758 let NumMicroOps = 31;
1759 let ResourceCycles = [1,8,1,21];
1761 def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
1763 def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
1765 let NumMicroOps = 18;
1766 let ResourceCycles = [1,1,2,3,1,1,1,8];
1768 def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
1770 def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1772 let NumMicroOps = 39;
1773 let ResourceCycles = [1,10,1,1,26];
1775 def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
1777 def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1779 let NumMicroOps = 22;
1780 let ResourceCycles = [2,20];
1782 def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
1784 def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1786 let NumMicroOps = 40;
1787 let ResourceCycles = [1,11,1,1,26];
1789 def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
1790 def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
1792 def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1794 let NumMicroOps = 44;
1795 let ResourceCycles = [1,11,1,1,30];
1797 def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
1799 def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
1801 let NumMicroOps = 64;
1802 let ResourceCycles = [2,8,5,10,39];
1804 def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
1806 def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1808 let NumMicroOps = 88;
1809 let ResourceCycles = [4,4,31,1,2,1,45];
1811 def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
1813 def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1815 let NumMicroOps = 90;
1816 let ResourceCycles = [4,2,33,1,2,1,47];
1818 def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
1820 def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
1822 let NumMicroOps = 15;
1823 let ResourceCycles = [6,3,6];
1825 def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
1827 def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1829 let NumMicroOps = 32;
1830 let ResourceCycles = [7,2,8,3,1,11];
1832 def: InstRW<[SKLWriteResGroup221], (instregex "DIV(16|32|64)r")>;
1834 def SKLWriteResGroup222 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1836 let NumMicroOps = 66;
1837 let ResourceCycles = [4,2,4,8,14,34];
1839 def: InstRW<[SKLWriteResGroup222], (instregex "IDIV(16|32|64)r")>;
1841 def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
1843 let NumMicroOps = 100;
1844 let ResourceCycles = [9,1,11,16,1,11,21,30];
1846 def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
1848 def: InstRW<[WriteZero], (instrs CLC)>;