contrib/llvm/lib/Target/X86/X86SchedSkylakeServer.td

   1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for Skylake Server to support
  11 // instruction scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 def SkylakeServerModel : SchedMachineModel {
  16   // All x86 instructions are modeled as a single micro-op, and SKylake can
  17   // decode 6 instructions per cycle.
  18   let IssueWidth = 6;
  19   let MicroOpBufferSize = 224; // Based on the reorder buffer.
  20   let LoadLatency = 5;
  21   let MispredictPenalty = 14;
  22
  23   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  24   let LoopMicroOpBufferSize = 50;
  25
  26   // This flag is set to allow the scheduler to assign a default model to
  27   // unrecognized opcodes.
  28   let CompleteModel = 0;
  29 }
  30
  31 let SchedModel = SkylakeServerModel in {
  32
  33 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
  34
  35 // Ports 0, 1, 5, and 6 handle all computation.
  36 // Port 4 gets the data half of stores. Store data can be available later than
  37 // the store address, but since we don't model the latency of stores, we can
  38 // ignore that.
  39 // Ports 2 and 3 are identical. They handle loads and the address half of
  40 // stores. Port 7 can handle address calculations.
  41 def SKXPort0 : ProcResource<1>;
  42 def SKXPort1 : ProcResource<1>;
  43 def SKXPort2 : ProcResource<1>;
  44 def SKXPort3 : ProcResource<1>;
  45 def SKXPort4 : ProcResource<1>;
  46 def SKXPort5 : ProcResource<1>;
  47 def SKXPort6 : ProcResource<1>;
  48 def SKXPort7 : ProcResource<1>;
  49
  50 // Many micro-ops are capable of issuing on multiple ports.
  51 def SKXPort01  : ProcResGroup<[SKXPort0, SKXPort1]>;
  52 def SKXPort23  : ProcResGroup<[SKXPort2, SKXPort3]>;
  53 def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>;
  54 def SKXPort04  : ProcResGroup<[SKXPort0, SKXPort4]>;
  55 def SKXPort05  : ProcResGroup<[SKXPort0, SKXPort5]>;
  56 def SKXPort06  : ProcResGroup<[SKXPort0, SKXPort6]>;
  57 def SKXPort15  : ProcResGroup<[SKXPort1, SKXPort5]>;
  58 def SKXPort16  : ProcResGroup<[SKXPort1, SKXPort6]>;
  59 def SKXPort56  : ProcResGroup<[SKXPort5, SKXPort6]>;
  60 def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
  61 def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
  62 def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
  63
  64 def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
  65 // FP division and sqrt on port 0.
  66 def SKXFPDivider : ProcResource<1>;
  67
  68 // 60 Entry Unified Scheduler
  69 def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
  70                               SKXPort5, SKXPort6, SKXPort7]> {
  71   let BufferSize=60;
  72 }
  73
  74 // Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  75 // cycles after the memory operand.
  76 def : ReadAdvance<ReadAfterLd, 5>;
  77
  78 // Many SchedWrites are defined in pairs with and without a folded load.
  79 // Instructions with folded loads are usually micro-fused, so they only appear
  80 // as two micro-ops when queued in the reservation station.
  81 // This multiclass defines the resource usage for variants with and without
  82 // folded loads.
  83 multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
  84                           list<ProcResourceKind> ExePorts,
  85                           int Lat, list<int> Res = [1], int UOps = 1,
  86                           int LoadLat = 5> {
  87   // Register variant is using a single cycle on ExePort.
  88   def : WriteRes<SchedRW, ExePorts> {
  89     let Latency = Lat;
  90     let ResourceCycles = Res;
  91     let NumMicroOps = UOps;
  92   }
  93
  94   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
  95   // the latency (default = 5).
  96   def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
  97     let Latency = !add(Lat, LoadLat);
  98     let ResourceCycles = !listconcat([1], Res);
  99     let NumMicroOps = !add(UOps, 1);
 100   }
 101 }
 102
 103 // A folded store needs a cycle on port 4 for the store data, and an extra port
 104 // 2/3/7 cycle to recompute the address.
 105 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
 106
 107 // Arithmetic.
 108 defm : SKXWriteResPair<WriteALU,    [SKXPort0156], 1>; // Simple integer ALU op.
 109 defm : SKXWriteResPair<WriteADC,    [SKXPort06],   1>; // Integer ALU + flags op.
 110 defm : SKXWriteResPair<WriteIMul,   [SKXPort1],    3>; // Integer multiplication.
 111 defm : SKXWriteResPair<WriteIMul64, [SKXPort1],    3>; // Integer 64-bit multiplication.
 112
 113 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
 114 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
 115
 116 defm : SKXWriteResPair<WriteDiv8,   [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 117 defm : SKXWriteResPair<WriteDiv16,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 118 defm : SKXWriteResPair<WriteDiv32,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 119 defm : SKXWriteResPair<WriteDiv64,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 120 defm : SKXWriteResPair<WriteIDiv8,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 121 defm : SKXWriteResPair<WriteIDiv16, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 122 defm : SKXWriteResPair<WriteIDiv32, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 123 defm : SKXWriteResPair<WriteIDiv64, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 124
 125 defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
 126
 127 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 128 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
 129
 130 defm : SKXWriteResPair<WriteCMOV,  [SKXPort06], 1, [1], 1>; // Conditional move.
 131 defm : SKXWriteResPair<WriteCMOV2, [SKXPort06], 2, [2], 2>; // Conditional (CF + ZF flag) move.
 132 defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move.
 133 def  : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
 134 def  : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
 135   let Latency = 2;
 136   let NumMicroOps = 3;
 137 }
 138 def  : WriteRes<WriteLAHFSAHF, [SKXPort06]>;
 139 def  : WriteRes<WriteBitTest,[SKXPort06]>; //
 140
 141 // Integer shifts and rotates.
 142 defm : SKXWriteResPair<WriteShift, [SKXPort06],  1>;
 143
 144 // SHLD/SHRD.
 145 defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;
 146 defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>;
 147 defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>;
 148 defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>;
 149
 150 // Bit counts.
 151 defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
 152 defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
 153 defm : SKXWriteResPair<WriteLZCNT,          [SKXPort1], 3>;
 154 defm : SKXWriteResPair<WriteTZCNT,          [SKXPort1], 3>;
 155 defm : SKXWriteResPair<WritePOPCNT,         [SKXPort1], 3>;
 156
 157 // BMI1 BEXTR, BMI2 BZHI
 158 defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;
 159 defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>;
 160
 161 // Loads, stores, and moves, not folded with other operations.
 162 defm : X86WriteRes<WriteLoad,    [SKXPort23], 5, [1], 1>;
 163 defm : X86WriteRes<WriteStore,   [SKXPort237, SKXPort4], 1, [1,1], 1>;
 164 defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;
 165 defm : X86WriteRes<WriteMove,    [SKXPort0156], 1, [1], 1>;
 166
 167 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 168 // These can often bypass execution ports completely.
 169 def : WriteRes<WriteZero,  []>;
 170
 171 // Branches don't produce values, so they have no latency, but they still
 172 // consume resources. Indirect branches can fold loads.
 173 defm : SKXWriteResPair<WriteJump,  [SKXPort06],   1>;
 174
 175 // Floating point. This covers both scalar and vector operations.
 176 defm : X86WriteRes<WriteFLD0,          [SKXPort05], 1, [1], 1>;
 177 defm : X86WriteRes<WriteFLD1,          [SKXPort05], 1, [2], 2>;
 178 defm : X86WriteRes<WriteFLDC,          [SKXPort05], 1, [2], 2>;
 179 defm : X86WriteRes<WriteFLoad,         [SKXPort23], 5, [1], 1>;
 180 defm : X86WriteRes<WriteFLoadX,        [SKXPort23], 6, [1], 1>;
 181 defm : X86WriteRes<WriteFLoadY,        [SKXPort23], 7, [1], 1>;
 182 defm : X86WriteRes<WriteFMaskedLoad,   [SKXPort23,SKXPort015], 7, [1,1], 2>;
 183 defm : X86WriteRes<WriteFMaskedLoadY,  [SKXPort23,SKXPort015], 8, [1,1], 2>;
 184 defm : X86WriteRes<WriteFStore,        [SKXPort237,SKXPort4], 1, [1,1], 2>;
 185 defm : X86WriteRes<WriteFStoreX,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 186 defm : X86WriteRes<WriteFStoreY,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 187 defm : X86WriteRes<WriteFStoreNT,      [SKXPort237,SKXPort4], 1, [1,1], 2>;
 188 defm : X86WriteRes<WriteFStoreNTX,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 189 defm : X86WriteRes<WriteFStoreNTY,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 190 defm : X86WriteRes<WriteFMaskedStore,  [SKXPort237,SKXPort0], 2, [1,1], 2>;
 191 defm : X86WriteRes<WriteFMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
 192 defm : X86WriteRes<WriteFMove,         [SKXPort015], 1, [1], 1>;
 193 defm : X86WriteRes<WriteFMoveX,        [SKXPort015], 1, [1], 1>;
 194 defm : X86WriteRes<WriteFMoveY,        [SKXPort015], 1, [1], 1>;
 195 defm : X86WriteRes<WriteEMMS,          [SKXPort05,SKXPort0156], 10, [9,1], 10>;
 196
 197 defm : SKXWriteResPair<WriteFAdd,      [SKXPort01],  4, [1], 1, 5>; // Floating point add/sub.
 198 defm : SKXWriteResPair<WriteFAddX,     [SKXPort01],  4, [1], 1, 6>;
 199 defm : SKXWriteResPair<WriteFAddY,     [SKXPort01],  4, [1], 1, 7>;
 200 defm : SKXWriteResPair<WriteFAddZ,     [SKXPort05],  4, [1], 1, 7>;
 201 defm : SKXWriteResPair<WriteFAdd64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double add/sub.
 202 defm : SKXWriteResPair<WriteFAdd64X,   [SKXPort01],  4, [1], 1, 6>;
 203 defm : SKXWriteResPair<WriteFAdd64Y,   [SKXPort01],  4, [1], 1, 7>;
 204 defm : SKXWriteResPair<WriteFAdd64Z,   [SKXPort05],  4, [1], 1, 7>;
 205
 206 defm : SKXWriteResPair<WriteFCmp,      [SKXPort01],  4, [1], 1, 5>; // Floating point compare.
 207 defm : SKXWriteResPair<WriteFCmpX,     [SKXPort01],  4, [1], 1, 6>;
 208 defm : SKXWriteResPair<WriteFCmpY,     [SKXPort01],  4, [1], 1, 7>;
 209 defm : SKXWriteResPair<WriteFCmpZ,     [SKXPort05],  4, [1], 1, 7>;
 210 defm : SKXWriteResPair<WriteFCmp64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double compare.
 211 defm : SKXWriteResPair<WriteFCmp64X,   [SKXPort01],  4, [1], 1, 6>;
 212 defm : SKXWriteResPair<WriteFCmp64Y,   [SKXPort01],  4, [1], 1, 7>;
 213 defm : SKXWriteResPair<WriteFCmp64Z,   [SKXPort05],  4, [1], 1, 7>;
 214
 215 defm : SKXWriteResPair<WriteFCom,       [SKXPort0],  2>; // Floating point compare to flags.
 216
 217 defm : SKXWriteResPair<WriteFMul,      [SKXPort01],  4, [1], 1, 5>; // Floating point multiplication.
 218 defm : SKXWriteResPair<WriteFMulX,     [SKXPort01],  4, [1], 1, 6>;
 219 defm : SKXWriteResPair<WriteFMulY,     [SKXPort01],  4, [1], 1, 7>;
 220 defm : SKXWriteResPair<WriteFMulZ,     [SKXPort05],  4, [1], 1, 7>;
 221 defm : SKXWriteResPair<WriteFMul64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double multiplication.
 222 defm : SKXWriteResPair<WriteFMul64X,   [SKXPort01],  4, [1], 1, 6>;
 223 defm : SKXWriteResPair<WriteFMul64Y,   [SKXPort01],  4, [1], 1, 7>;
 224 defm : SKXWriteResPair<WriteFMul64Z,   [SKXPort05],  4, [1], 1, 7>;
 225
 226 defm : SKXWriteResPair<WriteFDiv,     [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
 227 //defm : SKXWriteResPair<WriteFDivX,    [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles.
 228 defm : SKXWriteResPair<WriteFDivY,    [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.
 229 defm : SKXWriteResPair<WriteFDivZ,    [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles.
 230 //defm : SKXWriteResPair<WriteFDiv64,   [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
 231 //defm : SKXWriteResPair<WriteFDiv64X,  [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles.
 232 //defm : SKXWriteResPair<WriteFDiv64Y,  [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles.
 233 defm : SKXWriteResPair<WriteFDiv64Z,  [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles.
 234
 235 defm : SKXWriteResPair<WriteFSqrt,    [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
 236 defm : SKXWriteResPair<WriteFSqrtX,   [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>;
 237 defm : SKXWriteResPair<WriteFSqrtY,   [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;
 238 defm : SKXWriteResPair<WriteFSqrtZ,   [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;
 239 defm : SKXWriteResPair<WriteFSqrt64,  [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
 240 defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>;
 241 defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;
 242 defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;
 243 defm : SKXWriteResPair<WriteFSqrt80,  [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root.
 244
 245 defm : SKXWriteResPair<WriteFRcp,   [SKXPort0],  4, [1], 1, 5>; // Floating point reciprocal estimate.
 246 defm : SKXWriteResPair<WriteFRcpX,  [SKXPort0],  4, [1], 1, 6>;
 247 defm : SKXWriteResPair<WriteFRcpY,  [SKXPort0],  4, [1], 1, 7>;
 248 defm : SKXWriteResPair<WriteFRcpZ,  [SKXPort0,SKXPort5],  4, [2,1], 3, 7>;
 249
 250 defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0],  4, [1], 1, 5>; // Floating point reciprocal square root estimate.
 251 defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0],  4, [1], 1, 6>;
 252 defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0],  4, [1], 1, 7>;
 253 defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5],  9, [2,1], 3, 7>;
 254
 255 defm : SKXWriteResPair<WriteFMA,  [SKXPort01],  4, [1], 1, 5>; // Fused Multiply Add.
 256 defm : SKXWriteResPair<WriteFMAX, [SKXPort01],  4, [1], 1, 6>;
 257 defm : SKXWriteResPair<WriteFMAY, [SKXPort01],  4, [1], 1, 7>;
 258 defm : SKXWriteResPair<WriteFMAZ, [SKXPort05],  4, [1], 1, 7>;
 259 defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015],  9, [1,2], 3, 6>; // Floating point double dot product.
 260 defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>;
 261 defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
 262 defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
 263 defm : SKXWriteResPair<WriteFSign,  [SKXPort0],  1>; // Floating point fabs/fchs.
 264 defm : SKXWriteResPair<WriteFRnd,   [SKXPort01], 8, [2], 2, 6>; // Floating point rounding.
 265 defm : SKXWriteResPair<WriteFRndY,  [SKXPort01], 8, [2], 2, 7>;
 266 defm : SKXWriteResPair<WriteFRndZ,  [SKXPort05], 8, [2], 2, 7>;
 267 defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
 268 defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;
 269 defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;
 270 defm : SKXWriteResPair<WriteFTest,  [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
 271 defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;
 272 defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;
 273 defm : SKXWriteResPair<WriteFShuffle,  [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 274 defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;
 275 defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 276 defm : SKXWriteResPair<WriteFVarShuffle,  [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
 277 defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
 278 defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 279 defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends.
 280 defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;
 281 defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;
 282 defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends.
 283 defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;
 284 defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;
 285
 286 // FMA Scheduling helper class.
 287 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 288
 289 // Vector integer operations.
 290 defm : X86WriteRes<WriteVecLoad,         [SKXPort23], 5, [1], 1>;
 291 defm : X86WriteRes<WriteVecLoadX,        [SKXPort23], 6, [1], 1>;
 292 defm : X86WriteRes<WriteVecLoadY,        [SKXPort23], 7, [1], 1>;
 293 defm : X86WriteRes<WriteVecLoadNT,       [SKXPort23], 6, [1], 1>;
 294 defm : X86WriteRes<WriteVecLoadNTY,      [SKXPort23], 7, [1], 1>;
 295 defm : X86WriteRes<WriteVecMaskedLoad,   [SKXPort23,SKXPort015], 7, [1,1], 2>;
 296 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKXPort23,SKXPort015], 8, [1,1], 2>;
 297 defm : X86WriteRes<WriteVecStore,        [SKXPort237,SKXPort4], 1, [1,1], 2>;
 298 defm : X86WriteRes<WriteVecStoreX,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 299 defm : X86WriteRes<WriteVecStoreY,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 300 defm : X86WriteRes<WriteVecStoreNT,      [SKXPort237,SKXPort4], 1, [1,1], 2>;
 301 defm : X86WriteRes<WriteVecStoreNTY,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 302 defm : X86WriteRes<WriteVecMaskedStore,  [SKXPort237,SKXPort0], 2, [1,1], 2>;
 303 defm : X86WriteRes<WriteVecMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
 304 defm : X86WriteRes<WriteVecMove,         [SKXPort05],  1, [1], 1>;
 305 defm : X86WriteRes<WriteVecMoveX,        [SKXPort015], 1, [1], 1>;
 306 defm : X86WriteRes<WriteVecMoveY,        [SKXPort015], 1, [1], 1>;
 307 defm : X86WriteRes<WriteVecMoveToGpr,    [SKXPort0], 2, [1], 1>;
 308 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKXPort5], 1, [1], 1>;
 309
 310 defm : SKXWriteResPair<WriteVecALU,   [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 311 defm : SKXWriteResPair<WriteVecALUX,  [SKXPort01], 1, [1], 1, 6>;
 312 defm : SKXWriteResPair<WriteVecALUY,  [SKXPort01], 1, [1], 1, 7>;
 313 defm : SKXWriteResPair<WriteVecALUZ,  [SKXPort0], 1, [1], 1, 7>;
 314 defm : SKXWriteResPair<WriteVecLogic, [SKXPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
 315 defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>;
 316 defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;
 317 defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;
 318 defm : SKXWriteResPair<WriteVecTest,  [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
 319 defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
 320 defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
 321 defm : SKXWriteResPair<WriteVecIMul,  [SKXPort0],    4, [1], 1, 5>; // Vector integer multiply.
 322 defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01],  4, [1], 1, 6>;
 323 defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01],  4, [1], 1, 7>;
 324 defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05],  4, [1], 1, 7>;
 325 defm : SKXWriteResPair<WritePMULLD,   [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD.
 326 defm : SKXWriteResPair<WritePMULLDY,  [SKXPort01], 10, [2], 2, 7>;
 327 defm : SKXWriteResPair<WritePMULLDZ,  [SKXPort05], 10, [2], 2, 7>;
 328 defm : SKXWriteResPair<WriteShuffle,  [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.
 329 defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>;
 330 defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;
 331 defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 332 defm : SKXWriteResPair<WriteVarShuffle,  [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 333 defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>;
 334 defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
 335 defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 336 defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
 337 defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;
 338 defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;
 339 defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
 340 defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>;
 341 defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05],  2, [1], 1, 6>;
 342 defm : SKXWriteResPair<WriteMPSAD,   [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
 343 defm : SKXWriteResPair<WriteMPSADY,  [SKXPort5], 4, [2], 2, 7>;
 344 defm : SKXWriteResPair<WriteMPSADZ,  [SKXPort5], 4, [2], 2, 7>;
 345 defm : SKXWriteResPair<WritePSADBW,  [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW.
 346 defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>;
 347 defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;
 348 defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>;
 349 defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
 350
 351 // Vector integer shifts.
 352 defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>;
 353 defm : X86WriteRes<WriteVecShiftX,    [SKXPort5,SKXPort01],  2, [1,1], 2>;
 354 defm : X86WriteRes<WriteVecShiftY,    [SKXPort5,SKXPort01],  4, [1,1], 2>;
 355 defm : X86WriteRes<WriteVecShiftZ,    [SKXPort5,SKXPort0],   4, [1,1], 2>;
 356 defm : X86WriteRes<WriteVecShiftXLd,  [SKXPort01,SKXPort23], 7, [1,1], 2>;
 357 defm : X86WriteRes<WriteVecShiftYLd,  [SKXPort01,SKXPort23], 8, [1,1], 2>;
 358 defm : X86WriteRes<WriteVecShiftZLd,  [SKXPort0,SKXPort23],  8, [1,1], 2>;
 359
 360 defm : SKXWriteResPair<WriteVecShiftImm,  [SKXPort0],  1, [1], 1, 5>;
 361 defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts.
 362 defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;
 363 defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;
 364 defm : SKXWriteResPair<WriteVarVecShift,  [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.
 365 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
 366 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
 367
 368 // Vector insert/extract operations.
 369 def : WriteRes<WriteVecInsert, [SKXPort5]> {
 370   let Latency = 2;
 371   let NumMicroOps = 2;
 372   let ResourceCycles = [2];
 373 }
 374 def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
 375   let Latency = 6;
 376   let NumMicroOps = 2;
 377 }
 378 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 379
 380 def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {
 381   let Latency = 3;
 382   let NumMicroOps = 2;
 383 }
 384 def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> {
 385   let Latency = 2;
 386   let NumMicroOps = 3;
 387 }
 388
 389 // Conversion between integer and float.
 390 defm : SKXWriteResPair<WriteCvtSS2I,   [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
 391 defm : SKXWriteResPair<WriteCvtPS2I,   [SKXPort01], 3>;
 392 defm : SKXWriteResPair<WriteCvtPS2IY,  [SKXPort01], 3>;
 393 defm : SKXWriteResPair<WriteCvtPS2IZ,  [SKXPort05], 3>;
 394 defm : SKXWriteResPair<WriteCvtSD2I,   [SKXPort01], 6, [2], 2>;
 395 defm : SKXWriteResPair<WriteCvtPD2I,   [SKXPort01], 3>;
 396 defm : SKXWriteResPair<WriteCvtPD2IY,  [SKXPort01], 3>;
 397 defm : SKXWriteResPair<WriteCvtPD2IZ,  [SKXPort05], 3>;
 398
 399 defm : SKXWriteResPair<WriteCvtI2SS,   [SKXPort1], 4>;
 400 defm : SKXWriteResPair<WriteCvtI2PS,   [SKXPort01], 4>;
 401 defm : SKXWriteResPair<WriteCvtI2PSY,  [SKXPort01], 4>;
 402 defm : SKXWriteResPair<WriteCvtI2PSZ,  [SKXPort05], 4>;  // Needs more work: DD vs DQ.
 403 defm : SKXWriteResPair<WriteCvtI2SD,   [SKXPort1], 4>;
 404 defm : SKXWriteResPair<WriteCvtI2PD,   [SKXPort01], 4>;
 405 defm : SKXWriteResPair<WriteCvtI2PDY,  [SKXPort01], 4>;
 406 defm : SKXWriteResPair<WriteCvtI2PDZ,  [SKXPort05], 4>;
 407
 408 defm : SKXWriteResPair<WriteCvtSS2SD,  [SKXPort1], 3>;
 409 defm : SKXWriteResPair<WriteCvtPS2PD,  [SKXPort1], 3>;
 410 defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
 411 defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>;
 412 defm : SKXWriteResPair<WriteCvtSD2SS,  [SKXPort1], 3>;
 413 defm : SKXWriteResPair<WriteCvtPD2PS,  [SKXPort1], 3>;
 414 defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
 415 defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>;
 416
 417 defm : X86WriteRes<WriteCvtPH2PS,     [SKXPort5,SKXPort01],  5, [1,1], 2>;
 418 defm : X86WriteRes<WriteCvtPH2PSY,    [SKXPort5,SKXPort01],  7, [1,1], 2>;
 419 defm : X86WriteRes<WriteCvtPH2PSZ,    [SKXPort5,SKXPort0],   7, [1,1], 2>;
 420 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKXPort23,SKXPort01],  9, [1,1], 2>;
 421 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>;
 422 defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>;
 423
 424 defm : X86WriteRes<WriteCvtPS2PH,    [SKXPort5,SKXPort01], 5, [1,1], 2>;
 425 defm : X86WriteRes<WriteCvtPS2PHY,   [SKXPort5,SKXPort01], 7, [1,1], 2>;
 426 defm : X86WriteRes<WriteCvtPS2PHZ,   [SKXPort5,SKXPort05], 7, [1,1], 2>;
 427 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>;
 428 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>;
 429 defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;
 430
 431 // Strings instructions.
 432
 433 // Packed Compare Implicit Length Strings, Return Mask
 434 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
 435   let Latency = 10;
 436   let NumMicroOps = 3;
 437   let ResourceCycles = [3];
 438 }
 439 def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
 440   let Latency = 16;
 441   let NumMicroOps = 4;
 442   let ResourceCycles = [3,1];
 443 }
 444
 445 // Packed Compare Explicit Length Strings, Return Mask
 446 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
 447   let Latency = 19;
 448   let NumMicroOps = 9;
 449   let ResourceCycles = [4,3,1,1];
 450 }
 451 def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
 452   let Latency = 25;
 453   let NumMicroOps = 10;
 454   let ResourceCycles = [4,3,1,1,1];
 455 }
 456
 457 // Packed Compare Implicit Length Strings, Return Index
 458 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
 459   let Latency = 10;
 460   let NumMicroOps = 3;
 461   let ResourceCycles = [3];
 462 }
 463 def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
 464   let Latency = 16;
 465   let NumMicroOps = 4;
 466   let ResourceCycles = [3,1];
 467 }
 468
 469 // Packed Compare Explicit Length Strings, Return Index
 470 def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
 471   let Latency = 18;
 472   let NumMicroOps = 8;
 473   let ResourceCycles = [4,3,1];
 474 }
 475 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
 476   let Latency = 24;
 477   let NumMicroOps = 9;
 478   let ResourceCycles = [4,3,1,1];
 479 }
 480
 481 // MOVMSK Instructions.
 482 def : WriteRes<WriteFMOVMSK,    [SKXPort0]> { let Latency = 2; }
 483 def : WriteRes<WriteVecMOVMSK,  [SKXPort0]> { let Latency = 2; }
 484 def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }
 485 def : WriteRes<WriteMMXMOVMSK,  [SKXPort0]> { let Latency = 2; }
 486
 487 // AES instructions.
 488 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
 489   let Latency = 4;
 490   let NumMicroOps = 1;
 491   let ResourceCycles = [1];
 492 }
 493 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
 494   let Latency = 10;
 495   let NumMicroOps = 2;
 496   let ResourceCycles = [1,1];
 497 }
 498
 499 def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
 500   let Latency = 8;
 501   let NumMicroOps = 2;
 502   let ResourceCycles = [2];
 503 }
 504 def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
 505   let Latency = 14;
 506   let NumMicroOps = 3;
 507   let ResourceCycles = [2,1];
 508 }
 509
 510 def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
 511   let Latency = 20;
 512   let NumMicroOps = 11;
 513   let ResourceCycles = [3,6,2];
 514 }
 515 def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
 516   let Latency = 25;
 517   let NumMicroOps = 11;
 518   let ResourceCycles = [3,6,1,1];
 519 }
 520
 521 // Carry-less multiplication instructions.
 522 def : WriteRes<WriteCLMul, [SKXPort5]> {
 523   let Latency = 6;
 524   let NumMicroOps = 1;
 525   let ResourceCycles = [1];
 526 }
 527 def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
 528   let Latency = 12;
 529   let NumMicroOps = 2;
 530   let ResourceCycles = [1,1];
 531 }
 532
 533 // Catch-all for expensive system instructions.
 534 def : WriteRes<WriteSystem,     [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 535
 536 // AVX2.
 537 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 538 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 539 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 540 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 541
 542 // Old microcoded instructions that nobody use.
 543 def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 544
 545 // Fence instructions.
 546 def : WriteRes<WriteFence,  [SKXPort23, SKXPort4]>;
 547
 548 // Load/store MXCSR.
 549 def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 550 def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 551
 552 // Nop, not very useful expect it provides a model for nops!
 553 def : WriteRes<WriteNop, []>;
 554
 555 ////////////////////////////////////////////////////////////////////////////////
 556 // Horizontal add/sub  instructions.
 557 ////////////////////////////////////////////////////////////////////////////////
 558
 559 defm : SKXWriteResPair<WriteFHAdd,  [SKXPort5,SKXPort015], 6, [2,1], 3, 6>;
 560 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>;
 561 defm : SKXWriteResPair<WritePHAdd,  [SKXPort5,SKXPort05],  3, [2,1], 3, 5>;
 562 defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;
 563 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
 564
 565 // Remaining instrs.
 566
 567 def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
 568   let Latency = 1;
 569   let NumMicroOps = 1;
 570   let ResourceCycles = [1];
 571 }
 572 def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
 573                                             "KANDN(B|D|Q|W)rr",
 574                                             "KMOV(B|D|Q|W)kk",
 575                                             "KNOT(B|D|Q|W)rr",
 576                                             "KOR(B|D|Q|W)rr",
 577                                             "KXNOR(B|D|Q|W)rr",
 578                                             "KXOR(B|D|Q|W)rr",
 579                                             "MMX_PADDS(B|W)irr",
 580                                             "MMX_PADDUS(B|W)irr",
 581                                             "MMX_PAVG(B|W)irr",
 582                                             "MMX_PCMPEQ(B|D|W)irr",
 583                                             "MMX_PCMPGT(B|D|W)irr",
 584                                             "MMX_P(MAX|MIN)SWirr",
 585                                             "MMX_P(MAX|MIN)UBirr",
 586                                             "MMX_PSUBS(B|W)irr",
 587                                             "MMX_PSUBUS(B|W)irr",
 588                                             "VPMOVB2M(Z|Z128|Z256)rr",
 589                                             "VPMOVD2M(Z|Z128|Z256)rr",
 590                                             "VPMOVQ2M(Z|Z128|Z256)rr",
 591                                             "VPMOVW2M(Z|Z128|Z256)rr")>;
 592
 593 def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
 594   let Latency = 1;
 595   let NumMicroOps = 1;
 596   let ResourceCycles = [1];
 597 }
 598 def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
 599                                             "KMOV(B|D|Q|W)kr",
 600                                             "UCOM_F(P?)r")>;
 601
 602 def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
 603   let Latency = 1;
 604   let NumMicroOps = 1;
 605   let ResourceCycles = [1];
 606 }
 607 def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 608
 609 def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
 610   let Latency = 1;
 611   let NumMicroOps = 1;
 612   let ResourceCycles = [1];
 613 }
 614 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
 615
 616 def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
 617   let Latency = 1;
 618   let NumMicroOps = 1;
 619   let ResourceCycles = [1];
 620 }
 621 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 622
 623 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
 624   let Latency = 1;
 625   let NumMicroOps = 1;
 626   let ResourceCycles = [1];
 627 }
 628 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr",
 629                                             "BLSI(32|64)rr",
 630                                             "BLSMSK(32|64)rr",
 631                                             "BLSR(32|64)rr")>;
 632
 633 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
 634   let Latency = 1;
 635   let NumMicroOps = 1;
 636   let ResourceCycles = [1];
 637 }
 638 def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
 639                                             "VBLENDMPS(Z128|Z256)rr",
 640                                             "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
 641                                             "(V?)PADD(B|D|Q|W)rr",
 642                                             "VPBLENDD(Y?)rri",
 643                                             "VPBLENDMB(Z128|Z256)rr",
 644                                             "VPBLENDMD(Z128|Z256)rr",
 645                                             "VPBLENDMQ(Z128|Z256)rr",
 646                                             "VPBLENDMW(Z128|Z256)rr",
 647                                             "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rr",
 648                                             "(V?)PSUB(B|D|Q|W)rr",
 649                                             "VPTERNLOGD(Z|Z128|Z256)rri",
 650                                             "VPTERNLOGQ(Z|Z128|Z256)rri")>;
 651
 652 def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
 653   let Latency = 1;
 654   let NumMicroOps = 1;
 655   let ResourceCycles = [1];
 656 }
 657 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
 658                                           CMC, STC)>;
 659 def: InstRW<[SKXWriteResGroup10], (instregex "SGDT64m",
 660                                              "SIDT64m",
 661                                              "SMSW16m",
 662                                              "STRm",
 663                                              "SYSCALL")>;
 664
 665 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
 666   let Latency = 1;
 667   let NumMicroOps = 2;
 668   let ResourceCycles = [1,1];
 669 }
 670 def: InstRW<[SKXWriteResGroup11], (instregex "FBSTPm",
 671                                              "KMOV(B|D|Q|W)mk",
 672                                              "ST_FP(32|64|80)m",
 673                                              "VMPTRSTm")>;
 674
 675 def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
 676   let Latency = 2;
 677   let NumMicroOps = 2;
 678   let ResourceCycles = [2];
 679 }
 680 def: InstRW<[SKXWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>;
 681
 682 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
 683   let Latency = 2;
 684   let NumMicroOps = 2;
 685   let ResourceCycles = [2];
 686 }
 687 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP)>;
 688 def: InstRW<[SKXWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>;
 689
 690 def SKXWriteResGroup15 : SchedWriteRes<[SKXPort06]> {
 691   let Latency = 2;
 692   let NumMicroOps = 2;
 693   let ResourceCycles = [2];
 694 }
 695 def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)r1",
 696                                              "ROL(8|16|32|64)ri",
 697                                              "ROR(8|16|32|64)r1",
 698                                              "ROR(8|16|32|64)ri",
 699                                              "SET(A|BE)r")>;
 700
 701 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
 702   let Latency = 2;
 703   let NumMicroOps = 2;
 704   let ResourceCycles = [2];
 705 }
 706 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
 707                                           WAIT,
 708                                           XGETBV)>;
 709
 710 def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
 711   let Latency = 2;
 712   let NumMicroOps = 2;
 713   let ResourceCycles = [1,1];
 714 }
 715 def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
 716
 717 def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
 718   let Latency = 2;
 719   let NumMicroOps = 2;
 720   let ResourceCycles = [1,1];
 721 }
 722 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
 723
 724 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
 725   let Latency = 2;
 726   let NumMicroOps = 2;
 727   let ResourceCycles = [1,1];
 728 }
 729 def: InstRW<[SKXWriteResGroup23], (instrs CWD)>;
 730 def: InstRW<[SKXWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>;
 731 def: InstRW<[SKXWriteResGroup23], (instregex "ADC8i8",
 732                                              "ADC8ri",
 733                                              "SBB8i8",
 734                                              "SBB8ri")>;
 735
 736 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
 737   let Latency = 2;
 738   let NumMicroOps = 3;
 739   let ResourceCycles = [1,1,1];
 740 }
 741 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
 742
 743 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
 744   let Latency = 2;
 745   let NumMicroOps = 3;
 746   let ResourceCycles = [1,1,1];
 747 }
 748 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 749
 750 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
 751   let Latency = 2;
 752   let NumMicroOps = 3;
 753   let ResourceCycles = [1,1,1];
 754 }
 755 def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r,
 756                                           STOSB, STOSL, STOSQ, STOSW)>;
 757 def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr",
 758                                              "PUSH64i8")>;
 759
 760 def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
 761   let Latency = 2;
 762   let NumMicroOps = 5;
 763   let ResourceCycles = [2,2,1];
 764 }
 765 def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
 766
 767 def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
 768   let Latency = 3;
 769   let NumMicroOps = 1;
 770   let ResourceCycles = [1];
 771 }
 772 def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
 773                                              "KORTEST(B|D|Q|W)rr",
 774                                              "KTEST(B|D|Q|W)rr")>;
 775
 776 def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
 777   let Latency = 3;
 778   let NumMicroOps = 1;
 779   let ResourceCycles = [1];
 780 }
 781 def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
 782                                              "PEXT(32|64)rr")>;
 783
 784 def SKXWriteResGroup31_16i : SchedWriteRes<[SKXPort1, SKXPort0156]> {
 785   let Latency = 4;
 786   let NumMicroOps = 2;
 787   let ResourceCycles = [1,1];
 788 }
 789 def: InstRW<[SKXWriteResGroup31_16i], (instrs IMUL16rri, IMUL16rri8)>;
 790
 791
 792 def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
 793   let Latency = 3;
 794   let NumMicroOps = 1;
 795   let ResourceCycles = [1];
 796 }
 797 def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
 798                                              "KADD(B|D|Q|W)rr",
 799                                              "KSHIFTL(B|D|Q|W)ri",
 800                                              "KSHIFTR(B|D|Q|W)ri",
 801                                              "KUNPCKBWrr",
 802                                              "KUNPCKDQrr",
 803                                              "KUNPCKWDrr",
 804                                              "VALIGND(Z|Z128|Z256)rri",
 805                                              "VALIGNQ(Z|Z128|Z256)rri",
 806                                              "VCMPPD(Z|Z128|Z256)rri",
 807                                              "VCMPPS(Z|Z128|Z256)rri",
 808                                              "VCMPSDZrr",
 809                                              "VCMPSSZrr",
 810                                              "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined.
 811                                              "VFPCLASSPD(Z|Z128|Z256)rr",
 812                                              "VFPCLASSPS(Z|Z128|Z256)rr",
 813                                              "VFPCLASSSDZrr",
 814                                              "VFPCLASSSSZrr",
 815                                              "VPBROADCASTBrr",
 816                                              "VPBROADCASTWrr",
 817                                              "VPCMPB(Z|Z128|Z256)rri",
 818                                              "VPCMPD(Z|Z128|Z256)rri",
 819                                              "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
 820                                              "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
 821                                              "(V?)PCMPGTQ(Y?)rr",
 822                                              "VPCMPQ(Z|Z128|Z256)rri",
 823                                              "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
 824                                              "VPCMPW(Z|Z128|Z256)rri",
 825                                              "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr",
 826                                              "VPSADBWZrr", // TODO: 512-bit ops require ports 0/1 to be joined.
 827                                              "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
 828
 829 def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
 830   let Latency = 3;
 831   let NumMicroOps = 2;
 832   let ResourceCycles = [1,1];
 833 }
 834 def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
 835
 836 def SKXWriteResGroup35 : SchedWriteRes<[SKXPort06]> {
 837   let Latency = 3;
 838   let NumMicroOps = 3;
 839   let ResourceCycles = [3];
 840 }
 841 def: InstRW<[SKXWriteResGroup35], (instregex "ROL(8|16|32|64)rCL",
 842                                              "ROR(8|16|32|64)rCL",
 843                                              "SAR(8|16|32|64)rCL",
 844                                              "SHL(8|16|32|64)rCL",
 845                                              "SHR(8|16|32|64)rCL")>;
 846
 847 def SKXWriteResGroup36 : SchedWriteRes<[SKXPort0156]> {
 848   let Latency = 2;
 849   let NumMicroOps = 3;
 850   let ResourceCycles = [3];
 851 }
 852 def: InstRW<[SKXWriteResGroup36], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr,
 853                                           XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr,
 854                                           XCHG16ar, XCHG32ar, XCHG64ar)>;
 855
 856 def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
 857   let Latency = 3;
 858   let NumMicroOps = 3;
 859   let ResourceCycles = [1,2];
 860 }
 861 def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 862
 863 def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
 864   let Latency = 3;
 865   let NumMicroOps = 3;
 866   let ResourceCycles = [2,1];
 867 }
 868 def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
 869
 870 def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
 871   let Latency = 3;
 872   let NumMicroOps = 3;
 873   let ResourceCycles = [2,1];
 874 }
 875 def: InstRW<[SKXWriteResGroup41], (instregex "MMX_PACKSSDWirr",
 876                                              "MMX_PACKSSWBirr",
 877                                              "MMX_PACKUSWBirr")>;
 878
 879 def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
 880   let Latency = 3;
 881   let NumMicroOps = 3;
 882   let ResourceCycles = [1,2];
 883 }
 884 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
 885
 886 def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
 887   let Latency = 3;
 888   let NumMicroOps = 3;
 889   let ResourceCycles = [1,2];
 890 }
 891 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
 892
 893 def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
 894   let Latency = 3;
 895   let NumMicroOps = 3;
 896   let ResourceCycles = [1,2];
 897 }
 898 def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r1",
 899                                              "RCL(8|16|32|64)ri",
 900                                              "RCR(8|16|32|64)r1",
 901                                              "RCR(8|16|32|64)ri")>;
 902
 903 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
 904   let Latency = 3;
 905   let NumMicroOps = 3;
 906   let ResourceCycles = [1,1,1];
 907 }
 908 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
 909
 910 def SKXWriteResGroup46 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
 911   let Latency = 3;
 912   let NumMicroOps = 4;
 913   let ResourceCycles = [1,1,2];
 914 }
 915 def: InstRW<[SKXWriteResGroup46], (instregex "SET(A|BE)m")>;
 916
 917 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
 918   let Latency = 3;
 919   let NumMicroOps = 4;
 920   let ResourceCycles = [1,1,1,1];
 921 }
 922 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
 923
 924 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
 925   let Latency = 3;
 926   let NumMicroOps = 4;
 927   let ResourceCycles = [1,1,1,1];
 928 }
 929 def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
 930
 931 def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
 932   let Latency = 4;
 933   let NumMicroOps = 1;
 934   let ResourceCycles = [1];
 935 }
 936 def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 937
 938 def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
 939   let Latency = 4;
 940   let NumMicroOps = 1;
 941   let ResourceCycles = [1];
 942 }
 943 def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr",
 944                                              "(V?)CVTDQ2PSrr",
 945                                              "VCVTPD2QQ(Z128|Z256)rr",
 946                                              "VCVTPD2UQQ(Z128|Z256)rr",
 947                                              "VCVTPS2DQ(Y|Z128|Z256)rr",
 948                                              "(V?)CVTPS2DQrr",
 949                                              "VCVTPS2UDQ(Z128|Z256)rr",
 950                                              "VCVTQQ2PD(Z128|Z256)rr",
 951                                              "VCVTTPD2QQ(Z128|Z256)rr",
 952                                              "VCVTTPD2UQQ(Z128|Z256)rr",
 953                                              "VCVTTPS2DQ(Z128|Z256)rr",
 954                                              "(V?)CVTTPS2DQrr",
 955                                              "VCVTTPS2UDQ(Z128|Z256)rr",
 956                                              "VCVTUDQ2PS(Z128|Z256)rr",
 957                                              "VCVTUQQ2PD(Z128|Z256)rr")>;
 958
 959 def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
 960   let Latency = 4;
 961   let NumMicroOps = 1;
 962   let ResourceCycles = [1];
 963 }
 964 def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
 965                                            VCVTPD2QQZrr,
 966                                            VCVTPD2UQQZrr,
 967                                            VCVTPS2DQZrr,
 968                                            VCVTPS2UDQZrr,
 969                                            VCVTQQ2PDZrr,
 970                                            VCVTTPD2QQZrr,
 971                                            VCVTTPD2UQQZrr,
 972                                            VCVTTPS2DQZrr,
 973                                            VCVTTPS2UDQZrr,
 974                                            VCVTUDQ2PSZrr,
 975                                            VCVTUQQ2PDZrr)>;
 976
 977 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
 978   let Latency = 4;
 979   let NumMicroOps = 2;
 980   let ResourceCycles = [2];
 981 }
 982 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
 983                                              "VEXPANDPS(Z|Z128|Z256)rr",
 984                                              "VPEXPANDD(Z|Z128|Z256)rr",
 985                                              "VPEXPANDQ(Z|Z128|Z256)rr",
 986                                              "VPMOVDB(Z|Z128|Z256)rr",
 987                                              "VPMOVDW(Z|Z128|Z256)rr",
 988                                              "VPMOVQB(Z|Z128|Z256)rr",
 989                                              "VPMOVQW(Z|Z128|Z256)rr",
 990                                              "VPMOVSDB(Z|Z128|Z256)rr",
 991                                              "VPMOVSDW(Z|Z128|Z256)rr",
 992                                              "VPMOVSQB(Z|Z128|Z256)rr",
 993                                              "VPMOVSQD(Z|Z128|Z256)rr",
 994                                              "VPMOVSQW(Z|Z128|Z256)rr",
 995                                              "VPMOVSWB(Z|Z128|Z256)rr",
 996                                              "VPMOVUSDB(Z|Z128|Z256)rr",
 997                                              "VPMOVUSDW(Z|Z128|Z256)rr",
 998                                              "VPMOVUSQB(Z|Z128|Z256)rr",
 999                                              "VPMOVUSQD(Z|Z128|Z256)rr",
1000                                              "VPMOVUSWB(Z|Z128|Z256)rr",
1001                                              "VPMOVWB(Z|Z128|Z256)rr")>;
1002
1003 def SKXWriteResGroup52 : SchedWriteRes<[SKXPort1,SKXPort5]> {
1004   let Latency = 4;
1005   let NumMicroOps = 2;
1006   let ResourceCycles = [1,1];
1007 }
1008 def: InstRW<[SKXWriteResGroup52], (instrs IMUL64r, MUL64r, MULX64rr)>;
1009
1010 def SKXWriteResGroup52_16 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1011   let Latency = 4;
1012   let NumMicroOps = 4;
1013   let ResourceCycles = [1,1,2];
1014 }
1015 def: InstRW<[SKXWriteResGroup52_16], (instrs IMUL16r, MUL16r)>;
1016
1017 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1018   let Latency = 4;
1019   let NumMicroOps = 3;
1020   let ResourceCycles = [1,1,1];
1021 }
1022 def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
1023                                              "IST_F(16|32)m",
1024                                              "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
1025
1026 def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
1027   let Latency = 4;
1028   let NumMicroOps = 4;
1029   let ResourceCycles = [4];
1030 }
1031 def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
1032
1033 def SKXWriteResGroup56 : SchedWriteRes<[SKXPort015,SKXPort0156]> {
1034   let Latency = 4;
1035   let NumMicroOps = 4;
1036   let ResourceCycles = [1,3];
1037 }
1038 def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
1039
1040 def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
1041   let Latency = 4;
1042   let NumMicroOps = 4;
1043   let ResourceCycles = [1,1,2];
1044 }
1045 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1046
1047 def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> {
1048   let Latency = 5;
1049   let NumMicroOps = 1;
1050   let ResourceCycles = [1];
1051 }
1052 def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm16",
1053                                              "MOVSX(16|32|64)rm32",
1054                                              "MOVSX(16|32|64)rm8",
1055                                              "MOVZX(16|32|64)rm16",
1056                                              "MOVZX(16|32|64)rm8",
1057                                              "(V?)MOVDDUPrm")>;  // TODO: Should this be SKXWriteResGroup71?
1058
1059 def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1060   let Latency = 5;
1061   let NumMicroOps = 2;
1062   let ResourceCycles = [1,1];
1063 }
1064 def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr",
1065                                              "MMX_CVT(T?)PS2PIirr",
1066                                              "VCVTDQ2PDZ128rr",
1067                                              "VCVTPD2DQZ128rr",
1068                                              "(V?)CVT(T?)PD2DQrr",
1069                                              "VCVTPD2PSZ128rr",
1070                                              "(V?)CVTPD2PSrr",
1071                                              "VCVTPD2UDQZ128rr",
1072                                              "VCVTPS2PDZ128rr",
1073                                              "(V?)CVTPS2PDrr",
1074                                              "VCVTPS2QQZ128rr",
1075                                              "VCVTPS2UQQZ128rr",
1076                                              "VCVTQQ2PSZ128rr",
1077                                              "(V?)CVTSD2SS(Z?)rr",
1078                                              "(V?)CVTSI(64)?2SDrr",
1079                                              "VCVTSI2SSZrr",
1080                                              "(V?)CVTSI2SSrr",
1081                                              "VCVTSI(64)?2SDZrr",
1082                                              "VCVTSS2SDZrr",
1083                                              "(V?)CVTSS2SDrr",
1084                                              "VCVTTPD2DQZ128rr",
1085                                              "VCVTTPD2UDQZ128rr",
1086                                              "VCVTTPS2QQZ128rr",
1087                                              "VCVTTPS2UQQZ128rr",
1088                                              "VCVTUDQ2PDZ128rr",
1089                                              "VCVTUQQ2PSZ128rr",
1090                                              "VCVTUSI2SSZrr",
1091                                              "VCVTUSI(64)?2SDZrr")>;
1092
1093 def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1094   let Latency = 5;
1095   let NumMicroOps = 3;
1096   let ResourceCycles = [2,1];
1097 }
1098 def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
1099
1100 def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
1101   let Latency = 5;
1102   let NumMicroOps = 3;
1103   let ResourceCycles = [1,1,1];
1104 }
1105 def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
1106
1107 def SKXWriteResGroup64 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1108   let Latency = 4;
1109   let NumMicroOps = 3;
1110   let ResourceCycles = [1,1,1];
1111 }
1112 def: InstRW<[SKXWriteResGroup64], (instrs IMUL32r, MUL32r, MULX32rr)>;
1113
1114 def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> {
1115   let Latency = 5;
1116   let NumMicroOps = 3;
1117   let ResourceCycles = [1,1,1];
1118 }
1119 def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
1120                                              "VCVTPS2PHZ256mr(b?)",
1121                                              "VCVTPS2PHZmr(b?)")>;
1122
1123 def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1124   let Latency = 5;
1125   let NumMicroOps = 4;
1126   let ResourceCycles = [1,2,1];
1127 }
1128 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
1129                                              "VPMOVDW(Z|Z128|Z256)mr(b?)",
1130                                              "VPMOVQB(Z|Z128|Z256)mr(b?)",
1131                                              "VPMOVQW(Z|Z128|Z256)mr(b?)",
1132                                              "VPMOVSDB(Z|Z128|Z256)mr(b?)",
1133                                              "VPMOVSDW(Z|Z128|Z256)mr(b?)",
1134                                              "VPMOVSQB(Z|Z128|Z256)mr(b?)",
1135                                              "VPMOVSQD(Z|Z128|Z256)mr(b?)",
1136                                              "VPMOVSQW(Z|Z128|Z256)mr(b?)",
1137                                              "VPMOVSWB(Z|Z128|Z256)mr(b?)",
1138                                              "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
1139                                              "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
1140                                              "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
1141                                              "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
1142                                              "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
1143                                              "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
1144                                              "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
1145
1146 def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1147   let Latency = 5;
1148   let NumMicroOps = 5;
1149   let ResourceCycles = [1,4];
1150 }
1151 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
1152
1153 def SKXWriteResGroup68 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1154   let Latency = 5;
1155   let NumMicroOps = 5;
1156   let ResourceCycles = [2,3];
1157 }
1158 def: InstRW<[SKXWriteResGroup68], (instregex "CMPXCHG(8|16|32|64)rr")>;
1159
1160 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
1161   let Latency = 5;
1162   let NumMicroOps = 6;
1163   let ResourceCycles = [1,1,4];
1164 }
1165 def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
1166
1167 def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
1168   let Latency = 6;
1169   let NumMicroOps = 1;
1170   let ResourceCycles = [1];
1171 }
1172 def: InstRW<[SKXWriteResGroup71], (instregex "VBROADCASTSSrm",
1173                                              "(V?)MOVSHDUPrm",
1174                                              "(V?)MOVSLDUPrm",
1175                                              "VPBROADCASTDrm",
1176                                              "VPBROADCASTQrm")>;
1177
1178 def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
1179   let Latency = 6;
1180   let NumMicroOps = 2;
1181   let ResourceCycles = [2];
1182 }
1183 def: InstRW<[SKXWriteResGroup72], (instregex "MMX_CVTPI2PSirr",
1184                                              "VCOMPRESSPD(Z|Z128|Z256)rr",
1185                                              "VCOMPRESSPS(Z|Z128|Z256)rr",
1186                                              "VPCOMPRESSD(Z|Z128|Z256)rr",
1187                                              "VPCOMPRESSQ(Z|Z128|Z256)rr",
1188                                              "VPERMW(Z|Z128|Z256)rr")>;
1189
1190 def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1191   let Latency = 6;
1192   let NumMicroOps = 2;
1193   let ResourceCycles = [1,1];
1194 }
1195 def: InstRW<[SKXWriteResGroup73], (instregex "MMX_PADDSBirm",
1196                                              "MMX_PADDSWirm",
1197                                              "MMX_PADDUSBirm",
1198                                              "MMX_PADDUSWirm",
1199                                              "MMX_PAVGBirm",
1200                                              "MMX_PAVGWirm",
1201                                              "MMX_PCMPEQBirm",
1202                                              "MMX_PCMPEQDirm",
1203                                              "MMX_PCMPEQWirm",
1204                                              "MMX_PCMPGTBirm",
1205                                              "MMX_PCMPGTDirm",
1206                                              "MMX_PCMPGTWirm",
1207                                              "MMX_PMAXSWirm",
1208                                              "MMX_PMAXUBirm",
1209                                              "MMX_PMINSWirm",
1210                                              "MMX_PMINUBirm",
1211                                              "MMX_PSUBSBirm",
1212                                              "MMX_PSUBSWirm",
1213                                              "MMX_PSUBUSBirm",
1214                                              "MMX_PSUBUSWirm")>;
1215
1216 def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
1217   let Latency = 6;
1218   let NumMicroOps = 2;
1219   let ResourceCycles = [1,1];
1220 }
1221 def: InstRW<[SKXWriteResGroup76], (instregex "FARJMP64",
1222                                              "JMP(16|32|64)m")>;
1223
1224 def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> {
1225   let Latency = 6;
1226   let NumMicroOps = 2;
1227   let ResourceCycles = [1,1];
1228 }
1229 def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>;
1230
1231 def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
1232   let Latency = 6;
1233   let NumMicroOps = 2;
1234   let ResourceCycles = [1,1];
1235 }
1236 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
1237                                              "BLSI(32|64)rm",
1238                                              "BLSMSK(32|64)rm",
1239                                              "BLSR(32|64)rm",
1240                                              "MOVBE(16|32|64)rm")>;
1241
1242 def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1243   let Latency = 6;
1244   let NumMicroOps = 2;
1245   let ResourceCycles = [1,1];
1246 }
1247 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)",
1248                                              "VMOVDI2PDIZrm(b?)")>;
1249
1250 def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1251   let Latency = 6;
1252   let NumMicroOps = 2;
1253   let ResourceCycles = [1,1];
1254 }
1255 def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
1256 def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
1257
1258 def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1259   let Latency = 6;
1260   let NumMicroOps = 3;
1261   let ResourceCycles = [2,1];
1262 }
1263 def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
1264                                              "VCVTSI642SSZrr",
1265                                              "VCVTUSI642SSZrr")>;
1266
1267 def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
1268   let Latency = 6;
1269   let NumMicroOps = 4;
1270   let ResourceCycles = [1,1,1,1];
1271 }
1272 def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
1273
1274 def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1275   let Latency = 6;
1276   let NumMicroOps = 4;
1277   let ResourceCycles = [1,1,1,1];
1278 }
1279 def: InstRW<[SKXWriteResGroup86], (instregex "BTC(16|32|64)mi8",
1280                                              "BTR(16|32|64)mi8",
1281                                              "BTS(16|32|64)mi8",
1282                                              "SAR(8|16|32|64)m1",
1283                                              "SAR(8|16|32|64)mi",
1284                                              "SHL(8|16|32|64)m1",
1285                                              "SHL(8|16|32|64)mi",
1286                                              "SHR(8|16|32|64)m1",
1287                                              "SHR(8|16|32|64)mi")>;
1288
1289 def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1290   let Latency = 6;
1291   let NumMicroOps = 4;
1292   let ResourceCycles = [1,1,1,1];
1293 }
1294 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
1295                                              "PUSH(16|32|64)rmm")>;
1296
1297 def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
1298   let Latency = 6;
1299   let NumMicroOps = 6;
1300   let ResourceCycles = [1,5];
1301 }
1302 def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
1303
1304 def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
1305   let Latency = 7;
1306   let NumMicroOps = 1;
1307   let ResourceCycles = [1];
1308 }
1309 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m",
1310                                              "VBROADCASTF128",
1311                                              "VBROADCASTI128",
1312                                              "VBROADCASTSDYrm",
1313                                              "VBROADCASTSSYrm",
1314                                              "VMOVDDUPYrm",
1315                                              "VMOVSHDUPYrm",
1316                                              "VMOVSLDUPYrm",
1317                                              "VPBROADCASTDYrm",
1318                                              "VPBROADCASTQYrm")>;
1319
1320 def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
1321   let Latency = 7;
1322   let NumMicroOps = 2;
1323   let ResourceCycles = [1,1];
1324 }
1325 def: InstRW<[SKXWriteResGroup90], (instregex "VCVTDQ2PDYrr")>;
1326
1327 def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1328   let Latency = 7;
1329   let NumMicroOps = 2;
1330   let ResourceCycles = [1,1];
1331 }
1332 def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
1333                                              "VMOVSSZrm(b?)")>;
1334
1335 def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
1336   let Latency = 6;
1337   let NumMicroOps = 2;
1338   let ResourceCycles = [1,1];
1339 }
1340 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
1341                                               "(V?)PMOV(SX|ZX)BQrm",
1342                                               "(V?)PMOV(SX|ZX)BWrm",
1343                                               "(V?)PMOV(SX|ZX)DQrm",
1344                                               "(V?)PMOV(SX|ZX)WDrm",
1345                                               "(V?)PMOV(SX|ZX)WQrm")>;
1346
1347 def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1348   let Latency = 7;
1349   let NumMicroOps = 2;
1350   let ResourceCycles = [1,1];
1351 }
1352 def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
1353                                              "VCVTPD2DQ(Y|Z256)rr",
1354                                              "VCVTPD2PS(Y|Z256)rr",
1355                                              "VCVTPD2UDQZ256rr",
1356                                              "VCVTPS2PD(Y|Z256)rr",
1357                                              "VCVTPS2QQZ256rr",
1358                                              "VCVTPS2UQQZ256rr",
1359                                              "VCVTQQ2PSZ256rr",
1360                                              "VCVTTPD2DQ(Y|Z256)rr",
1361                                              "VCVTTPD2UDQZ256rr",
1362                                              "VCVTTPS2QQZ256rr",
1363                                              "VCVTTPS2UQQZ256rr",
1364                                              "VCVTUDQ2PDZ256rr",
1365                                              "VCVTUQQ2PSZ256rr")>;
1366
1367 def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
1368   let Latency = 7;
1369   let NumMicroOps = 2;
1370   let ResourceCycles = [1,1];
1371 }
1372 def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
1373                                            VCVTPD2DQZrr,
1374                                            VCVTPD2PSZrr,
1375                                            VCVTPD2UDQZrr,
1376                                            VCVTPS2PDZrr,
1377                                            VCVTPS2QQZrr,
1378                                            VCVTPS2UQQZrr,
1379                                            VCVTQQ2PSZrr,
1380                                            VCVTTPD2DQZrr,
1381                                            VCVTTPD2UDQZrr,
1382                                            VCVTTPS2QQZrr,
1383                                            VCVTTPS2UQQZrr,
1384                                            VCVTUDQ2PDZrr,
1385                                            VCVTUQQ2PSZrr)>;
1386
1387 def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1388   let Latency = 7;
1389   let NumMicroOps = 2;
1390   let ResourceCycles = [1,1];
1391 }
1392 def: InstRW<[SKXWriteResGroup95], (instregex "VBLENDMPDZ128rm(b?)",
1393                                              "VBLENDMPSZ128rm(b?)",
1394                                              "VBROADCASTI32X2Z128m(b?)",
1395                                              "VBROADCASTSSZ128m(b?)",
1396                                              "VINSERTF128rm",
1397                                              "VINSERTI128rm",
1398                                              "VMOVAPDZ128rm(b?)",
1399                                              "VMOVAPSZ128rm(b?)",
1400                                              "VMOVDDUPZ128rm(b?)",
1401                                              "VMOVDQA32Z128rm(b?)",
1402                                              "VMOVDQA64Z128rm(b?)",
1403                                              "VMOVDQU16Z128rm(b?)",
1404                                              "VMOVDQU32Z128rm(b?)",
1405                                              "VMOVDQU64Z128rm(b?)",
1406                                              "VMOVDQU8Z128rm(b?)",
1407                                              "VMOVNTDQAZ128rm(b?)",
1408                                              "VMOVSHDUPZ128rm(b?)",
1409                                              "VMOVSLDUPZ128rm(b?)",
1410                                              "VMOVUPDZ128rm(b?)",
1411                                              "VMOVUPSZ128rm(b?)",
1412                                              "VPADD(B|D|Q|W)Z128rm(b?)",
1413                                              "(V?)PADD(B|D|Q|W)rm",
1414                                              "VPBLENDDrmi",
1415                                              "VPBLENDM(B|D|Q|W)Z128rm(b?)",
1416                                              "VPBROADCASTDZ128m(b?)",
1417                                              "VPBROADCASTQZ128m(b?)",
1418                                              "VPSUB(B|D|Q|W)Z128rm(b?)",
1419                                              "(V?)PSUB(B|D|Q|W)rm",
1420                                              "VPTERNLOGDZ128rm(b?)i",
1421                                              "VPTERNLOGQZ128rm(b?)i")>;
1422
1423 def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1424   let Latency = 7;
1425   let NumMicroOps = 3;
1426   let ResourceCycles = [2,1];
1427 }
1428 def: InstRW<[SKXWriteResGroup96], (instregex "MMX_PACKSSDWirm",
1429                                              "MMX_PACKSSWBirm",
1430                                              "MMX_PACKUSWBirm")>;
1431
1432 def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1433   let Latency = 7;
1434   let NumMicroOps = 3;
1435   let ResourceCycles = [2,1];
1436 }
1437 def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
1438                                              "VPERMI2W256rr",
1439                                              "VPERMI2Wrr",
1440                                              "VPERMT2W128rr",
1441                                              "VPERMT2W256rr",
1442                                              "VPERMT2Wrr")>;
1443
1444 def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1445   let Latency = 7;
1446   let NumMicroOps = 3;
1447   let ResourceCycles = [1,2];
1448 }
1449 def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
1450                                           SCASB, SCASL, SCASQ, SCASW)>;
1451
1452 def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
1453   let Latency = 7;
1454   let NumMicroOps = 3;
1455   let ResourceCycles = [1,1,1];
1456 }
1457 def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
1458                                               "(V?)CVTSS2SI64(Z?)rr",
1459                                               "(V?)CVTTSS2SI64(Z?)rr",
1460                                               "VCVTTSS2USI64Zrr")>;
1461
1462 def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
1463   let Latency = 7;
1464   let NumMicroOps = 3;
1465   let ResourceCycles = [1,1,1];
1466 }
1467 def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
1468
1469 def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
1470   let Latency = 7;
1471   let NumMicroOps = 3;
1472   let ResourceCycles = [1,1,1];
1473 }
1474 def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
1475
1476 def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
1477   let Latency = 7;
1478   let NumMicroOps = 3;
1479   let ResourceCycles = [1,1,1];
1480 }
1481 def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>;
1482
1483 def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1484   let Latency = 7;
1485   let NumMicroOps = 4;
1486   let ResourceCycles = [1,2,1];
1487 }
1488 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
1489                                               "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
1490                                               "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
1491                                               "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
1492
1493 def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1494   let Latency = 7;
1495   let NumMicroOps = 5;
1496   let ResourceCycles = [1,1,1,2];
1497 }
1498 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m1",
1499                                               "ROL(8|16|32|64)mi",
1500                                               "ROR(8|16|32|64)m1",
1501                                               "ROR(8|16|32|64)mi")>;
1502
1503 def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1504   let Latency = 7;
1505   let NumMicroOps = 5;
1506   let ResourceCycles = [1,1,1,2];
1507 }
1508 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
1509
1510 def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
1511   let Latency = 7;
1512   let NumMicroOps = 5;
1513   let ResourceCycles = [1,1,1,1,1];
1514 }
1515 def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m",
1516                                               "FARCALL64")>;
1517
1518 def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1519   let Latency = 7;
1520   let NumMicroOps = 7;
1521   let ResourceCycles = [1,2,2,2];
1522 }
1523 def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
1524                                            VPSCATTERQQZ128mr,
1525                                            VSCATTERDPDZ128mr,
1526                                            VSCATTERQPDZ128mr)>;
1527
1528 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
1529   let Latency = 7;
1530   let NumMicroOps = 7;
1531   let ResourceCycles = [1,3,1,2];
1532 }
1533 def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
1534
1535 def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1536   let Latency = 7;
1537   let NumMicroOps = 11;
1538   let ResourceCycles = [1,4,4,2];
1539 }
1540 def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
1541                                            VPSCATTERQQZ256mr,
1542                                            VSCATTERDPDZ256mr,
1543                                            VSCATTERQPDZ256mr)>;
1544
1545 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1546   let Latency = 7;
1547   let NumMicroOps = 19;
1548   let ResourceCycles = [1,8,8,2];
1549 }
1550 def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
1551                                            VPSCATTERQQZmr,
1552                                            VSCATTERDPDZmr,
1553                                            VSCATTERQPDZmr)>;
1554
1555 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1556   let Latency = 7;
1557   let NumMicroOps = 36;
1558   let ResourceCycles = [1,16,1,16,2];
1559 }
1560 def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
1561
1562 def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
1563   let Latency = 8;
1564   let NumMicroOps = 2;
1565   let ResourceCycles = [1,1];
1566 }
1567 def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
1568                                               "PEXT(32|64)rm")>;
1569
1570 def SKXWriteResGroup118_16_1 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]> {
1571   let Latency = 8;
1572   let NumMicroOps = 3;
1573   let ResourceCycles = [1,1,1];
1574 }
1575 def: InstRW<[SKXWriteResGroup118_16_1], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
1576
1577 def SKXWriteResGroup118_16_2 : SchedWriteRes<[SKXPort1, SKXPort06, SKXPort0156, SKXPort23]> {
1578   let Latency = 9;
1579   let NumMicroOps = 5;
1580   let ResourceCycles = [1,1,2,1];
1581 }
1582 def: InstRW<[SKXWriteResGroup118_16_2], (instrs IMUL16m, MUL16m)>;
1583
1584 def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1585   let Latency = 8;
1586   let NumMicroOps = 2;
1587   let ResourceCycles = [1,1];
1588 }
1589 def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
1590                                               "VFPCLASSSDZrm(b?)",
1591                                               "VPBROADCASTBYrm",
1592                                               "VPBROADCASTB(Z|Z256)m(b?)",
1593                                               "VPBROADCASTWYrm",
1594                                               "VPBROADCASTW(Z|Z256)m(b?)",
1595                                               "VPMOVSXBDYrm",
1596                                               "VPMOVSXBQYrm",
1597                                               "VPMOVSXWQYrm")>;
1598
1599 def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1600   let Latency = 8;
1601   let NumMicroOps = 2;
1602   let ResourceCycles = [1,1];
1603 }
1604 def: InstRW<[SKXWriteResGroup121], (instregex "VBLENDMPD(Z|Z256)rm(b?)",
1605                                               "VBLENDMPS(Z|Z256)rm(b?)",
1606                                               "VBROADCASTF32X2Z256m(b?)",
1607                                               "VBROADCASTF32X2Zm(b?)",
1608                                               "VBROADCASTF32X4Z256rm(b?)",
1609                                               "VBROADCASTF32X4rm(b?)",
1610                                               "VBROADCASTF32X8rm(b?)",
1611                                               "VBROADCASTF64X2Z128rm(b?)",
1612                                               "VBROADCASTF64X2rm(b?)",
1613                                               "VBROADCASTF64X4rm(b?)",
1614                                               "VBROADCASTI32X2Z256m(b?)",
1615                                               "VBROADCASTI32X2Zm(b?)",
1616                                               "VBROADCASTI32X4Z256rm(b?)",
1617                                               "VBROADCASTI32X4rm(b?)",
1618                                               "VBROADCASTI32X8rm(b?)",
1619                                               "VBROADCASTI64X2Z128rm(b?)",
1620                                               "VBROADCASTI64X2rm(b?)",
1621                                               "VBROADCASTI64X4rm(b?)",
1622                                               "VBROADCASTSD(Z|Z256)m(b?)",
1623                                               "VBROADCASTSS(Z|Z256)m(b?)",
1624                                               "VINSERTF32x4(Z|Z256)rm(b?)",
1625                                               "VINSERTF32x8Zrm(b?)",
1626                                               "VINSERTF64x2(Z|Z256)rm(b?)",
1627                                               "VINSERTF64x4Zrm(b?)",
1628                                               "VINSERTI32x4(Z|Z256)rm(b?)",
1629                                               "VINSERTI32x8Zrm(b?)",
1630                                               "VINSERTI64x2(Z|Z256)rm(b?)",
1631                                               "VINSERTI64x4Zrm(b?)",
1632                                               "VMOVAPD(Z|Z256)rm(b?)",
1633                                               "VMOVAPS(Z|Z256)rm(b?)",
1634                                               "VMOVDDUP(Z|Z256)rm(b?)",
1635                                               "VMOVDQA32(Z|Z256)rm(b?)",
1636                                               "VMOVDQA64(Z|Z256)rm(b?)",
1637                                               "VMOVDQU16(Z|Z256)rm(b?)",
1638                                               "VMOVDQU32(Z|Z256)rm(b?)",
1639                                               "VMOVDQU64(Z|Z256)rm(b?)",
1640                                               "VMOVDQU8(Z|Z256)rm(b?)",
1641                                               "VMOVNTDQAZ256rm(b?)",
1642                                               "VMOVSHDUP(Z|Z256)rm(b?)",
1643                                               "VMOVSLDUP(Z|Z256)rm(b?)",
1644                                               "VMOVUPD(Z|Z256)rm(b?)",
1645                                               "VMOVUPS(Z|Z256)rm(b?)",
1646                                               "VPADD(B|D|Q|W)Yrm",
1647                                               "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",
1648                                               "VPBLENDDYrmi",
1649                                               "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",
1650                                               "VPBROADCASTD(Z|Z256)m(b?)",
1651                                               "VPBROADCASTQ(Z|Z256)m(b?)",
1652                                               "VPSUB(B|D|Q|W)Yrm",
1653                                               "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
1654                                               "VPTERNLOGD(Z|Z256)rm(b?)i",
1655                                               "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
1656
1657 def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1658   let Latency = 8;
1659   let NumMicroOps = 4;
1660   let ResourceCycles = [1,2,1];
1661 }
1662 def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1663
1664 def SKXWriteResGroup126 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06]> {
1665   let Latency = 8;
1666   let NumMicroOps = 5;
1667   let ResourceCycles = [1,1,3];
1668 }
1669 def: InstRW<[SKXWriteResGroup126], (instregex "ROR(8|16|32|64)mCL")>;
1670
1671 def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1672   let Latency = 8;
1673   let NumMicroOps = 5;
1674   let ResourceCycles = [1,1,1,2];
1675 }
1676 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m1",
1677                                               "RCL(8|16|32|64)mi",
1678                                               "RCR(8|16|32|64)m1",
1679                                               "RCR(8|16|32|64)mi")>;
1680
1681 def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1682   let Latency = 8;
1683   let NumMicroOps = 6;
1684   let ResourceCycles = [1,1,1,3];
1685 }
1686 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
1687                                               "SAR(8|16|32|64)mCL",
1688                                               "SHL(8|16|32|64)mCL",
1689                                               "SHR(8|16|32|64)mCL")>;
1690
1691 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1692   let Latency = 8;
1693   let NumMicroOps = 6;
1694   let ResourceCycles = [1,1,1,2,1];
1695 }
1696 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
1697 def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(8|16|32|64)rm")>;
1698
1699 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1700   let Latency = 8;
1701   let NumMicroOps = 8;
1702   let ResourceCycles = [1,2,1,2,2];
1703 }
1704 def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
1705                                            VPSCATTERQDZ256mr,
1706                                            VSCATTERQPSZ128mr,
1707                                            VSCATTERQPSZ256mr)>;
1708
1709 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1710   let Latency = 8;
1711   let NumMicroOps = 12;
1712   let ResourceCycles = [1,4,1,4,2];
1713 }
1714 def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
1715                                            VSCATTERDPSZ128mr)>;
1716
1717 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1718   let Latency = 8;
1719   let NumMicroOps = 20;
1720   let ResourceCycles = [1,8,1,8,2];
1721 }
1722 def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
1723                                            VSCATTERDPSZ256mr)>;
1724
1725 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1726   let Latency = 8;
1727   let NumMicroOps = 36;
1728   let ResourceCycles = [1,16,1,16,2];
1729 }
1730 def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
1731
1732 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1733   let Latency = 9;
1734   let NumMicroOps = 2;
1735   let ResourceCycles = [1,1];
1736 }
1737 def: InstRW<[SKXWriteResGroup135], (instregex "MMX_CVTPI2PSirm")>;
1738
1739 def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1740   let Latency = 9;
1741   let NumMicroOps = 2;
1742   let ResourceCycles = [1,1];
1743 }
1744 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGNDZ128rm(b?)i",
1745                                               "VALIGNQZ128rm(b?)i",
1746                                               "VCMPPDZ128rm(b?)i",
1747                                               "VCMPPSZ128rm(b?)i",
1748                                               "VCMPSDZrm",
1749                                               "VCMPSSZrm",
1750                                               "VFPCLASSSSZrm(b?)",
1751                                               "VPCMPBZ128rmi(b?)",
1752                                               "VPCMPDZ128rmi(b?)",
1753                                               "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
1754                                               "VPCMPGT(B|D|Q|W)Z128rm(b?)",
1755                                               "(V?)PCMPGTQrm",
1756                                               "VPCMPQZ128rmi(b?)",
1757                                               "VPCMPU(B|D|Q|W)Z128rmi(b?)",
1758                                               "VPCMPWZ128rmi(b?)",
1759                                               "VPERMI2D128rm(b?)",
1760                                               "VPERMI2PD128rm(b?)",
1761                                               "VPERMI2PS128rm(b?)",
1762                                               "VPERMI2Q128rm(b?)",
1763                                               "VPERMT2D128rm(b?)",
1764                                               "VPERMT2PD128rm(b?)",
1765                                               "VPERMT2PS128rm(b?)",
1766                                               "VPERMT2Q128rm(b?)",
1767                                               "VPMAXSQZ128rm(b?)",
1768                                               "VPMAXUQZ128rm(b?)",
1769                                               "VPMINSQZ128rm(b?)",
1770                                               "VPMINUQZ128rm(b?)",
1771                                               "VPMOVSXBDZ128rm(b?)",
1772                                               "VPMOVSXBQZ128rm(b?)",
1773                                               "VPMOVSXBWYrm",
1774                                               "VPMOVSXBWZ128rm(b?)",
1775                                               "VPMOVSXDQYrm",
1776                                               "VPMOVSXDQZ128rm(b?)",
1777                                               "VPMOVSXWDYrm",
1778                                               "VPMOVSXWDZ128rm(b?)",
1779                                               "VPMOVSXWQZ128rm(b?)",
1780                                               "VPMOVZXBDZ128rm(b?)",
1781                                               "VPMOVZXBQZ128rm(b?)",
1782                                               "VPMOVZXBWZ128rm(b?)",
1783                                               "VPMOVZXDQZ128rm(b?)",
1784                                               "VPMOVZXWDYrm",
1785                                               "VPMOVZXWDZ128rm(b?)",
1786                                               "VPMOVZXWQZ128rm(b?)",
1787                                               "VPTESTMBZ128rm(b?)",
1788                                               "VPTESTMDZ128rm(b?)",
1789                                               "VPTESTMQZ128rm(b?)",
1790                                               "VPTESTMWZ128rm(b?)",
1791                                               "VPTESTNMBZ128rm(b?)",
1792                                               "VPTESTNMDZ128rm(b?)",
1793                                               "VPTESTNMQZ128rm(b?)",
1794                                               "VPTESTNMWZ128rm(b?)")>;
1795
1796 def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1797   let Latency = 9;
1798   let NumMicroOps = 2;
1799   let ResourceCycles = [1,1];
1800 }
1801 def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm",
1802                                               "(V?)CVTPS2PDrm")>;
1803
1804 def SKXWriteResGroup142 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort23]> {
1805   let Latency = 9;
1806   let NumMicroOps = 3;
1807   let ResourceCycles = [1,1,1];
1808 }
1809 def: InstRW<[SKXWriteResGroup142], (instrs IMUL64m, MUL64m, MULX64rm)>;
1810
1811 def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1812   let Latency = 9;
1813   let NumMicroOps = 4;
1814   let ResourceCycles = [2,1,1];
1815 }
1816 def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
1817                                               "(V?)PHSUBSWrm")>;
1818
1819 def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
1820   let Latency = 9;
1821   let NumMicroOps = 5;
1822   let ResourceCycles = [1,2,1,1];
1823 }
1824 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
1825                                               "LSL(16|32|64)rm")>;
1826
1827 def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1828   let Latency = 10;
1829   let NumMicroOps = 2;
1830   let ResourceCycles = [1,1];
1831 }
1832 def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1833                                               "ILD_F(16|32|64)m",
1834                                               "VALIGND(Z|Z256)rm(b?)i",
1835                                               "VALIGNQ(Z|Z256)rm(b?)i",
1836                                               "VCMPPD(Z|Z256)rm(b?)i",
1837                                               "VCMPPS(Z|Z256)rm(b?)i",
1838                                               "VPCMPB(Z|Z256)rmi(b?)",
1839                                               "VPCMPD(Z|Z256)rmi(b?)",
1840                                               "VPCMPEQB(Z|Z256)rm(b?)",
1841                                               "VPCMPEQD(Z|Z256)rm(b?)",
1842                                               "VPCMPEQQ(Z|Z256)rm(b?)",
1843                                               "VPCMPEQW(Z|Z256)rm(b?)",
1844                                               "VPCMPGTB(Z|Z256)rm(b?)",
1845                                               "VPCMPGTD(Z|Z256)rm(b?)",
1846                                               "VPCMPGTQYrm",
1847                                               "VPCMPGTQ(Z|Z256)rm(b?)",
1848                                               "VPCMPGTW(Z|Z256)rm(b?)",
1849                                               "VPCMPQ(Z|Z256)rmi(b?)",
1850                                               "VPCMPU(B|D|Q|W)Z256rmi(b?)",
1851                                               "VPCMPU(B|D|Q|W)Zrmi(b?)",
1852                                               "VPCMPW(Z|Z256)rmi(b?)",
1853                                               "VPMAXSQ(Z|Z256)rm(b?)",
1854                                               "VPMAXUQ(Z|Z256)rm(b?)",
1855                                               "VPMINSQ(Z|Z256)rm(b?)",
1856                                               "VPMINUQ(Z|Z256)rm(b?)",
1857                                               "VPTESTM(B|D|Q|W)Z256rm(b?)",
1858                                               "VPTESTM(B|D|Q|W)Zrm(b?)",
1859                                               "VPTESTNM(B|D|Q|W)Z256rm(b?)",
1860                                               "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
1861
1862 def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1863   let Latency = 10;
1864   let NumMicroOps = 2;
1865   let ResourceCycles = [1,1];
1866 }
1867 def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
1868                                               "VCVTDQ2PSZ128rm(b?)",
1869                                               "(V?)CVTDQ2PSrm",
1870                                               "VCVTPD2QQZ128rm(b?)",
1871                                               "VCVTPD2UQQZ128rm(b?)",
1872                                               "VCVTPH2PSZ128rm(b?)",
1873                                               "VCVTPS2DQZ128rm(b?)",
1874                                               "(V?)CVTPS2DQrm",
1875                                               "VCVTPS2PDZ128rm(b?)",
1876                                               "VCVTPS2QQZ128rm(b?)",
1877                                               "VCVTPS2UDQZ128rm(b?)",
1878                                               "VCVTPS2UQQZ128rm(b?)",
1879                                               "VCVTQQ2PDZ128rm(b?)",
1880                                               "VCVTQQ2PSZ128rm(b?)",
1881                                               "VCVTSS2SDZrm",
1882                                               "(V?)CVTSS2SDrm",
1883                                               "VCVTTPD2QQZ128rm(b?)",
1884                                               "VCVTTPD2UQQZ128rm(b?)",
1885                                               "VCVTTPS2DQZ128rm(b?)",
1886                                               "(V?)CVTTPS2DQrm",
1887                                               "VCVTTPS2QQZ128rm(b?)",
1888                                               "VCVTTPS2UDQZ128rm(b?)",
1889                                               "VCVTTPS2UQQZ128rm(b?)",
1890                                               "VCVTUDQ2PDZ128rm(b?)",
1891                                               "VCVTUDQ2PSZ128rm(b?)",
1892                                               "VCVTUQQ2PDZ128rm(b?)",
1893                                               "VCVTUQQ2PSZ128rm(b?)")>;
1894
1895 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1896   let Latency = 10;
1897   let NumMicroOps = 3;
1898   let ResourceCycles = [2,1];
1899 }
1900 def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
1901                                               "VEXPANDPSZ128rm(b?)",
1902                                               "VPEXPANDDZ128rm(b?)",
1903                                               "VPEXPANDQZ128rm(b?)")>;
1904
1905 def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1906   let Latency = 10;
1907   let NumMicroOps = 3;
1908   let ResourceCycles = [1,1,1];
1909 }
1910 def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>;
1911
1912 def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1913   let Latency = 10;
1914   let NumMicroOps = 4;
1915   let ResourceCycles = [2,1,1];
1916 }
1917 def: InstRW<[SKXWriteResGroup154], (instregex "VPHADDSWYrm",
1918                                               "VPHSUBSWYrm")>;
1919
1920 def SKXWriteResGroup156 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort06,SKXPort0156]> {
1921   let Latency = 9;
1922   let NumMicroOps = 4;
1923   let ResourceCycles = [1,1,1,1];
1924 }
1925 def: InstRW<[SKXWriteResGroup156], (instrs IMUL32m, MUL32m, MULX32rm)>;
1926
1927 def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1928   let Latency = 10;
1929   let NumMicroOps = 8;
1930   let ResourceCycles = [1,1,1,1,1,3];
1931 }
1932 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
1933
1934 def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
1935   let Latency = 11;
1936   let NumMicroOps = 1;
1937   let ResourceCycles = [1,3];
1938 }
1939 def : SchedAlias<WriteFDivX,  SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair
1940
1941 def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1942   let Latency = 11;
1943   let NumMicroOps = 2;
1944   let ResourceCycles = [1,1];
1945 }
1946 def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
1947
1948 def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1949   let Latency = 11;
1950   let NumMicroOps = 2;
1951   let ResourceCycles = [1,1];
1952 }
1953 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2PD(Z|Z256)rm(b?)",
1954                                               "VCVTDQ2PSYrm",
1955                                               "VCVTDQ2PS(Z|Z256)rm(b?)",
1956                                               "VCVTPH2PS(Z|Z256)rm(b?)",
1957                                               "VCVTPS2PDYrm",
1958                                               "VCVTPS2PD(Z|Z256)rm(b?)",
1959                                               "VCVTQQ2PD(Z|Z256)rm(b?)",
1960                                               "VCVTQQ2PSZ256rm(b?)",
1961                                               "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1962                                               "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1963                                               "VCVT(T?)PS2DQYrm",
1964                                               "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1965                                               "VCVT(T?)PS2QQZ256rm(b?)",
1966                                               "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1967                                               "VCVT(T?)PS2UQQZ256rm(b?)",
1968                                               "VCVTUDQ2PD(Z|Z256)rm(b?)",
1969                                               "VCVTUDQ2PS(Z|Z256)rm(b?)",
1970                                               "VCVTUQQ2PD(Z|Z256)rm(b?)",
1971                                               "VCVTUQQ2PSZ256rm(b?)")>;
1972
1973 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1974   let Latency = 11;
1975   let NumMicroOps = 3;
1976   let ResourceCycles = [2,1];
1977 }
1978 def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
1979                                               "VEXPANDPD(Z|Z256)rm(b?)",
1980                                               "VEXPANDPS(Z|Z256)rm(b?)",
1981                                               "VPEXPANDD(Z|Z256)rm(b?)",
1982                                               "VPEXPANDQ(Z|Z256)rm(b?)")>;
1983
1984 def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1985   let Latency = 11;
1986   let NumMicroOps = 3;
1987   let ResourceCycles = [1,2];
1988 }
1989 def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>;
1990
1991 def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1992   let Latency = 11;
1993   let NumMicroOps = 3;
1994   let ResourceCycles = [1,1,1];
1995 }
1996 def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
1997
1998 def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1999   let Latency = 11;
2000   let NumMicroOps = 3;
2001   let ResourceCycles = [1,1,1];
2002 }
2003 def: InstRW<[SKXWriteResGroup166], (instregex "CVTPD2PSrm",
2004                                               "CVT(T?)PD2DQrm",
2005                                               "MMX_CVT(T?)PD2PIirm")>;
2006
2007 def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2008   let Latency = 11;
2009   let NumMicroOps = 4;
2010   let ResourceCycles = [2,1,1];
2011 }
2012 def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
2013
2014 def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
2015   let Latency = 11;
2016   let NumMicroOps = 7;
2017   let ResourceCycles = [2,3,2];
2018 }
2019 def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
2020                                               "RCR(16|32|64)rCL")>;
2021
2022 def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2023   let Latency = 11;
2024   let NumMicroOps = 9;
2025   let ResourceCycles = [1,5,1,2];
2026 }
2027 def: InstRW<[SKXWriteResGroup170], (instregex "RCL8rCL")>;
2028
2029 def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
2030   let Latency = 11;
2031   let NumMicroOps = 11;
2032   let ResourceCycles = [2,9];
2033 }
2034 def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
2035
2036 def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
2037   let Latency = 12;
2038   let NumMicroOps = 3;
2039   let ResourceCycles = [3];
2040 }
2041 def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
2042
2043 def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
2044   let Latency = 12;
2045   let NumMicroOps = 3;
2046   let ResourceCycles = [3];
2047 }
2048 def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
2049
2050 def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
2051   let Latency = 12;
2052   let NumMicroOps = 3;
2053   let ResourceCycles = [2,1];
2054 }
2055 def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
2056
2057 def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
2058   let Latency = 12;
2059   let NumMicroOps = 3;
2060   let ResourceCycles = [1,1,1];
2061 }
2062 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
2063                                               "VCVT(T?)SS2USI64Zrm(b?)")>;
2064
2065 def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2066   let Latency = 12;
2067   let NumMicroOps = 3;
2068   let ResourceCycles = [1,1,1];
2069 }
2070 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
2071                                               "VCVT(T?)PS2UQQZrm(b?)")>;
2072
2073 def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
2074   let Latency = 12;
2075   let NumMicroOps = 4;
2076   let ResourceCycles = [1,1,1,1];
2077 }
2078 def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
2079
2080 def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
2081   let Latency = 13;
2082   let NumMicroOps = 3;
2083   let ResourceCycles = [2,1];
2084 }
2085 def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
2086                                               "VPERMWZ256rm(b?)",
2087                                               "VPERMWZrm(b?)")>;
2088
2089 def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2090   let Latency = 13;
2091   let NumMicroOps = 3;
2092   let ResourceCycles = [1,1,1];
2093 }
2094 def: InstRW<[SKXWriteResGroup181], (instregex "VCVTDQ2PDYrm")>;
2095
2096 def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2097   let Latency = 13;
2098   let NumMicroOps = 4;
2099   let ResourceCycles = [2,1,1];
2100 }
2101 def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
2102                                               "VPERMT2W128rm(b?)")>;
2103
2104 def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2105   let Latency = 14;
2106   let NumMicroOps = 1;
2107   let ResourceCycles = [1,3];
2108 }
2109 def : SchedAlias<WriteFDiv64,  SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2110 def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2111
2112 def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2113   let Latency = 14;
2114   let NumMicroOps = 1;
2115   let ResourceCycles = [1,5];
2116 }
2117 def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair
2118
2119 def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2120   let Latency = 14;
2121   let NumMicroOps = 3;
2122   let ResourceCycles = [1,1,1];
2123 }
2124 def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
2125
2126 def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2127   let Latency = 14;
2128   let NumMicroOps = 3;
2129   let ResourceCycles = [1,1,1];
2130 }
2131 def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
2132                                               "VCVTPD2PSZrm(b?)",
2133                                               "VCVTPD2UDQZrm(b?)",
2134                                               "VCVTQQ2PSZrm(b?)",
2135                                               "VCVTTPD2DQZrm(b?)",
2136                                               "VCVTTPD2UDQZrm(b?)",
2137                                               "VCVTUQQ2PSZrm(b?)")>;
2138
2139 def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2140   let Latency = 14;
2141   let NumMicroOps = 4;
2142   let ResourceCycles = [2,1,1];
2143 }
2144 def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
2145                                               "VPERMI2Wrm(b?)",
2146                                               "VPERMT2W256rm(b?)",
2147                                               "VPERMT2Wrm(b?)")>;
2148
2149 def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2150   let Latency = 14;
2151   let NumMicroOps = 10;
2152   let ResourceCycles = [2,4,1,3];
2153 }
2154 def: InstRW<[SKXWriteResGroup190], (instregex "RCR8rCL")>;
2155
2156 def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
2157   let Latency = 15;
2158   let NumMicroOps = 1;
2159   let ResourceCycles = [1];
2160 }
2161 def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
2162
2163 def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2164   let Latency = 15;
2165   let NumMicroOps = 8;
2166   let ResourceCycles = [1,2,2,1,2];
2167 }
2168 def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
2169
2170 def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2171   let Latency = 15;
2172   let NumMicroOps = 10;
2173   let ResourceCycles = [1,1,1,5,1,1];
2174 }
2175 def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
2176
2177 def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2178   let Latency = 16;
2179   let NumMicroOps = 14;
2180   let ResourceCycles = [1,1,1,4,2,5];
2181 }
2182 def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
2183
2184 def SKXWriteResGroup200 : SchedWriteRes<[SKXPort0156]> {
2185   let Latency = 16;
2186   let NumMicroOps = 16;
2187   let ResourceCycles = [16];
2188 }
2189 def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
2190
2191 def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2192   let Latency = 17;
2193   let NumMicroOps = 2;
2194   let ResourceCycles = [1,1,5];
2195 }
2196 def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair
2197
2198 def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2199   let Latency = 17;
2200   let NumMicroOps = 15;
2201   let ResourceCycles = [2,1,2,4,2,4];
2202 }
2203 def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
2204
2205 def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2206   let Latency = 18;
2207   let NumMicroOps = 4;
2208   let ResourceCycles = [1,3];
2209 }
2210 def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
2211
2212 def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2213   let Latency = 18;
2214   let NumMicroOps = 8;
2215   let ResourceCycles = [1,1,1,5];
2216 }
2217 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
2218
2219 def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2220   let Latency = 18;
2221   let NumMicroOps = 11;
2222   let ResourceCycles = [2,1,1,4,1,2];
2223 }
2224 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
2225
2226 def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2227   let Latency = 19;
2228   let NumMicroOps = 2;
2229   let ResourceCycles = [1,1,4];
2230 }
2231 def : SchedAlias<WriteFDiv64Ld,  SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair
2232
2233 def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2234   let Latency = 19;
2235   let NumMicroOps = 4;
2236   let ResourceCycles = [1,3];
2237 }
2238 def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)",
2239                                               "VPMULLQZrm(b?)")>;
2240
2241 def SKXWriteResGroup214 : SchedWriteRes<[]> {
2242   let Latency = 20;
2243   let NumMicroOps = 0;
2244 }
2245 def: InstRW<[SKXWriteResGroup214], (instrs VGATHERDPSZ128rm,
2246                                            VGATHERQPSZrm,
2247                                            VPGATHERDDZ128rm)>;
2248
2249 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
2250   let Latency = 20;
2251   let NumMicroOps = 1;
2252   let ResourceCycles = [1];
2253 }
2254 def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
2255
2256 def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2257   let Latency = 20;
2258   let NumMicroOps = 2;
2259   let ResourceCycles = [1,1,4];
2260 }
2261 def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair
2262
2263 def SKXWriteResGroup218 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2264   let Latency = 20;
2265   let NumMicroOps = 5;
2266   let ResourceCycles = [1,2,1,1];
2267 }
2268 def: InstRW<[SKXWriteResGroup218], (instrs VGATHERQPSZ128rm,
2269                                            VGATHERQPSZ256rm,
2270                                            VPGATHERQDZ128rm,
2271                                            VPGATHERQDZ256rm)>;
2272
2273 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2274   let Latency = 20;
2275   let NumMicroOps = 8;
2276   let ResourceCycles = [1,1,1,1,1,1,2];
2277 }
2278 def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
2279
2280 def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
2281   let Latency = 20;
2282   let NumMicroOps = 10;
2283   let ResourceCycles = [1,2,7];
2284 }
2285 def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
2286
2287 def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2288   let Latency = 21;
2289   let NumMicroOps = 2;
2290   let ResourceCycles = [1,1,8];
2291 }
2292 def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair
2293
2294 def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2295   let Latency = 22;
2296   let NumMicroOps = 2;
2297   let ResourceCycles = [1,1];
2298 }
2299 def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
2300
2301 def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2302   let Latency = 22;
2303   let NumMicroOps = 5;
2304   let ResourceCycles = [1,2,1,1];
2305 }
2306 def: InstRW<[SKXWriteResGroup224], (instrs VGATHERDPDZ128rm,
2307                                            VGATHERQPDZ128rm,
2308                                            VPGATHERDQZ128rm,
2309                                            VPGATHERQQZ128rm)>;
2310
2311 def SKXWriteResGroup224_2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2312   let Latency = 22;
2313   let NumMicroOps = 5;
2314   let ResourceCycles = [1,2,1,1];
2315 }
2316 def: InstRW<[SKXWriteResGroup224_2], (instrs VGATHERDPSrm,
2317                                              VGATHERDPDrm,
2318                                              VGATHERQPDrm,
2319                                              VGATHERQPSrm,
2320                                              VPGATHERDDrm,
2321                                              VPGATHERDQrm,
2322                                              VPGATHERQDrm,
2323                                              VPGATHERQQrm,
2324                                              VPGATHERDDrm,
2325                                              VPGATHERQDrm,
2326                                              VPGATHERDQrm,
2327                                              VPGATHERQQrm,
2328                                              VGATHERDPSrm,
2329                                              VGATHERQPSrm,
2330                                              VGATHERDPDrm,
2331                                              VGATHERQPDrm)>;
2332
2333 def SKXWriteResGroup224_3 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2334   let Latency = 25;
2335   let NumMicroOps = 5;
2336   let ResourceCycles = [1,2,1,1];
2337 }
2338 def: InstRW<[SKXWriteResGroup224_3], (instrs VGATHERDPSYrm,
2339                                              VGATHERQPDYrm,
2340                                              VGATHERQPSYrm,
2341                                              VPGATHERDDYrm,
2342                                              VPGATHERDQYrm,
2343                                              VPGATHERQDYrm,
2344                                              VPGATHERQQYrm,
2345                                              VPGATHERDDYrm,
2346                                              VPGATHERQDYrm,
2347                                              VPGATHERDQYrm,
2348                                              VPGATHERQQYrm,
2349                                              VGATHERDPSYrm,
2350                                              VGATHERQPSYrm,
2351                                              VGATHERDPDYrm)>;
2352
2353 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2354   let Latency = 22;
2355   let NumMicroOps = 14;
2356   let ResourceCycles = [5,5,4];
2357 }
2358 def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
2359                                               "VPCONFLICTQZ256rr")>;
2360
2361 def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2362   let Latency = 23;
2363   let NumMicroOps = 19;
2364   let ResourceCycles = [2,1,4,1,1,4,6];
2365 }
2366 def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
2367
2368 def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2369   let Latency = 25;
2370   let NumMicroOps = 3;
2371   let ResourceCycles = [1,1,1];
2372 }
2373 def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
2374
2375 def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2376   let Latency = 25;
2377   let NumMicroOps = 5;
2378   let ResourceCycles = [1,2,1,1];
2379 }
2380 def: InstRW<[SKXWriteResGroup234], (instrs VGATHERDPDZ256rm,
2381                                            VGATHERQPDZ256rm,
2382                                            VPGATHERDQZ256rm,
2383                                            VPGATHERQDZrm,
2384                                            VPGATHERQQZ256rm)>;
2385
2386 def SKXWriteResGroup238 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2387   let Latency = 26;
2388   let NumMicroOps = 5;
2389   let ResourceCycles = [1,2,1,1];
2390 }
2391 def: InstRW<[SKXWriteResGroup238], (instrs VGATHERDPDZrm,
2392                                            VGATHERQPDZrm,
2393                                            VPGATHERDQZrm,
2394                                            VPGATHERQQZrm)>;
2395
2396 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2397   let Latency = 27;
2398   let NumMicroOps = 2;
2399   let ResourceCycles = [1,1];
2400 }
2401 def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
2402
2403 def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2404   let Latency = 27;
2405   let NumMicroOps = 5;
2406   let ResourceCycles = [1,2,1,1];
2407 }
2408 def: InstRW<[SKXWriteResGroup240], (instrs VGATHERDPSZ256rm,
2409                                            VPGATHERDDZ256rm)>;
2410
2411 def SKXWriteResGroup241 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort0156]> {
2412   let Latency = 28;
2413   let NumMicroOps = 8;
2414   let ResourceCycles = [2,4,1,1];
2415 }
2416 def: InstRW<[SKXWriteResGroup241], (instregex "IDIV(8|16|32|64)m")>;
2417
2418 def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2419   let Latency = 29;
2420   let NumMicroOps = 15;
2421   let ResourceCycles = [5,5,1,4];
2422 }
2423 def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
2424
2425 def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2426   let Latency = 30;
2427   let NumMicroOps = 3;
2428   let ResourceCycles = [1,1,1];
2429 }
2430 def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
2431
2432 def SKXWriteResGroup245 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2433   let Latency = 30;
2434   let NumMicroOps = 5;
2435   let ResourceCycles = [1,2,1,1];
2436 }
2437 def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm,
2438                                            VPGATHERDDZrm)>;
2439
2440 def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
2441   let Latency = 35;
2442   let NumMicroOps = 23;
2443   let ResourceCycles = [1,5,3,4,10];
2444 }
2445 def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
2446                                               "IN(8|16|32)rr")>;
2447
2448 def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2449   let Latency = 35;
2450   let NumMicroOps = 23;
2451   let ResourceCycles = [1,5,2,1,4,10];
2452 }
2453 def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
2454                                               "OUT(8|16|32)rr")>;
2455
2456 def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2457   let Latency = 37;
2458   let NumMicroOps = 21;
2459   let ResourceCycles = [9,7,5];
2460 }
2461 def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
2462                                               "VPCONFLICTQZrr")>;
2463
2464 def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
2465   let Latency = 37;
2466   let NumMicroOps = 31;
2467   let ResourceCycles = [1,8,1,21];
2468 }
2469 def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
2470
2471 def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
2472   let Latency = 40;
2473   let NumMicroOps = 18;
2474   let ResourceCycles = [1,1,2,3,1,1,1,8];
2475 }
2476 def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
2477
2478 def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2479   let Latency = 41;
2480   let NumMicroOps = 39;
2481   let ResourceCycles = [1,10,1,1,26];
2482 }
2483 def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
2484
2485 def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
2486   let Latency = 42;
2487   let NumMicroOps = 22;
2488   let ResourceCycles = [2,20];
2489 }
2490 def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
2491
2492 def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2493   let Latency = 42;
2494   let NumMicroOps = 40;
2495   let ResourceCycles = [1,11,1,1,26];
2496 }
2497 def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
2498 def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
2499
2500 def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2501   let Latency = 44;
2502   let NumMicroOps = 22;
2503   let ResourceCycles = [9,7,1,5];
2504 }
2505 def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
2506                                               "VPCONFLICTQZrm(b?)")>;
2507
2508 def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
2509   let Latency = 62;
2510   let NumMicroOps = 64;
2511   let ResourceCycles = [2,8,5,10,39];
2512 }
2513 def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
2514
2515 def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2516   let Latency = 63;
2517   let NumMicroOps = 88;
2518   let ResourceCycles = [4,4,31,1,2,1,45];
2519 }
2520 def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
2521
2522 def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2523   let Latency = 63;
2524   let NumMicroOps = 90;
2525   let ResourceCycles = [4,2,33,1,2,1,47];
2526 }
2527 def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
2528
2529 def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2530   let Latency = 67;
2531   let NumMicroOps = 35;
2532   let ResourceCycles = [17,11,7];
2533 }
2534 def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
2535
2536 def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2537   let Latency = 74;
2538   let NumMicroOps = 36;
2539   let ResourceCycles = [17,11,1,7];
2540 }
2541 def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
2542
2543 def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
2544   let Latency = 75;
2545   let NumMicroOps = 15;
2546   let ResourceCycles = [6,3,6];
2547 }
2548 def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
2549
2550 def SKXWriteResGroup264 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2551   let Latency = 76;
2552   let NumMicroOps = 32;
2553   let ResourceCycles = [7,2,8,3,1,11];
2554 }
2555 def: InstRW<[SKXWriteResGroup264], (instregex "DIV(16|32|64)r")>;
2556
2557 def SKXWriteResGroup265 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2558   let Latency = 102;
2559   let NumMicroOps = 66;
2560   let ResourceCycles = [4,2,4,8,14,34];
2561 }
2562 def: InstRW<[SKXWriteResGroup265], (instregex "IDIV(16|32|64)r")>;
2563
2564 def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
2565   let Latency = 106;
2566   let NumMicroOps = 100;
2567   let ResourceCycles = [9,1,11,16,1,11,21,30];
2568 }
2569 def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
2570
2571 def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
2572   let Latency = 140;
2573   let NumMicroOps = 4;
2574   let ResourceCycles = [1,3];
2575 }
2576 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
2577
2578 def: InstRW<[WriteZero], (instrs CLC)>;
2579
2580 } // SchedModel