contrib/llvm/lib/Target/X86/X86SchedSkylakeServer.td

   1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for Skylake Server to support
  11 // instruction scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 def SkylakeServerModel : SchedMachineModel {
  16   // All x86 instructions are modeled as a single micro-op, and SKylake can
  17   // decode 6 instructions per cycle.
  18   let IssueWidth = 6;
  19   let MicroOpBufferSize = 224; // Based on the reorder buffer.
  20   let LoadLatency = 5;
  21   let MispredictPenalty = 14;
  22
  23   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  24   let LoopMicroOpBufferSize = 50;
  25
  26   // This flag is set to allow the scheduler to assign a default model to
  27   // unrecognized opcodes.
  28   let CompleteModel = 0;
  29 }
  30
  31 let SchedModel = SkylakeServerModel in {
  32
  33 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
  34
  35 // Ports 0, 1, 5, and 6 handle all computation.
  36 // Port 4 gets the data half of stores. Store data can be available later than
  37 // the store address, but since we don't model the latency of stores, we can
  38 // ignore that.
  39 // Ports 2 and 3 are identical. They handle loads and the address half of
  40 // stores. Port 7 can handle address calculations.
  41 def SKXPort0 : ProcResource<1>;
  42 def SKXPort1 : ProcResource<1>;
  43 def SKXPort2 : ProcResource<1>;
  44 def SKXPort3 : ProcResource<1>;
  45 def SKXPort4 : ProcResource<1>;
  46 def SKXPort5 : ProcResource<1>;
  47 def SKXPort6 : ProcResource<1>;
  48 def SKXPort7 : ProcResource<1>;
  49
  50 // Many micro-ops are capable of issuing on multiple ports.
  51 def SKXPort01  : ProcResGroup<[SKXPort0, SKXPort1]>;
  52 def SKXPort23  : ProcResGroup<[SKXPort2, SKXPort3]>;
  53 def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>;
  54 def SKXPort04  : ProcResGroup<[SKXPort0, SKXPort4]>;
  55 def SKXPort05  : ProcResGroup<[SKXPort0, SKXPort5]>;
  56 def SKXPort06  : ProcResGroup<[SKXPort0, SKXPort6]>;
  57 def SKXPort15  : ProcResGroup<[SKXPort1, SKXPort5]>;
  58 def SKXPort16  : ProcResGroup<[SKXPort1, SKXPort6]>;
  59 def SKXPort56  : ProcResGroup<[SKXPort5, SKXPort6]>;
  60 def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
  61 def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
  62 def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
  63
  64 def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
  65 // FP division and sqrt on port 0.
  66 def SKXFPDivider : ProcResource<1>;
  67
  68 // 60 Entry Unified Scheduler
  69 def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
  70                               SKXPort5, SKXPort6, SKXPort7]> {
  71   let BufferSize=60;
  72 }
  73
  74 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  75 // cycles after the memory operand.
  76 def : ReadAdvance<ReadAfterLd, 5>;
  77
  78 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
  79 // until 5/6/7 cycles after the memory operand.
  80 def : ReadAdvance<ReadAfterVecLd, 5>;
  81 def : ReadAdvance<ReadAfterVecXLd, 6>;
  82 def : ReadAdvance<ReadAfterVecYLd, 7>;
  83
  84 // Many SchedWrites are defined in pairs with and without a folded load.
  85 // Instructions with folded loads are usually micro-fused, so they only appear
  86 // as two micro-ops when queued in the reservation station.
  87 // This multiclass defines the resource usage for variants with and without
  88 // folded loads.
  89 multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
  90                           list<ProcResourceKind> ExePorts,
  91                           int Lat, list<int> Res = [1], int UOps = 1,
  92                           int LoadLat = 5> {
  93   // Register variant is using a single cycle on ExePort.
  94   def : WriteRes<SchedRW, ExePorts> {
  95     let Latency = Lat;
  96     let ResourceCycles = Res;
  97     let NumMicroOps = UOps;
  98   }
  99
 100   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 101   // the latency (default = 5).
 102   def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
 103     let Latency = !add(Lat, LoadLat);
 104     let ResourceCycles = !listconcat([1], Res);
 105     let NumMicroOps = !add(UOps, 1);
 106   }
 107 }
 108
 109 // A folded store needs a cycle on port 4 for the store data, and an extra port
 110 // 2/3/7 cycle to recompute the address.
 111 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
 112
 113 // Arithmetic.
 114 defm : SKXWriteResPair<WriteALU,    [SKXPort0156], 1>; // Simple integer ALU op.
 115 defm : SKXWriteResPair<WriteADC,    [SKXPort06],   1>; // Integer ALU + flags op.
 116
 117 // Integer multiplication.
 118 defm : SKXWriteResPair<WriteIMul8,     [SKXPort1],   3>;
 119 defm : SKXWriteResPair<WriteIMul16,    [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>;
 120 defm : X86WriteRes<WriteIMul16Imm,     [SKXPort1,SKXPort0156], 4, [1,1], 2>;
 121 defm : X86WriteRes<WriteIMul16ImmLd,   [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
 122 defm : X86WriteRes<WriteIMul16Reg,     [SKXPort1],   3, [1], 1>;
 123 defm : X86WriteRes<WriteIMul16RegLd,   [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
 124 defm : SKXWriteResPair<WriteIMul32,    [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
 125 defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1],   3>;
 126 defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1],   3>;
 127 defm : SKXWriteResPair<WriteIMul64,    [SKXPort1,SKXPort5], 4, [1,1], 2>;
 128 defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1],   3>;
 129 defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1],   3>;
 130 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 131
 132 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
 133 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
 134 defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;
 135 defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>;
 136 defm : X86WriteRes<WriteXCHG,       [SKXPort0156], 2, [3], 3>;
 137
 138 // TODO: Why isn't the SKXDivider used?
 139 defm : SKXWriteResPair<WriteDiv8,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 140 defm : X86WriteRes<WriteDiv16,     [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
 141 defm : X86WriteRes<WriteDiv32,     [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
 142 defm : X86WriteRes<WriteDiv64,     [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
 143 defm : X86WriteRes<WriteDiv16Ld,   [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
 144 defm : X86WriteRes<WriteDiv32Ld,   [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
 145 defm : X86WriteRes<WriteDiv64Ld,   [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
 146
 147 defm : X86WriteRes<WriteIDiv8,     [SKXPort0, SKXDivider], 25, [1,10], 1>;
 148 defm : X86WriteRes<WriteIDiv16,    [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
 149 defm : X86WriteRes<WriteIDiv32,    [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
 150 defm : X86WriteRes<WriteIDiv64,    [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
 151 defm : X86WriteRes<WriteIDiv8Ld,   [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
 152 defm : X86WriteRes<WriteIDiv16Ld,  [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
 153 defm : X86WriteRes<WriteIDiv32Ld,  [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
 154 defm : X86WriteRes<WriteIDiv64Ld,  [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
 155
 156 defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
 157
 158 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
 159
 160 defm : SKXWriteResPair<WriteCMOV,  [SKXPort06], 1, [1], 1>; // Conditional move.
 161 defm : SKXWriteResPair<WriteCMOV2, [SKXPort06], 2, [2], 2>; // Conditional (CF + ZF flag) move.
 162 defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move.
 163 def  : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
 164 def  : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
 165   let Latency = 2;
 166   let NumMicroOps = 3;
 167 }
 168 defm : X86WriteRes<WriteLAHFSAHF,        [SKXPort06], 1, [1], 1>;
 169 defm : X86WriteRes<WriteBitTest,         [SKXPort06], 1, [1], 1>;
 170 defm : X86WriteRes<WriteBitTestImmLd,    [SKXPort06,SKXPort23], 6, [1,1], 2>;
 171 defm : X86WriteRes<WriteBitTestRegLd,    [SKXPort0156,SKXPort23], 6, [1,1], 2>;
 172 defm : X86WriteRes<WriteBitTestSet,      [SKXPort06], 1, [1], 1>;
 173 defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 5, [1,1], 3>;
 174 defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>;
 175
 176 // Integer shifts and rotates.
 177 defm : SKXWriteResPair<WriteShift,    [SKXPort06],  1>;
 178 defm : SKXWriteResPair<WriteShiftCL,  [SKXPort06],  3, [3], 3>;
 179 defm : SKXWriteResPair<WriteRotate,   [SKXPort06],  2, [2], 2>;
 180 defm : SKXWriteResPair<WriteRotateCL, [SKXPort06],  3, [3], 3>;
 181
 182 // SHLD/SHRD.
 183 defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;
 184 defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>;
 185 defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>;
 186 defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>;
 187
 188 // Bit counts.
 189 defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
 190 defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
 191 defm : SKXWriteResPair<WriteLZCNT,          [SKXPort1], 3>;
 192 defm : SKXWriteResPair<WriteTZCNT,          [SKXPort1], 3>;
 193 defm : SKXWriteResPair<WritePOPCNT,         [SKXPort1], 3>;
 194
 195 // BMI1 BEXTR/BLS, BMI2 BZHI
 196 defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;
 197 defm : SKXWriteResPair<WriteBLS,   [SKXPort15], 1>;
 198 defm : SKXWriteResPair<WriteBZHI,  [SKXPort15], 1>;
 199
 200 // Loads, stores, and moves, not folded with other operations.
 201 defm : X86WriteRes<WriteLoad,    [SKXPort23], 5, [1], 1>;
 202 defm : X86WriteRes<WriteStore,   [SKXPort237, SKXPort4], 1, [1,1], 1>;
 203 defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;
 204 defm : X86WriteRes<WriteMove,    [SKXPort0156], 1, [1], 1>;
 205
 206 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 207 // These can often bypass execution ports completely.
 208 def : WriteRes<WriteZero,  []>;
 209
 210 // Branches don't produce values, so they have no latency, but they still
 211 // consume resources. Indirect branches can fold loads.
 212 defm : SKXWriteResPair<WriteJump,  [SKXPort06],   1>;
 213
 214 // Floating point. This covers both scalar and vector operations.
 215 defm : X86WriteRes<WriteFLD0,          [SKXPort05], 1, [1], 1>;
 216 defm : X86WriteRes<WriteFLD1,          [SKXPort05], 1, [2], 2>;
 217 defm : X86WriteRes<WriteFLDC,          [SKXPort05], 1, [2], 2>;
 218 defm : X86WriteRes<WriteFLoad,         [SKXPort23], 5, [1], 1>;
 219 defm : X86WriteRes<WriteFLoadX,        [SKXPort23], 6, [1], 1>;
 220 defm : X86WriteRes<WriteFLoadY,        [SKXPort23], 7, [1], 1>;
 221 defm : X86WriteRes<WriteFMaskedLoad,   [SKXPort23,SKXPort015], 7, [1,1], 2>;
 222 defm : X86WriteRes<WriteFMaskedLoadY,  [SKXPort23,SKXPort015], 8, [1,1], 2>;
 223 defm : X86WriteRes<WriteFStore,        [SKXPort237,SKXPort4], 1, [1,1], 2>;
 224 defm : X86WriteRes<WriteFStoreX,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 225 defm : X86WriteRes<WriteFStoreY,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 226 defm : X86WriteRes<WriteFStoreNT,      [SKXPort237,SKXPort4], 1, [1,1], 2>;
 227 defm : X86WriteRes<WriteFStoreNTX,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 228 defm : X86WriteRes<WriteFStoreNTY,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 229 defm : X86WriteRes<WriteFMaskedStore,  [SKXPort237,SKXPort0], 2, [1,1], 2>;
 230 defm : X86WriteRes<WriteFMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
 231 defm : X86WriteRes<WriteFMove,         [SKXPort015], 1, [1], 1>;
 232 defm : X86WriteRes<WriteFMoveX,        [SKXPort015], 1, [1], 1>;
 233 defm : X86WriteRes<WriteFMoveY,        [SKXPort015], 1, [1], 1>;
 234 defm : X86WriteRes<WriteEMMS,          [SKXPort05,SKXPort0156], 10, [9,1], 10>;
 235
 236 defm : SKXWriteResPair<WriteFAdd,      [SKXPort01],  4, [1], 1, 5>; // Floating point add/sub.
 237 defm : SKXWriteResPair<WriteFAddX,     [SKXPort01],  4, [1], 1, 6>;
 238 defm : SKXWriteResPair<WriteFAddY,     [SKXPort01],  4, [1], 1, 7>;
 239 defm : SKXWriteResPair<WriteFAddZ,     [SKXPort05],  4, [1], 1, 7>;
 240 defm : SKXWriteResPair<WriteFAdd64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double add/sub.
 241 defm : SKXWriteResPair<WriteFAdd64X,   [SKXPort01],  4, [1], 1, 6>;
 242 defm : SKXWriteResPair<WriteFAdd64Y,   [SKXPort01],  4, [1], 1, 7>;
 243 defm : SKXWriteResPair<WriteFAdd64Z,   [SKXPort05],  4, [1], 1, 7>;
 244
 245 defm : SKXWriteResPair<WriteFCmp,      [SKXPort01],  4, [1], 1, 5>; // Floating point compare.
 246 defm : SKXWriteResPair<WriteFCmpX,     [SKXPort01],  4, [1], 1, 6>;
 247 defm : SKXWriteResPair<WriteFCmpY,     [SKXPort01],  4, [1], 1, 7>;
 248 defm : SKXWriteResPair<WriteFCmpZ,     [SKXPort05],  4, [1], 1, 7>;
 249 defm : SKXWriteResPair<WriteFCmp64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double compare.
 250 defm : SKXWriteResPair<WriteFCmp64X,   [SKXPort01],  4, [1], 1, 6>;
 251 defm : SKXWriteResPair<WriteFCmp64Y,   [SKXPort01],  4, [1], 1, 7>;
 252 defm : SKXWriteResPair<WriteFCmp64Z,   [SKXPort05],  4, [1], 1, 7>;
 253
 254 defm : SKXWriteResPair<WriteFCom,       [SKXPort0],  2>; // Floating point compare to flags.
 255
 256 defm : SKXWriteResPair<WriteFMul,      [SKXPort01],  4, [1], 1, 5>; // Floating point multiplication.
 257 defm : SKXWriteResPair<WriteFMulX,     [SKXPort01],  4, [1], 1, 6>;
 258 defm : SKXWriteResPair<WriteFMulY,     [SKXPort01],  4, [1], 1, 7>;
 259 defm : SKXWriteResPair<WriteFMulZ,     [SKXPort05],  4, [1], 1, 7>;
 260 defm : SKXWriteResPair<WriteFMul64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double multiplication.
 261 defm : SKXWriteResPair<WriteFMul64X,   [SKXPort01],  4, [1], 1, 6>;
 262 defm : SKXWriteResPair<WriteFMul64Y,   [SKXPort01],  4, [1], 1, 7>;
 263 defm : SKXWriteResPair<WriteFMul64Z,   [SKXPort05],  4, [1], 1, 7>;
 264
 265 defm : SKXWriteResPair<WriteFDiv,     [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
 266 //defm : SKXWriteResPair<WriteFDivX,    [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles.
 267 defm : SKXWriteResPair<WriteFDivY,    [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.
 268 defm : SKXWriteResPair<WriteFDivZ,    [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles.
 269 //defm : SKXWriteResPair<WriteFDiv64,   [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
 270 //defm : SKXWriteResPair<WriteFDiv64X,  [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles.
 271 //defm : SKXWriteResPair<WriteFDiv64Y,  [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles.
 272 defm : SKXWriteResPair<WriteFDiv64Z,  [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles.
 273
 274 defm : SKXWriteResPair<WriteFSqrt,    [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
 275 defm : SKXWriteResPair<WriteFSqrtX,   [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>;
 276 defm : SKXWriteResPair<WriteFSqrtY,   [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;
 277 defm : SKXWriteResPair<WriteFSqrtZ,   [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;
 278 defm : SKXWriteResPair<WriteFSqrt64,  [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
 279 defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>;
 280 defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;
 281 defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;
 282 defm : SKXWriteResPair<WriteFSqrt80,  [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root.
 283
 284 defm : SKXWriteResPair<WriteFRcp,   [SKXPort0],  4, [1], 1, 5>; // Floating point reciprocal estimate.
 285 defm : SKXWriteResPair<WriteFRcpX,  [SKXPort0],  4, [1], 1, 6>;
 286 defm : SKXWriteResPair<WriteFRcpY,  [SKXPort0],  4, [1], 1, 7>;
 287 defm : SKXWriteResPair<WriteFRcpZ,  [SKXPort0,SKXPort5],  4, [2,1], 3, 7>;
 288
 289 defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0],  4, [1], 1, 5>; // Floating point reciprocal square root estimate.
 290 defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0],  4, [1], 1, 6>;
 291 defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0],  4, [1], 1, 7>;
 292 defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5],  9, [2,1], 3, 7>;
 293
 294 defm : SKXWriteResPair<WriteFMA,  [SKXPort01],  4, [1], 1, 5>; // Fused Multiply Add.
 295 defm : SKXWriteResPair<WriteFMAX, [SKXPort01],  4, [1], 1, 6>;
 296 defm : SKXWriteResPair<WriteFMAY, [SKXPort01],  4, [1], 1, 7>;
 297 defm : SKXWriteResPair<WriteFMAZ, [SKXPort05],  4, [1], 1, 7>;
 298 defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015],  9, [1,2], 3, 6>; // Floating point double dot product.
 299 defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>;
 300 defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
 301 defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
 302 defm : SKXWriteResPair<WriteFSign,  [SKXPort0],  1>; // Floating point fabs/fchs.
 303 defm : SKXWriteResPair<WriteFRnd,   [SKXPort01], 8, [2], 2, 6>; // Floating point rounding.
 304 defm : SKXWriteResPair<WriteFRndY,  [SKXPort01], 8, [2], 2, 7>;
 305 defm : SKXWriteResPair<WriteFRndZ,  [SKXPort05], 8, [2], 2, 7>;
 306 defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
 307 defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;
 308 defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;
 309 defm : SKXWriteResPair<WriteFTest,  [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
 310 defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;
 311 defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;
 312 defm : SKXWriteResPair<WriteFShuffle,  [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 313 defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;
 314 defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 315 defm : SKXWriteResPair<WriteFVarShuffle,  [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
 316 defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
 317 defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 318 defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends.
 319 defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;
 320 defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;
 321 defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends.
 322 defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;
 323 defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;
 324
 325 // FMA Scheduling helper class.
 326 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 327
 328 // Vector integer operations.
 329 defm : X86WriteRes<WriteVecLoad,         [SKXPort23], 5, [1], 1>;
 330 defm : X86WriteRes<WriteVecLoadX,        [SKXPort23], 6, [1], 1>;
 331 defm : X86WriteRes<WriteVecLoadY,        [SKXPort23], 7, [1], 1>;
 332 defm : X86WriteRes<WriteVecLoadNT,       [SKXPort23], 6, [1], 1>;
 333 defm : X86WriteRes<WriteVecLoadNTY,      [SKXPort23], 7, [1], 1>;
 334 defm : X86WriteRes<WriteVecMaskedLoad,   [SKXPort23,SKXPort015], 7, [1,1], 2>;
 335 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKXPort23,SKXPort015], 8, [1,1], 2>;
 336 defm : X86WriteRes<WriteVecStore,        [SKXPort237,SKXPort4], 1, [1,1], 2>;
 337 defm : X86WriteRes<WriteVecStoreX,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 338 defm : X86WriteRes<WriteVecStoreY,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 339 defm : X86WriteRes<WriteVecStoreNT,      [SKXPort237,SKXPort4], 1, [1,1], 2>;
 340 defm : X86WriteRes<WriteVecStoreNTY,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 341 defm : X86WriteRes<WriteVecMaskedStore,  [SKXPort237,SKXPort0], 2, [1,1], 2>;
 342 defm : X86WriteRes<WriteVecMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
 343 defm : X86WriteRes<WriteVecMove,         [SKXPort05],  1, [1], 1>;
 344 defm : X86WriteRes<WriteVecMoveX,        [SKXPort015], 1, [1], 1>;
 345 defm : X86WriteRes<WriteVecMoveY,        [SKXPort015], 1, [1], 1>;
 346 defm : X86WriteRes<WriteVecMoveToGpr,    [SKXPort0], 2, [1], 1>;
 347 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKXPort5], 1, [1], 1>;
 348
 349 defm : SKXWriteResPair<WriteVecALU,   [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 350 defm : SKXWriteResPair<WriteVecALUX,  [SKXPort01], 1, [1], 1, 6>;
 351 defm : SKXWriteResPair<WriteVecALUY,  [SKXPort01], 1, [1], 1, 7>;
 352 defm : SKXWriteResPair<WriteVecALUZ,  [SKXPort0], 1, [1], 1, 7>;
 353 defm : SKXWriteResPair<WriteVecLogic, [SKXPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
 354 defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>;
 355 defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;
 356 defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;
 357 defm : SKXWriteResPair<WriteVecTest,  [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
 358 defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
 359 defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
 360 defm : SKXWriteResPair<WriteVecIMul,  [SKXPort0],    4, [1], 1, 5>; // Vector integer multiply.
 361 defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01],  4, [1], 1, 6>;
 362 defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01],  4, [1], 1, 7>;
 363 defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05],  4, [1], 1, 7>;
 364 defm : SKXWriteResPair<WritePMULLD,   [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD.
 365 defm : SKXWriteResPair<WritePMULLDY,  [SKXPort01], 10, [2], 2, 7>;
 366 defm : SKXWriteResPair<WritePMULLDZ,  [SKXPort05], 10, [2], 2, 7>;
 367 defm : SKXWriteResPair<WriteShuffle,  [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.
 368 defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>;
 369 defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;
 370 defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 371 defm : SKXWriteResPair<WriteVarShuffle,  [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 372 defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>;
 373 defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
 374 defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 375 defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
 376 defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;
 377 defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;
 378 defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
 379 defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>;
 380 defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05],  2, [1], 1, 6>;
 381 defm : SKXWriteResPair<WriteMPSAD,   [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
 382 defm : SKXWriteResPair<WriteMPSADY,  [SKXPort5], 4, [2], 2, 7>;
 383 defm : SKXWriteResPair<WriteMPSADZ,  [SKXPort5], 4, [2], 2, 7>;
 384 defm : SKXWriteResPair<WritePSADBW,  [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW.
 385 defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>;
 386 defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;
 387 defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>;
 388 defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
 389
 390 // Vector integer shifts.
 391 defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>;
 392 defm : X86WriteRes<WriteVecShiftX,    [SKXPort5,SKXPort01],  2, [1,1], 2>;
 393 defm : X86WriteRes<WriteVecShiftY,    [SKXPort5,SKXPort01],  4, [1,1], 2>;
 394 defm : X86WriteRes<WriteVecShiftZ,    [SKXPort5,SKXPort0],   4, [1,1], 2>;
 395 defm : X86WriteRes<WriteVecShiftXLd,  [SKXPort01,SKXPort23], 7, [1,1], 2>;
 396 defm : X86WriteRes<WriteVecShiftYLd,  [SKXPort01,SKXPort23], 8, [1,1], 2>;
 397 defm : X86WriteRes<WriteVecShiftZLd,  [SKXPort0,SKXPort23],  8, [1,1], 2>;
 398
 399 defm : SKXWriteResPair<WriteVecShiftImm,  [SKXPort0],  1, [1], 1, 5>;
 400 defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts.
 401 defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;
 402 defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;
 403 defm : SKXWriteResPair<WriteVarVecShift,  [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.
 404 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
 405 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
 406
 407 // Vector insert/extract operations.
 408 def : WriteRes<WriteVecInsert, [SKXPort5]> {
 409   let Latency = 2;
 410   let NumMicroOps = 2;
 411   let ResourceCycles = [2];
 412 }
 413 def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
 414   let Latency = 6;
 415   let NumMicroOps = 2;
 416 }
 417 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 418
 419 def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {
 420   let Latency = 3;
 421   let NumMicroOps = 2;
 422 }
 423 def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> {
 424   let Latency = 2;
 425   let NumMicroOps = 3;
 426 }
 427
 428 // Conversion between integer and float.
 429 defm : SKXWriteResPair<WriteCvtSS2I,   [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
 430 defm : SKXWriteResPair<WriteCvtPS2I,   [SKXPort01], 3>;
 431 defm : SKXWriteResPair<WriteCvtPS2IY,  [SKXPort01], 3>;
 432 defm : SKXWriteResPair<WriteCvtPS2IZ,  [SKXPort05], 3>;
 433 defm : SKXWriteResPair<WriteCvtSD2I,   [SKXPort01], 6, [2], 2>;
 434 defm : SKXWriteResPair<WriteCvtPD2I,   [SKXPort01], 3>;
 435 defm : SKXWriteResPair<WriteCvtPD2IY,  [SKXPort01], 3>;
 436 defm : SKXWriteResPair<WriteCvtPD2IZ,  [SKXPort05], 3>;
 437
 438 defm : SKXWriteResPair<WriteCvtI2SS,   [SKXPort1], 4>;
 439 defm : SKXWriteResPair<WriteCvtI2PS,   [SKXPort01], 4>;
 440 defm : SKXWriteResPair<WriteCvtI2PSY,  [SKXPort01], 4>;
 441 defm : SKXWriteResPair<WriteCvtI2PSZ,  [SKXPort05], 4>;  // Needs more work: DD vs DQ.
 442 defm : SKXWriteResPair<WriteCvtI2SD,   [SKXPort1], 4>;
 443 defm : SKXWriteResPair<WriteCvtI2PD,   [SKXPort01], 4>;
 444 defm : SKXWriteResPair<WriteCvtI2PDY,  [SKXPort01], 4>;
 445 defm : SKXWriteResPair<WriteCvtI2PDZ,  [SKXPort05], 4>;
 446
 447 defm : SKXWriteResPair<WriteCvtSS2SD,  [SKXPort1], 3>;
 448 defm : SKXWriteResPair<WriteCvtPS2PD,  [SKXPort1], 3>;
 449 defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
 450 defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>;
 451 defm : SKXWriteResPair<WriteCvtSD2SS,  [SKXPort1], 3>;
 452 defm : SKXWriteResPair<WriteCvtPD2PS,  [SKXPort1], 3>;
 453 defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
 454 defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>;
 455
 456 defm : X86WriteRes<WriteCvtPH2PS,     [SKXPort5,SKXPort01],  5, [1,1], 2>;
 457 defm : X86WriteRes<WriteCvtPH2PSY,    [SKXPort5,SKXPort01],  7, [1,1], 2>;
 458 defm : X86WriteRes<WriteCvtPH2PSZ,    [SKXPort5,SKXPort0],   7, [1,1], 2>;
 459 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKXPort23,SKXPort01],  9, [1,1], 2>;
 460 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>;
 461 defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>;
 462
 463 defm : X86WriteRes<WriteCvtPS2PH,    [SKXPort5,SKXPort01], 5, [1,1], 2>;
 464 defm : X86WriteRes<WriteCvtPS2PHY,   [SKXPort5,SKXPort01], 7, [1,1], 2>;
 465 defm : X86WriteRes<WriteCvtPS2PHZ,   [SKXPort5,SKXPort05], 7, [1,1], 2>;
 466 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>;
 467 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>;
 468 defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;
 469
 470 // Strings instructions.
 471
 472 // Packed Compare Implicit Length Strings, Return Mask
 473 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
 474   let Latency = 10;
 475   let NumMicroOps = 3;
 476   let ResourceCycles = [3];
 477 }
 478 def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
 479   let Latency = 16;
 480   let NumMicroOps = 4;
 481   let ResourceCycles = [3,1];
 482 }
 483
 484 // Packed Compare Explicit Length Strings, Return Mask
 485 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
 486   let Latency = 19;
 487   let NumMicroOps = 9;
 488   let ResourceCycles = [4,3,1,1];
 489 }
 490 def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
 491   let Latency = 25;
 492   let NumMicroOps = 10;
 493   let ResourceCycles = [4,3,1,1,1];
 494 }
 495
 496 // Packed Compare Implicit Length Strings, Return Index
 497 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
 498   let Latency = 10;
 499   let NumMicroOps = 3;
 500   let ResourceCycles = [3];
 501 }
 502 def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
 503   let Latency = 16;
 504   let NumMicroOps = 4;
 505   let ResourceCycles = [3,1];
 506 }
 507
 508 // Packed Compare Explicit Length Strings, Return Index
 509 def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
 510   let Latency = 18;
 511   let NumMicroOps = 8;
 512   let ResourceCycles = [4,3,1];
 513 }
 514 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
 515   let Latency = 24;
 516   let NumMicroOps = 9;
 517   let ResourceCycles = [4,3,1,1];
 518 }
 519
 520 // MOVMSK Instructions.
 521 def : WriteRes<WriteFMOVMSK,    [SKXPort0]> { let Latency = 2; }
 522 def : WriteRes<WriteVecMOVMSK,  [SKXPort0]> { let Latency = 2; }
 523 def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }
 524 def : WriteRes<WriteMMXMOVMSK,  [SKXPort0]> { let Latency = 2; }
 525
 526 // AES instructions.
 527 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
 528   let Latency = 4;
 529   let NumMicroOps = 1;
 530   let ResourceCycles = [1];
 531 }
 532 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
 533   let Latency = 10;
 534   let NumMicroOps = 2;
 535   let ResourceCycles = [1,1];
 536 }
 537
 538 def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
 539   let Latency = 8;
 540   let NumMicroOps = 2;
 541   let ResourceCycles = [2];
 542 }
 543 def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
 544   let Latency = 14;
 545   let NumMicroOps = 3;
 546   let ResourceCycles = [2,1];
 547 }
 548
 549 def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
 550   let Latency = 20;
 551   let NumMicroOps = 11;
 552   let ResourceCycles = [3,6,2];
 553 }
 554 def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
 555   let Latency = 25;
 556   let NumMicroOps = 11;
 557   let ResourceCycles = [3,6,1,1];
 558 }
 559
 560 // Carry-less multiplication instructions.
 561 def : WriteRes<WriteCLMul, [SKXPort5]> {
 562   let Latency = 6;
 563   let NumMicroOps = 1;
 564   let ResourceCycles = [1];
 565 }
 566 def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
 567   let Latency = 12;
 568   let NumMicroOps = 2;
 569   let ResourceCycles = [1,1];
 570 }
 571
 572 // Catch-all for expensive system instructions.
 573 def : WriteRes<WriteSystem,     [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 574
 575 // AVX2.
 576 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 577 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 578 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 579 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 580
 581 // Old microcoded instructions that nobody use.
 582 def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 583
 584 // Fence instructions.
 585 def : WriteRes<WriteFence,  [SKXPort23, SKXPort4]>;
 586
 587 // Load/store MXCSR.
 588 def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 589 def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 590
 591 // Nop, not very useful expect it provides a model for nops!
 592 def : WriteRes<WriteNop, []>;
 593
 594 ////////////////////////////////////////////////////////////////////////////////
 595 // Horizontal add/sub  instructions.
 596 ////////////////////////////////////////////////////////////////////////////////
 597
 598 defm : SKXWriteResPair<WriteFHAdd,  [SKXPort5,SKXPort015], 6, [2,1], 3, 6>;
 599 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>;
 600 defm : SKXWriteResPair<WritePHAdd,  [SKXPort5,SKXPort05],  3, [2,1], 3, 5>;
 601 defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;
 602 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
 603
 604 // Remaining instrs.
 605
 606 def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
 607   let Latency = 1;
 608   let NumMicroOps = 1;
 609   let ResourceCycles = [1];
 610 }
 611 def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
 612                                             "KANDN(B|D|Q|W)rr",
 613                                             "KMOV(B|D|Q|W)kk",
 614                                             "KNOT(B|D|Q|W)rr",
 615                                             "KOR(B|D|Q|W)rr",
 616                                             "KXNOR(B|D|Q|W)rr",
 617                                             "KXOR(B|D|Q|W)rr",
 618                                             "MMX_PADDS(B|W)irr",
 619                                             "MMX_PADDUS(B|W)irr",
 620                                             "MMX_PAVG(B|W)irr",
 621                                             "MMX_PCMPEQ(B|D|W)irr",
 622                                             "MMX_PCMPGT(B|D|W)irr",
 623                                             "MMX_P(MAX|MIN)SWirr",
 624                                             "MMX_P(MAX|MIN)UBirr",
 625                                             "MMX_PSUBS(B|W)irr",
 626                                             "MMX_PSUBUS(B|W)irr",
 627                                             "VPMOVB2M(Z|Z128|Z256)rr",
 628                                             "VPMOVD2M(Z|Z128|Z256)rr",
 629                                             "VPMOVQ2M(Z|Z128|Z256)rr",
 630                                             "VPMOVW2M(Z|Z128|Z256)rr")>;
 631
 632 def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
 633   let Latency = 1;
 634   let NumMicroOps = 1;
 635   let ResourceCycles = [1];
 636 }
 637 def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
 638                                             "KMOV(B|D|Q|W)kr",
 639                                             "UCOM_F(P?)r")>;
 640
 641 def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
 642   let Latency = 1;
 643   let NumMicroOps = 1;
 644   let ResourceCycles = [1];
 645 }
 646 def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 647
 648 def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
 649   let Latency = 1;
 650   let NumMicroOps = 1;
 651   let ResourceCycles = [1];
 652 }
 653 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
 654
 655 def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
 656   let Latency = 1;
 657   let NumMicroOps = 1;
 658   let ResourceCycles = [1];
 659 }
 660 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 661
 662 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
 663   let Latency = 1;
 664   let NumMicroOps = 1;
 665   let ResourceCycles = [1];
 666 }
 667 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 668
 669 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
 670   let Latency = 1;
 671   let NumMicroOps = 1;
 672   let ResourceCycles = [1];
 673 }
 674 def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
 675                                             "VBLENDMPS(Z128|Z256)rr",
 676                                             "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
 677                                             "(V?)PADD(B|D|Q|W)rr",
 678                                             "VPBLENDD(Y?)rri",
 679                                             "VPBLENDMB(Z128|Z256)rr",
 680                                             "VPBLENDMD(Z128|Z256)rr",
 681                                             "VPBLENDMQ(Z128|Z256)rr",
 682                                             "VPBLENDMW(Z128|Z256)rr",
 683                                             "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rr",
 684                                             "(V?)PSUB(B|D|Q|W)rr",
 685                                             "VPTERNLOGD(Z|Z128|Z256)rri",
 686                                             "VPTERNLOGQ(Z|Z128|Z256)rri")>;
 687
 688 def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
 689   let Latency = 1;
 690   let NumMicroOps = 1;
 691   let ResourceCycles = [1];
 692 }
 693 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
 694                                           CMC, STC,
 695                                           SGDT64m,
 696                                           SIDT64m,
 697                                           SMSW16m,
 698                                           STRm,
 699                                           SYSCALL)>;
 700
 701 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
 702   let Latency = 1;
 703   let NumMicroOps = 2;
 704   let ResourceCycles = [1,1];
 705 }
 706 def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
 707 def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
 708                                              "ST_FP(32|64|80)m")>;
 709
 710 def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
 711   let Latency = 2;
 712   let NumMicroOps = 2;
 713   let ResourceCycles = [2];
 714 }
 715 def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
 716
 717 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
 718   let Latency = 2;
 719   let NumMicroOps = 2;
 720   let ResourceCycles = [2];
 721 }
 722 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
 723                                           MMX_MOVDQ2Qrr)>;
 724
 725 def SKXWriteResGroup15 : SchedWriteRes<[SKXPort06]> {
 726   let Latency = 2;
 727   let NumMicroOps = 2;
 728   let ResourceCycles = [2];
 729 }
 730 def: InstRW<[SKXWriteResGroup15], (instregex "SET(A|BE)r")>;
 731
 732 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
 733   let Latency = 2;
 734   let NumMicroOps = 2;
 735   let ResourceCycles = [2];
 736 }
 737 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
 738                                           WAIT,
 739                                           XGETBV)>;
 740
 741 def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
 742   let Latency = 2;
 743   let NumMicroOps = 2;
 744   let ResourceCycles = [1,1];
 745 }
 746 def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
 747
 748 def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
 749   let Latency = 2;
 750   let NumMicroOps = 2;
 751   let ResourceCycles = [1,1];
 752 }
 753 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
 754
 755 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
 756   let Latency = 2;
 757   let NumMicroOps = 2;
 758   let ResourceCycles = [1,1];
 759 }
 760 def: InstRW<[SKXWriteResGroup23], (instrs CWD,
 761                                           JCXZ, JECXZ, JRCXZ,
 762                                           ADC8i8, SBB8i8)>;
 763 def: InstRW<[SKXWriteResGroup23], (instregex "ADC8ri",
 764                                              "SBB8ri")>;
 765
 766 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
 767   let Latency = 2;
 768   let NumMicroOps = 3;
 769   let ResourceCycles = [1,1,1];
 770 }
 771 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
 772
 773 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
 774   let Latency = 2;
 775   let NumMicroOps = 3;
 776   let ResourceCycles = [1,1,1];
 777 }
 778 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 779
 780 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
 781   let Latency = 2;
 782   let NumMicroOps = 3;
 783   let ResourceCycles = [1,1,1];
 784 }
 785 def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
 786                                           STOSB, STOSL, STOSQ, STOSW)>;
 787 def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
 788
 789 def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
 790   let Latency = 2;
 791   let NumMicroOps = 5;
 792   let ResourceCycles = [2,2,1];
 793 }
 794 def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
 795
 796 def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
 797   let Latency = 3;
 798   let NumMicroOps = 1;
 799   let ResourceCycles = [1];
 800 }
 801 def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
 802                                              "KORTEST(B|D|Q|W)rr",
 803                                              "KTEST(B|D|Q|W)rr")>;
 804
 805 def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
 806   let Latency = 3;
 807   let NumMicroOps = 1;
 808   let ResourceCycles = [1];
 809 }
 810 def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
 811                                              "PEXT(32|64)rr")>;
 812
 813 def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
 814   let Latency = 3;
 815   let NumMicroOps = 1;
 816   let ResourceCycles = [1];
 817 }
 818 def: InstRW<[SKXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined.
 819 def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
 820                                              "KADD(B|D|Q|W)rr",
 821                                              "KSHIFTL(B|D|Q|W)ri",
 822                                              "KSHIFTR(B|D|Q|W)ri",
 823                                              "KUNPCK(BW|DQ|WD)rr",
 824                                              "VALIGND(Z|Z128|Z256)rri",
 825                                              "VALIGNQ(Z|Z128|Z256)rri",
 826                                              "VCMPPD(Z|Z128|Z256)rri",
 827                                              "VCMPPS(Z|Z128|Z256)rri",
 828                                              "VCMP(SD|SS)Zrr",
 829                                              "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined.
 830                                              "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
 831                                              "VFPCLASS(SD|SS)Zrr",
 832                                              "VPBROADCAST(B|W)rr",
 833                                              "VPCMPB(Z|Z128|Z256)rri",
 834                                              "VPCMPD(Z|Z128|Z256)rri",
 835                                              "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
 836                                              "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
 837                                              "(V?)PCMPGTQ(Y?)rr",
 838                                              "VPCMPQ(Z|Z128|Z256)rri",
 839                                              "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
 840                                              "VPCMPW(Z|Z128|Z256)rri",
 841                                              "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr",
 842                                              "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
 843
 844 def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
 845   let Latency = 3;
 846   let NumMicroOps = 2;
 847   let ResourceCycles = [1,1];
 848 }
 849 def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
 850
 851 def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
 852   let Latency = 3;
 853   let NumMicroOps = 3;
 854   let ResourceCycles = [1,2];
 855 }
 856 def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 857
 858 def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
 859   let Latency = 3;
 860   let NumMicroOps = 3;
 861   let ResourceCycles = [2,1];
 862 }
 863 def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
 864
 865 def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
 866   let Latency = 3;
 867   let NumMicroOps = 3;
 868   let ResourceCycles = [2,1];
 869 }
 870 def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWirr,
 871                                           MMX_PACKSSWBirr,
 872                                           MMX_PACKUSWBirr)>;
 873
 874 def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
 875   let Latency = 3;
 876   let NumMicroOps = 3;
 877   let ResourceCycles = [1,2];
 878 }
 879 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
 880
 881 def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
 882   let Latency = 3;
 883   let NumMicroOps = 3;
 884   let ResourceCycles = [1,2];
 885 }
 886 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
 887
 888 def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
 889   let Latency = 3;
 890   let NumMicroOps = 3;
 891   let ResourceCycles = [1,2];
 892 }
 893 def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)",
 894                                              "RCR(8|16|32|64)r(1|i)")>;
 895
 896 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
 897   let Latency = 3;
 898   let NumMicroOps = 3;
 899   let ResourceCycles = [1,1,1];
 900 }
 901 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
 902
 903 def SKXWriteResGroup46 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
 904   let Latency = 3;
 905   let NumMicroOps = 4;
 906   let ResourceCycles = [1,1,2];
 907 }
 908 def: InstRW<[SKXWriteResGroup46], (instregex "SET(A|BE)m")>;
 909
 910 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
 911   let Latency = 3;
 912   let NumMicroOps = 4;
 913   let ResourceCycles = [1,1,1,1];
 914 }
 915 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
 916
 917 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
 918   let Latency = 3;
 919   let NumMicroOps = 4;
 920   let ResourceCycles = [1,1,1,1];
 921 }
 922 def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
 923
 924 def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
 925   let Latency = 4;
 926   let NumMicroOps = 1;
 927   let ResourceCycles = [1];
 928 }
 929 def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 930
 931 def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
 932   let Latency = 4;
 933   let NumMicroOps = 1;
 934   let ResourceCycles = [1];
 935 }
 936 def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr",
 937                                              "(V?)CVTDQ2PSrr",
 938                                              "VCVTPD2QQ(Z128|Z256)rr",
 939                                              "VCVTPD2UQQ(Z128|Z256)rr",
 940                                              "VCVTPS2DQ(Y|Z128|Z256)rr",
 941                                              "(V?)CVTPS2DQrr",
 942                                              "VCVTPS2UDQ(Z128|Z256)rr",
 943                                              "VCVTQQ2PD(Z128|Z256)rr",
 944                                              "VCVTTPD2QQ(Z128|Z256)rr",
 945                                              "VCVTTPD2UQQ(Z128|Z256)rr",
 946                                              "VCVTTPS2DQ(Z128|Z256)rr",
 947                                              "(V?)CVTTPS2DQrr",
 948                                              "VCVTTPS2UDQ(Z128|Z256)rr",
 949                                              "VCVTUDQ2PS(Z128|Z256)rr",
 950                                              "VCVTUQQ2PD(Z128|Z256)rr")>;
 951
 952 def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
 953   let Latency = 4;
 954   let NumMicroOps = 1;
 955   let ResourceCycles = [1];
 956 }
 957 def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
 958                                            VCVTPD2QQZrr,
 959                                            VCVTPD2UQQZrr,
 960                                            VCVTPS2DQZrr,
 961                                            VCVTPS2UDQZrr,
 962                                            VCVTQQ2PDZrr,
 963                                            VCVTTPD2QQZrr,
 964                                            VCVTTPD2UQQZrr,
 965                                            VCVTTPS2DQZrr,
 966                                            VCVTTPS2UDQZrr,
 967                                            VCVTUDQ2PSZrr,
 968                                            VCVTUQQ2PDZrr)>;
 969
 970 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
 971   let Latency = 4;
 972   let NumMicroOps = 2;
 973   let ResourceCycles = [2];
 974 }
 975 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
 976                                              "VEXPANDPS(Z|Z128|Z256)rr",
 977                                              "VPEXPANDD(Z|Z128|Z256)rr",
 978                                              "VPEXPANDQ(Z|Z128|Z256)rr",
 979                                              "VPMOVDB(Z|Z128|Z256)rr",
 980                                              "VPMOVDW(Z|Z128|Z256)rr",
 981                                              "VPMOVQB(Z|Z128|Z256)rr",
 982                                              "VPMOVQW(Z|Z128|Z256)rr",
 983                                              "VPMOVSDB(Z|Z128|Z256)rr",
 984                                              "VPMOVSDW(Z|Z128|Z256)rr",
 985                                              "VPMOVSQB(Z|Z128|Z256)rr",
 986                                              "VPMOVSQD(Z|Z128|Z256)rr",
 987                                              "VPMOVSQW(Z|Z128|Z256)rr",
 988                                              "VPMOVSWB(Z|Z128|Z256)rr",
 989                                              "VPMOVUSDB(Z|Z128|Z256)rr",
 990                                              "VPMOVUSDW(Z|Z128|Z256)rr",
 991                                              "VPMOVUSQB(Z|Z128|Z256)rr",
 992                                              "VPMOVUSQD(Z|Z128|Z256)rr",
 993                                              "VPMOVUSWB(Z|Z128|Z256)rr",
 994                                              "VPMOVWB(Z|Z128|Z256)rr")>;
 995
 996 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
 997   let Latency = 4;
 998   let NumMicroOps = 3;
 999   let ResourceCycles = [1,1,1];
1000 }
1001 def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
1002                                              "IST_F(16|32)m",
1003                                              "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
1004
1005 def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
1006   let Latency = 4;
1007   let NumMicroOps = 4;
1008   let ResourceCycles = [4];
1009 }
1010 def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
1011
1012 def SKXWriteResGroup56 : SchedWriteRes<[]> {
1013   let Latency = 0;
1014   let NumMicroOps = 4;
1015   let ResourceCycles = [];
1016 }
1017 def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
1018
1019 def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
1020   let Latency = 4;
1021   let NumMicroOps = 4;
1022   let ResourceCycles = [1,1,2];
1023 }
1024 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1025
1026 def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> {
1027   let Latency = 5;
1028   let NumMicroOps = 1;
1029   let ResourceCycles = [1];
1030 }
1031 def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
1032                                              "MOVZX(16|32|64)rm(8|16)",
1033                                              "(V?)MOVDDUPrm")>;  // TODO: Should this be SKXWriteResGroup71?
1034
1035 def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1036   let Latency = 5;
1037   let NumMicroOps = 2;
1038   let ResourceCycles = [1,1];
1039 }
1040 def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr",
1041                                              "MMX_CVT(T?)PS2PIirr",
1042                                              "VCVTDQ2PDZ128rr",
1043                                              "VCVTPD2DQZ128rr",
1044                                              "(V?)CVT(T?)PD2DQrr",
1045                                              "VCVTPD2PSZ128rr",
1046                                              "(V?)CVTPD2PSrr",
1047                                              "VCVTPD2UDQZ128rr",
1048                                              "VCVTPS2PDZ128rr",
1049                                              "(V?)CVTPS2PDrr",
1050                                              "VCVTPS2QQZ128rr",
1051                                              "VCVTPS2UQQZ128rr",
1052                                              "VCVTQQ2PSZ128rr",
1053                                              "(V?)CVTSD2SS(Z?)rr",
1054                                              "(V?)CVTSI(64)?2SDrr",
1055                                              "VCVTSI2SSZrr",
1056                                              "(V?)CVTSI2SSrr",
1057                                              "VCVTSI(64)?2SDZrr",
1058                                              "VCVTSS2SDZrr",
1059                                              "(V?)CVTSS2SDrr",
1060                                              "VCVTTPD2DQZ128rr",
1061                                              "VCVTTPD2UDQZ128rr",
1062                                              "VCVTTPS2QQZ128rr",
1063                                              "VCVTTPS2UQQZ128rr",
1064                                              "VCVTUDQ2PDZ128rr",
1065                                              "VCVTUQQ2PSZ128rr",
1066                                              "VCVTUSI2SSZrr",
1067                                              "VCVTUSI(64)?2SDZrr")>;
1068
1069 def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1070   let Latency = 5;
1071   let NumMicroOps = 3;
1072   let ResourceCycles = [2,1];
1073 }
1074 def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
1075
1076 def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
1077   let Latency = 5;
1078   let NumMicroOps = 3;
1079   let ResourceCycles = [1,1,1];
1080 }
1081 def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
1082
1083 def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> {
1084   let Latency = 5;
1085   let NumMicroOps = 3;
1086   let ResourceCycles = [1,1,1];
1087 }
1088 def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
1089                                              "VCVTPS2PHZ256mr(b?)",
1090                                              "VCVTPS2PHZmr(b?)")>;
1091
1092 def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1093   let Latency = 5;
1094   let NumMicroOps = 4;
1095   let ResourceCycles = [1,2,1];
1096 }
1097 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
1098                                              "VPMOVDW(Z|Z128|Z256)mr(b?)",
1099                                              "VPMOVQB(Z|Z128|Z256)mr(b?)",
1100                                              "VPMOVQW(Z|Z128|Z256)mr(b?)",
1101                                              "VPMOVSDB(Z|Z128|Z256)mr(b?)",
1102                                              "VPMOVSDW(Z|Z128|Z256)mr(b?)",
1103                                              "VPMOVSQB(Z|Z128|Z256)mr(b?)",
1104                                              "VPMOVSQD(Z|Z128|Z256)mr(b?)",
1105                                              "VPMOVSQW(Z|Z128|Z256)mr(b?)",
1106                                              "VPMOVSWB(Z|Z128|Z256)mr(b?)",
1107                                              "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
1108                                              "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
1109                                              "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
1110                                              "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
1111                                              "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
1112                                              "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
1113                                              "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
1114
1115 def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1116   let Latency = 5;
1117   let NumMicroOps = 5;
1118   let ResourceCycles = [1,4];
1119 }
1120 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
1121
1122 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
1123   let Latency = 5;
1124   let NumMicroOps = 6;
1125   let ResourceCycles = [1,1,4];
1126 }
1127 def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
1128
1129 def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
1130   let Latency = 6;
1131   let NumMicroOps = 1;
1132   let ResourceCycles = [1];
1133 }
1134 def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm,
1135                                           VPBROADCASTDrm,
1136                                           VPBROADCASTQrm,
1137                                           VMOVSHDUPrm,
1138                                           VMOVSLDUPrm,
1139                                           MOVSHDUPrm,
1140                                           MOVSLDUPrm)>;
1141
1142 def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
1143   let Latency = 6;
1144   let NumMicroOps = 2;
1145   let ResourceCycles = [2];
1146 }
1147 def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>;
1148 def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
1149                                              "VCOMPRESSPS(Z|Z128|Z256)rr",
1150                                              "VPCOMPRESSD(Z|Z128|Z256)rr",
1151                                              "VPCOMPRESSQ(Z|Z128|Z256)rr",
1152                                              "VPERMW(Z|Z128|Z256)rr")>;
1153
1154 def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1155   let Latency = 6;
1156   let NumMicroOps = 2;
1157   let ResourceCycles = [1,1];
1158 }
1159 def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBirm,
1160                                           MMX_PADDSWirm,
1161                                           MMX_PADDUSBirm,
1162                                           MMX_PADDUSWirm,
1163                                           MMX_PAVGBirm,
1164                                           MMX_PAVGWirm,
1165                                           MMX_PCMPEQBirm,
1166                                           MMX_PCMPEQDirm,
1167                                           MMX_PCMPEQWirm,
1168                                           MMX_PCMPGTBirm,
1169                                           MMX_PCMPGTDirm,
1170                                           MMX_PCMPGTWirm,
1171                                           MMX_PMAXSWirm,
1172                                           MMX_PMAXUBirm,
1173                                           MMX_PMINSWirm,
1174                                           MMX_PMINUBirm,
1175                                           MMX_PSUBSBirm,
1176                                           MMX_PSUBSWirm,
1177                                           MMX_PSUBUSBirm,
1178                                           MMX_PSUBUSWirm)>;
1179
1180 def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
1181   let Latency = 6;
1182   let NumMicroOps = 2;
1183   let ResourceCycles = [1,1];
1184 }
1185 def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64)>;
1186 def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
1187
1188 def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
1189   let Latency = 6;
1190   let NumMicroOps = 2;
1191   let ResourceCycles = [1,1];
1192 }
1193 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
1194                                              "MOVBE(16|32|64)rm")>;
1195
1196 def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1197   let Latency = 6;
1198   let NumMicroOps = 2;
1199   let ResourceCycles = [1,1];
1200 }
1201 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
1202 def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
1203
1204 def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1205   let Latency = 6;
1206   let NumMicroOps = 2;
1207   let ResourceCycles = [1,1];
1208 }
1209 def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
1210 def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
1211
1212 def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1213   let Latency = 6;
1214   let NumMicroOps = 3;
1215   let ResourceCycles = [2,1];
1216 }
1217 def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
1218                                              "VCVTSI642SSZrr",
1219                                              "VCVTUSI642SSZrr")>;
1220
1221 def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
1222   let Latency = 6;
1223   let NumMicroOps = 4;
1224   let ResourceCycles = [1,1,1,1];
1225 }
1226 def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
1227
1228 def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1229   let Latency = 6;
1230   let NumMicroOps = 4;
1231   let ResourceCycles = [1,1,1,1];
1232 }
1233 def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
1234                                              "SHL(8|16|32|64)m(1|i)",
1235                                              "SHR(8|16|32|64)m(1|i)")>;
1236
1237 def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1238   let Latency = 6;
1239   let NumMicroOps = 4;
1240   let ResourceCycles = [1,1,1,1];
1241 }
1242 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
1243                                              "PUSH(16|32|64)rmm")>;
1244
1245 def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
1246   let Latency = 6;
1247   let NumMicroOps = 6;
1248   let ResourceCycles = [1,5];
1249 }
1250 def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
1251
1252 def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
1253   let Latency = 7;
1254   let NumMicroOps = 1;
1255   let ResourceCycles = [1];
1256 }
1257 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
1258 def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
1259                                           VBROADCASTI128,
1260                                           VBROADCASTSDYrm,
1261                                           VBROADCASTSSYrm,
1262                                           VMOVDDUPYrm,
1263                                           VMOVSHDUPYrm,
1264                                           VMOVSLDUPYrm,
1265                                           VPBROADCASTDYrm,
1266                                           VPBROADCASTQYrm)>;
1267
1268 def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
1269   let Latency = 7;
1270   let NumMicroOps = 2;
1271   let ResourceCycles = [1,1];
1272 }
1273 def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
1274
1275 def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1276   let Latency = 7;
1277   let NumMicroOps = 2;
1278   let ResourceCycles = [1,1];
1279 }
1280 def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
1281                                              "VMOVSSZrm(b?)")>;
1282
1283 def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
1284   let Latency = 6;
1285   let NumMicroOps = 2;
1286   let ResourceCycles = [1,1];
1287 }
1288 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
1289                                               "(V?)PMOV(SX|ZX)BQrm",
1290                                               "(V?)PMOV(SX|ZX)BWrm",
1291                                               "(V?)PMOV(SX|ZX)DQrm",
1292                                               "(V?)PMOV(SX|ZX)WDrm",
1293                                               "(V?)PMOV(SX|ZX)WQrm")>;
1294
1295 def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1296   let Latency = 7;
1297   let NumMicroOps = 2;
1298   let ResourceCycles = [1,1];
1299 }
1300 def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
1301                                              "VCVTPD2DQ(Y|Z256)rr",
1302                                              "VCVTPD2PS(Y|Z256)rr",
1303                                              "VCVTPD2UDQZ256rr",
1304                                              "VCVTPS2PD(Y|Z256)rr",
1305                                              "VCVTPS2QQZ256rr",
1306                                              "VCVTPS2UQQZ256rr",
1307                                              "VCVTQQ2PSZ256rr",
1308                                              "VCVTTPD2DQ(Y|Z256)rr",
1309                                              "VCVTTPD2UDQZ256rr",
1310                                              "VCVTTPS2QQZ256rr",
1311                                              "VCVTTPS2UQQZ256rr",
1312                                              "VCVTUDQ2PDZ256rr",
1313                                              "VCVTUQQ2PSZ256rr")>;
1314
1315 def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
1316   let Latency = 7;
1317   let NumMicroOps = 2;
1318   let ResourceCycles = [1,1];
1319 }
1320 def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
1321                                            VCVTPD2DQZrr,
1322                                            VCVTPD2PSZrr,
1323                                            VCVTPD2UDQZrr,
1324                                            VCVTPS2PDZrr,
1325                                            VCVTPS2QQZrr,
1326                                            VCVTPS2UQQZrr,
1327                                            VCVTQQ2PSZrr,
1328                                            VCVTTPD2DQZrr,
1329                                            VCVTTPD2UDQZrr,
1330                                            VCVTTPS2QQZrr,
1331                                            VCVTTPS2UQQZrr,
1332                                            VCVTUDQ2PDZrr,
1333                                            VCVTUQQ2PSZrr)>;
1334
1335 def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1336   let Latency = 7;
1337   let NumMicroOps = 2;
1338   let ResourceCycles = [1,1];
1339 }
1340 def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm,
1341                                           VPBLENDDrmi)>;
1342 def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd],
1343                                   (instregex "VBLENDMPDZ128rm(b?)",
1344                                              "VBLENDMPSZ128rm(b?)",
1345                                              "VBROADCASTI32X2Z128m(b?)",
1346                                              "VBROADCASTSSZ128m(b?)",
1347                                              "VINSERT(F|I)128rm",
1348                                              "VMOVAPDZ128rm(b?)",
1349                                              "VMOVAPSZ128rm(b?)",
1350                                              "VMOVDDUPZ128rm(b?)",
1351                                              "VMOVDQA32Z128rm(b?)",
1352                                              "VMOVDQA64Z128rm(b?)",
1353                                              "VMOVDQU16Z128rm(b?)",
1354                                              "VMOVDQU32Z128rm(b?)",
1355                                              "VMOVDQU64Z128rm(b?)",
1356                                              "VMOVDQU8Z128rm(b?)",
1357                                              "VMOVSHDUPZ128rm(b?)",
1358                                              "VMOVSLDUPZ128rm(b?)",
1359                                              "VMOVUPDZ128rm(b?)",
1360                                              "VMOVUPSZ128rm(b?)",
1361                                              "VPADD(B|D|Q|W)Z128rm(b?)",
1362                                              "(V?)PADD(B|D|Q|W)rm",
1363                                              "VPBLENDM(B|D|Q|W)Z128rm(b?)",
1364                                              "VPBROADCASTDZ128m(b?)",
1365                                              "VPBROADCASTQZ128m(b?)",
1366                                              "VPSUB(B|D|Q|W)Z128rm(b?)",
1367                                              "(V?)PSUB(B|D|Q|W)rm",
1368                                              "VPTERNLOGDZ128rm(b?)i",
1369                                              "VPTERNLOGQZ128rm(b?)i")>;
1370
1371 def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1372   let Latency = 7;
1373   let NumMicroOps = 3;
1374   let ResourceCycles = [2,1];
1375 }
1376 def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWirm,
1377                                           MMX_PACKSSWBirm,
1378                                           MMX_PACKUSWBirm)>;
1379
1380 def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1381   let Latency = 7;
1382   let NumMicroOps = 3;
1383   let ResourceCycles = [2,1];
1384 }
1385 def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
1386                                              "VPERMI2W256rr",
1387                                              "VPERMI2Wrr",
1388                                              "VPERMT2W128rr",
1389                                              "VPERMT2W256rr",
1390                                              "VPERMT2Wrr")>;
1391
1392 def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1393   let Latency = 7;
1394   let NumMicroOps = 3;
1395   let ResourceCycles = [1,2];
1396 }
1397 def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
1398                                           SCASB, SCASL, SCASQ, SCASW)>;
1399
1400 def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
1401   let Latency = 7;
1402   let NumMicroOps = 3;
1403   let ResourceCycles = [1,1,1];
1404 }
1405 def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
1406                                               "(V?)CVTSS2SI64(Z?)rr",
1407                                               "(V?)CVTTSS2SI64(Z?)rr",
1408                                               "VCVTTSS2USI64Zrr")>;
1409
1410 def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
1411   let Latency = 7;
1412   let NumMicroOps = 3;
1413   let ResourceCycles = [1,1,1];
1414 }
1415 def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
1416
1417 def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
1418   let Latency = 7;
1419   let NumMicroOps = 3;
1420   let ResourceCycles = [1,1,1];
1421 }
1422 def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
1423
1424 def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
1425   let Latency = 7;
1426   let NumMicroOps = 3;
1427   let ResourceCycles = [1,1,1];
1428 }
1429 def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>;
1430
1431 def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1432   let Latency = 7;
1433   let NumMicroOps = 4;
1434   let ResourceCycles = [1,2,1];
1435 }
1436 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
1437                                               "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
1438                                               "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
1439                                               "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
1440
1441 def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1442   let Latency = 7;
1443   let NumMicroOps = 5;
1444   let ResourceCycles = [1,1,1,2];
1445 }
1446 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1447                                               "ROR(8|16|32|64)m(1|i)")>;
1448
1449 def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1450   let Latency = 7;
1451   let NumMicroOps = 5;
1452   let ResourceCycles = [1,1,1,2];
1453 }
1454 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
1455
1456 def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
1457   let Latency = 7;
1458   let NumMicroOps = 5;
1459   let ResourceCycles = [1,1,1,1,1];
1460 }
1461 def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
1462 def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64)>;
1463
1464 def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1465   let Latency = 7;
1466   let NumMicroOps = 7;
1467   let ResourceCycles = [1,2,2,2];
1468 }
1469 def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
1470                                            VPSCATTERQQZ128mr,
1471                                            VSCATTERDPDZ128mr,
1472                                            VSCATTERQPDZ128mr)>;
1473
1474 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
1475   let Latency = 7;
1476   let NumMicroOps = 7;
1477   let ResourceCycles = [1,3,1,2];
1478 }
1479 def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
1480
1481 def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1482   let Latency = 7;
1483   let NumMicroOps = 11;
1484   let ResourceCycles = [1,4,4,2];
1485 }
1486 def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
1487                                            VPSCATTERQQZ256mr,
1488                                            VSCATTERDPDZ256mr,
1489                                            VSCATTERQPDZ256mr)>;
1490
1491 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1492   let Latency = 7;
1493   let NumMicroOps = 19;
1494   let ResourceCycles = [1,8,8,2];
1495 }
1496 def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
1497                                            VPSCATTERQQZmr,
1498                                            VSCATTERDPDZmr,
1499                                            VSCATTERQPDZmr)>;
1500
1501 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1502   let Latency = 7;
1503   let NumMicroOps = 36;
1504   let ResourceCycles = [1,16,1,16,2];
1505 }
1506 def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
1507
1508 def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
1509   let Latency = 8;
1510   let NumMicroOps = 2;
1511   let ResourceCycles = [1,1];
1512 }
1513 def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
1514                                               "PEXT(32|64)rm")>;
1515
1516 def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1517   let Latency = 8;
1518   let NumMicroOps = 2;
1519   let ResourceCycles = [1,1];
1520 }
1521 def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
1522                                               "VFPCLASSSDZrm(b?)",
1523                                               "VPBROADCASTB(Z|Z256)m(b?)",
1524                                               "VPBROADCASTW(Z|Z256)m(b?)")>;
1525 def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm,
1526                                            VPBROADCASTWYrm,
1527                                            VPMOVSXBDYrm,
1528                                            VPMOVSXBQYrm,
1529                                            VPMOVSXWQYrm)>;
1530
1531 def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1532   let Latency = 8;
1533   let NumMicroOps = 2;
1534   let ResourceCycles = [1,1];
1535 }
1536 def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm,
1537                                            VPBLENDDYrmi)>;
1538 def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd],
1539                                    (instregex "VBLENDMPD(Z|Z256)rm(b?)",
1540                                               "VBLENDMPS(Z|Z256)rm(b?)",
1541                                               "VBROADCASTF32X2Z256m(b?)",
1542                                               "VBROADCASTF32X2Zm(b?)",
1543                                               "VBROADCASTF32X4Z256rm(b?)",
1544                                               "VBROADCASTF32X4rm(b?)",
1545                                               "VBROADCASTF32X8rm(b?)",
1546                                               "VBROADCASTF64X2Z128rm(b?)",
1547                                               "VBROADCASTF64X2rm(b?)",
1548                                               "VBROADCASTF64X4rm(b?)",
1549                                               "VBROADCASTI32X2Z256m(b?)",
1550                                               "VBROADCASTI32X2Zm(b?)",
1551                                               "VBROADCASTI32X4Z256rm(b?)",
1552                                               "VBROADCASTI32X4rm(b?)",
1553                                               "VBROADCASTI32X8rm(b?)",
1554                                               "VBROADCASTI64X2Z128rm(b?)",
1555                                               "VBROADCASTI64X2rm(b?)",
1556                                               "VBROADCASTI64X4rm(b?)",
1557                                               "VBROADCASTSD(Z|Z256)m(b?)",
1558                                               "VBROADCASTSS(Z|Z256)m(b?)",
1559                                               "VINSERTF32x4(Z|Z256)rm(b?)",
1560                                               "VINSERTF32x8Zrm(b?)",
1561                                               "VINSERTF64x2(Z|Z256)rm(b?)",
1562                                               "VINSERTF64x4Zrm(b?)",
1563                                               "VINSERTI32x4(Z|Z256)rm(b?)",
1564                                               "VINSERTI32x8Zrm(b?)",
1565                                               "VINSERTI64x2(Z|Z256)rm(b?)",
1566                                               "VINSERTI64x4Zrm(b?)",
1567                                               "VMOVAPD(Z|Z256)rm(b?)",
1568                                               "VMOVAPS(Z|Z256)rm(b?)",
1569                                               "VMOVDDUP(Z|Z256)rm(b?)",
1570                                               "VMOVDQA32(Z|Z256)rm(b?)",
1571                                               "VMOVDQA64(Z|Z256)rm(b?)",
1572                                               "VMOVDQU16(Z|Z256)rm(b?)",
1573                                               "VMOVDQU32(Z|Z256)rm(b?)",
1574                                               "VMOVDQU64(Z|Z256)rm(b?)",
1575                                               "VMOVDQU8(Z|Z256)rm(b?)",
1576                                               "VMOVSHDUP(Z|Z256)rm(b?)",
1577                                               "VMOVSLDUP(Z|Z256)rm(b?)",
1578                                               "VMOVUPD(Z|Z256)rm(b?)",
1579                                               "VMOVUPS(Z|Z256)rm(b?)",
1580                                               "VPADD(B|D|Q|W)Yrm",
1581                                               "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",
1582                                               "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",
1583                                               "VPBROADCASTD(Z|Z256)m(b?)",
1584                                               "VPBROADCASTQ(Z|Z256)m(b?)",
1585                                               "VPSUB(B|D|Q|W)Yrm",
1586                                               "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
1587                                               "VPTERNLOGD(Z|Z256)rm(b?)i",
1588                                               "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
1589
1590 def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1591   let Latency = 8;
1592   let NumMicroOps = 4;
1593   let ResourceCycles = [1,2,1];
1594 }
1595 def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1596
1597 def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1598   let Latency = 8;
1599   let NumMicroOps = 5;
1600   let ResourceCycles = [1,1,1,2];
1601 }
1602 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
1603                                               "RCR(8|16|32|64)m(1|i)")>;
1604
1605 def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1606   let Latency = 8;
1607   let NumMicroOps = 6;
1608   let ResourceCycles = [1,1,1,3];
1609 }
1610 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
1611                                               "ROR(8|16|32|64)mCL",
1612                                               "SAR(8|16|32|64)mCL",
1613                                               "SHL(8|16|32|64)mCL",
1614                                               "SHR(8|16|32|64)mCL")>;
1615
1616 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1617   let Latency = 8;
1618   let NumMicroOps = 6;
1619   let ResourceCycles = [1,1,1,2,1];
1620 }
1621 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
1622
1623 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1624   let Latency = 8;
1625   let NumMicroOps = 8;
1626   let ResourceCycles = [1,2,1,2,2];
1627 }
1628 def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
1629                                            VPSCATTERQDZ256mr,
1630                                            VSCATTERQPSZ128mr,
1631                                            VSCATTERQPSZ256mr)>;
1632
1633 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1634   let Latency = 8;
1635   let NumMicroOps = 12;
1636   let ResourceCycles = [1,4,1,4,2];
1637 }
1638 def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
1639                                            VSCATTERDPSZ128mr)>;
1640
1641 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1642   let Latency = 8;
1643   let NumMicroOps = 20;
1644   let ResourceCycles = [1,8,1,8,2];
1645 }
1646 def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
1647                                            VSCATTERDPSZ256mr)>;
1648
1649 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1650   let Latency = 8;
1651   let NumMicroOps = 36;
1652   let ResourceCycles = [1,16,1,16,2];
1653 }
1654 def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
1655
1656 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1657   let Latency = 9;
1658   let NumMicroOps = 2;
1659   let ResourceCycles = [1,1];
1660 }
1661 def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>;
1662
1663 def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1664   let Latency = 9;
1665   let NumMicroOps = 2;
1666   let ResourceCycles = [1,1];
1667 }
1668 def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm,
1669                                            VPMOVSXDQYrm,
1670                                            VPMOVSXWDYrm,
1671                                            VPMOVZXWDYrm)>;
1672 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
1673                                               "VCMP(PD|PS)Z128rm(b?)i",
1674                                               "VCMP(SD|SS)Zrm",
1675                                               "VFPCLASSSSZrm(b?)",
1676                                               "VPCMPBZ128rmi(b?)",
1677                                               "VPCMPDZ128rmi(b?)",
1678                                               "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
1679                                               "VPCMPGT(B|D|Q|W)Z128rm(b?)",
1680                                               "(V?)PCMPGTQrm",
1681                                               "VPCMPQZ128rmi(b?)",
1682                                               "VPCMPU(B|D|Q|W)Z128rmi(b?)",
1683                                               "VPCMPWZ128rmi(b?)",
1684                                               "VPERMI2D128rm(b?)",
1685                                               "VPERMI2PD128rm(b?)",
1686                                               "VPERMI2PS128rm(b?)",
1687                                               "VPERMI2Q128rm(b?)",
1688                                               "VPERMT2D128rm(b?)",
1689                                               "VPERMT2PD128rm(b?)",
1690                                               "VPERMT2PS128rm(b?)",
1691                                               "VPERMT2Q128rm(b?)",
1692                                               "VPMAXSQZ128rm(b?)",
1693                                               "VPMAXUQZ128rm(b?)",
1694                                               "VPMINSQZ128rm(b?)",
1695                                               "VPMINUQZ128rm(b?)",
1696                                               "VPMOVSXBDZ128rm(b?)",
1697                                               "VPMOVSXBQZ128rm(b?)",
1698                                               "VPMOVSXBWZ128rm(b?)",
1699                                               "VPMOVSXDQZ128rm(b?)",
1700                                               "VPMOVSXWDZ128rm(b?)",
1701                                               "VPMOVSXWQZ128rm(b?)",
1702                                               "VPMOVZXBDZ128rm(b?)",
1703                                               "VPMOVZXBQZ128rm(b?)",
1704                                               "VPMOVZXBWZ128rm(b?)",
1705                                               "VPMOVZXDQZ128rm(b?)",
1706                                               "VPMOVZXWDZ128rm(b?)",
1707                                               "VPMOVZXWQZ128rm(b?)",
1708                                               "VPTESTMBZ128rm(b?)",
1709                                               "VPTESTMDZ128rm(b?)",
1710                                               "VPTESTMQZ128rm(b?)",
1711                                               "VPTESTMWZ128rm(b?)",
1712                                               "VPTESTNMBZ128rm(b?)",
1713                                               "VPTESTNMDZ128rm(b?)",
1714                                               "VPTESTNMQZ128rm(b?)",
1715                                               "VPTESTNMWZ128rm(b?)")>;
1716
1717 def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1718   let Latency = 9;
1719   let NumMicroOps = 2;
1720   let ResourceCycles = [1,1];
1721 }
1722 def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm",
1723                                               "(V?)CVTPS2PDrm")>;
1724
1725 def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1726   let Latency = 9;
1727   let NumMicroOps = 4;
1728   let ResourceCycles = [2,1,1];
1729 }
1730 def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
1731                                               "(V?)PHSUBSWrm")>;
1732
1733 def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
1734   let Latency = 9;
1735   let NumMicroOps = 5;
1736   let ResourceCycles = [1,2,1,1];
1737 }
1738 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
1739                                               "LSL(16|32|64)rm")>;
1740
1741 def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1742   let Latency = 10;
1743   let NumMicroOps = 2;
1744   let ResourceCycles = [1,1];
1745 }
1746 def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>;
1747 def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1748                                               "ILD_F(16|32|64)m",
1749                                               "VALIGND(Z|Z256)rm(b?)i",
1750                                               "VALIGNQ(Z|Z256)rm(b?)i",
1751                                               "VCMPPD(Z|Z256)rm(b?)i",
1752                                               "VCMPPS(Z|Z256)rm(b?)i",
1753                                               "VPCMPB(Z|Z256)rmi(b?)",
1754                                               "VPCMPD(Z|Z256)rmi(b?)",
1755                                               "VPCMPEQB(Z|Z256)rm(b?)",
1756                                               "VPCMPEQD(Z|Z256)rm(b?)",
1757                                               "VPCMPEQQ(Z|Z256)rm(b?)",
1758                                               "VPCMPEQW(Z|Z256)rm(b?)",
1759                                               "VPCMPGTB(Z|Z256)rm(b?)",
1760                                               "VPCMPGTD(Z|Z256)rm(b?)",
1761                                               "VPCMPGTQ(Z|Z256)rm(b?)",
1762                                               "VPCMPGTW(Z|Z256)rm(b?)",
1763                                               "VPCMPQ(Z|Z256)rmi(b?)",
1764                                               "VPCMPU(B|D|Q|W)Z256rmi(b?)",
1765                                               "VPCMPU(B|D|Q|W)Zrmi(b?)",
1766                                               "VPCMPW(Z|Z256)rmi(b?)",
1767                                               "VPMAXSQ(Z|Z256)rm(b?)",
1768                                               "VPMAXUQ(Z|Z256)rm(b?)",
1769                                               "VPMINSQ(Z|Z256)rm(b?)",
1770                                               "VPMINUQ(Z|Z256)rm(b?)",
1771                                               "VPTESTM(B|D|Q|W)Z256rm(b?)",
1772                                               "VPTESTM(B|D|Q|W)Zrm(b?)",
1773                                               "VPTESTNM(B|D|Q|W)Z256rm(b?)",
1774                                               "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
1775
1776 def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1777   let Latency = 10;
1778   let NumMicroOps = 2;
1779   let ResourceCycles = [1,1];
1780 }
1781 def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
1782                                               "VCVTDQ2PSZ128rm(b?)",
1783                                               "(V?)CVTDQ2PSrm",
1784                                               "VCVTPD2QQZ128rm(b?)",
1785                                               "VCVTPD2UQQZ128rm(b?)",
1786                                               "VCVTPH2PSZ128rm(b?)",
1787                                               "VCVTPS2DQZ128rm(b?)",
1788                                               "(V?)CVTPS2DQrm",
1789                                               "VCVTPS2PDZ128rm(b?)",
1790                                               "VCVTPS2QQZ128rm(b?)",
1791                                               "VCVTPS2UDQZ128rm(b?)",
1792                                               "VCVTPS2UQQZ128rm(b?)",
1793                                               "VCVTQQ2PDZ128rm(b?)",
1794                                               "VCVTQQ2PSZ128rm(b?)",
1795                                               "VCVTSS2SDZrm",
1796                                               "(V?)CVTSS2SDrm",
1797                                               "VCVTTPD2QQZ128rm(b?)",
1798                                               "VCVTTPD2UQQZ128rm(b?)",
1799                                               "VCVTTPS2DQZ128rm(b?)",
1800                                               "(V?)CVTTPS2DQrm",
1801                                               "VCVTTPS2QQZ128rm(b?)",
1802                                               "VCVTTPS2UDQZ128rm(b?)",
1803                                               "VCVTTPS2UQQZ128rm(b?)",
1804                                               "VCVTUDQ2PDZ128rm(b?)",
1805                                               "VCVTUDQ2PSZ128rm(b?)",
1806                                               "VCVTUQQ2PDZ128rm(b?)",
1807                                               "VCVTUQQ2PSZ128rm(b?)")>;
1808
1809 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1810   let Latency = 10;
1811   let NumMicroOps = 3;
1812   let ResourceCycles = [2,1];
1813 }
1814 def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
1815                                               "VEXPANDPSZ128rm(b?)",
1816                                               "VPEXPANDDZ128rm(b?)",
1817                                               "VPEXPANDQZ128rm(b?)")>;
1818
1819 def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1820   let Latency = 10;
1821   let NumMicroOps = 3;
1822   let ResourceCycles = [1,1,1];
1823 }
1824 def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>;
1825
1826 def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1827   let Latency = 10;
1828   let NumMicroOps = 4;
1829   let ResourceCycles = [2,1,1];
1830 }
1831 def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,
1832                                            VPHSUBSWYrm)>;
1833
1834 def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1835   let Latency = 10;
1836   let NumMicroOps = 8;
1837   let ResourceCycles = [1,1,1,1,1,3];
1838 }
1839 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
1840
1841 def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
1842   let Latency = 11;
1843   let NumMicroOps = 1;
1844   let ResourceCycles = [1,3];
1845 }
1846 def : SchedAlias<WriteFDivX,  SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair
1847
1848 def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1849   let Latency = 11;
1850   let NumMicroOps = 2;
1851   let ResourceCycles = [1,1];
1852 }
1853 def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
1854
1855 def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1856   let Latency = 11;
1857   let NumMicroOps = 2;
1858   let ResourceCycles = [1,1];
1859 }
1860 def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm,
1861                                            VCVTPS2PDYrm)>;
1862 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
1863                                               "VCVTPH2PS(Z|Z256)rm(b?)",
1864                                               "VCVTPS2PD(Z|Z256)rm(b?)",
1865                                               "VCVTQQ2PD(Z|Z256)rm(b?)",
1866                                               "VCVTQQ2PSZ256rm(b?)",
1867                                               "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1868                                               "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1869                                               "VCVT(T?)PS2DQYrm",
1870                                               "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1871                                               "VCVT(T?)PS2QQZ256rm(b?)",
1872                                               "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1873                                               "VCVT(T?)PS2UQQZ256rm(b?)",
1874                                               "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",
1875                                               "VCVTUQQ2PD(Z|Z256)rm(b?)",
1876                                               "VCVTUQQ2PSZ256rm(b?)")>;
1877
1878 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1879   let Latency = 11;
1880   let NumMicroOps = 3;
1881   let ResourceCycles = [2,1];
1882 }
1883 def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
1884                                               "VEXPANDPD(Z|Z256)rm(b?)",
1885                                               "VEXPANDPS(Z|Z256)rm(b?)",
1886                                               "VPEXPANDD(Z|Z256)rm(b?)",
1887                                               "VPEXPANDQ(Z|Z256)rm(b?)")>;
1888
1889 def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1890   let Latency = 11;
1891   let NumMicroOps = 3;
1892   let ResourceCycles = [1,2];
1893 }
1894 def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>;
1895
1896 def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1897   let Latency = 11;
1898   let NumMicroOps = 3;
1899   let ResourceCycles = [1,1,1];
1900 }
1901 def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
1902
1903 def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1904   let Latency = 11;
1905   let NumMicroOps = 3;
1906   let ResourceCycles = [1,1,1];
1907 }
1908 def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2PSrm,
1909                                            CVTPD2DQrm,
1910                                            CVTTPD2DQrm,
1911                                            MMX_CVTPD2PIirm,
1912                                            MMX_CVTTPD2PIirm)>;
1913
1914 def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1915   let Latency = 11;
1916   let NumMicroOps = 4;
1917   let ResourceCycles = [2,1,1];
1918 }
1919 def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
1920
1921 def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1922   let Latency = 11;
1923   let NumMicroOps = 7;
1924   let ResourceCycles = [2,3,2];
1925 }
1926 def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
1927                                               "RCR(16|32|64)rCL")>;
1928
1929 def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
1930   let Latency = 11;
1931   let NumMicroOps = 9;
1932   let ResourceCycles = [1,5,1,2];
1933 }
1934 def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>;
1935
1936 def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1937   let Latency = 11;
1938   let NumMicroOps = 11;
1939   let ResourceCycles = [2,9];
1940 }
1941 def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
1942
1943 def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
1944   let Latency = 12;
1945   let NumMicroOps = 3;
1946   let ResourceCycles = [3];
1947 }
1948 def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
1949
1950 def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
1951   let Latency = 12;
1952   let NumMicroOps = 3;
1953   let ResourceCycles = [3];
1954 }
1955 def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
1956
1957 def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1958   let Latency = 12;
1959   let NumMicroOps = 3;
1960   let ResourceCycles = [2,1];
1961 }
1962 def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
1963
1964 def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
1965   let Latency = 12;
1966   let NumMicroOps = 3;
1967   let ResourceCycles = [1,1,1];
1968 }
1969 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
1970                                               "VCVT(T?)SS2USI64Zrm(b?)")>;
1971
1972 def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1973   let Latency = 12;
1974   let NumMicroOps = 3;
1975   let ResourceCycles = [1,1,1];
1976 }
1977 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
1978                                               "VCVT(T?)PS2UQQZrm(b?)")>;
1979
1980 def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
1981   let Latency = 12;
1982   let NumMicroOps = 4;
1983   let ResourceCycles = [1,1,1,1];
1984 }
1985 def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
1986
1987 def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1988   let Latency = 13;
1989   let NumMicroOps = 3;
1990   let ResourceCycles = [2,1];
1991 }
1992 def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
1993                                               "VPERMWZ256rm(b?)",
1994                                               "VPERMWZrm(b?)")>;
1995
1996 def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1997   let Latency = 13;
1998   let NumMicroOps = 3;
1999   let ResourceCycles = [1,1,1];
2000 }
2001 def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
2002
2003 def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2004   let Latency = 13;
2005   let NumMicroOps = 4;
2006   let ResourceCycles = [2,1,1];
2007 }
2008 def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
2009                                               "VPERMT2W128rm(b?)")>;
2010
2011 def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2012   let Latency = 14;
2013   let NumMicroOps = 1;
2014   let ResourceCycles = [1,3];
2015 }
2016 def : SchedAlias<WriteFDiv64,  SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2017 def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2018
2019 def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2020   let Latency = 14;
2021   let NumMicroOps = 1;
2022   let ResourceCycles = [1,5];
2023 }
2024 def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair
2025
2026 def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2027   let Latency = 14;
2028   let NumMicroOps = 3;
2029   let ResourceCycles = [1,1,1];
2030 }
2031 def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
2032
2033 def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2034   let Latency = 14;
2035   let NumMicroOps = 3;
2036   let ResourceCycles = [1,1,1];
2037 }
2038 def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
2039                                               "VCVTPD2PSZrm(b?)",
2040                                               "VCVTPD2UDQZrm(b?)",
2041                                               "VCVTQQ2PSZrm(b?)",
2042                                               "VCVTTPD2DQZrm(b?)",
2043                                               "VCVTTPD2UDQZrm(b?)",
2044                                               "VCVTUQQ2PSZrm(b?)")>;
2045
2046 def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2047   let Latency = 14;
2048   let NumMicroOps = 4;
2049   let ResourceCycles = [2,1,1];
2050 }
2051 def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
2052                                               "VPERMI2Wrm(b?)",
2053                                               "VPERMT2W256rm(b?)",
2054                                               "VPERMT2Wrm(b?)")>;
2055
2056 def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2057   let Latency = 14;
2058   let NumMicroOps = 10;
2059   let ResourceCycles = [2,4,1,3];
2060 }
2061 def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>;
2062
2063 def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
2064   let Latency = 15;
2065   let NumMicroOps = 1;
2066   let ResourceCycles = [1];
2067 }
2068 def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
2069
2070 def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2071   let Latency = 15;
2072   let NumMicroOps = 8;
2073   let ResourceCycles = [1,2,2,1,2];
2074 }
2075 def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
2076
2077 def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2078   let Latency = 15;
2079   let NumMicroOps = 10;
2080   let ResourceCycles = [1,1,1,5,1,1];
2081 }
2082 def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
2083
2084 def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2085   let Latency = 16;
2086   let NumMicroOps = 14;
2087   let ResourceCycles = [1,1,1,4,2,5];
2088 }
2089 def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
2090
2091 def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> {
2092   let Latency = 12;
2093   let NumMicroOps = 34;
2094   let ResourceCycles = [1, 4, 5];
2095 }
2096 def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
2097
2098 def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2099   let Latency = 17;
2100   let NumMicroOps = 2;
2101   let ResourceCycles = [1,1,5];
2102 }
2103 def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair
2104
2105 def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2106   let Latency = 17;
2107   let NumMicroOps = 15;
2108   let ResourceCycles = [2,1,2,4,2,4];
2109 }
2110 def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
2111
2112 def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2113   let Latency = 18;
2114   let NumMicroOps = 4;
2115   let ResourceCycles = [1,3];
2116 }
2117 def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
2118
2119 def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2120   let Latency = 18;
2121   let NumMicroOps = 8;
2122   let ResourceCycles = [1,1,1,5];
2123 }
2124 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
2125
2126 def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2127   let Latency = 18;
2128   let NumMicroOps = 11;
2129   let ResourceCycles = [2,1,1,4,1,2];
2130 }
2131 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
2132
2133 def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2134   let Latency = 19;
2135   let NumMicroOps = 2;
2136   let ResourceCycles = [1,1,4];
2137 }
2138 def : SchedAlias<WriteFDiv64Ld,  SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair
2139
2140 def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2141   let Latency = 19;
2142   let NumMicroOps = 4;
2143   let ResourceCycles = [1,3];
2144 }
2145 def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)",
2146                                               "VPMULLQZrm(b?)")>;
2147
2148 def SKXWriteResGroup214 : SchedWriteRes<[]> {
2149   let Latency = 20;
2150   let NumMicroOps = 0;
2151 }
2152 def: InstRW<[SKXWriteResGroup214], (instrs VGATHERDPSZ128rm,
2153                                            VGATHERQPSZrm,
2154                                            VPGATHERDDZ128rm)>;
2155
2156 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
2157   let Latency = 20;
2158   let NumMicroOps = 1;
2159   let ResourceCycles = [1];
2160 }
2161 def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
2162
2163 def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2164   let Latency = 20;
2165   let NumMicroOps = 2;
2166   let ResourceCycles = [1,1,4];
2167 }
2168 def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair
2169
2170 def SKXWriteResGroup218 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2171   let Latency = 20;
2172   let NumMicroOps = 5;
2173   let ResourceCycles = [1,2,1,1];
2174 }
2175 def: InstRW<[SKXWriteResGroup218], (instrs VGATHERQPSZ128rm,
2176                                            VGATHERQPSZ256rm,
2177                                            VPGATHERQDZ128rm,
2178                                            VPGATHERQDZ256rm)>;
2179
2180 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2181   let Latency = 20;
2182   let NumMicroOps = 8;
2183   let ResourceCycles = [1,1,1,1,1,1,2];
2184 }
2185 def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
2186
2187 def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
2188   let Latency = 20;
2189   let NumMicroOps = 10;
2190   let ResourceCycles = [1,2,7];
2191 }
2192 def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
2193
2194 def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2195   let Latency = 21;
2196   let NumMicroOps = 2;
2197   let ResourceCycles = [1,1,8];
2198 }
2199 def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair
2200
2201 def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2202   let Latency = 22;
2203   let NumMicroOps = 2;
2204   let ResourceCycles = [1,1];
2205 }
2206 def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
2207
2208 def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2209   let Latency = 22;
2210   let NumMicroOps = 5;
2211   let ResourceCycles = [1,2,1,1];
2212 }
2213 def: InstRW<[SKXWriteResGroup224], (instrs VGATHERDPDZ128rm,
2214                                            VGATHERQPDZ128rm,
2215                                            VPGATHERDQZ128rm,
2216                                            VPGATHERQQZ128rm)>;
2217
2218 def SKXWriteResGroup224_2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2219   let Latency = 22;
2220   let NumMicroOps = 5;
2221   let ResourceCycles = [1,2,1,1];
2222 }
2223 def: InstRW<[SKXWriteResGroup224_2], (instrs VGATHERDPSrm,
2224                                              VGATHERDPDrm,
2225                                              VGATHERQPDrm,
2226                                              VGATHERQPSrm,
2227                                              VPGATHERDDrm,
2228                                              VPGATHERDQrm,
2229                                              VPGATHERQDrm,
2230                                              VPGATHERQQrm,
2231                                              VPGATHERDDrm,
2232                                              VPGATHERQDrm,
2233                                              VPGATHERDQrm,
2234                                              VPGATHERQQrm,
2235                                              VGATHERDPSrm,
2236                                              VGATHERQPSrm,
2237                                              VGATHERDPDrm,
2238                                              VGATHERQPDrm)>;
2239
2240 def SKXWriteResGroup224_3 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2241   let Latency = 25;
2242   let NumMicroOps = 5;
2243   let ResourceCycles = [1,2,1,1];
2244 }
2245 def: InstRW<[SKXWriteResGroup224_3], (instrs VGATHERDPSYrm,
2246                                              VGATHERQPDYrm,
2247                                              VGATHERQPSYrm,
2248                                              VPGATHERDDYrm,
2249                                              VPGATHERDQYrm,
2250                                              VPGATHERQDYrm,
2251                                              VPGATHERQQYrm,
2252                                              VPGATHERDDYrm,
2253                                              VPGATHERQDYrm,
2254                                              VPGATHERDQYrm,
2255                                              VPGATHERQQYrm,
2256                                              VGATHERDPSYrm,
2257                                              VGATHERQPSYrm,
2258                                              VGATHERDPDYrm)>;
2259
2260 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2261   let Latency = 22;
2262   let NumMicroOps = 14;
2263   let ResourceCycles = [5,5,4];
2264 }
2265 def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
2266                                               "VPCONFLICTQZ256rr")>;
2267
2268 def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2269   let Latency = 23;
2270   let NumMicroOps = 19;
2271   let ResourceCycles = [2,1,4,1,1,4,6];
2272 }
2273 def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
2274
2275 def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2276   let Latency = 25;
2277   let NumMicroOps = 3;
2278   let ResourceCycles = [1,1,1];
2279 }
2280 def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
2281
2282 def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2283   let Latency = 25;
2284   let NumMicroOps = 5;
2285   let ResourceCycles = [1,2,1,1];
2286 }
2287 def: InstRW<[SKXWriteResGroup234], (instrs VGATHERDPDZ256rm,
2288                                            VGATHERQPDZ256rm,
2289                                            VPGATHERDQZ256rm,
2290                                            VPGATHERQDZrm,
2291                                            VPGATHERQQZ256rm)>;
2292
2293 def SKXWriteResGroup238 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2294   let Latency = 26;
2295   let NumMicroOps = 5;
2296   let ResourceCycles = [1,2,1,1];
2297 }
2298 def: InstRW<[SKXWriteResGroup238], (instrs VGATHERDPDZrm,
2299                                            VGATHERQPDZrm,
2300                                            VPGATHERDQZrm,
2301                                            VPGATHERQQZrm)>;
2302
2303 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2304   let Latency = 27;
2305   let NumMicroOps = 2;
2306   let ResourceCycles = [1,1];
2307 }
2308 def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
2309
2310 def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2311   let Latency = 27;
2312   let NumMicroOps = 5;
2313   let ResourceCycles = [1,2,1,1];
2314 }
2315 def: InstRW<[SKXWriteResGroup240], (instrs VGATHERDPSZ256rm,
2316                                            VPGATHERDDZ256rm)>;
2317
2318 def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2319   let Latency = 29;
2320   let NumMicroOps = 15;
2321   let ResourceCycles = [5,5,1,4];
2322 }
2323 def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
2324
2325 def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2326   let Latency = 30;
2327   let NumMicroOps = 3;
2328   let ResourceCycles = [1,1,1];
2329 }
2330 def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
2331
2332 def SKXWriteResGroup245 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2333   let Latency = 30;
2334   let NumMicroOps = 5;
2335   let ResourceCycles = [1,2,1,1];
2336 }
2337 def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm,
2338                                            VPGATHERDDZrm)>;
2339
2340 def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
2341   let Latency = 35;
2342   let NumMicroOps = 23;
2343   let ResourceCycles = [1,5,3,4,10];
2344 }
2345 def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
2346                                               "IN(8|16|32)rr")>;
2347
2348 def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2349   let Latency = 35;
2350   let NumMicroOps = 23;
2351   let ResourceCycles = [1,5,2,1,4,10];
2352 }
2353 def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
2354                                               "OUT(8|16|32)rr")>;
2355
2356 def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2357   let Latency = 37;
2358   let NumMicroOps = 21;
2359   let ResourceCycles = [9,7,5];
2360 }
2361 def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
2362                                               "VPCONFLICTQZrr")>;
2363
2364 def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
2365   let Latency = 37;
2366   let NumMicroOps = 31;
2367   let ResourceCycles = [1,8,1,21];
2368 }
2369 def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
2370
2371 def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
2372   let Latency = 40;
2373   let NumMicroOps = 18;
2374   let ResourceCycles = [1,1,2,3,1,1,1,8];
2375 }
2376 def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
2377
2378 def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2379   let Latency = 41;
2380   let NumMicroOps = 39;
2381   let ResourceCycles = [1,10,1,1,26];
2382 }
2383 def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
2384
2385 def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
2386   let Latency = 42;
2387   let NumMicroOps = 22;
2388   let ResourceCycles = [2,20];
2389 }
2390 def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
2391
2392 def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2393   let Latency = 42;
2394   let NumMicroOps = 40;
2395   let ResourceCycles = [1,11,1,1,26];
2396 }
2397 def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
2398 def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
2399
2400 def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2401   let Latency = 44;
2402   let NumMicroOps = 22;
2403   let ResourceCycles = [9,7,1,5];
2404 }
2405 def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
2406                                               "VPCONFLICTQZrm(b?)")>;
2407
2408 def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
2409   let Latency = 62;
2410   let NumMicroOps = 64;
2411   let ResourceCycles = [2,8,5,10,39];
2412 }
2413 def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
2414
2415 def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2416   let Latency = 63;
2417   let NumMicroOps = 88;
2418   let ResourceCycles = [4,4,31,1,2,1,45];
2419 }
2420 def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
2421
2422 def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2423   let Latency = 63;
2424   let NumMicroOps = 90;
2425   let ResourceCycles = [4,2,33,1,2,1,47];
2426 }
2427 def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
2428
2429 def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2430   let Latency = 67;
2431   let NumMicroOps = 35;
2432   let ResourceCycles = [17,11,7];
2433 }
2434 def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
2435
2436 def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2437   let Latency = 74;
2438   let NumMicroOps = 36;
2439   let ResourceCycles = [17,11,1,7];
2440 }
2441 def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
2442
2443 def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
2444   let Latency = 75;
2445   let NumMicroOps = 15;
2446   let ResourceCycles = [6,3,6];
2447 }
2448 def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
2449
2450 def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
2451   let Latency = 106;
2452   let NumMicroOps = 100;
2453   let ResourceCycles = [9,1,11,16,1,11,21,30];
2454 }
2455 def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
2456
2457 def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
2458   let Latency = 140;
2459   let NumMicroOps = 4;
2460   let ResourceCycles = [1,3];
2461 }
2462 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
2463
2464 def: InstRW<[WriteZero], (instrs CLC)>;
2465
2466 } // SchedModel