1 //===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the schedule class data for the Intel Atom
11 // in order (Saltwell-32nm/Bonnell-45nm) processors.
13 //===----------------------------------------------------------------------===//
16 // Scheduling information derived from the "Intel 64 and IA32 Architectures
17 // Optimization Reference Manual", Chapter 13, Section 4.
19 // Atom machine model.
20 def AtomModel : SchedMachineModel {
21 let IssueWidth = 2; // Allows 2 instructions per scheduling group.
22 let MicroOpBufferSize = 0; // In-order execution, always hide latency.
23 let LoadLatency = 3; // Expected cycles, may be overriden.
24 let HighLatency = 30;// Expected, may be overriden.
26 // On the Atom, the throughput for taken branches is 2 cycles. For small
27 // simple loops, expand by a small factor to hide the backedge cost.
28 let LoopMicroOpBufferSize = 10;
29 let PostRAScheduler = 1;
30 let CompleteModel = 0;
33 let SchedModel = AtomModel in {
36 def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store
37 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
38 def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA
39 // SIMD/FP: SIMD ALU, FP Adder
41 def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>;
43 // Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
44 // cycles after the memory operand.
45 def : ReadAdvance<ReadAfterLd, 3>;
47 // Many SchedWrites are defined in pairs with and without a folded load.
48 // Instructions with folded loads are usually micro-fused, so they only appear
49 // as two micro-ops when dispatched by the schedulers.
50 // This multiclass defines the resource usage for variants with and without
52 multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,
53 list<ProcResourceKind> RRPorts,
54 list<ProcResourceKind> RMPorts,
55 int RRLat = 1, int RMLat = 1,
56 list<int> RRRes = [1],
57 list<int> RMRes = [1]> {
58 // Register variant is using a single cycle on ExePort.
59 def : WriteRes<SchedRW, RRPorts> {
61 let ResourceCycles = RRRes;
64 // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
66 def : WriteRes<SchedRW.Folded, RMPorts> {
68 let ResourceCycles = RMRes;
72 // A folded store needs a cycle on Port0 for the store data.
73 def : WriteRes<WriteRMW, [AtomPort0]>;
75 ////////////////////////////////////////////////////////////////////////////////
77 ////////////////////////////////////////////////////////////////////////////////
79 defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>;
80 defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>;
81 defm : AtomWriteResPair<WriteIMul, [AtomPort01], [AtomPort01], 7, 7, [7], [7]>;
82 defm : AtomWriteResPair<WriteIMul64, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>;
84 defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>;
85 defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>;
87 defm : AtomWriteResPair<WriteDiv8, [AtomPort01], [AtomPort01], 50, 68, [50], [68]>;
88 defm : AtomWriteResPair<WriteDiv16, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>;
89 defm : AtomWriteResPair<WriteDiv32, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>;
90 defm : AtomWriteResPair<WriteDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>;
91 defm : AtomWriteResPair<WriteIDiv8, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
92 defm : AtomWriteResPair<WriteIDiv16, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
93 defm : AtomWriteResPair<WriteIDiv32, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
94 defm : AtomWriteResPair<WriteIDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>;
96 defm : X86WriteResPairUnsupported<WriteCRC32>;
98 defm : AtomWriteResPair<WriteCMOV, [AtomPort01], [AtomPort0]>;
99 defm : AtomWriteResPair<WriteCMOV2, [AtomPort01], [AtomPort0]>;
100 defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move.
102 def : WriteRes<WriteSETCC, [AtomPort01]>;
103 def : WriteRes<WriteSETCCStore, [AtomPort01]> {
105 let ResourceCycles = [2];
107 def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
109 let ResourceCycles = [2];
111 def : WriteRes<WriteBitTest,[AtomPort01]>;
113 defm : X86WriteResUnsupported<WriteIMulH>;
115 // This is for simple LEAs with one or two input operands.
116 def : WriteRes<WriteLEA, [AtomPort1]>;
118 def AtomWriteIMul16Ld : SchedWriteRes<[AtomPort01]> {
120 let ResourceCycles = [8];
122 def : InstRW<[AtomWriteIMul16Ld], (instrs MUL16m, IMUL16m)>;
124 def AtomWriteIMul32 : SchedWriteRes<[AtomPort01]> {
126 let ResourceCycles = [6];
128 def : InstRW<[AtomWriteIMul32], (instrs MUL32r, IMUL32r)>;
130 def AtomWriteIMul64I : SchedWriteRes<[AtomPort01]> {
132 let ResourceCycles = [14];
134 def : InstRW<[AtomWriteIMul64I], (instrs IMUL64rri8, IMUL64rri32,
135 IMUL64rmi8, IMUL64rmi32)>;
138 defm : AtomWriteResPair<WriteBSF, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>;
139 defm : AtomWriteResPair<WriteBSR, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>;
140 defm : X86WriteResPairUnsupported<WritePOPCNT>;
141 defm : X86WriteResPairUnsupported<WriteLZCNT>;
142 defm : X86WriteResPairUnsupported<WriteTZCNT>;
144 // BMI1 BEXTR, BMI2 BZHI
145 defm : X86WriteResPairUnsupported<WriteBEXTR>;
146 defm : X86WriteResPairUnsupported<WriteBZHI>;
148 ////////////////////////////////////////////////////////////////////////////////
149 // Integer shifts and rotates.
150 ////////////////////////////////////////////////////////////////////////////////
152 defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>;
154 defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>;
155 defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>;
156 defm : X86WriteRes<WriteSHDmri, [AtomPort01], 4, [4], 1>;
157 defm : X86WriteRes<WriteSHDmrcl,[AtomPort01], 4, [4], 1>;
159 ////////////////////////////////////////////////////////////////////////////////
160 // Loads, stores, and moves, not folded with other operations.
161 ////////////////////////////////////////////////////////////////////////////////
163 def : WriteRes<WriteLoad, [AtomPort0]>;
164 def : WriteRes<WriteStore, [AtomPort0]>;
165 def : WriteRes<WriteStoreNT, [AtomPort0]>;
166 def : WriteRes<WriteMove, [AtomPort01]>;
168 // Treat misc copies as a move.
169 def : InstRW<[WriteMove], (instrs COPY)>;
171 ////////////////////////////////////////////////////////////////////////////////
172 // Idioms that clear a register, like xorps %xmm0, %xmm0.
173 // These can often bypass execution ports completely.
174 ////////////////////////////////////////////////////////////////////////////////
176 def : WriteRes<WriteZero, []>;
178 ////////////////////////////////////////////////////////////////////////////////
179 // Branches don't produce values, so they have no latency, but they still
180 // consume resources. Indirect branches can fold loads.
181 ////////////////////////////////////////////////////////////////////////////////
183 defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>;
185 ////////////////////////////////////////////////////////////////////////////////
186 // Special case scheduling classes.
187 ////////////////////////////////////////////////////////////////////////////////
189 def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; }
190 def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; }
191 def : WriteRes<WriteFence, [AtomPort0]>;
193 // Nops don't have dependencies, so there's no actual latency, but we set this
194 // to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
195 def : WriteRes<WriteNop, [AtomPort01]>;
197 ////////////////////////////////////////////////////////////////////////////////
198 // Floating point. This covers both scalar and vector operations.
199 ////////////////////////////////////////////////////////////////////////////////
201 defm : X86WriteRes<WriteFLD0, [AtomPort01], 1, [1], 1>;
202 defm : X86WriteRes<WriteFLD1, [AtomPort01], 6, [6], 1>;
203 def : WriteRes<WriteFLoad, [AtomPort0]>;
204 def : WriteRes<WriteFLoadX, [AtomPort0]>;
205 defm : X86WriteResUnsupported<WriteFLoadY>;
206 defm : X86WriteResUnsupported<WriteFMaskedLoad>;
207 defm : X86WriteResUnsupported<WriteFMaskedLoadY>;
209 def : WriteRes<WriteFStore, [AtomPort0]>;
210 def : WriteRes<WriteFStoreX, [AtomPort0]>;
211 defm : X86WriteResUnsupported<WriteFStoreY>;
212 def : WriteRes<WriteFStoreNT, [AtomPort0]>;
213 def : WriteRes<WriteFStoreNTX, [AtomPort0]>;
214 defm : X86WriteResUnsupported<WriteFStoreNTY>;
215 defm : X86WriteResUnsupported<WriteFMaskedStore>;
216 defm : X86WriteResUnsupported<WriteFMaskedStoreY>;
218 def : WriteRes<WriteFMove, [AtomPort01]>;
219 def : WriteRes<WriteFMoveX, [AtomPort01]>;
220 defm : X86WriteResUnsupported<WriteFMoveY>;
222 defm : X86WriteRes<WriteEMMS, [AtomPort01], 5, [5], 1>;
224 defm : AtomWriteResPair<WriteFAdd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
225 defm : AtomWriteResPair<WriteFAddX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
226 defm : X86WriteResPairUnsupported<WriteFAddY>;
227 defm : X86WriteResPairUnsupported<WriteFAddZ>;
228 defm : AtomWriteResPair<WriteFAdd64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
229 defm : AtomWriteResPair<WriteFAdd64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
230 defm : X86WriteResPairUnsupported<WriteFAdd64Y>;
231 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
232 defm : AtomWriteResPair<WriteFCmp, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
233 defm : AtomWriteResPair<WriteFCmpX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
234 defm : X86WriteResPairUnsupported<WriteFCmpY>;
235 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
236 defm : AtomWriteResPair<WriteFCmp64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
237 defm : AtomWriteResPair<WriteFCmp64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
238 defm : X86WriteResPairUnsupported<WriteFCmp64Y>;
239 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
240 defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
241 defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
242 defm : AtomWriteResPair<WriteFMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
243 defm : X86WriteResPairUnsupported<WriteFMulY>;
244 defm : X86WriteResPairUnsupported<WriteFMulZ>;
245 defm : AtomWriteResPair<WriteFMul64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
246 defm : AtomWriteResPair<WriteFMul64X, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>;
247 defm : X86WriteResPairUnsupported<WriteFMul64Y>;
248 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
249 defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
250 defm : AtomWriteResPair<WriteFRcpX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>;
251 defm : X86WriteResPairUnsupported<WriteFRcpY>;
252 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
253 defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
254 defm : AtomWriteResPair<WriteFRsqrtX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>;
255 defm : X86WriteResPairUnsupported<WriteFRsqrtY>;
256 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
257 defm : AtomWriteResPair<WriteFDiv, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>;
258 defm : AtomWriteResPair<WriteFDivX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>;
259 defm : X86WriteResPairUnsupported<WriteFDivY>;
260 defm : X86WriteResPairUnsupported<WriteFDivZ>;
261 defm : AtomWriteResPair<WriteFDiv64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
262 defm : AtomWriteResPair<WriteFDiv64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>;
263 defm : X86WriteResPairUnsupported<WriteFDiv64Y>;
264 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
265 defm : AtomWriteResPair<WriteFSqrt, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>;
266 defm : AtomWriteResPair<WriteFSqrtX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>;
267 defm : X86WriteResPairUnsupported<WriteFSqrtY>;
268 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
269 defm : AtomWriteResPair<WriteFSqrt64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
270 defm : AtomWriteResPair<WriteFSqrt64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>;
271 defm : X86WriteResPairUnsupported<WriteFSqrt64Y>;
272 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
273 defm : AtomWriteResPair<WriteFSqrt80, [AtomPort01], [AtomPort01], 71, 71, [71], [71]>;
274 defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>;
275 defm : AtomWriteResPair<WriteFRnd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
276 defm : X86WriteResPairUnsupported<WriteFRndY>;
277 defm : X86WriteResPairUnsupported<WriteFRndZ>;
278 defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>;
279 defm : X86WriteResPairUnsupported<WriteFLogicY>;
280 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
281 defm : AtomWriteResPair<WriteFTest, [AtomPort01], [AtomPort0]>;
282 defm : X86WriteResPairUnsupported<WriteFTestY>;
283 defm : X86WriteResPairUnsupported<WriteFTestZ>;
284 defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>;
285 defm : X86WriteResPairUnsupported<WriteFShuffleY>;
286 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
287 defm : X86WriteResPairUnsupported<WriteFVarShuffle>;
288 defm : X86WriteResPairUnsupported<WriteFVarShuffleY>;
289 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
290 defm : X86WriteResPairUnsupported<WriteFMA>;
291 defm : X86WriteResPairUnsupported<WriteFMAX>;
292 defm : X86WriteResPairUnsupported<WriteFMAY>;
293 defm : X86WriteResPairUnsupported<WriteFMAZ>;
294 defm : X86WriteResPairUnsupported<WriteDPPD>;
295 defm : X86WriteResPairUnsupported<WriteDPPS>;
296 defm : X86WriteResPairUnsupported<WriteDPPSY>;
297 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
298 defm : X86WriteResPairUnsupported<WriteFBlend>;
299 defm : X86WriteResPairUnsupported<WriteFBlendY>;
300 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
301 defm : X86WriteResPairUnsupported<WriteFVarBlend>;
302 defm : X86WriteResPairUnsupported<WriteFVarBlendY>;
303 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
304 defm : X86WriteResPairUnsupported<WriteFShuffle256>;
305 defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
307 ////////////////////////////////////////////////////////////////////////////////
309 ////////////////////////////////////////////////////////////////////////////////
311 defm : AtomWriteResPair<WriteCvtSS2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
312 defm : AtomWriteResPair<WriteCvtPS2I, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
313 defm : X86WriteResPairUnsupported<WriteCvtPS2IY>;
314 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
315 defm : AtomWriteResPair<WriteCvtSD2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
316 defm : AtomWriteResPair<WriteCvtPD2I, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
317 defm : X86WriteResPairUnsupported<WriteCvtPD2IY>;
318 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
320 defm : AtomWriteResPair<WriteCvtI2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
321 defm : AtomWriteResPair<WriteCvtI2PS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
322 defm : X86WriteResPairUnsupported<WriteCvtI2PSY>;
323 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
324 defm : AtomWriteResPair<WriteCvtI2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
325 defm : AtomWriteResPair<WriteCvtI2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
326 defm : X86WriteResPairUnsupported<WriteCvtI2PDY>;
327 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
329 defm : AtomWriteResPair<WriteCvtSS2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
330 defm : AtomWriteResPair<WriteCvtPS2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
331 defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>;
332 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
333 defm : AtomWriteResPair<WriteCvtSD2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
334 defm : AtomWriteResPair<WriteCvtPD2PS, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
335 defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>;
336 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
338 defm : X86WriteResPairUnsupported<WriteCvtPH2PS>;
339 defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>;
340 defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
341 defm : X86WriteResUnsupported<WriteCvtPS2PH>;
342 defm : X86WriteResUnsupported<WriteCvtPS2PHSt>;
343 defm : X86WriteResUnsupported<WriteCvtPS2PHY>;
344 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
345 defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>;
346 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
348 ////////////////////////////////////////////////////////////////////////////////
349 // Vector integer operations.
350 ////////////////////////////////////////////////////////////////////////////////
352 def : WriteRes<WriteVecLoad, [AtomPort0]>;
353 def : WriteRes<WriteVecLoadX, [AtomPort0]>;
354 defm : X86WriteResUnsupported<WriteVecLoadY>;
355 def : WriteRes<WriteVecLoadNT, [AtomPort0]>;
356 defm : X86WriteResUnsupported<WriteVecLoadNTY>;
357 defm : X86WriteResUnsupported<WriteVecMaskedLoad>;
358 defm : X86WriteResUnsupported<WriteVecMaskedLoadY>;
360 def : WriteRes<WriteVecStore, [AtomPort0]>;
361 def : WriteRes<WriteVecStoreX, [AtomPort0]>;
362 defm : X86WriteResUnsupported<WriteVecStoreY>;
363 def : WriteRes<WriteVecStoreNT, [AtomPort0]>;
364 defm : X86WriteResUnsupported<WriteVecStoreNTY>;
365 def : WriteRes<WriteVecMaskedStore, [AtomPort0]>;
366 defm : X86WriteResUnsupported<WriteVecMaskedStoreY>;
368 def : WriteRes<WriteVecMove, [AtomPort0]>;
369 def : WriteRes<WriteVecMoveX, [AtomPort01]>;
370 defm : X86WriteResUnsupported<WriteVecMoveY>;
371 defm : X86WriteRes<WriteVecMoveToGpr, [AtomPort0], 3, [3], 1>;
372 defm : X86WriteRes<WriteVecMoveFromGpr, [AtomPort0], 1, [1], 1>;
374 defm : AtomWriteResPair<WriteVecALU, [AtomPort01], [AtomPort0], 1, 1>;
375 defm : AtomWriteResPair<WriteVecALUX, [AtomPort01], [AtomPort0], 1, 1>;
376 defm : X86WriteResPairUnsupported<WriteVecALUY>;
377 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
378 defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>;
379 defm : AtomWriteResPair<WriteVecLogicX, [AtomPort01], [AtomPort0], 1, 1>;
380 defm : X86WriteResPairUnsupported<WriteVecLogicY>;
381 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
382 defm : AtomWriteResPair<WriteVecTest, [AtomPort01], [AtomPort0], 1, 1>;
383 defm : X86WriteResPairUnsupported<WriteVecTestY>;
384 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
385 defm : AtomWriteResPair<WriteVecShift, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
386 defm : AtomWriteResPair<WriteVecShiftX, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
387 defm : X86WriteResPairUnsupported<WriteVecShiftY>;
388 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
389 defm : AtomWriteResPair<WriteVecShiftImm, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>;
390 defm : AtomWriteResPair<WriteVecShiftImmX, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>;
391 defm : X86WriteResPairUnsupported<WriteVecShiftImmY>;
392 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
393 defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
394 defm : AtomWriteResPair<WriteVecIMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
395 defm : X86WriteResPairUnsupported<WriteVecIMulY>;
396 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
397 defm : X86WriteResPairUnsupported<WritePMULLD>;
398 defm : X86WriteResPairUnsupported<WritePMULLDY>;
399 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
400 defm : X86WriteResPairUnsupported<WritePHMINPOS>;
401 defm : X86WriteResPairUnsupported<WriteMPSAD>;
402 defm : X86WriteResPairUnsupported<WriteMPSADY>;
403 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
404 defm : AtomWriteResPair<WritePSADBW, [AtomPort01], [AtomPort01], 4, 4, [4], [4]>;
405 defm : AtomWriteResPair<WritePSADBWX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
406 defm : X86WriteResPairUnsupported<WritePSADBWY>;
407 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
408 defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>;
409 defm : AtomWriteResPair<WriteShuffleX, [AtomPort0], [AtomPort0], 1, 1>;
410 defm : X86WriteResPairUnsupported<WriteShuffleY>;
411 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
412 defm : AtomWriteResPair<WriteVarShuffle, [AtomPort0], [AtomPort0], 1, 1>;
413 defm : AtomWriteResPair<WriteVarShuffleX, [AtomPort01], [AtomPort01], 4, 5, [4], [5]>;
414 defm : X86WriteResPairUnsupported<WriteVarShuffleY>;
415 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
416 defm : X86WriteResPairUnsupported<WriteBlend>;
417 defm : X86WriteResPairUnsupported<WriteBlendY>;
418 defm : X86WriteResPairUnsupported<WriteBlendZ>;
419 defm : X86WriteResPairUnsupported<WriteVarBlend>;
420 defm : X86WriteResPairUnsupported<WriteVarBlendY>;
421 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
422 defm : X86WriteResPairUnsupported<WriteShuffle256>;
423 defm : X86WriteResPairUnsupported<WriteVarShuffle256>;
424 defm : X86WriteResPairUnsupported<WriteVarVecShift>;
425 defm : X86WriteResPairUnsupported<WriteVarVecShiftY>;
426 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
428 ////////////////////////////////////////////////////////////////////////////////
429 // Vector insert/extract operations.
430 ////////////////////////////////////////////////////////////////////////////////
432 defm : AtomWriteResPair<WriteVecInsert, [AtomPort0], [AtomPort0], 1, 1>;
433 def : WriteRes<WriteVecExtract, [AtomPort0]>;
434 def : WriteRes<WriteVecExtractSt, [AtomPort0]>;
436 ////////////////////////////////////////////////////////////////////////////////
437 // SSE42 String instructions.
438 ////////////////////////////////////////////////////////////////////////////////
440 defm : X86WriteResPairUnsupported<WritePCmpIStrI>;
441 defm : X86WriteResPairUnsupported<WritePCmpIStrM>;
442 defm : X86WriteResPairUnsupported<WritePCmpEStrI>;
443 defm : X86WriteResPairUnsupported<WritePCmpEStrM>;
445 ////////////////////////////////////////////////////////////////////////////////
446 // MOVMSK Instructions.
447 ////////////////////////////////////////////////////////////////////////////////
449 def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
450 def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
451 defm : X86WriteResUnsupported<WriteVecMOVMSKY>;
452 def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
454 ////////////////////////////////////////////////////////////////////////////////
456 ////////////////////////////////////////////////////////////////////////////////
458 defm : X86WriteResPairUnsupported<WriteAESIMC>;
459 defm : X86WriteResPairUnsupported<WriteAESKeyGen>;
460 defm : X86WriteResPairUnsupported<WriteAESDecEnc>;
462 ////////////////////////////////////////////////////////////////////////////////
463 // Horizontal add/sub instructions.
464 ////////////////////////////////////////////////////////////////////////////////
466 defm : AtomWriteResPair<WriteFHAdd, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
467 defm : AtomWriteResPair<WriteFHAddY, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
468 defm : AtomWriteResPair<WritePHAdd, [AtomPort01], [AtomPort01], 3, 4, [3], [4]>;
469 defm : AtomWriteResPair<WritePHAddX, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
470 defm : AtomWriteResPair<WritePHAddY, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
472 ////////////////////////////////////////////////////////////////////////////////
473 // Carry-less multiplication instructions.
474 ////////////////////////////////////////////////////////////////////////////////
476 defm : X86WriteResPairUnsupported<WriteCLMul>;
478 ////////////////////////////////////////////////////////////////////////////////
480 ////////////////////////////////////////////////////////////////////////////////
482 def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; }
483 def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; }
485 ////////////////////////////////////////////////////////////////////////////////
487 ////////////////////////////////////////////////////////////////////////////////
490 def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> {
492 let ResourceCycles = [1];
494 def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr,
496 def : SchedAlias<WriteALURMW, AtomWrite0_1>;
497 def : SchedAlias<WriteADCRMW, AtomWrite0_1>;
498 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
499 "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>;
501 def AtomWrite0_5 : SchedWriteRes<[AtomPort0]> {
503 let ResourceCycles = [5];
505 def : InstRW<[AtomWrite0_5], (instregex "IMUL32(rm|rr)")>;
508 def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> {
510 let ResourceCycles = [1];
512 def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;
513 def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r",
514 "BT(C|R|S)?(16|32|64)(rr|ri8)")>;
516 def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> {
518 let ResourceCycles = [5];
520 def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm,
521 MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>;
524 def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> {
526 let ResourceCycles = [1, 1];
528 def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
529 POP16rmr, POP32rmr, POP64rmr,
530 PUSH16r, PUSH32r, PUSH64r,
532 PUSH16rmr, PUSH32rmr, PUSH64rmr,
533 PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32,
535 def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$",
538 def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
540 let ResourceCycles = [5, 5];
542 def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>;
543 def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;
546 def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> {
548 let ResourceCycles = [1];
550 def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
552 STOSB, STOSL, STOSQ, STOSW,
553 MOVSSrr, MOVSSrr_REV,
554 PSLLDQri, PSRLDQri)>;
555 def : InstRW<[AtomWrite01_1], (instregex "MMX_PACK(SSDW|SSWB|USWB)irr",
556 "MMX_PUNPCKH(BW|DQ|WD)irr")>;
558 def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> {
560 let ResourceCycles = [2];
562 def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r,
563 PUSH16rmm, PUSH32rmm, PUSH64rmm,
564 LODSB, LODSL, LODSQ, LODSW,
565 SCASB, SCASL, SCASQ, SCASW)>;
566 def : InstRW<[AtomWrite01_2], (instregex "BT(C|R|S)(16|32|64)mi8",
567 "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)",
568 "XADD(8|16|32|64)rr",
569 "XCHG(8|16|32|64)(ar|rr)",
570 "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)",
571 "MMX_P(ADD|SUB)Qirr",
573 "MOV(UPS|UPD|DQU)mr",
577 def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> {
579 let ResourceCycles = [3];
581 def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,
582 CMPSB, CMPSL, CMPSQ, CMPSW,
583 MOVSB, MOVSL, MOVSQ, MOVSW,
584 POP16rmm, POP32rmm, POP64rmm)>;
585 def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",
586 "XCHG(8|16|32|64)rm",
589 "MMX_P(ADD|SUB)Qirm",
590 "MOV(UPS|UPD|DQU)rm",
593 def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> {
595 let ResourceCycles = [4];
597 def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO,
600 def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm",
601 "(MMX_)?PEXTRWrr(_REV)?")>;
603 def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> {
605 let ResourceCycles = [5];
607 def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>;
608 def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>;
610 def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> {
612 let ResourceCycles = [6];
614 def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT,
615 SHLD16rrCL, SHRD16rrCL,
616 SHLD16rri8, SHRD16rri8,
617 SHLD16mrCL, SHRD16mrCL,
618 SHLD16mri8, SHRD16mri8)>;
619 def : InstRW<[AtomWrite01_6], (instregex "IMUL16rr",
620 "IST_F(P)?(16|32|64)?m",
621 "MMX_PH(ADD|SUB)S?Wrm")>;
623 def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> {
625 let ResourceCycles = [7];
627 def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>;
629 def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> {
631 let ResourceCycles = [8];
633 def : InstRW<[AtomWrite01_8], (instrs LOOPE,
635 SHLD64rrCL, SHRD64rrCL,
638 def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> {
640 let ResourceCycles = [9];
642 def : InstRW<[AtomWrite01_9], (instrs BT16mr, BT32mr, BT64mr,
644 PUSHF16, PUSHF32, PUSHF64,
645 SHLD64mrCL, SHRD64mrCL,
646 SHLD64mri8, SHRD64mri8,
647 SHLD64rri8, SHRD64rri8,
649 def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F",
651 "CVT(T)?SS2SI64rr(_Int)?")>;
653 def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> {
655 let ResourceCycles = [10];
657 def : SchedAlias<WriteFLDC, AtomWrite01_10>;
658 def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm",
659 "CVT(T)?SS2SI64rm(_Int)?")>;
661 def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> {
663 let ResourceCycles = [11];
665 def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>;
666 def : InstRW<[AtomWrite01_11], (instregex "BT(C|R|S)(16|32|64)mr")>;
668 def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> {
670 let ResourceCycles = [13];
672 def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>;
674 def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> {
676 let ResourceCycles = [14];
678 def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
680 def AtomWrite01_15 : SchedWriteRes<[AtomPort01]> {
682 let ResourceCycles = [15];
684 def : InstRW<[AtomWrite01_15], (instrs CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr)>;
686 def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {
688 let ResourceCycles = [17];
690 def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>;
692 def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> {
694 let ResourceCycles = [18];
696 def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>;
698 def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> {
700 let ResourceCycles = [20];
702 def : InstRW<[AtomWrite01_20], (instrs DAS)>;
704 def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> {
706 let ResourceCycles = [21];
708 def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>;
710 def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> {
712 let ResourceCycles = [22];
714 def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>;
716 def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> {
718 let ResourceCycles = [23];
720 def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>;
722 def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> {
724 let ResourceCycles = [25];
726 def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>;
728 def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> {
730 let ResourceCycles = [26];
732 def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>;
734 def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> {
736 let ResourceCycles = [29];
738 def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>;
740 def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> {
742 let ResourceCycles = [30];
744 def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>;
746 def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> {
748 let ResourceCycles = [32];
750 def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>;
752 def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> {
754 let ResourceCycles = [45];
756 def : InstRW<[AtomWrite01_45], (instrs MONITORrrr)>;
758 def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> {
760 let ResourceCycles = [46];
762 def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>;
764 def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> {
766 let ResourceCycles = [48];
768 def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>;
770 def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> {
772 let ResourceCycles = [55];
774 def : InstRW<[AtomWrite01_55], (instrs FPREM)>;
776 def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> {
778 let ResourceCycles = [59];
780 def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>;
782 def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> {
784 let ResourceCycles = [63];
786 def : InstRW<[AtomWrite01_63], (instrs FNINIT)>;
788 def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> {
790 let ResourceCycles = [68];
792 def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>;
794 def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> {
796 let ResourceCycles = [71];
798 def : InstRW<[AtomWrite01_71], (instrs FPREM1,
799 INVLPG, INVLPGA32, INVLPGA64)>;
801 def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> {
803 let ResourceCycles = [72];
805 def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>;
807 def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> {
809 let ResourceCycles = [74];
811 def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>;
813 def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> {
815 let ResourceCycles = [77];
817 def : InstRW<[AtomWrite01_77], (instrs FSCALE)>;
819 def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> {
821 let ResourceCycles = [78];
823 def : InstRW<[AtomWrite01_78], (instrs RDMSR)>;
825 def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> {
827 let ResourceCycles = [79];
829 def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$",
832 def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> {
834 let ResourceCycles = [92];
836 def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>;
838 def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> {
840 let ResourceCycles = [94];
842 def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>;
844 def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> {
846 let ResourceCycles = [99];
848 def : InstRW<[AtomWrite01_99], (instrs F2XM1)>;
850 def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> {
852 let ResourceCycles = [121];
854 def : InstRW<[AtomWrite01_121], (instrs CPUID)>;
856 def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> {
858 let ResourceCycles = [127];
860 def : InstRW<[AtomWrite01_127], (instrs INT)>;
862 def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> {
864 let ResourceCycles = [130];
866 def : InstRW<[AtomWrite01_130], (instrs INT3)>;
868 def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> {
870 let ResourceCycles = [140];
872 def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>;
874 def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> {
876 let ResourceCycles = [141];
878 def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>;
880 def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> {
882 let ResourceCycles = [146];
884 def : InstRW<[AtomWrite01_146], (instrs FYL2X)>;
886 def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> {
888 let ResourceCycles = [147];
890 def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>;
892 def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> {
894 let ResourceCycles = [168];
896 def : InstRW<[AtomWrite01_168], (instrs FPTAN)>;
898 def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> {
900 let ResourceCycles = [174];
902 def : InstRW<[AtomWrite01_174], (instrs FSINCOS)>;
903 def : InstRW<[AtomWrite01_174], (instregex "(COS|SIN)_F")>;
905 def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> {
907 let ResourceCycles = [183];
909 def : InstRW<[AtomWrite01_183], (instrs FPATAN)>;
911 def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> {
913 let ResourceCycles = [202];
915 def : InstRW<[AtomWrite01_202], (instrs WRMSR)>;