1 //=- X86ScheduleBtVer2.td - X86 BtVer2 (Jaguar) Scheduling ---*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for AMD btver2 (Jaguar) to support
11 // instruction scheduling and other instruction cost heuristics. Based off AMD Software
12 // Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix.
14 //===----------------------------------------------------------------------===//
16 def BtVer2Model : SchedMachineModel {
17 // All x86 instructions are modeled as a single micro-op, and btver2 can
18 // decode 2 instructions per cycle.
20 let MicroOpBufferSize = 64; // Retire Control Unit
21 let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency)
23 let MispredictPenalty = 14; // Minimum branch misdirection penalty
24 let PostRAScheduler = 1;
26 // FIXME: SSE4/AVX is unimplemented. This flag is set to allow
27 // the scheduler to assign a default model to unrecognized opcodes.
28 let CompleteModel = 0;
31 let SchedModel = BtVer2Model in {
33 // Jaguar can issue up to 6 micro-ops in one cycle
34 def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam)
35 def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV
36 def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
37 def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA)
38 def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
39 def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
41 // Any pipe - FIXME we need this until we can discriminate between int/fpu load/store/moves properly
42 def JAny : ProcResGroup<[JALU0, JALU1, JLAGU, JSAGU, JFPU0, JFPU1]>;
44 // Integer Pipe Scheduler
45 def JALU01 : ProcResGroup<[JALU0, JALU1]> {
50 def JLSAGU : ProcResGroup<[JLAGU, JSAGU]> {
55 def JFPU01 : ProcResGroup<[JFPU0, JFPU1]> {
59 def JDiv : ProcResource<1>; // integer division
60 def JMul : ProcResource<1>; // integer multiplication
61 def JVALU0 : ProcResource<1>; // vector integer
62 def JVALU1 : ProcResource<1>; // vector integer
63 def JVIMUL : ProcResource<1>; // vector integer multiplication
64 def JSTC : ProcResource<1>; // vector store/convert
65 def JFPM : ProcResource<1>; // FP multiplication
66 def JFPA : ProcResource<1>; // FP addition
68 // Integer loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
69 // cycles after the memory operand.
70 def : ReadAdvance<ReadAfterLd, 3>;
72 // Many SchedWrites are defined in pairs with and without a folded load.
73 // Instructions with folded loads are usually micro-fused, so they only appear
74 // as two micro-ops when dispatched by the schedulers.
75 // This multiclass defines the resource usage for variants with and without
77 multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
78 ProcResourceKind ExePort,
80 // Register variant is using a single cycle on ExePort.
81 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
83 // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
85 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
86 let Latency = !add(Lat, 3);
90 multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
91 ProcResourceKind ExePort,
93 // Register variant is using a single cycle on ExePort.
94 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
96 // Memory variant also uses a cycle on JLAGU and adds 5 cycles to the
98 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
99 let Latency = !add(Lat, 5);
103 // A folded store needs a cycle on the SAGU for the store data.
104 def : WriteRes<WriteRMW, [JSAGU]>;
106 ////////////////////////////////////////////////////////////////////////////////
108 ////////////////////////////////////////////////////////////////////////////////
110 defm : JWriteResIntPair<WriteALU, JALU01, 1>;
111 defm : JWriteResIntPair<WriteIMul, JALU1, 3>;
113 def : WriteRes<WriteIMulH, [JALU1]> {
115 let ResourceCycles = [4];
118 // FIXME 8/16 bit divisions
119 def : WriteRes<WriteIDiv, [JALU1, JDiv]> {
121 let ResourceCycles = [1, 25];
123 def : WriteRes<WriteIDivLd, [JALU1, JLAGU, JDiv]> {
125 let ResourceCycles = [1, 1, 25];
128 // This is for simple LEAs with one or two input operands.
129 // FIXME: SAGU 3-operand LEA
130 def : WriteRes<WriteLEA, [JALU01]>;
132 ////////////////////////////////////////////////////////////////////////////////
133 // Integer shifts and rotates.
134 ////////////////////////////////////////////////////////////////////////////////
136 defm : JWriteResIntPair<WriteShift, JALU01, 1>;
138 def WriteSHLDrri : SchedWriteRes<[JALU01]> {
140 let ResourceCycles = [6];
143 def: InstRW<[WriteSHLDrri], (instregex "SHLD(16|32|64)rri8")>;
144 def: InstRW<[WriteSHLDrri], (instregex "SHRD(16|32|64)rri8")>;
146 def WriteSHLDrrCL : SchedWriteRes<[JALU01]> {
148 let ResourceCycles = [8];
151 def: InstRW<[WriteSHLDrrCL], (instregex "SHLD(16|32|64)rrCL")>;
152 def: InstRW<[WriteSHLDrrCL], (instregex "SHRD(16|32|64)rrCL")>;
154 def WriteSHLDm : SchedWriteRes<[JLAGU, JALU01]> {
156 let ResourceCycles = [1, 22];
159 def: InstRW<[WriteSHLDm], (instregex "SHLD(16|32|64)mr(i8|CL)")>;
160 def: InstRW<[WriteSHLDm], (instregex "SHRD(16|32|64)mr(i8|CL)")>;
162 ////////////////////////////////////////////////////////////////////////////////
163 // Loads, stores, and moves, not folded with other operations.
164 // FIXME: Split x86 and SSE load/store/moves
165 ////////////////////////////////////////////////////////////////////////////////
167 def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; }
168 def : WriteRes<WriteStore, [JSAGU]>;
169 def : WriteRes<WriteMove, [JALU01]>;
171 // Treat misc copies as a move.
172 def : InstRW<[WriteMove], (instrs COPY)>;
174 ////////////////////////////////////////////////////////////////////////////////
175 // Idioms that clear a register, like xorps %xmm0, %xmm0.
176 // These can often bypass execution ports completely.
177 ////////////////////////////////////////////////////////////////////////////////
179 def : WriteRes<WriteZero, []>;
181 ////////////////////////////////////////////////////////////////////////////////
182 // Branches don't produce values, so they have no latency, but they still
183 // consume resources. Indirect branches can fold loads.
184 ////////////////////////////////////////////////////////////////////////////////
186 defm : JWriteResIntPair<WriteJump, JALU01, 1>;
188 ////////////////////////////////////////////////////////////////////////////////
189 // Floating point. This covers both scalar and vector operations.
190 // FIXME: should we bother splitting JFPU pipe + unit stages for fast instructions?
191 // FIXME: Double precision latencies
192 // FIXME: SS vs PS latencies
193 // FIXME: ymm latencies
194 ////////////////////////////////////////////////////////////////////////////////
196 defm : JWriteResFpuPair<WriteFAdd, JFPU0, 3>;
197 defm : JWriteResFpuPair<WriteFMul, JFPU1, 2>;
198 defm : JWriteResFpuPair<WriteFMA, JFPU1, 2>; // NOTE: Doesn't exist on Jaguar.
199 defm : JWriteResFpuPair<WriteFRcp, JFPU1, 2>;
200 defm : JWriteResFpuPair<WriteFRsqrt, JFPU1, 2>;
201 defm : JWriteResFpuPair<WriteFShuffle, JFPU01, 1>;
202 defm : JWriteResFpuPair<WriteFBlend, JFPU01, 1>;
203 defm : JWriteResFpuPair<WriteFShuffle256, JFPU01, 1>;
205 def : WriteRes<WriteFSqrt, [JFPU1, JLAGU, JFPM]> {
207 let ResourceCycles = [1, 1, 21];
209 def : WriteRes<WriteFSqrtLd, [JFPU1, JLAGU, JFPM]> {
211 let ResourceCycles = [1, 1, 21];
214 def : WriteRes<WriteFDiv, [JFPU1, JLAGU, JFPM]> {
216 let ResourceCycles = [1, 1, 19];
218 def : WriteRes<WriteFDivLd, [JFPU1, JLAGU, JFPM]> {
220 let ResourceCycles = [1, 1, 19];
223 // FIXME: integer pipes
224 defm : JWriteResFpuPair<WriteCvtF2I, JFPU1, 3>; // Float -> Integer.
225 defm : JWriteResFpuPair<WriteCvtI2F, JFPU1, 3>; // Integer -> Float.
226 defm : JWriteResFpuPair<WriteCvtF2F, JFPU1, 3>; // Float -> Float size conversion.
228 def : WriteRes<WriteFVarBlend, [JFPU01]> {
230 let ResourceCycles = [4];
233 def : WriteRes<WriteFVarBlendLd, [JLAGU, JFPU01]> {
235 let ResourceCycles = [1, 4];
239 // Vector integer operations.
240 defm : JWriteResFpuPair<WriteVecALU, JFPU01, 1>;
241 defm : JWriteResFpuPair<WriteVecShift, JFPU01, 1>;
242 defm : JWriteResFpuPair<WriteVecIMul, JFPU0, 2>;
243 defm : JWriteResFpuPair<WriteShuffle, JFPU01, 1>;
244 defm : JWriteResFpuPair<WriteBlend, JFPU01, 1>;
245 defm : JWriteResFpuPair<WriteVecLogic, JFPU01, 1>;
246 defm : JWriteResFpuPair<WriteShuffle256, JFPU01, 1>;
248 def : WriteRes<WriteVarBlend, [JFPU01]> {
250 let ResourceCycles = [4];
253 def : WriteRes<WriteVarBlendLd, [JLAGU, JFPU01]> {
255 let ResourceCycles = [1, 4];
259 // FIXME: why do we need to define AVX2 resource on CPU that doesn't have AVX2?
260 def : WriteRes<WriteVarVecShift, [JFPU01]> {}
261 def : WriteRes<WriteVarVecShiftLd, [JLAGU, JFPU01]> {
263 let ResourceCycles = [1, 2];
266 def : WriteRes<WriteMPSAD, [JFPU0]> {
268 let ResourceCycles = [2];
270 def : WriteRes<WriteMPSADLd, [JLAGU, JFPU0]> {
272 let ResourceCycles = [1, 2];
275 ////////////////////////////////////////////////////////////////////////////////
276 // String instructions.
277 // Packed Compare Implicit Length Strings, Return Mask
278 // FIXME: approximate latencies + pipe dependencies
279 ////////////////////////////////////////////////////////////////////////////////
281 def : WriteRes<WritePCmpIStrM, [JFPU1,JFPU0]> {
283 let ResourceCycles = [2, 2];
286 def : WriteRes<WritePCmpIStrMLd, [JLAGU, JFPU1, JFPU0]> {
288 let ResourceCycles = [1, 2, 2];
292 // Packed Compare Explicit Length Strings, Return Mask
293 def : WriteRes<WritePCmpEStrM, [JFPU1, JLAGU, JFPU01,JFPU1, JFPU0]> {
295 let ResourceCycles = [5, 5, 5, 5, 5];
298 def : WriteRes<WritePCmpEStrMLd, [JLAGU, JFPU1, JLAGU, JFPU01,JFPU1, JFPU0]> {
300 let ResourceCycles = [1, 5, 5, 5, 5, 5];
304 // Packed Compare Implicit Length Strings, Return Index
305 def : WriteRes<WritePCmpIStrI, [JFPU1, JFPU0]> {
307 let ResourceCycles = [2, 2];
309 def : WriteRes<WritePCmpIStrILd, [JLAGU, JFPU1, JFPU0]> {
311 let ResourceCycles = [1, 2, 2];
314 // Packed Compare Explicit Length Strings, Return Index
315 def : WriteRes<WritePCmpEStrI, [JFPU1, JLAGU, JFPU01,JFPU1, JFPU0]> {
317 let ResourceCycles = [5, 5, 5, 5, 5];
320 def : WriteRes<WritePCmpEStrILd, [JLAGU, JFPU1, JLAGU, JFPU01,JFPU1, JFPU0]> {
322 let ResourceCycles = [1, 5, 5, 5, 5, 5];
326 ////////////////////////////////////////////////////////////////////////////////
328 ////////////////////////////////////////////////////////////////////////////////
330 def : WriteRes<WriteAESDecEnc, [JFPU01, JVIMUL]> {
332 let ResourceCycles = [1, 1];
334 def : WriteRes<WriteAESDecEncLd, [JFPU01, JLAGU, JVIMUL]> {
336 let ResourceCycles = [1, 1, 1];
339 def : WriteRes<WriteAESIMC, [JVIMUL]> {
341 let ResourceCycles = [1];
343 def : WriteRes<WriteAESIMCLd, [JLAGU, JVIMUL]> {
345 let ResourceCycles = [1, 1];
348 def : WriteRes<WriteAESKeyGen, [JVIMUL]> {
350 let ResourceCycles = [1];
352 def : WriteRes<WriteAESKeyGenLd, [JLAGU, JVIMUL]> {
354 let ResourceCycles = [1, 1];
357 ////////////////////////////////////////////////////////////////////////////////
358 // Horizontal add/sub instructions.
359 ////////////////////////////////////////////////////////////////////////////////
361 def : WriteRes<WriteFHAdd, [JFPU0]> {
365 def : WriteRes<WriteFHAddLd, [JLAGU, JFPU0]> {
369 def : WriteRes<WritePHAdd, [JFPU01]> {
370 let ResourceCycles = [1];
372 def : WriteRes<WritePHAddLd, [JLAGU, JFPU01 ]> {
374 let ResourceCycles = [1, 1];
377 def WriteFHAddY: SchedWriteRes<[JFPU0]> {
379 let ResourceCycles = [2];
381 def : InstRW<[WriteFHAddY], (instregex "VH(ADD|SUB)P(S|D)Yrr")>;
383 def WriteFHAddYLd: SchedWriteRes<[JLAGU, JFPU0]> {
385 let ResourceCycles = [1, 2];
387 def : InstRW<[WriteFHAddYLd], (instregex "VH(ADD|SUB)P(S|D)Yrm")>;
389 ////////////////////////////////////////////////////////////////////////////////
390 // Carry-less multiplication instructions.
391 ////////////////////////////////////////////////////////////////////////////////
393 def : WriteRes<WriteCLMul, [JVIMUL]> {
395 let ResourceCycles = [1];
397 def : WriteRes<WriteCLMulLd, [JLAGU, JVIMUL]> {
399 let ResourceCycles = [1, 1];
402 // FIXME: pipe for system/microcode?
403 def : WriteRes<WriteSystem, [JAny]> { let Latency = 100; }
404 def : WriteRes<WriteMicrocoded, [JAny]> { let Latency = 100; }
405 def : WriteRes<WriteFence, [JSAGU]>;
406 def : WriteRes<WriteNop, []>;
408 ////////////////////////////////////////////////////////////////////////////////
409 // SSE4.1 instructions.
410 ////////////////////////////////////////////////////////////////////////////////
412 def WriteDPPS: SchedWriteRes<[JFPU0, JFPU1]> {
414 let ResourceCycles = [3,3];
417 def : InstRW<[WriteDPPS], (instregex "(V)?DPPSrri")>;
419 def WriteDPPSLd: SchedWriteRes<[JLAGU, JFPU0, JFPU1]> {
421 let ResourceCycles = [1,3,3];
424 def : InstRW<[WriteDPPSLd], (instregex "(V)?DPPSrmi")>;
426 def WriteDPPD: SchedWriteRes<[JFPU0, JFPU1]> {
428 let ResourceCycles = [3,3];
431 def : InstRW<[WriteDPPD], (instregex "(V)?DPPDrri")>;
433 def WriteDPPDLd: SchedWriteRes<[JLAGU, JFPU0, JFPU1]> {
435 let ResourceCycles = [1,3,3];
438 def : InstRW<[WriteDPPDLd], (instregex "(V)?DPPDrmi")>;
440 ////////////////////////////////////////////////////////////////////////////////
441 // SSE4A instructions.
442 ////////////////////////////////////////////////////////////////////////////////
444 def WriteEXTRQ: SchedWriteRes<[JFPU01]> {
446 let ResourceCycles = [1];
448 def : InstRW<[WriteEXTRQ], (instregex "EXTRQ")>;
450 def WriteINSERTQ: SchedWriteRes<[JFPU01]> {
452 let ResourceCycles = [4];
454 def : InstRW<[WriteINSERTQ], (instregex "INSERTQ")>;
456 ////////////////////////////////////////////////////////////////////////////////
457 // F16C instructions.
458 ////////////////////////////////////////////////////////////////////////////////
460 def WriteCVT3: SchedWriteRes<[JFPU1]> {
463 def : InstRW<[WriteCVT3], (instregex "VCVTPS2PHrr")>;
464 def : InstRW<[WriteCVT3], (instregex "VCVTPH2PSrr")>;
466 def WriteCVT3St: SchedWriteRes<[JFPU1, JSAGU]> {
468 let ResourceCycles = [1, 1];
470 def : InstRW<[WriteCVT3St], (instregex "VCVTPS2PHmr")>;
472 def WriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1]> {
474 let ResourceCycles = [1, 1];
476 def : InstRW<[WriteCVT3Ld], (instregex "VCVTPH2PSrm")>;
478 def WriteCVTPS2PHY: SchedWriteRes<[JFPU1, JFPU01]> {
480 let ResourceCycles = [2,2];
483 def : InstRW<[WriteCVTPS2PHY], (instregex "VCVTPS2PHYrr")>;
485 def WriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JFPU01, JSAGU]> {
487 let ResourceCycles = [2,2,1];
490 def : InstRW<[WriteCVTPS2PHYSt], (instregex "VCVTPS2PHYmr")>;
492 def WriteCVTPH2PSY: SchedWriteRes<[JFPU1]> {
494 let ResourceCycles = [2];
497 def : InstRW<[WriteCVTPH2PSY], (instregex "VCVTPH2PSYrr")>;
499 def WriteCVTPH2PSYLd: SchedWriteRes<[JLAGU, JFPU1]> {
501 let ResourceCycles = [1,2];
504 def : InstRW<[WriteCVTPH2PSYLd], (instregex "VCVTPH2PSYrm")>;
506 ////////////////////////////////////////////////////////////////////////////////
508 ////////////////////////////////////////////////////////////////////////////////
510 def WriteVDPPSY: SchedWriteRes<[JFPU1, JFPU0]> {
512 let ResourceCycles = [6, 6];
513 let NumMicroOps = 10;
515 def : InstRW<[WriteVDPPSY], (instregex "VDPPSYrr")>;
517 def WriteVDPPSYLd: SchedWriteRes<[JLAGU, JFPU1, JFPU0]> {
519 let ResourceCycles = [1, 6, 6];
520 let NumMicroOps = 11;
522 def : InstRW<[WriteVDPPSYLd, ReadAfterLd], (instregex "VDPPSYrm")>;
524 def WriteFAddY: SchedWriteRes<[JFPU0]> {
526 let ResourceCycles = [2];
528 def : InstRW<[WriteFAddY], (instregex "VADD(SUB)?P(S|D)Yrr", "VSUBP(S|D)Yrr")>;
530 def WriteFAddYLd: SchedWriteRes<[JLAGU, JFPU0]> {
532 let ResourceCycles = [1, 2];
534 def : InstRW<[WriteFAddYLd, ReadAfterLd], (instregex "VADD(SUB)?P(S|D)Yrm", "VSUBP(S|D)Yrm")>;
536 def WriteFDivY: SchedWriteRes<[JFPU1]> {
538 let ResourceCycles = [38];
540 def : InstRW<[WriteFDivY], (instregex "VDIVP(D|S)Yrr")>;
542 def WriteFDivYLd: SchedWriteRes<[JLAGU, JFPU1]> {
544 let ResourceCycles = [1, 38];
546 def : InstRW<[WriteFDivYLd, ReadAfterLd], (instregex "VDIVP(S|D)Yrm")>;
548 def WriteVMULYPD: SchedWriteRes<[JFPU1]> {
550 let ResourceCycles = [4];
552 def : InstRW<[WriteVMULYPD], (instregex "VMULPDYrr")>;
554 def WriteVMULYPDLd: SchedWriteRes<[JLAGU, JFPU1]> {
556 let ResourceCycles = [1, 4];
558 def : InstRW<[WriteVMULYPDLd, ReadAfterLd], (instregex "VMULPDYrm")>;
560 def WriteVMULYPS: SchedWriteRes<[JFPU1]> {
562 let ResourceCycles = [2];
564 def : InstRW<[WriteVMULYPS], (instregex "VMULPSYrr", "VRCPPSYr", "VRSQRTPSYr")>;
566 def WriteVMULYPSLd: SchedWriteRes<[JLAGU, JFPU1]> {
568 let ResourceCycles = [1, 2];
570 def : InstRW<[WriteVMULYPSLd, ReadAfterLd], (instregex "VMULPSYrm", "VRCPPSYm", "VRSQRTPSYm")>;
572 def WriteVCVTY: SchedWriteRes<[JSTC]> {
574 let ResourceCycles = [2];
576 def : InstRW<[WriteVCVTY], (instregex "VCVTDQ2P(S|D)Yrr")>;
577 def : InstRW<[WriteVCVTY], (instregex "VROUNDYP(S|D)r")>;
578 def : InstRW<[WriteVCVTY], (instregex "VCVTPS2DQYrr")>;
579 def : InstRW<[WriteVCVTY], (instregex "VCVTTPS2DQYrr")>;
581 def WriteVCVTYLd: SchedWriteRes<[JLAGU, JSTC]> {
583 let ResourceCycles = [1, 2];
585 def : InstRW<[WriteVCVTYLd, ReadAfterLd], (instregex "VCVTDQ2P(S|D)Yrm")>;
586 def : InstRW<[WriteVCVTYLd, ReadAfterLd], (instregex "VROUNDYP(S|D)m")>;
587 def : InstRW<[WriteVCVTYLd, ReadAfterLd], (instregex "VCVTPS2DQYrm")>;
588 def : InstRW<[WriteVCVTYLd, ReadAfterLd], (instregex "VCVTTPS2DQYrm")>;
590 def WriteVMONTPSt: SchedWriteRes<[JSTC, JLAGU]> {
592 let ResourceCycles = [2,1];
594 def : InstRW<[WriteVMONTPSt], (instregex "VMOVNTP(S|D)Ymr")>;
595 def : InstRW<[WriteVMONTPSt], (instregex "VMOVNTDQYmr")>;
597 def WriteVCVTPDY: SchedWriteRes<[JSTC, JFPU01]> {
599 let ResourceCycles = [2, 4];
601 def : InstRW<[WriteVCVTPDY], (instregex "VCVTPD2(DQ|PS)Yrr")>;
602 def : InstRW<[WriteVCVTPDY], (instregex "VCVTTPD2DQYrr")>;
604 def WriteVCVTPDYLd: SchedWriteRes<[JLAGU, JSTC, JFPU01]> {
606 let ResourceCycles = [1, 2, 4];
608 def : InstRW<[WriteVCVTPDYLd, ReadAfterLd], (instregex "VCVTPD2(DQ|PS)Yrm")>;
609 def : InstRW<[WriteVCVTPDYLd, ReadAfterLd], (instregex "VCVTTPD2DQYrm")>;
611 def WriteVBlendVPY: SchedWriteRes<[JFPU01]> {
613 let ResourceCycles = [6];
615 def : InstRW<[WriteVBlendVPY], (instregex "VBLENDVP(S|D)Yrr", "VPERMILP(D|S)Yrr")>;
617 def WriteVBlendVPYLd: SchedWriteRes<[JLAGU, JFPU01]> {
619 let ResourceCycles = [1, 6];
621 def : InstRW<[WriteVBlendVPYLd, ReadAfterLd], (instregex "VBLENDVP(S|D)Yrm")>;
623 def WriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01]> {
625 let ResourceCycles = [1, 4];
627 def : InstRW<[WriteVBROADCASTYLd, ReadAfterLd], (instregex "VBROADCASTS(S|D)Yrm")>;
629 def WriteFPAY22: SchedWriteRes<[JFPU0]> {
631 let ResourceCycles = [2];
633 def : InstRW<[WriteFPAY22], (instregex "VCMPP(S|D)Yrri", "VM(AX|IN)P(D|S)Yrr")>;
635 def WriteFPAY22Ld: SchedWriteRes<[JLAGU, JFPU0]> {
637 let ResourceCycles = [1, 2];
639 def : InstRW<[WriteFPAY22Ld, ReadAfterLd], (instregex "VCMPP(S|D)Yrmi", "VM(AX|IN)P(D|S)Yrm")>;
641 def WriteVHAddSubY: SchedWriteRes<[JFPU0]> {
643 let ResourceCycles = [2];
645 def : InstRW<[WriteVHAddSubY], (instregex "VH(ADD|SUB)P(D|S)Yrr")>;
647 def WriteVHAddSubYLd: SchedWriteRes<[JLAGU, JFPU0]> {
649 let ResourceCycles = [1, 2];
651 def : InstRW<[WriteVHAddSubYLd], (instregex "VH(ADD|SUB)P(D|S)Yrm")>;
653 def WriteVMaskMovLd: SchedWriteRes<[JLAGU,JFPU01]> {
655 let ResourceCycles = [1, 2];
657 def : InstRW<[WriteVMaskMovLd], (instregex "VMASKMOVP(D|S)rm")>;
659 def WriteVMaskMovYLd: SchedWriteRes<[JLAGU,JFPU01]> {
661 let ResourceCycles = [1, 4];
663 def : InstRW<[WriteVMaskMovYLd], (instregex "VMASKMOVP(D|S)Yrm")>;
665 def WriteVMaskMovSt: SchedWriteRes<[JFPU01,JSAGU]> {
667 let ResourceCycles = [4, 1];
669 def : InstRW<[WriteVMaskMovSt], (instregex "VMASKMOVP(D|S)mr")>;
671 def WriteVMaskMovYSt: SchedWriteRes<[JFPU01,JSAGU]> {
673 let ResourceCycles = [4, 1];
675 def : InstRW<[WriteVMaskMovYSt], (instregex "VMASKMOVP(D|S)Ymr")>;
677 // TODO: In fact we have latency '2+i'. The +i represents an additional 1 cycle transfer
678 // operation which moves the floating point result to the integer unit. During this
679 // additional cycle the floating point unit execution resources are not occupied
680 // and ALU0 in the integer unit is occupied instead.
681 def WriteVMOVMSK: SchedWriteRes<[JFPU0]> {
684 def : InstRW<[WriteVMOVMSK], (instregex "VMOVMSKP(D|S)(Y)?rr")>;
686 // TODO: In fact we have latency '3+i'. The +i represents an additional 1 cycle transfer
687 // operation which moves the floating point result to the integer unit. During this
688 // additional cycle the floating point unit execution resources are not occupied
689 // and ALU0 in the integer unit is occupied instead.
690 def WriteVTESTY: SchedWriteRes<[JFPU01, JFPU0]> {
692 let ResourceCycles = [2, 2];
695 def : InstRW<[WriteVTESTY], (instregex "VTESTP(S|D)Yrr")>;
696 def : InstRW<[WriteVTESTY], (instregex "VPTESTYrr")>;
698 def WriteVTESTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPU0]> {
700 let ResourceCycles = [1, 2, 2];
703 def : InstRW<[WriteVTESTYLd], (instregex "VTESTP(S|D)Yrm")>;
704 def : InstRW<[WriteVTESTYLd], (instregex "VPTESTYrm")>;
706 def WriteVTEST: SchedWriteRes<[JFPU0]> {
709 def : InstRW<[WriteVTEST], (instregex "VTESTP(S|D)rr")>;
710 def : InstRW<[WriteVTEST], (instregex "VPTESTrr")>;
712 def WriteVTESTLd: SchedWriteRes<[JLAGU, JFPU0]> {
715 def : InstRW<[WriteVTESTLd], (instregex "VTESTP(S|D)rm")>;
716 def : InstRW<[WriteVTESTLd], (instregex "VPTESTrm")>;
718 def WriteVSQRTYPD: SchedWriteRes<[JFPU1]> {
720 let ResourceCycles = [54];
722 def : InstRW<[WriteVSQRTYPD], (instregex "VSQRTPDYr")>;
724 def WriteVSQRTYPDLd: SchedWriteRes<[JLAGU, JFPU1]> {
726 let ResourceCycles = [1, 54];
728 def : InstRW<[WriteVSQRTYPDLd], (instregex "VSQRTPDYm")>;
730 def WriteVSQRTYPS: SchedWriteRes<[JFPU1]> {
732 let ResourceCycles = [42];
734 def : InstRW<[WriteVSQRTYPS], (instregex "VSQRTPSYr")>;
736 def WriteVSQRTYPSLd: SchedWriteRes<[JLAGU, JFPU1]> {
738 let ResourceCycles = [1, 42];
740 def : InstRW<[WriteVSQRTYPSLd], (instregex "VSQRTPSYm")>;
742 def WriteJVZEROALL: SchedWriteRes<[]> {
744 let NumMicroOps = 73;
746 def : InstRW<[WriteJVZEROALL], (instregex "VZEROALL")>;
748 def WriteJVZEROUPPER: SchedWriteRes<[]> {
750 let NumMicroOps = 37;
752 def : InstRW<[WriteJVZEROUPPER], (instregex "VZEROUPPER")>;