1 //=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Intel Silvermont to support
11 // instruction scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def SLMModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and SLM can decode 2
17 // instructions per cycle.
19 let MicroOpBufferSize = 32; // Based on the reorder buffer.
21 let MispredictPenalty = 10;
22 let PostRAScheduler = 1;
24 // For small loops, expand by a small factor to hide the backedge cost.
25 let LoopMicroOpBufferSize = 10;
27 // FIXME: SSE4 is unimplemented. This flag is set to allow
28 // the scheduler to assign a default model to unrecognized opcodes.
29 let CompleteModel = 0;
32 let SchedModel = SLMModel in {
34 // Silvermont has 5 reservation stations for micro-ops
35 def SLM_IEC_RSV0 : ProcResource<1>;
36 def SLM_IEC_RSV1 : ProcResource<1>;
37 def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
38 def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
39 def SLM_MEC_RSV : ProcResource<1>;
41 // Many micro-ops are capable of issuing on multiple ports.
42 def SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>;
43 def SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>;
45 def SLMDivider : ProcResource<1>;
46 def SLMFPMultiplier : ProcResource<1>;
47 def SLMFPDivider : ProcResource<1>;
49 // Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
50 // cycles after the memory operand.
51 def : ReadAdvance<ReadAfterLd, 3>;
53 // Many SchedWrites are defined in pairs with and without a folded load.
54 // Instructions with folded loads are usually micro-fused, so they only appear
55 // as two micro-ops when queued in the reservation station.
56 // This multiclass defines the resource usage for variants with and without
58 multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
59 list<ProcResourceKind> ExePorts,
60 int Lat, list<int> Res = [1], int UOps = 1,
62 // Register variant is using a single cycle on ExePort.
63 def : WriteRes<SchedRW, ExePorts> {
65 let ResourceCycles = Res;
66 let NumMicroOps = UOps;
69 // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to
70 // the latency (default = 3).
71 def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
72 let Latency = !add(Lat, LoadLat);
73 let ResourceCycles = !listconcat([1], Res);
74 let NumMicroOps = UOps;
78 // A folded store needs a cycle on MEC_RSV for the store data, but it does not
79 // need an extra port cycle to recompute the address.
80 def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
82 def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
83 def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
84 def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; }
85 def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
86 def : WriteRes<WriteZero, []>;
89 // FIXME: These are probably wrong. They are copy pasted from WriteStore/Load.
90 def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
91 def : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; }
93 // Treat misc copies as a move.
94 def : InstRW<[WriteMove], (instrs COPY)>;
96 defm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>;
97 defm : SLMWriteResPair<WriteADC, [SLM_IEC_RSV01], 1>;
98 defm : SLMWriteResPair<WriteIMul, [SLM_IEC_RSV1], 3>;
99 defm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1], 3>;
101 defm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>;
102 defm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>;
104 defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>;
106 defm : X86WriteRes<WriteSHDrri, [SLM_IEC_RSV0], 1, [1], 1>;
107 defm : X86WriteRes<WriteSHDrrcl,[SLM_IEC_RSV0], 1, [1], 1>;
108 defm : X86WriteRes<WriteSHDmri, [SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>;
109 defm : X86WriteRes<WriteSHDmrcl,[SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>;
111 defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>;
112 defm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1], 3>;
114 defm : SLMWriteResPair<WriteCMOV, [SLM_IEC_RSV01], 2, [2]>;
115 defm : SLMWriteResPair<WriteCMOV2, [SLM_IEC_RSV01], 2, [2]>;
116 defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional move.
117 def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
118 def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
119 // FIXME Latency and NumMicrOps?
120 let ResourceCycles = [2,1];
122 def : WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01]>;
123 def : WriteRes<WriteBitTest,[SLM_IEC_RSV01]>;
125 // This is for simple LEAs with one or two input operands.
126 // The complex ones can only execute on port 1, and they require two cycles on
127 // the port to read all inputs. We don't model that.
128 def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
131 defm : SLMWriteResPair<WriteBSF, [SLM_IEC_RSV01], 10, [20], 10>;
132 defm : SLMWriteResPair<WriteBSR, [SLM_IEC_RSV01], 10, [20], 10>;
133 defm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>;
134 defm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>;
135 defm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>;
137 // BMI1 BEXTR, BMI2 BZHI
138 defm : X86WriteResPairUnsupported<WriteBEXTR>;
139 defm : X86WriteResPairUnsupported<WriteBZHI>;
141 defm : SLMWriteResPair<WriteDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
142 defm : SLMWriteResPair<WriteDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
143 defm : SLMWriteResPair<WriteDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
144 defm : SLMWriteResPair<WriteDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
145 defm : SLMWriteResPair<WriteIDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
146 defm : SLMWriteResPair<WriteIDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
147 defm : SLMWriteResPair<WriteIDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
148 defm : SLMWriteResPair<WriteIDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
150 // Scalar and vector floating point.
151 defm : X86WriteRes<WriteFLD0, [SLM_FPC_RSV01], 1, [1], 1>;
152 defm : X86WriteRes<WriteFLD1, [SLM_FPC_RSV01], 1, [1], 1>;
153 defm : X86WriteRes<WriteFLDC, [SLM_FPC_RSV01], 1, [2], 2>;
154 def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; }
155 def : WriteRes<WriteFLoadX, [SLM_MEC_RSV]> { let Latency = 3; }
156 def : WriteRes<WriteFLoadY, [SLM_MEC_RSV]> { let Latency = 3; }
157 def : WriteRes<WriteFMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; }
158 def : WriteRes<WriteFMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; }
159 def : WriteRes<WriteFStore, [SLM_MEC_RSV]>;
160 def : WriteRes<WriteFStoreX, [SLM_MEC_RSV]>;
161 def : WriteRes<WriteFStoreY, [SLM_MEC_RSV]>;
162 def : WriteRes<WriteFStoreNT, [SLM_MEC_RSV]>;
163 def : WriteRes<WriteFStoreNTX, [SLM_MEC_RSV]>;
164 def : WriteRes<WriteFStoreNTY, [SLM_MEC_RSV]>;
165 def : WriteRes<WriteFMaskedStore, [SLM_MEC_RSV]>;
166 def : WriteRes<WriteFMaskedStoreY, [SLM_MEC_RSV]>;
167 def : WriteRes<WriteFMove, [SLM_FPC_RSV01]>;
168 def : WriteRes<WriteFMoveX, [SLM_FPC_RSV01]>;
169 def : WriteRes<WriteFMoveY, [SLM_FPC_RSV01]>;
170 defm : X86WriteRes<WriteEMMS, [SLM_FPC_RSV01], 10, [10], 9>;
172 defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>;
173 defm : SLMWriteResPair<WriteFAddX, [SLM_FPC_RSV1], 3>;
174 defm : SLMWriteResPair<WriteFAddY, [SLM_FPC_RSV1], 3>;
175 defm : X86WriteResPairUnsupported<WriteFAddZ>;
176 defm : SLMWriteResPair<WriteFAdd64, [SLM_FPC_RSV1], 3>;
177 defm : SLMWriteResPair<WriteFAdd64X, [SLM_FPC_RSV1], 3>;
178 defm : SLMWriteResPair<WriteFAdd64Y, [SLM_FPC_RSV1], 3>;
179 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
180 defm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>;
181 defm : SLMWriteResPair<WriteFCmpX, [SLM_FPC_RSV1], 3>;
182 defm : SLMWriteResPair<WriteFCmpY, [SLM_FPC_RSV1], 3>;
183 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
184 defm : SLMWriteResPair<WriteFCmp64, [SLM_FPC_RSV1], 3>;
185 defm : SLMWriteResPair<WriteFCmp64X, [SLM_FPC_RSV1], 3>;
186 defm : SLMWriteResPair<WriteFCmp64Y, [SLM_FPC_RSV1], 3>;
187 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
188 defm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>;
189 defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
190 defm : SLMWriteResPair<WriteFMulX, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
191 defm : SLMWriteResPair<WriteFMulY, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
192 defm : X86WriteResPairUnsupported<WriteFMulZ>;
193 defm : SLMWriteResPair<WriteFMul64, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
194 defm : SLMWriteResPair<WriteFMul64X, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
195 defm : SLMWriteResPair<WriteFMul64Y, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
196 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
197 defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 19, [1,17]>;
198 defm : SLMWriteResPair<WriteFDivX, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>;
199 defm : SLMWriteResPair<WriteFDivY, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>;
200 defm : X86WriteResPairUnsupported<WriteFDivZ>;
201 defm : SLMWriteResPair<WriteFDiv64, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,32]>;
202 defm : SLMWriteResPair<WriteFDiv64X, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>;
203 defm : SLMWriteResPair<WriteFDiv64Y, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>;
204 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
205 defm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 5>;
206 defm : SLMWriteResPair<WriteFRcpX, [SLM_FPC_RSV0], 5>;
207 defm : SLMWriteResPair<WriteFRcpY, [SLM_FPC_RSV0], 5>;
208 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
209 defm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 5>;
210 defm : SLMWriteResPair<WriteFRsqrtX, [SLM_FPC_RSV0], 5>;
211 defm : SLMWriteResPair<WriteFRsqrtY, [SLM_FPC_RSV0], 5>;
212 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
213 defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0,SLMFPDivider], 20, [1,20], 1, 3>;
214 defm : SLMWriteResPair<WriteFSqrtX, [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>;
215 defm : SLMWriteResPair<WriteFSqrtY, [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>;
216 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
217 defm : SLMWriteResPair<WriteFSqrt64, [SLM_FPC_RSV0,SLMFPDivider], 35, [1,35], 1, 3>;
218 defm : SLMWriteResPair<WriteFSqrt64X, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>;
219 defm : SLMWriteResPair<WriteFSqrt64Y, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>;
220 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
221 defm : SLMWriteResPair<WriteFSqrt80, [SLM_FPC_RSV0,SLMFPDivider], 40, [1,40]>;
222 defm : SLMWriteResPair<WriteDPPD, [SLM_FPC_RSV1], 3>;
223 defm : SLMWriteResPair<WriteDPPS, [SLM_FPC_RSV1], 3>;
224 defm : SLMWriteResPair<WriteDPPSY, [SLM_FPC_RSV1], 3>;
225 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
226 defm : SLMWriteResPair<WriteFSign, [SLM_FPC_RSV01], 1>;
227 defm : SLMWriteResPair<WriteFRnd, [SLM_FPC_RSV1], 3>;
228 defm : SLMWriteResPair<WriteFRndY, [SLM_FPC_RSV1], 3>;
229 defm : X86WriteResPairUnsupported<WriteFRndZ>;
230 defm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>;
231 defm : SLMWriteResPair<WriteFLogicY, [SLM_FPC_RSV01], 1>;
232 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
233 defm : SLMWriteResPair<WriteFTest, [SLM_FPC_RSV01], 1>;
234 defm : SLMWriteResPair<WriteFTestY, [SLM_FPC_RSV01], 1>;
235 defm : X86WriteResPairUnsupported<WriteFTestZ>;
236 defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>;
237 defm : SLMWriteResPair<WriteFShuffleY, [SLM_FPC_RSV0], 1>;
238 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
239 defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>;
240 defm : SLMWriteResPair<WriteFVarShuffleY,[SLM_FPC_RSV0], 1>;
241 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
242 defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>;
244 // Conversion between integer and float.
245 defm : SLMWriteResPair<WriteCvtSS2I, [SLM_FPC_RSV01], 4>;
246 defm : SLMWriteResPair<WriteCvtPS2I, [SLM_FPC_RSV01], 4>;
247 defm : SLMWriteResPair<WriteCvtPS2IY, [SLM_FPC_RSV01], 4>;
248 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
249 defm : SLMWriteResPair<WriteCvtSD2I, [SLM_FPC_RSV01], 4>;
250 defm : SLMWriteResPair<WriteCvtPD2I, [SLM_FPC_RSV01], 4>;
251 defm : SLMWriteResPair<WriteCvtPD2IY, [SLM_FPC_RSV01], 4>;
252 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
254 defm : SLMWriteResPair<WriteCvtI2SS, [SLM_FPC_RSV01], 4>;
255 defm : SLMWriteResPair<WriteCvtI2PS, [SLM_FPC_RSV01], 4>;
256 defm : SLMWriteResPair<WriteCvtI2PSY, [SLM_FPC_RSV01], 4>;
257 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
258 defm : SLMWriteResPair<WriteCvtI2SD, [SLM_FPC_RSV01], 4>;
259 defm : SLMWriteResPair<WriteCvtI2PD, [SLM_FPC_RSV01], 4>;
260 defm : SLMWriteResPair<WriteCvtI2PDY, [SLM_FPC_RSV01], 4>;
261 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
263 defm : SLMWriteResPair<WriteCvtSS2SD, [SLM_FPC_RSV01], 4>;
264 defm : SLMWriteResPair<WriteCvtPS2PD, [SLM_FPC_RSV01], 4>;
265 defm : SLMWriteResPair<WriteCvtPS2PDY, [SLM_FPC_RSV01], 4>;
266 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
267 defm : SLMWriteResPair<WriteCvtSD2SS, [SLM_FPC_RSV01], 4>;
268 defm : SLMWriteResPair<WriteCvtPD2PS, [SLM_FPC_RSV01], 4>;
269 defm : SLMWriteResPair<WriteCvtPD2PSY, [SLM_FPC_RSV01], 4>;
270 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
272 // Vector integer operations.
273 def : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; }
274 def : WriteRes<WriteVecLoadX, [SLM_MEC_RSV]> { let Latency = 3; }
275 def : WriteRes<WriteVecLoadY, [SLM_MEC_RSV]> { let Latency = 3; }
276 def : WriteRes<WriteVecLoadNT, [SLM_MEC_RSV]> { let Latency = 3; }
277 def : WriteRes<WriteVecLoadNTY, [SLM_MEC_RSV]> { let Latency = 3; }
278 def : WriteRes<WriteVecMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; }
279 def : WriteRes<WriteVecMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; }
280 def : WriteRes<WriteVecStore, [SLM_MEC_RSV]>;
281 def : WriteRes<WriteVecStoreX, [SLM_MEC_RSV]>;
282 def : WriteRes<WriteVecStoreY, [SLM_MEC_RSV]>;
283 def : WriteRes<WriteVecStoreNT, [SLM_MEC_RSV]>;
284 def : WriteRes<WriteVecStoreNTY, [SLM_MEC_RSV]>;
285 def : WriteRes<WriteVecMaskedStore, [SLM_MEC_RSV]>;
286 def : WriteRes<WriteVecMaskedStoreY, [SLM_MEC_RSV]>;
287 def : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>;
288 def : WriteRes<WriteVecMoveX, [SLM_FPC_RSV01]>;
289 def : WriteRes<WriteVecMoveY, [SLM_FPC_RSV01]>;
290 def : WriteRes<WriteVecMoveToGpr, [SLM_IEC_RSV01]>;
291 def : WriteRes<WriteVecMoveFromGpr, [SLM_IEC_RSV01]>;
293 defm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 1>;
294 defm : SLMWriteResPair<WriteVecShiftX, [SLM_FPC_RSV0], 1>;
295 defm : SLMWriteResPair<WriteVecShiftY, [SLM_FPC_RSV0], 1>;
296 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
297 defm : SLMWriteResPair<WriteVecShiftImm, [SLM_FPC_RSV0], 1>;
298 defm : SLMWriteResPair<WriteVecShiftImmX,[SLM_FPC_RSV0], 1>;
299 defm : SLMWriteResPair<WriteVecShiftImmY,[SLM_FPC_RSV0], 1>;
300 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
301 defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>;
302 defm : SLMWriteResPair<WriteVecLogicX,[SLM_FPC_RSV01], 1>;
303 defm : SLMWriteResPair<WriteVecLogicY,[SLM_FPC_RSV01], 1>;
304 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
305 defm : SLMWriteResPair<WriteVecTest, [SLM_FPC_RSV01], 1>;
306 defm : SLMWriteResPair<WriteVecTestY, [SLM_FPC_RSV01], 1>;
307 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
308 defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>;
309 defm : SLMWriteResPair<WriteVecALUX, [SLM_FPC_RSV01], 1>;
310 defm : SLMWriteResPair<WriteVecALUY, [SLM_FPC_RSV01], 1>;
311 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
312 defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>;
313 defm : SLMWriteResPair<WriteVecIMulX, [SLM_FPC_RSV0], 4>;
314 defm : SLMWriteResPair<WriteVecIMulY, [SLM_FPC_RSV0], 4>;
315 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
316 // FIXME: The below is closer to correct, but caused some perf regressions.
317 //defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>;
318 defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 4>;
319 defm : SLMWriteResPair<WritePMULLDY, [SLM_FPC_RSV0], 4>;
320 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
321 defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>;
322 defm : SLMWriteResPair<WriteShuffleY, [SLM_FPC_RSV0], 1>;
323 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
324 defm : SLMWriteResPair<WriteShuffleX, [SLM_FPC_RSV0], 1>;
325 defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>;
326 defm : SLMWriteResPair<WriteVarShuffleX, [SLM_FPC_RSV0], 1>;
327 defm : SLMWriteResPair<WriteVarShuffleY, [SLM_FPC_RSV0], 1>;
328 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
329 defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>;
330 defm : SLMWriteResPair<WriteBlendY, [SLM_FPC_RSV0], 1>;
331 defm : X86WriteResPairUnsupported<WriteBlendZ>;
332 defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>;
333 defm : SLMWriteResPair<WriteMPSADY, [SLM_FPC_RSV0], 7>;
334 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
335 defm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>;
336 defm : SLMWriteResPair<WritePSADBWX, [SLM_FPC_RSV0], 4>;
337 defm : SLMWriteResPair<WritePSADBWY, [SLM_FPC_RSV0], 4>;
338 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
339 defm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>;
341 // Vector insert/extract operations.
342 defm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0], 1>;
344 def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]>;
345 def : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
348 let ResourceCycles = [1, 2];
351 ////////////////////////////////////////////////////////////////////////////////
352 // Horizontal add/sub instructions.
353 ////////////////////////////////////////////////////////////////////////////////
355 defm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV01], 3, [2]>;
356 defm : SLMWriteResPair<WriteFHAddY, [SLM_FPC_RSV01], 3, [2]>;
357 defm : X86WriteResPairUnsupported<WriteFHAddZ>;
358 defm : SLMWriteResPair<WritePHAdd, [SLM_FPC_RSV01], 1>;
359 defm : SLMWriteResPair<WritePHAddX, [SLM_FPC_RSV01], 1>;
360 defm : SLMWriteResPair<WritePHAddY, [SLM_FPC_RSV01], 1>;
361 defm : X86WriteResPairUnsupported<WritePHAddZ>;
363 // String instructions.
364 // Packed Compare Implicit Length Strings, Return Mask
365 def : WriteRes<WritePCmpIStrM, [SLM_FPC_RSV0]> {
367 let ResourceCycles = [13];
369 def : WriteRes<WritePCmpIStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
371 let ResourceCycles = [13, 1];
374 // Packed Compare Explicit Length Strings, Return Mask
375 def : WriteRes<WritePCmpEStrM, [SLM_FPC_RSV0]> {
377 let ResourceCycles = [17];
379 def : WriteRes<WritePCmpEStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
381 let ResourceCycles = [17, 1];
384 // Packed Compare Implicit Length Strings, Return Index
385 def : WriteRes<WritePCmpIStrI, [SLM_FPC_RSV0]> {
387 let ResourceCycles = [17];
389 def : WriteRes<WritePCmpIStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
391 let ResourceCycles = [17, 1];
394 // Packed Compare Explicit Length Strings, Return Index
395 def : WriteRes<WritePCmpEStrI, [SLM_FPC_RSV0]> {
397 let ResourceCycles = [21];
399 def : WriteRes<WritePCmpEStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
401 let ResourceCycles = [21, 1];
404 // MOVMSK Instructions.
405 def : WriteRes<WriteFMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
406 def : WriteRes<WriteVecMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
407 def : WriteRes<WriteVecMOVMSKY, [SLM_FPC_RSV1]> { let Latency = 4; }
408 def : WriteRes<WriteMMXMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
411 def : WriteRes<WriteAESDecEnc, [SLM_FPC_RSV0]> {
413 let ResourceCycles = [5];
415 def : WriteRes<WriteAESDecEncLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
417 let ResourceCycles = [5, 1];
420 def : WriteRes<WriteAESIMC, [SLM_FPC_RSV0]> {
422 let ResourceCycles = [5];
424 def : WriteRes<WriteAESIMCLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
426 let ResourceCycles = [5, 1];
429 def : WriteRes<WriteAESKeyGen, [SLM_FPC_RSV0]> {
431 let ResourceCycles = [5];
433 def : WriteRes<WriteAESKeyGenLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
435 let ResourceCycles = [5, 1];
438 // Carry-less multiplication instructions.
439 def : WriteRes<WriteCLMul, [SLM_FPC_RSV0]> {
441 let ResourceCycles = [10];
443 def : WriteRes<WriteCLMulLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
445 let ResourceCycles = [10, 1];
448 def : WriteRes<WriteSystem, [SLM_FPC_RSV0]> { let Latency = 100; }
449 def : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; }
450 def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
451 def : WriteRes<WriteNop, []>;
453 // AVX/FMA is not supported on that architecture, but we should define the basic
454 // scheduling resources anyway.
455 def : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>;
456 defm : X86WriteResPairUnsupported<WriteFBlendY>;
457 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
458 defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>;
459 defm : X86WriteResPairUnsupported<WriteVarBlendY>;
460 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
461 defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 1>;
462 defm : X86WriteResPairUnsupported<WriteFVarBlendY>;
463 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
464 defm : X86WriteResPairUnsupported<WriteFShuffle256>;
465 defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
466 defm : X86WriteResPairUnsupported<WriteShuffle256>;
467 defm : X86WriteResPairUnsupported<WriteVarShuffle256>;
468 defm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>;
469 defm : X86WriteResPairUnsupported<WriteVarVecShiftY>;
470 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
471 defm : X86WriteResPairUnsupported<WriteFMA>;
472 defm : X86WriteResPairUnsupported<WriteFMAX>;
473 defm : X86WriteResPairUnsupported<WriteFMAY>;
474 defm : X86WriteResPairUnsupported<WriteFMAZ>;
476 defm : X86WriteResPairUnsupported<WriteCvtPH2PS>;
477 defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>;
478 defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
479 defm : X86WriteResUnsupported<WriteCvtPS2PH>;
480 defm : X86WriteResUnsupported<WriteCvtPS2PHY>;
481 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
482 defm : X86WriteResUnsupported<WriteCvtPS2PHSt>;
483 defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>;
484 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;