1 //===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86SelectionDAGInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
15 #include "X86ISelLowering.h"
16 #include "X86RegisterInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86SelectionDAGInfo.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/IR/DerivedTypes.h"
21 #include "llvm/Target/TargetLowering.h"
25 #define DEBUG_TYPE "x86-selectiondag-info"
27 bool X86SelectionDAGInfo::isBaseRegConflictPossible(
28 SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const {
29 // We cannot use TRI->hasBasePointer() until *after* we select all basic
30 // blocks. Legalization may introduce new stack temporaries with large
31 // alignment requirements. Fall back to generic code if there are any
32 // dynamic stack adjustments (hopefully rare) and the base pointer would
33 // conflict if we had to use it.
34 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
35 if (!MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
38 const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>(
39 DAG.getSubtarget().getRegisterInfo());
40 unsigned BaseReg = TRI->getBaseRegister();
41 for (unsigned R : ClobberSet)
47 SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset(
48 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
49 SDValue Size, unsigned Align, bool isVolatile,
50 MachinePointerInfo DstPtrInfo) const {
51 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
52 const X86Subtarget &Subtarget =
53 DAG.getMachineFunction().getSubtarget<X86Subtarget>();
56 // If the base register might conflict with our physical registers, bail out.
57 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
58 X86::ECX, X86::EAX, X86::EDI};
59 assert(!isBaseRegConflictPossible(DAG, ClobberSet));
62 // If to a segment-relative address space, use the default lowering.
63 if (DstPtrInfo.getAddrSpace() >= 256)
66 // If not DWORD aligned or size is more than the threshold, call the library.
67 // The libc version is likely to be faster for these cases. It can use the
68 // address value and run time information about the CPU.
69 if ((Align & 3) != 0 || !ConstantSize ||
70 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) {
71 // Check to see if there is a specialized entry-point for memory zeroing.
72 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
74 if (const char *bzeroEntry = V &&
75 V->isNullValue() ? Subtarget.getBZeroEntry() : nullptr) {
76 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
77 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
78 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
79 TargetLowering::ArgListTy Args;
80 TargetLowering::ArgListEntry Entry;
83 Args.push_back(Entry);
85 Args.push_back(Entry);
87 TargetLowering::CallLoweringInfo CLI(DAG);
90 .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
91 DAG.getExternalSymbol(bzeroEntry, IntPtr),
95 std::pair<SDValue,SDValue> CallResult = TLI.LowerCallTo(CLI);
96 return CallResult.second;
99 // Otherwise have the target-independent code call memset.
103 uint64_t SizeVal = ConstantSize->getZExtValue();
107 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
108 unsigned BytesLeft = 0;
111 uint64_t Val = ValC->getZExtValue() & 255;
113 // If the value is a constant, then we can potentially use larger sets.
115 case 2: // WORD aligned
118 Val = (Val << 8) | Val;
120 case 0: // DWORD aligned
123 Val = (Val << 8) | Val;
124 Val = (Val << 16) | Val;
125 if (Subtarget.is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
128 Val = (Val << 32) | Val;
131 default: // Byte aligned
134 Count = DAG.getIntPtrConstant(SizeVal, dl);
138 if (AVT.bitsGT(MVT::i8)) {
139 unsigned UBytes = AVT.getSizeInBits() / 8;
140 Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl);
141 BytesLeft = SizeVal % UBytes;
144 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT),
146 InFlag = Chain.getValue(1);
149 Count = DAG.getIntPtrConstant(SizeVal, dl);
150 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
151 InFlag = Chain.getValue(1);
154 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX,
156 InFlag = Chain.getValue(1);
157 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI,
159 InFlag = Chain.getValue(1);
161 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
162 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
163 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
166 // Handle the last 1 - 7 bytes.
167 unsigned Offset = SizeVal - BytesLeft;
168 EVT AddrVT = Dst.getValueType();
169 EVT SizeVT = Size.getValueType();
171 Chain = DAG.getMemset(Chain, dl,
172 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
173 DAG.getConstant(Offset, dl, AddrVT)),
175 DAG.getConstant(BytesLeft, dl, SizeVT),
176 Align, isVolatile, false,
177 DstPtrInfo.getWithOffset(Offset));
180 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
186 // Represents a cover of a buffer of SizeVal bytes with blocks of size
187 // AVT, as well as how many bytes remain (BytesLeft is always smaller than
189 struct RepMovsRepeats {
190 RepMovsRepeats(const uint64_t SizeVal, const MVT& AVT) {
191 const unsigned UBytes = AVT.getSizeInBits() / 8;
192 Count = SizeVal / UBytes;
193 BytesLeft = SizeVal % UBytes;
202 SDValue X86SelectionDAGInfo::EmitTargetCodeForMemcpy(
203 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
204 SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline,
205 MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
206 // This requires the copy size to be a constant, preferably
207 // within a subtarget-specific limit.
208 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
209 const X86Subtarget &Subtarget =
210 DAG.getMachineFunction().getSubtarget<X86Subtarget>();
213 uint64_t SizeVal = ConstantSize->getZExtValue();
214 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold())
217 /// If not DWORD aligned, it is more efficient to call the library. However
218 /// if calling the library is not allowed (AlwaysInline), then soldier on as
219 /// the code generated here is better than the long load-store sequence we
220 /// would otherwise get.
221 if (!AlwaysInline && (Align & 3) != 0)
224 // If to a segment-relative address space, use the default lowering.
225 if (DstPtrInfo.getAddrSpace() >= 256 ||
226 SrcPtrInfo.getAddrSpace() >= 256)
229 // If the base register might conflict with our physical registers, bail out.
230 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI,
231 X86::ECX, X86::ESI, X86::EDI};
232 if (isBaseRegConflictPossible(DAG, ClobberSet))
236 if (Subtarget.hasERMSB())
237 // If the target has enhanced REPMOVSB, then it's at least as fast to use
238 // REP MOVSB instead of REP MOVS{W,D,Q}, and it avoids having to handle
250 AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32;
252 RepMovsRepeats Repeats(SizeVal, AVT);
253 if (Repeats.BytesLeft > 0 &&
254 DAG.getMachineFunction().getFunction()->optForMinSize()) {
255 // When agressively optimizing for size, avoid generating the code to handle
258 Repeats = RepMovsRepeats(SizeVal, AVT);
262 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX,
263 DAG.getIntPtrConstant(Repeats.Count, dl), InFlag);
264 InFlag = Chain.getValue(1);
265 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI,
267 InFlag = Chain.getValue(1);
268 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RSI : X86::ESI,
270 InFlag = Chain.getValue(1);
272 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
273 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
274 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops);
276 SmallVector<SDValue, 4> Results;
277 Results.push_back(RepMovs);
278 if (Repeats.BytesLeft) {
279 // Handle the last 1 - 7 bytes.
280 unsigned Offset = SizeVal - Repeats.BytesLeft;
281 EVT DstVT = Dst.getValueType();
282 EVT SrcVT = Src.getValueType();
283 EVT SizeVT = Size.getValueType();
284 Results.push_back(DAG.getMemcpy(Chain, dl,
285 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
286 DAG.getConstant(Offset, dl,
288 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
289 DAG.getConstant(Offset, dl,
291 DAG.getConstant(Repeats.BytesLeft, dl,
293 Align, isVolatile, AlwaysInline, false,
294 DstPtrInfo.getWithOffset(Offset),
295 SrcPtrInfo.getWithOffset(Offset)));
298 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);