1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #include "X86RegisterBankInfo.h"
19 #include "X86Subtarget.h"
20 #include "MCTargetDesc/X86BaseInfo.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/ConstantRange.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/CodeGen.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
43 #define DEBUG_TYPE "subtarget"
45 #define GET_SUBTARGETINFO_TARGET_DESC
46 #define GET_SUBTARGETINFO_CTOR
47 #include "X86GenSubtargetInfo.inc"
49 // Temporary option to control early if-conversion for x86 while adding machine
52 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
53 cl::desc("Enable early if-conversion on X86"));
56 /// Classify a blockaddress reference for the current subtarget according to how
57 /// we should reference it in a non-pcrel context.
58 unsigned char X86Subtarget::classifyBlockAddressReference() const {
59 return classifyLocalReference(nullptr);
62 /// Classify a global variable reference for the current subtarget according to
63 /// how we should reference it in a non-pcrel context.
65 X86Subtarget::classifyGlobalReference(const GlobalValue *GV) const {
66 return classifyGlobalReference(GV, *GV->getParent());
70 X86Subtarget::classifyLocalReference(const GlobalValue *GV) const {
71 // If we're not PIC, it's not very interesting.
72 if (!isPositionIndependent())
73 return X86II::MO_NO_FLAG;
76 // 64-bit ELF PIC local references may use GOTOFF relocations.
78 switch (TM.getCodeModel()) {
79 // 64-bit small code model is simple: All rip-relative.
80 case CodeModel::Small:
81 case CodeModel::Kernel:
82 return X86II::MO_NO_FLAG;
84 // The large PIC code model uses GOTOFF.
85 case CodeModel::Large:
86 return X86II::MO_GOTOFF;
88 // Medium is a hybrid: RIP-rel for code, GOTOFF for DSO local data.
89 case CodeModel::Medium:
90 if (isa<Function>(GV))
91 return X86II::MO_NO_FLAG; // All code is RIP-relative
92 return X86II::MO_GOTOFF; // Local symbols use GOTOFF.
94 llvm_unreachable("invalid code model");
97 // Otherwise, this is either a RIP-relative reference or a 64-bit movabsq,
98 // both of which use MO_NO_FLAG.
99 return X86II::MO_NO_FLAG;
102 // The COFF dynamic linker just patches the executable sections.
104 return X86II::MO_NO_FLAG;
106 if (isTargetDarwin()) {
107 // 32 bit macho has no relocation for a-b if a is undefined, even if
108 // b is in the section that is being relocated.
109 // This means we have to use o load even for GVs that are known to be
111 if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
112 return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
114 return X86II::MO_PIC_BASE_OFFSET;
117 return X86II::MO_GOTOFF;
120 unsigned char X86Subtarget::classifyGlobalReference(const GlobalValue *GV,
121 const Module &M) const {
122 // The static large model never uses stubs.
123 if (TM.getCodeModel() == CodeModel::Large && !isPositionIndependent())
124 return X86II::MO_NO_FLAG;
126 // Absolute symbols can be referenced directly.
128 if (Optional<ConstantRange> CR = GV->getAbsoluteSymbolRange()) {
129 // See if we can use the 8-bit immediate form. Note that some instructions
130 // will sign extend the immediate operand, so to be conservative we only
131 // accept the range [0,128).
132 if (CR->getUnsignedMax().ult(128))
133 return X86II::MO_ABS8;
135 return X86II::MO_NO_FLAG;
139 if (TM.shouldAssumeDSOLocal(M, GV))
140 return classifyLocalReference(GV);
143 return X86II::MO_DLLIMPORT;
146 // ELF supports a large, truly PIC code model with non-PC relative GOT
147 // references. Other object file formats do not. Use the no-flag, 64-bit
148 // reference for them.
149 if (TM.getCodeModel() == CodeModel::Large)
150 return isTargetELF() ? X86II::MO_GOT : X86II::MO_NO_FLAG;
151 return X86II::MO_GOTPCREL;
154 if (isTargetDarwin()) {
155 if (!isPositionIndependent())
156 return X86II::MO_DARWIN_NONLAZY;
157 return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
160 return X86II::MO_GOT;
164 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV) const {
165 return classifyGlobalFunctionReference(GV, *GV->getParent());
169 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
170 const Module &M) const {
171 if (TM.shouldAssumeDSOLocal(M, GV))
172 return X86II::MO_NO_FLAG;
174 if (isTargetCOFF()) {
175 assert(GV->hasDLLImportStorageClass() &&
176 "shouldAssumeDSOLocal gave inconsistent answer");
177 return X86II::MO_DLLIMPORT;
180 const Function *F = dyn_cast_or_null<Function>(GV);
183 if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv()))
184 // According to psABI, PLT stub clobbers XMM8-XMM15.
185 // In Regcall calling convention those registers are used for passing
186 // parameters. Thus we need to prevent lazy binding in Regcall.
187 return X86II::MO_GOTPCREL;
188 // If PLT must be avoided then the call should be via GOTPCREL.
189 if (((F && F->hasFnAttribute(Attribute::NonLazyBind)) ||
190 (!F && M.getRtLibUseGOT())) &&
192 return X86II::MO_GOTPCREL;
193 return X86II::MO_PLT;
197 if (F && F->hasFnAttribute(Attribute::NonLazyBind))
198 // If the function is marked as non-lazy, generate an indirect call
199 // which loads from the GOT directly. This avoids runtime overhead
200 // at the cost of eager binding (and one extra byte of encoding).
201 return X86II::MO_GOTPCREL;
202 return X86II::MO_NO_FLAG;
205 return X86II::MO_NO_FLAG;
208 /// Return true if the subtarget allows calls to immediate address.
209 bool X86Subtarget::isLegalToCallImmediateAddr() const {
210 // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
211 // but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does,
212 // the following check for Win32 should be removed.
213 if (In64BitMode || isTargetWin32())
215 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
218 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
219 std::string CPUName = CPU;
223 // Make sure 64-bit features are available in 64-bit mode. (But make sure
224 // SSE2 can be turned off explicitly.)
225 std::string FullFS = FS;
228 FullFS = "+64bit,+sse2," + FullFS;
230 FullFS = "+64bit,+sse2";
233 // LAHF/SAHF are always supported in non-64-bit mode.
236 FullFS = "+sahf," + FullFS;
241 // Parse features string and set the CPU.
242 ParseSubtargetFeatures(CPUName, FullFS);
244 // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
245 // 16-bytes and under that are reasonably fast. These features were
246 // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
247 // micro-architectures respectively.
248 if (hasSSE42() || hasSSE4A())
249 IsUAMem16Slow = false;
251 // It's important to keep the MCSubtargetInfo feature bits in sync with
252 // target data structure which is shared with MC code emitter, etc.
254 ToggleFeature(X86::Mode64Bit);
255 else if (In32BitMode)
256 ToggleFeature(X86::Mode32Bit);
257 else if (In16BitMode)
258 ToggleFeature(X86::Mode16Bit);
260 llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
262 LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
263 << ", 3DNowLevel " << X863DNowLevel << ", 64bit "
264 << HasX86_64 << "\n");
265 assert((!In64BitMode || HasX86_64) &&
266 "64-bit code requested on a subtarget that doesn't support it!");
268 // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
269 // 32 and 64 bit) and for all 64-bit targets.
270 if (StackAlignOverride)
271 stackAlignment = StackAlignOverride;
272 else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
273 isTargetKFreeBSD() || In64BitMode)
276 // Some CPUs have more overhead for gather. The specified overhead is relative
277 // to the Load operation. "2" is the number provided by Intel architects. This
278 // parameter is used for cost estimation of Gather Op and comparison with
279 // other alternatives.
280 // TODO: Remove the explicit hasAVX512()?, That would mean we would only
281 // enable gather with a -march.
282 if (hasAVX512() || (hasAVX2() && hasFastGather()))
287 // Consume the vector width attribute or apply any target specific limit.
288 if (PreferVectorWidthOverride)
289 PreferVectorWidth = PreferVectorWidthOverride;
290 else if (Prefer256Bit)
291 PreferVectorWidth = 256;
294 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
296 initSubtargetFeatures(CPU, FS);
300 X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
301 const X86TargetMachine &TM,
302 unsigned StackAlignOverride,
303 unsigned PreferVectorWidthOverride,
304 unsigned RequiredVectorWidth)
305 : X86GenSubtargetInfo(TT, CPU, FS),
306 PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
307 StackAlignOverride(StackAlignOverride),
308 PreferVectorWidthOverride(PreferVectorWidthOverride),
309 RequiredVectorWidth(RequiredVectorWidth),
310 In64BitMode(TargetTriple.getArch() == Triple::x86_64),
311 In32BitMode(TargetTriple.getArch() == Triple::x86 &&
312 TargetTriple.getEnvironment() != Triple::CODE16),
313 In16BitMode(TargetTriple.getArch() == Triple::x86 &&
314 TargetTriple.getEnvironment() == Triple::CODE16),
315 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
316 FrameLowering(*this, getStackAlignment()) {
317 // Determine the PICStyle based on the target selected.
318 if (!isPositionIndependent())
319 setPICStyle(PICStyles::None);
321 setPICStyle(PICStyles::RIPRel);
322 else if (isTargetCOFF())
323 setPICStyle(PICStyles::None);
324 else if (isTargetDarwin())
325 setPICStyle(PICStyles::StubPIC);
326 else if (isTargetELF())
327 setPICStyle(PICStyles::GOT);
329 CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering()));
330 Legalizer.reset(new X86LegalizerInfo(*this, TM));
332 auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
333 RegBankInfo.reset(RBI);
334 InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
337 const CallLowering *X86Subtarget::getCallLowering() const {
338 return CallLoweringInfo.get();
341 const InstructionSelector *X86Subtarget::getInstructionSelector() const {
342 return InstSelector.get();
345 const LegalizerInfo *X86Subtarget::getLegalizerInfo() const {
346 return Legalizer.get();
349 const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
350 return RegBankInfo.get();
353 bool X86Subtarget::enableEarlyIfConversion() const {
354 return hasCMov() && X86EarlyIfConv;