1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #include "X86RegisterBankInfo.h"
19 #include "X86Subtarget.h"
20 #include "MCTargetDesc/X86BaseInfo.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/ConstantRange.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/CodeGen.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
43 #define DEBUG_TYPE "subtarget"
45 #define GET_SUBTARGETINFO_TARGET_DESC
46 #define GET_SUBTARGETINFO_CTOR
47 #include "X86GenSubtargetInfo.inc"
49 // Temporary option to control early if-conversion for x86 while adding machine
52 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
53 cl::desc("Enable early if-conversion on X86"));
56 /// Classify a blockaddress reference for the current subtarget according to how
57 /// we should reference it in a non-pcrel context.
58 unsigned char X86Subtarget::classifyBlockAddressReference() const {
59 return classifyLocalReference(nullptr);
62 /// Classify a global variable reference for the current subtarget according to
63 /// how we should reference it in a non-pcrel context.
65 X86Subtarget::classifyGlobalReference(const GlobalValue *GV) const {
66 return classifyGlobalReference(GV, *GV->getParent());
70 X86Subtarget::classifyLocalReference(const GlobalValue *GV) const {
71 // 64 bits can use %rip addressing for anything local.
73 return X86II::MO_NO_FLAG;
75 // If this is for a position dependent executable, the static linker can
77 if (!isPositionIndependent())
78 return X86II::MO_NO_FLAG;
80 // The COFF dynamic linker just patches the executable sections.
82 return X86II::MO_NO_FLAG;
84 if (isTargetDarwin()) {
85 // 32 bit macho has no relocation for a-b if a is undefined, even if
86 // b is in the section that is being relocated.
87 // This means we have to use o load even for GVs that are known to be
89 if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
90 return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
92 return X86II::MO_PIC_BASE_OFFSET;
95 return X86II::MO_GOTOFF;
98 unsigned char X86Subtarget::classifyGlobalReference(const GlobalValue *GV,
99 const Module &M) const {
100 // Large model never uses stubs.
101 if (TM.getCodeModel() == CodeModel::Large)
102 return X86II::MO_NO_FLAG;
104 // Absolute symbols can be referenced directly.
106 if (Optional<ConstantRange> CR = GV->getAbsoluteSymbolRange()) {
107 // See if we can use the 8-bit immediate form. Note that some instructions
108 // will sign extend the immediate operand, so to be conservative we only
109 // accept the range [0,128).
110 if (CR->getUnsignedMax().ult(128))
111 return X86II::MO_ABS8;
113 return X86II::MO_NO_FLAG;
117 if (TM.shouldAssumeDSOLocal(M, GV))
118 return classifyLocalReference(GV);
121 return X86II::MO_DLLIMPORT;
124 return X86II::MO_GOTPCREL;
126 if (isTargetDarwin()) {
127 if (!isPositionIndependent())
128 return X86II::MO_DARWIN_NONLAZY;
129 return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
132 return X86II::MO_GOT;
136 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV) const {
137 return classifyGlobalFunctionReference(GV, *GV->getParent());
141 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
142 const Module &M) const {
143 if (TM.shouldAssumeDSOLocal(M, GV))
144 return X86II::MO_NO_FLAG;
146 if (isTargetCOFF()) {
147 assert(GV->hasDLLImportStorageClass() &&
148 "shouldAssumeDSOLocal gave inconsistent answer");
149 return X86II::MO_DLLIMPORT;
152 const Function *F = dyn_cast_or_null<Function>(GV);
155 if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv()))
156 // According to psABI, PLT stub clobbers XMM8-XMM15.
157 // In Regcall calling convention those registers are used for passing
158 // parameters. Thus we need to prevent lazy binding in Regcall.
159 return X86II::MO_GOTPCREL;
160 if (F && F->hasFnAttribute(Attribute::NonLazyBind) && is64Bit())
161 return X86II::MO_GOTPCREL;
162 return X86II::MO_PLT;
166 if (F && F->hasFnAttribute(Attribute::NonLazyBind))
167 // If the function is marked as non-lazy, generate an indirect call
168 // which loads from the GOT directly. This avoids runtime overhead
169 // at the cost of eager binding (and one extra byte of encoding).
170 return X86II::MO_GOTPCREL;
171 return X86II::MO_NO_FLAG;
174 return X86II::MO_NO_FLAG;
177 /// Return true if the subtarget allows calls to immediate address.
178 bool X86Subtarget::isLegalToCallImmediateAddr() const {
179 // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
180 // but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does,
181 // the following check for Win32 should be removed.
182 if (In64BitMode || isTargetWin32())
184 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
187 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
188 std::string CPUName = CPU;
192 // Make sure 64-bit features are available in 64-bit mode. (But make sure
193 // SSE2 can be turned off explicitly.)
194 std::string FullFS = FS;
197 FullFS = "+64bit,+sse2," + FullFS;
199 FullFS = "+64bit,+sse2";
202 // LAHF/SAHF are always supported in non-64-bit mode.
205 FullFS = "+sahf," + FullFS;
210 // Parse features string and set the CPU.
211 ParseSubtargetFeatures(CPUName, FullFS);
213 // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
214 // 16-bytes and under that are reasonably fast. These features were
215 // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
216 // micro-architectures respectively.
217 if (hasSSE42() || hasSSE4A())
218 IsUAMem16Slow = false;
220 InstrItins = getInstrItineraryForCPU(CPUName);
222 // It's important to keep the MCSubtargetInfo feature bits in sync with
223 // target data structure which is shared with MC code emitter, etc.
225 ToggleFeature(X86::Mode64Bit);
226 else if (In32BitMode)
227 ToggleFeature(X86::Mode32Bit);
228 else if (In16BitMode)
229 ToggleFeature(X86::Mode16Bit);
231 llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
233 DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
234 << ", 3DNowLevel " << X863DNowLevel
235 << ", 64bit " << HasX86_64 << "\n");
236 assert((!In64BitMode || HasX86_64) &&
237 "64-bit code requested on a subtarget that doesn't support it!");
239 // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
240 // 32 and 64 bit) and for all 64-bit targets.
241 if (StackAlignOverride)
242 stackAlignment = StackAlignOverride;
243 else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
244 isTargetKFreeBSD() || In64BitMode)
247 // Some CPUs have more overhead for gather. The specified overhead is relative
248 // to the Load operation. "2" is the number provided by Intel architects. This
249 // parameter is used for cost estimation of Gather Op and comparison with
250 // other alternatives.
251 // TODO: Remove the explicit hasAVX512()?, That would mean we would only
252 // enable gather with a -march.
253 if (hasAVX512() || (hasAVX2() && hasFastGather()))
259 void X86Subtarget::initializeEnvironment() {
261 X863DNowLevel = NoThreeDNow;
275 HasVPCLMULQDQ = false;
297 HasVPOPCNTDQ = false;
305 HasPREFETCHWT1 = false;
315 HasCLFLUSHOPT = false;
317 UseRetpoline = false;
318 UseRetpolineExternalThunk = false;
319 IsPMULLDSlow = false;
321 IsUAMem16Slow = false;
322 IsUAMem32Slow = false;
323 HasSSEUnalignedMem = false;
324 HasCmpxchg16b = false;
326 HasFastVariableShuffle = false;
327 HasFastPartialYMMorZMMWrite = false;
328 HasFastGather = false;
329 HasFastScalarFSQRT = false;
330 HasFastVectorFSQRT = false;
331 HasFastLZCNT = false;
332 HasFastSHLDRotate = false;
333 HasMacroFusion = false;
335 HasSlowDivide32 = false;
336 HasSlowDivide64 = false;
337 PadShortFunctions = false;
338 SlowTwoMemOps = false;
344 // FIXME: this is a known good value for Yonah. How about others?
345 MaxInlineSizeThreshold = 128;
346 UseSoftFloat = false;
347 X86ProcFamily = Others;
348 GatherOverhead = 1024;
349 ScatterOverhead = 1024;
352 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
354 initializeEnvironment();
355 initSubtargetFeatures(CPU, FS);
359 X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
360 const X86TargetMachine &TM,
361 unsigned StackAlignOverride)
362 : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
363 PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
364 StackAlignOverride(StackAlignOverride),
365 In64BitMode(TargetTriple.getArch() == Triple::x86_64),
366 In32BitMode(TargetTriple.getArch() == Triple::x86 &&
367 TargetTriple.getEnvironment() != Triple::CODE16),
368 In16BitMode(TargetTriple.getArch() == Triple::x86 &&
369 TargetTriple.getEnvironment() == Triple::CODE16),
370 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
371 FrameLowering(*this, getStackAlignment()) {
372 // Determine the PICStyle based on the target selected.
373 if (!isPositionIndependent())
374 setPICStyle(PICStyles::None);
376 setPICStyle(PICStyles::RIPRel);
377 else if (isTargetCOFF())
378 setPICStyle(PICStyles::None);
379 else if (isTargetDarwin())
380 setPICStyle(PICStyles::StubPIC);
381 else if (isTargetELF())
382 setPICStyle(PICStyles::GOT);
384 CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering()));
385 Legalizer.reset(new X86LegalizerInfo(*this, TM));
387 auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
388 RegBankInfo.reset(RBI);
389 InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
392 const CallLowering *X86Subtarget::getCallLowering() const {
393 return CallLoweringInfo.get();
396 const InstructionSelector *X86Subtarget::getInstructionSelector() const {
397 return InstSelector.get();
400 const LegalizerInfo *X86Subtarget::getLegalizerInfo() const {
401 return Legalizer.get();
404 const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
405 return RegBankInfo.get();
408 bool X86Subtarget::enableEarlyIfConversion() const {
409 return hasCMov() && X86EarlyIfConv;