1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
24 #include "llvm/IR/CallingConv.h"
25 #include "llvm/MC/MCInstrItineraries.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetSubtargetInfo.h"
30 #define GET_SUBTARGETINFO_HEADER
31 #include "X86GenSubtargetInfo.inc"
37 /// The X86 backend supports a number of different styles of PIC.
42 StubPIC, // Used on i386-darwin in pic mode.
43 GOT, // Used on 32 bit elf on when in pic mode.
44 RIPRel, // Used on X86-64 when in pic mode.
45 None // Set when not in pic mode.
48 } // end namespace PICStyles
50 class X86Subtarget final : public X86GenSubtargetInfo {
53 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
57 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
60 enum X86ProcFamilyEnum {
61 Others, IntelAtom, IntelSLM
64 /// X86 processor family: Intel Atom, and others
65 X86ProcFamilyEnum X86ProcFamily;
67 /// Which PIC style to use
68 PICStyles::Style PICStyle;
70 const TargetMachine &TM;
72 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
73 X86SSEEnum X86SSELevel;
75 /// MMX, 3DNow, 3DNow Athlon, or none supported.
76 X863DNowEnum X863DNowLevel;
78 /// True if the processor supports X87 instructions.
81 /// True if this processor has conditional move instructions
82 /// (generally pentium pro+).
85 /// True if the processor supports X86-64 instructions.
88 /// True if the processor supports POPCNT.
91 /// True if the processor supports SSE4A instructions.
94 /// Target has AES instructions
97 /// Target has FXSAVE/FXRESTOR instructions
100 /// Target has XSAVE instructions
103 /// Target has XSAVEOPT instructions
106 /// Target has XSAVEC instructions
109 /// Target has XSAVES instructions
112 /// Target has carry-less multiplication
115 /// Target has 3-operand fused multiply-add
118 /// Target has 4-operand fused multiply-add
121 /// Target has XOP instructions
124 /// Target has TBM instructions.
127 /// Target has LWP instructions
130 /// True if the processor has the MOVBE instruction.
133 /// True if the processor has the RDRAND instruction.
136 /// Processor has 16-bit floating point conversion instructions.
139 /// Processor has FS/GS base insturctions.
142 /// Processor has LZCNT instruction.
145 /// Processor has BMI1 instructions.
148 /// Processor has BMI2 instructions.
151 /// Processor has VBMI instructions.
154 /// Processor has Integer Fused Multiply Add
157 /// Processor has RTM instructions.
160 /// Processor has ADX instructions.
163 /// Processor has SHA instructions.
166 /// Processor has PRFCHW instructions.
169 /// Processor has RDSEED instructions.
172 /// Processor has LAHF/SAHF instructions.
175 /// Processor has MONITORX/MWAITX instructions.
178 /// Processor has Cache Line Zero instruction
181 /// Processor has Prefetch with intent to Write instruction
182 bool HasPFPREFETCHWT1;
184 /// True if BT (bit test) of memory instructions are slow.
187 /// True if SHLD instructions are slow.
190 /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
194 /// True if unaligned memory accesses of 16-bytes are slow.
197 /// True if unaligned memory accesses of 32-bytes are slow.
200 /// True if SSE operations can have unaligned memory operands.
201 /// This may require setting a configuration bit in the processor.
202 bool HasSSEUnalignedMem;
204 /// True if this processor has the CMPXCHG16B instruction;
205 /// this is true for most x86-64 chips, but not the first AMD chips.
208 /// True if the LEA instruction should be used for adjusting
209 /// the stack pointer. This is an optimization for Intel Atom processors.
212 /// True if there is no performance penalty to writing only the lower parts
213 /// of a YMM or ZMM register without clearing the upper part.
214 bool HasFastPartialYMMorZMMWrite;
216 /// True if hardware SQRTSS instruction is at least as fast (latency) as
217 /// RSQRTSS followed by a Newton-Raphson iteration.
218 bool HasFastScalarFSQRT;
220 /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
221 /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
222 bool HasFastVectorFSQRT;
224 /// True if 8-bit divisions are significantly faster than
225 /// 32-bit divisions and should be used when possible.
226 bool HasSlowDivide32;
228 /// True if 32-bit divides are significantly faster than
229 /// 64-bit divisions and should be used when possible.
230 bool HasSlowDivide64;
232 /// True if LZCNT instruction is fast.
235 /// True if SHLD based rotate is fast.
236 bool HasFastSHLDRotate;
238 /// True if the processor has enhanced REP MOVSB/STOSB.
241 /// True if the short functions should be padded to prevent
242 /// a stall when returning too early.
243 bool PadShortFunctions;
245 /// True if the Calls with memory reference should be converted
246 /// to a register-based indirect call.
247 bool CallRegIndirect;
249 /// True if the LEA instruction inputs have to be ready at address generation
253 /// True if the LEA instruction with certain arguments is slow
256 /// True if INC and DEC instructions are slow when writing to flags
259 /// Processor has AVX-512 PreFetch Instructions
262 /// Processor has AVX-512 Exponential and Reciprocal Instructions
265 /// Processor has AVX-512 Conflict Detection Instructions
268 /// Processor has AVX-512 Doubleword and Quadword instructions
271 /// Processor has AVX-512 Byte and Word instructions
274 /// Processor has AVX-512 Vector Length eXtenstions
277 /// Processor has PKU extenstions
280 /// Processor supports MPX - Memory Protection Extensions
283 /// Processor has Software Guard Extensions
286 /// Processor supports Flush Cache Line instruction
289 /// Processor supports Cache Line Write Back instruction
292 /// Use software floating point for code generation.
295 /// The minimum alignment known to hold of the stack frame on
296 /// entry to the function and which must be maintained by every function.
297 unsigned stackAlignment;
299 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
301 unsigned MaxInlineSizeThreshold;
303 /// What processor and OS we're targeting.
306 /// Instruction itineraries for scheduling
307 InstrItineraryData InstrItins;
309 /// Gather the accessor points to GlobalISel-related APIs.
310 /// This is used to avoid ifndefs spreading around while GISel is
311 /// an optional library.
312 std::unique_ptr<GISelAccessor> GISel;
315 /// Override the stack alignment.
316 unsigned StackAlignOverride;
318 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
321 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
324 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
327 X86SelectionDAGInfo TSInfo;
328 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
329 // X86TargetLowering needs.
330 X86InstrInfo InstrInfo;
331 X86TargetLowering TLInfo;
332 X86FrameLowering FrameLowering;
338 /// This constructor initializes the data members to match that
339 /// of the specified triple.
341 X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
342 const X86TargetMachine &TM, unsigned StackAlignOverride,
343 bool OptForSize, bool OptForMinSize);
345 /// This object will take onwership of \p GISelAccessor.
346 void setGISelAccessor(GISelAccessor &GISel) { this->GISel.reset(&GISel); }
348 const X86TargetLowering *getTargetLowering() const override {
352 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
354 const X86FrameLowering *getFrameLowering() const override {
355 return &FrameLowering;
358 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
362 const X86RegisterInfo *getRegisterInfo() const override {
363 return &getInstrInfo()->getRegisterInfo();
366 /// Returns the minimum alignment known to hold of the
367 /// stack frame on entry to the function and which must be maintained by every
368 /// function for this subtarget.
369 unsigned getStackAlignment() const { return stackAlignment; }
371 /// Returns the maximum memset / memcpy size
372 /// that still makes it profitable to inline the call.
373 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
375 /// ParseSubtargetFeatures - Parses features string setting specified
376 /// subtarget options. Definition of function is auto generated by tblgen.
377 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
379 /// Methods used by Global ISel
380 const CallLowering *getCallLowering() const override;
381 const InstructionSelector *getInstructionSelector() const override;
382 const LegalizerInfo *getLegalizerInfo() const override;
383 const RegisterBankInfo *getRegBankInfo() const override;
386 /// Initialize the full set of dependencies so we can use an initializer
387 /// list for X86Subtarget.
388 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
389 void initializeEnvironment();
390 void initSubtargetFeatures(StringRef CPU, StringRef FS);
393 /// Is this x86_64? (disregarding specific ABI / programming model)
394 bool is64Bit() const {
398 bool is32Bit() const {
402 bool is16Bit() const {
406 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
407 bool isTarget64BitILP32() const {
408 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
409 TargetTriple.isOSNaCl());
412 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
413 bool isTarget64BitLP64() const {
414 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
415 !TargetTriple.isOSNaCl());
418 PICStyles::Style getPICStyle() const { return PICStyle; }
419 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
421 bool hasX87() const { return HasX87; }
422 bool hasCMov() const { return HasCMov; }
423 bool hasSSE1() const { return X86SSELevel >= SSE1; }
424 bool hasSSE2() const { return X86SSELevel >= SSE2; }
425 bool hasSSE3() const { return X86SSELevel >= SSE3; }
426 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
427 bool hasSSE41() const { return X86SSELevel >= SSE41; }
428 bool hasSSE42() const { return X86SSELevel >= SSE42; }
429 bool hasAVX() const { return X86SSELevel >= AVX; }
430 bool hasAVX2() const { return X86SSELevel >= AVX2; }
431 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
432 bool hasFp256() const { return hasAVX(); }
433 bool hasInt256() const { return hasAVX2(); }
434 bool hasSSE4A() const { return HasSSE4A; }
435 bool hasMMX() const { return X863DNowLevel >= MMX; }
436 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
437 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
438 bool hasPOPCNT() const { return HasPOPCNT; }
439 bool hasAES() const { return HasAES; }
440 bool hasFXSR() const { return HasFXSR; }
441 bool hasXSAVE() const { return HasXSAVE; }
442 bool hasXSAVEOPT() const { return HasXSAVEOPT; }
443 bool hasXSAVEC() const { return HasXSAVEC; }
444 bool hasXSAVES() const { return HasXSAVES; }
445 bool hasPCLMUL() const { return HasPCLMUL; }
446 // Prefer FMA4 to FMA - its better for commutation/memory folding and
447 // has equal or better performance on all supported targets.
448 bool hasFMA() const { return (HasFMA || hasAVX512()) && !HasFMA4; }
449 bool hasFMA4() const { return HasFMA4; }
450 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
451 bool hasXOP() const { return HasXOP; }
452 bool hasTBM() const { return HasTBM; }
453 bool hasLWP() const { return HasLWP; }
454 bool hasMOVBE() const { return HasMOVBE; }
455 bool hasRDRAND() const { return HasRDRAND; }
456 bool hasF16C() const { return HasF16C; }
457 bool hasFSGSBase() const { return HasFSGSBase; }
458 bool hasLZCNT() const { return HasLZCNT; }
459 bool hasBMI() const { return HasBMI; }
460 bool hasBMI2() const { return HasBMI2; }
461 bool hasVBMI() const { return HasVBMI; }
462 bool hasIFMA() const { return HasIFMA; }
463 bool hasRTM() const { return HasRTM; }
464 bool hasADX() const { return HasADX; }
465 bool hasSHA() const { return HasSHA; }
466 bool hasPRFCHW() const { return HasPRFCHW; }
467 bool hasRDSEED() const { return HasRDSEED; }
468 bool hasLAHFSAHF() const { return HasLAHFSAHF; }
469 bool hasMWAITX() const { return HasMWAITX; }
470 bool hasCLZERO() const { return HasCLZERO; }
471 bool isBTMemSlow() const { return IsBTMemSlow; }
472 bool isSHLDSlow() const { return IsSHLDSlow; }
473 bool isPMULLDSlow() const { return IsPMULLDSlow; }
474 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
475 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
476 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
477 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
478 bool useLeaForSP() const { return UseLeaForSP; }
479 bool hasFastPartialYMMorZMMWrite() const {
480 return HasFastPartialYMMorZMMWrite;
482 bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
483 bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
484 bool hasFastLZCNT() const { return HasFastLZCNT; }
485 bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
486 bool hasERMSB() const { return HasERMSB; }
487 bool hasSlowDivide32() const { return HasSlowDivide32; }
488 bool hasSlowDivide64() const { return HasSlowDivide64; }
489 bool padShortFunctions() const { return PadShortFunctions; }
490 bool callRegIndirect() const { return CallRegIndirect; }
491 bool LEAusesAG() const { return LEAUsesAG; }
492 bool slowLEA() const { return SlowLEA; }
493 bool slowIncDec() const { return SlowIncDec; }
494 bool hasCDI() const { return HasCDI; }
495 bool hasPFI() const { return HasPFI; }
496 bool hasERI() const { return HasERI; }
497 bool hasDQI() const { return HasDQI; }
498 bool hasBWI() const { return HasBWI; }
499 bool hasVLX() const { return HasVLX; }
500 bool hasPKU() const { return HasPKU; }
501 bool hasMPX() const { return HasMPX; }
502 bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
504 bool isXRaySupported() const override { return is64Bit(); }
506 bool isAtom() const { return X86ProcFamily == IntelAtom; }
507 bool isSLM() const { return X86ProcFamily == IntelSLM; }
508 bool useSoftFloat() const { return UseSoftFloat; }
510 bool getOptForSize() const { return OptForSize; }
511 bool getOptForMinSize() const { return OptForMinSize; }
513 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
514 /// no-sse2). There isn't any reason to disable it if the target processor
516 bool hasMFence() const { return hasSSE2() || is64Bit(); }
518 const Triple &getTargetTriple() const { return TargetTriple; }
520 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
521 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
522 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
523 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
524 bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
526 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
527 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
528 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
530 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
531 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
532 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
533 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
534 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
535 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
536 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
537 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
538 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
540 bool isTargetWindowsMSVC() const {
541 return TargetTriple.isWindowsMSVCEnvironment();
544 bool isTargetKnownWindowsMSVC() const {
545 return TargetTriple.isKnownWindowsMSVCEnvironment();
548 bool isTargetWindowsCoreCLR() const {
549 return TargetTriple.isWindowsCoreCLREnvironment();
552 bool isTargetWindowsCygwin() const {
553 return TargetTriple.isWindowsCygwinEnvironment();
556 bool isTargetWindowsGNU() const {
557 return TargetTriple.isWindowsGNUEnvironment();
560 bool isTargetWindowsItanium() const {
561 return TargetTriple.isWindowsItaniumEnvironment();
564 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
566 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
568 bool isTargetWin64() const {
569 return In64BitMode && TargetTriple.isOSWindows();
572 bool isTargetWin32() const {
573 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
576 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
577 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
579 bool isPICStyleStubPIC() const {
580 return PICStyle == PICStyles::StubPIC;
583 bool isPositionIndependent() const { return TM.isPositionIndependent(); }
585 bool isCallingConvWin64(CallingConv::ID CC) const {
587 // On Win64, all these conventions just use the default convention.
589 case CallingConv::Fast:
590 case CallingConv::X86_FastCall:
591 case CallingConv::X86_StdCall:
592 case CallingConv::X86_ThisCall:
593 case CallingConv::X86_VectorCall:
594 case CallingConv::Intel_OCL_BI:
595 return isTargetWin64();
596 // This convention allows using the Win64 convention on other targets.
597 case CallingConv::X86_64_Win64:
599 // This convention allows using the SysV convention on Windows targets.
600 case CallingConv::X86_64_SysV:
602 // Otherwise, who knows what this is.
608 /// Classify a global variable reference for the current subtarget according
609 /// to how we should reference it in a non-pcrel context.
610 unsigned char classifyLocalReference(const GlobalValue *GV) const;
612 unsigned char classifyGlobalReference(const GlobalValue *GV,
613 const Module &M) const;
614 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
616 /// Classify a global function reference for the current subtarget.
617 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
618 const Module &M) const;
619 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
621 /// Classify a blockaddress reference for the current subtarget according to
622 /// how we should reference it in a non-pcrel context.
623 unsigned char classifyBlockAddressReference() const;
625 /// Return true if the subtarget allows calls to immediate address.
626 bool isLegalToCallImmediateAddr() const;
628 /// This function returns the name of a function which has an interface
629 /// like the non-standard bzero function, if such a function exists on
630 /// the current subtarget and it is considered prefereable over
631 /// memset with zero passed as the second argument. Otherwise it
633 const char *getBZeroEntry() const;
635 /// This function returns true if the target has sincos() routine in its
636 /// compiler runtime or math libraries.
637 bool hasSinCos() const;
639 /// Enable the MachineScheduler pass for all X86 subtargets.
640 bool enableMachineScheduler() const override { return true; }
642 // TODO: Update the regression tests and return true.
643 bool supportPrintSchedInfo() const override { return false; }
645 bool enableEarlyIfConversion() const override;
647 /// Return the instruction itineraries based on the subtarget selection.
648 const InstrItineraryData *getInstrItineraryData() const override {
652 AntiDepBreakMode getAntiDepBreakMode() const override {
653 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
657 } // end namespace llvm
659 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H