1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "X86GenSubtargetInfo.inc"
35 /// The X86 backend supports a number of different styles of PIC.
39 StubPIC, // Used on i386-darwin in pic mode.
40 GOT, // Used on 32 bit elf on when in pic mode.
41 RIPRel, // Used on X86-64 when in pic mode.
42 None // Set when not in pic mode.
46 class X86Subtarget final : public X86GenSubtargetInfo {
50 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
54 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
57 enum X86ProcFamilyEnum {
58 Others, IntelAtom, IntelSLM
61 /// X86 processor family: Intel Atom, and others
62 X86ProcFamilyEnum X86ProcFamily;
64 /// Which PIC style to use
65 PICStyles::Style PICStyle;
67 const TargetMachine &TM;
69 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
70 X86SSEEnum X86SSELevel;
72 /// MMX, 3DNow, 3DNow Athlon, or none supported.
73 X863DNowEnum X863DNowLevel;
75 /// True if the processor supports X87 instructions.
78 /// True if this processor has conditional move instructions
79 /// (generally pentium pro+).
82 /// True if the processor supports X86-64 instructions.
85 /// True if the processor supports POPCNT.
88 /// True if the processor supports SSE4A instructions.
91 /// Target has AES instructions
94 /// Target has FXSAVE/FXRESTOR instructions
97 /// Target has XSAVE instructions
99 /// Target has XSAVEOPT instructions
101 /// Target has XSAVEC instructions
103 /// Target has XSAVES instructions
106 /// Target has carry-less multiplication
109 /// Target has 3-operand fused multiply-add
112 /// Target has 4-operand fused multiply-add
115 /// Target has XOP instructions
118 /// Target has TBM instructions.
121 /// True if the processor has the MOVBE instruction.
124 /// True if the processor has the RDRAND instruction.
127 /// Processor has 16-bit floating point conversion instructions.
130 /// Processor has FS/GS base insturctions.
133 /// Processor has LZCNT instruction.
136 /// Processor has BMI1 instructions.
139 /// Processor has BMI2 instructions.
142 /// Processor has VBMI instructions.
145 /// Processor has Integer Fused Multiply Add
148 /// Processor has RTM instructions.
151 /// Processor has HLE.
154 /// Processor has ADX instructions.
157 /// Processor has SHA instructions.
160 /// Processor has PRFCHW instructions.
163 /// Processor has RDSEED instructions.
166 /// Processor has LAHF/SAHF instructions.
169 /// Processor has MONITORX/MWAITX instructions.
172 /// Processor has Prefetch with intent to Write instruction
173 bool HasPFPREFETCHWT1;
175 /// True if BT (bit test) of memory instructions are slow.
178 /// True if SHLD instructions are slow.
181 /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
185 /// True if unaligned memory accesses of 16-bytes are slow.
188 /// True if unaligned memory accesses of 32-bytes are slow.
191 /// True if SSE operations can have unaligned memory operands.
192 /// This may require setting a configuration bit in the processor.
193 bool HasSSEUnalignedMem;
195 /// True if this processor has the CMPXCHG16B instruction;
196 /// this is true for most x86-64 chips, but not the first AMD chips.
199 /// True if the LEA instruction should be used for adjusting
200 /// the stack pointer. This is an optimization for Intel Atom processors.
203 /// True if there is no performance penalty to writing only the lower parts
204 /// of a YMM register without clearing the upper part.
205 bool HasFastPartialYMMWrite;
207 /// True if hardware SQRTSS instruction is at least as fast (latency) as
208 /// RSQRTSS followed by a Newton-Raphson iteration.
209 bool HasFastScalarFSQRT;
211 /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
212 /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
213 bool HasFastVectorFSQRT;
215 /// True if 8-bit divisions are significantly faster than
216 /// 32-bit divisions and should be used when possible.
217 bool HasSlowDivide32;
219 /// True if 32-bit divides are significantly faster than
220 /// 64-bit divisions and should be used when possible.
221 bool HasSlowDivide64;
223 /// True if LZCNT instruction is fast.
226 /// True if the short functions should be padded to prevent
227 /// a stall when returning too early.
228 bool PadShortFunctions;
230 /// True if the Calls with memory reference should be converted
231 /// to a register-based indirect call.
232 bool CallRegIndirect;
234 /// True if the LEA instruction inputs have to be ready at address generation
238 /// True if the LEA instruction with certain arguments is slow
241 /// True if INC and DEC instructions are slow when writing to flags
244 /// Processor has AVX-512 PreFetch Instructions
247 /// Processor has AVX-512 Exponential and Reciprocal Instructions
250 /// Processor has AVX-512 Conflict Detection Instructions
253 /// Processor has AVX-512 Doubleword and Quadword instructions
256 /// Processor has AVX-512 Byte and Word instructions
259 /// Processor has AVX-512 Vector Length eXtenstions
262 /// Processor has PKU extenstions
265 /// Processor supports MPX - Memory Protection Extensions
268 /// Processor supports Invalidate Process-Context Identifier
271 /// Processor has VM Functions
274 /// Processor has Supervisor Mode Access Protection
277 /// Processor has Software Guard Extensions
280 /// Processor supports Flush Cache Line instruction
283 /// Processor has Persistent Commit feature
286 /// Processor supports Cache Line Write Back instruction
289 /// Use software floating point for code generation.
292 /// The minimum alignment known to hold of the stack frame on
293 /// entry to the function and which must be maintained by every function.
294 unsigned stackAlignment;
296 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
298 unsigned MaxInlineSizeThreshold;
300 /// What processor and OS we're targeting.
303 /// Instruction itineraries for scheduling
304 InstrItineraryData InstrItins;
306 /// Gather the accessor points to GlobalISel-related APIs.
307 /// This is used to avoid ifndefs spreading around while GISel is
308 /// an optional library.
309 std::unique_ptr<GISelAccessor> GISel;
312 /// Override the stack alignment.
313 unsigned StackAlignOverride;
315 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
318 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
321 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
324 X86SelectionDAGInfo TSInfo;
325 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
326 // X86TargetLowering needs.
327 X86InstrInfo InstrInfo;
328 X86TargetLowering TLInfo;
329 X86FrameLowering FrameLowering;
332 /// This constructor initializes the data members to match that
333 /// of the specified triple.
335 X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
336 const X86TargetMachine &TM, unsigned StackAlignOverride);
338 /// This object will take onwership of \p GISelAccessor.
339 void setGISelAccessor(GISelAccessor &GISel) { this->GISel.reset(&GISel); }
341 const X86TargetLowering *getTargetLowering() const override {
344 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
345 const X86FrameLowering *getFrameLowering() const override {
346 return &FrameLowering;
348 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
351 const X86RegisterInfo *getRegisterInfo() const override {
352 return &getInstrInfo()->getRegisterInfo();
355 /// Returns the minimum alignment known to hold of the
356 /// stack frame on entry to the function and which must be maintained by every
357 /// function for this subtarget.
358 unsigned getStackAlignment() const { return stackAlignment; }
360 /// Returns the maximum memset / memcpy size
361 /// that still makes it profitable to inline the call.
362 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
364 /// ParseSubtargetFeatures - Parses features string setting specified
365 /// subtarget options. Definition of function is auto generated by tblgen.
366 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
368 /// Methods used by Global ISel
369 const CallLowering *getCallLowering() const override;
370 const InstructionSelector *getInstructionSelector() const override;
371 const LegalizerInfo *getLegalizerInfo() const override;
372 const RegisterBankInfo *getRegBankInfo() const override;
374 /// Initialize the full set of dependencies so we can use an initializer
375 /// list for X86Subtarget.
376 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
377 void initializeEnvironment();
378 void initSubtargetFeatures(StringRef CPU, StringRef FS);
380 /// Is this x86_64? (disregarding specific ABI / programming model)
381 bool is64Bit() const {
385 bool is32Bit() const {
389 bool is16Bit() const {
393 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
394 bool isTarget64BitILP32() const {
395 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
396 TargetTriple.isOSNaCl());
399 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
400 bool isTarget64BitLP64() const {
401 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
402 !TargetTriple.isOSNaCl());
405 PICStyles::Style getPICStyle() const { return PICStyle; }
406 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
408 bool hasX87() const { return HasX87; }
409 bool hasCMov() const { return HasCMov; }
410 bool hasSSE1() const { return X86SSELevel >= SSE1; }
411 bool hasSSE2() const { return X86SSELevel >= SSE2; }
412 bool hasSSE3() const { return X86SSELevel >= SSE3; }
413 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
414 bool hasSSE41() const { return X86SSELevel >= SSE41; }
415 bool hasSSE42() const { return X86SSELevel >= SSE42; }
416 bool hasAVX() const { return X86SSELevel >= AVX; }
417 bool hasAVX2() const { return X86SSELevel >= AVX2; }
418 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
419 bool hasFp256() const { return hasAVX(); }
420 bool hasInt256() const { return hasAVX2(); }
421 bool hasSSE4A() const { return HasSSE4A; }
422 bool hasMMX() const { return X863DNowLevel >= MMX; }
423 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
424 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
425 bool hasPOPCNT() const { return HasPOPCNT; }
426 bool hasAES() const { return HasAES; }
427 bool hasFXSR() const { return HasFXSR; }
428 bool hasXSAVE() const { return HasXSAVE; }
429 bool hasXSAVEOPT() const { return HasXSAVEOPT; }
430 bool hasXSAVEC() const { return HasXSAVEC; }
431 bool hasXSAVES() const { return HasXSAVES; }
432 bool hasPCLMUL() const { return HasPCLMUL; }
433 // Prefer FMA4 to FMA - its better for commutation/memory folding and
434 // has equal or better performance on all supported targets.
435 bool hasFMA() const { return HasFMA && !HasFMA4; }
436 bool hasFMA4() const { return HasFMA4; }
437 bool hasAnyFMA() const { return hasFMA() || hasFMA4() || hasAVX512(); }
438 bool hasXOP() const { return HasXOP; }
439 bool hasTBM() const { return HasTBM; }
440 bool hasMOVBE() const { return HasMOVBE; }
441 bool hasRDRAND() const { return HasRDRAND; }
442 bool hasF16C() const { return HasF16C; }
443 bool hasFSGSBase() const { return HasFSGSBase; }
444 bool hasLZCNT() const { return HasLZCNT; }
445 bool hasBMI() const { return HasBMI; }
446 bool hasBMI2() const { return HasBMI2; }
447 bool hasVBMI() const { return HasVBMI; }
448 bool hasIFMA() const { return HasIFMA; }
449 bool hasRTM() const { return HasRTM; }
450 bool hasHLE() const { return HasHLE; }
451 bool hasADX() const { return HasADX; }
452 bool hasSHA() const { return HasSHA; }
453 bool hasPRFCHW() const { return HasPRFCHW; }
454 bool hasRDSEED() const { return HasRDSEED; }
455 bool hasLAHFSAHF() const { return HasLAHFSAHF; }
456 bool hasMWAITX() const { return HasMWAITX; }
457 bool isBTMemSlow() const { return IsBTMemSlow; }
458 bool isSHLDSlow() const { return IsSHLDSlow; }
459 bool isPMULLDSlow() const { return IsPMULLDSlow; }
460 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
461 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
462 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
463 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
464 bool useLeaForSP() const { return UseLeaForSP; }
465 bool hasFastPartialYMMWrite() const { return HasFastPartialYMMWrite; }
466 bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
467 bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
468 bool hasFastLZCNT() const { return HasFastLZCNT; }
469 bool hasSlowDivide32() const { return HasSlowDivide32; }
470 bool hasSlowDivide64() const { return HasSlowDivide64; }
471 bool padShortFunctions() const { return PadShortFunctions; }
472 bool callRegIndirect() const { return CallRegIndirect; }
473 bool LEAusesAG() const { return LEAUsesAG; }
474 bool slowLEA() const { return SlowLEA; }
475 bool slowIncDec() const { return SlowIncDec; }
476 bool hasCDI() const { return HasCDI; }
477 bool hasPFI() const { return HasPFI; }
478 bool hasERI() const { return HasERI; }
479 bool hasDQI() const { return HasDQI; }
480 bool hasBWI() const { return HasBWI; }
481 bool hasVLX() const { return HasVLX; }
482 bool hasPKU() const { return HasPKU; }
483 bool hasMPX() const { return HasMPX; }
485 virtual bool isXRaySupported() const override { return is64Bit(); }
487 bool isAtom() const { return X86ProcFamily == IntelAtom; }
488 bool isSLM() const { return X86ProcFamily == IntelSLM; }
489 bool useSoftFloat() const { return UseSoftFloat; }
491 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
492 /// no-sse2). There isn't any reason to disable it if the target processor
494 bool hasMFence() const { return hasSSE2() || is64Bit(); }
496 const Triple &getTargetTriple() const { return TargetTriple; }
498 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
499 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
500 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
501 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
502 bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
504 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
505 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
506 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
508 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
509 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
510 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
511 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
512 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
513 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
514 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
515 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
517 bool isTargetWindowsMSVC() const {
518 return TargetTriple.isWindowsMSVCEnvironment();
521 bool isTargetKnownWindowsMSVC() const {
522 return TargetTriple.isKnownWindowsMSVCEnvironment();
525 bool isTargetWindowsCoreCLR() const {
526 return TargetTriple.isWindowsCoreCLREnvironment();
529 bool isTargetWindowsCygwin() const {
530 return TargetTriple.isWindowsCygwinEnvironment();
533 bool isTargetWindowsGNU() const {
534 return TargetTriple.isWindowsGNUEnvironment();
537 bool isTargetWindowsItanium() const {
538 return TargetTriple.isWindowsItaniumEnvironment();
541 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
543 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
545 bool isTargetWin64() const {
546 return In64BitMode && TargetTriple.isOSWindows();
549 bool isTargetWin32() const {
550 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
553 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
554 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
556 bool isPICStyleStubPIC() const {
557 return PICStyle == PICStyles::StubPIC;
560 bool isPositionIndependent() const { return TM.isPositionIndependent(); }
562 bool isCallingConvWin64(CallingConv::ID CC) const {
564 // On Win64, all these conventions just use the default convention.
566 case CallingConv::Fast:
567 case CallingConv::X86_FastCall:
568 case CallingConv::X86_StdCall:
569 case CallingConv::X86_ThisCall:
570 case CallingConv::X86_VectorCall:
571 case CallingConv::Intel_OCL_BI:
572 return isTargetWin64();
573 // This convention allows using the Win64 convention on other targets.
574 case CallingConv::X86_64_Win64:
576 // This convention allows using the SysV convention on Windows targets.
577 case CallingConv::X86_64_SysV:
579 // Otherwise, who knows what this is.
585 /// Classify a global variable reference for the current subtarget according
586 /// to how we should reference it in a non-pcrel context.
587 unsigned char classifyLocalReference(const GlobalValue *GV) const;
589 unsigned char classifyGlobalReference(const GlobalValue *GV,
590 const Module &M) const;
591 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
593 /// Classify a global function reference for the current subtarget.
594 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
595 const Module &M) const;
596 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
598 /// Classify a blockaddress reference for the current subtarget according to
599 /// how we should reference it in a non-pcrel context.
600 unsigned char classifyBlockAddressReference() const;
602 /// Return true if the subtarget allows calls to immediate address.
603 bool isLegalToCallImmediateAddr() const;
605 /// This function returns the name of a function which has an interface
606 /// like the non-standard bzero function, if such a function exists on
607 /// the current subtarget and it is considered prefereable over
608 /// memset with zero passed as the second argument. Otherwise it
610 const char *getBZeroEntry() const;
612 /// This function returns true if the target has sincos() routine in its
613 /// compiler runtime or math libraries.
614 bool hasSinCos() const;
616 /// Enable the MachineScheduler pass for all X86 subtargets.
617 bool enableMachineScheduler() const override { return true; }
619 bool enableEarlyIfConversion() const override;
621 /// Return the instruction itineraries based on the subtarget selection.
622 const InstrItineraryData *getInstrItineraryData() const override {
626 AntiDepBreakMode getAntiDepBreakMode() const override {
627 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
631 } // End llvm namespace