1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDepsFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetLoweringObjectFile.h"
38 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetOptions.h"
53 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
54 cl::desc("Enable the machine combiner pass"),
55 cl::init(true), cl::Hidden);
59 void initializeWinEHStatePassPass(PassRegistry &);
60 void initializeFixupLEAPassPass(PassRegistry &);
61 void initializeX86CallFrameOptimizationPass(PassRegistry &);
62 void initializeX86CmovConverterPassPass(PassRegistry &);
63 void initializeX86ExecutionDepsFixPass(PassRegistry &);
64 void initializeX86DomainReassignmentPass(PassRegistry &);
66 } // end namespace llvm
68 extern "C" void LLVMInitializeX86Target() {
69 // Register the target.
70 RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
71 RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
73 PassRegistry &PR = *PassRegistry::getPassRegistry();
74 initializeGlobalISel(PR);
75 initializeWinEHStatePassPass(PR);
76 initializeFixupBWInstPassPass(PR);
77 initializeEvexToVexInstPassPass(PR);
78 initializeFixupLEAPassPass(PR);
79 initializeX86CallFrameOptimizationPass(PR);
80 initializeX86CmovConverterPassPass(PR);
81 initializeX86ExecutionDepsFixPass(PR);
82 initializeX86DomainReassignmentPass(PR);
85 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
86 if (TT.isOSBinFormatMachO()) {
87 if (TT.getArch() == Triple::x86_64)
88 return llvm::make_unique<X86_64MachoTargetObjectFile>();
89 return llvm::make_unique<TargetLoweringObjectFileMachO>();
93 return llvm::make_unique<X86FreeBSDTargetObjectFile>();
94 if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
95 return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
97 return llvm::make_unique<X86SolarisTargetObjectFile>();
99 return llvm::make_unique<X86FuchsiaTargetObjectFile>();
100 if (TT.isOSBinFormatELF())
101 return llvm::make_unique<X86ELFTargetObjectFile>();
102 if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
103 return llvm::make_unique<X86WindowsTargetObjectFile>();
104 if (TT.isOSBinFormatCOFF())
105 return llvm::make_unique<TargetLoweringObjectFileCOFF>();
106 llvm_unreachable("unknown subtarget type");
109 static std::string computeDataLayout(const Triple &TT) {
110 // X86 is little endian
111 std::string Ret = "e";
113 Ret += DataLayout::getManglingComponent(TT);
114 // X86 and x32 have 32 bit pointers.
115 if ((TT.isArch64Bit() &&
116 (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
120 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
121 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
123 else if (TT.isOSIAMCU())
124 Ret += "-i64:32-f64:32";
128 // Some ABIs align long double to 128 bits, others to 32.
129 if (TT.isOSNaCl() || TT.isOSIAMCU())
131 else if (TT.isArch64Bit() || TT.isOSDarwin())
139 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
140 if (TT.isArch64Bit())
141 Ret += "-n8:16:32:64";
145 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
146 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
147 Ret += "-a:0:32-S32";
154 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
155 Optional<Reloc::Model> RM) {
156 bool is64Bit = TT.getArch() == Triple::x86_64;
157 if (!RM.hasValue()) {
158 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
159 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
160 // use static relocation model by default.
161 if (TT.isOSDarwin()) {
164 return Reloc::DynamicNoPIC;
166 if (TT.isOSWindows() && is64Bit)
168 return Reloc::Static;
171 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
172 // is defined as a model for code which may be used in static or dynamic
173 // executables but not necessarily a shared library. On X86-32 we just
174 // compile in -static mode, in x86-64 we use PIC.
175 if (*RM == Reloc::DynamicNoPIC) {
178 if (!TT.isOSDarwin())
179 return Reloc::Static;
182 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
183 // the Mach-O file format doesn't support it.
184 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
190 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
191 bool JIT, bool Is64Bit) {
195 return Is64Bit ? CodeModel::Large : CodeModel::Small;
196 return CodeModel::Small;
199 /// Create an X86 target.
201 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
202 StringRef CPU, StringRef FS,
203 const TargetOptions &Options,
204 Optional<Reloc::Model> RM,
205 Optional<CodeModel::Model> CM,
206 CodeGenOpt::Level OL, bool JIT)
208 T, computeDataLayout(TT), TT, CPU, FS, Options,
209 getEffectiveRelocModel(TT, RM),
210 getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL),
211 TLOF(createTLOF(getTargetTriple())) {
212 // Windows stack unwinder gets confused when execution flow "falls through"
213 // after a call to 'noreturn' function.
214 // To prevent that, we emit a trap for 'unreachable' IR instructions.
215 // (which on X86, happens to be the 'ud2' instruction)
216 // On PS4, the "return address" of a 'noreturn' call must still be within
217 // the calling function, and TrapUnreachable is an easy way to get that.
218 // The check here for 64-bit windows is a bit icky, but as we're unlikely
219 // to ever want to mix 32 and 64-bit windows code in a single module
220 // this should be fine.
221 if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4())
222 this->Options.TrapUnreachable = true;
227 X86TargetMachine::~X86TargetMachine() = default;
230 X86TargetMachine::getSubtargetImpl(const Function &F) const {
231 Attribute CPUAttr = F.getFnAttribute("target-cpu");
232 Attribute FSAttr = F.getFnAttribute("target-features");
234 StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
235 ? CPUAttr.getValueAsString()
236 : (StringRef)TargetCPU;
237 StringRef FS = !FSAttr.hasAttribute(Attribute::None)
238 ? FSAttr.getValueAsString()
239 : (StringRef)TargetFS;
241 SmallString<512> Key;
242 Key.reserve(CPU.size() + FS.size());
246 // FIXME: This is related to the code below to reset the target options,
247 // we need to know whether or not the soft float flag is set on the
248 // function before we can generate a subtarget. We also need to use
249 // it as a key for the subtarget since that can be the only difference
250 // between two functions.
252 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
253 // If the soft float attribute is set on the function turn on the soft float
254 // subtarget feature.
256 Key += FS.empty() ? "+soft-float" : ",+soft-float";
258 FS = Key.substr(CPU.size());
260 auto &I = SubtargetMap[Key];
262 // This needs to be done before we create a new subtarget since any
263 // creation will depend on the TM and the code generation flags on the
264 // function that reside in TargetOptions.
265 resetTargetOptions(F);
266 I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
267 Options.StackAlignmentOverride);
272 //===----------------------------------------------------------------------===//
273 // Command line options for x86
274 //===----------------------------------------------------------------------===//
276 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
277 cl::desc("Minimize AVX to SSE transition penalty"),
280 //===----------------------------------------------------------------------===//
282 //===----------------------------------------------------------------------===//
285 X86TargetMachine::getTargetTransformInfo(const Function &F) {
286 return TargetTransformInfo(X86TTIImpl(this, F));
289 //===----------------------------------------------------------------------===//
290 // Pass Pipeline Configuration
291 //===----------------------------------------------------------------------===//
295 /// X86 Code Generator Pass Configuration Options.
296 class X86PassConfig : public TargetPassConfig {
298 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
299 : TargetPassConfig(TM, PM) {}
301 X86TargetMachine &getX86TargetMachine() const {
302 return getTM<X86TargetMachine>();
306 createMachineScheduler(MachineSchedContext *C) const override {
307 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
308 DAG->addMutation(createX86MacroFusionDAGMutation());
312 void addIRPasses() override;
313 bool addInstSelector() override;
314 bool addIRTranslator() override;
315 bool addLegalizeMachineIR() override;
316 bool addRegBankSelect() override;
317 bool addGlobalInstructionSelect() override;
318 bool addILPOpts() override;
319 bool addPreISel() override;
320 void addMachineSSAOptimization() override;
321 void addPreRegAlloc() override;
322 void addPostRegAlloc() override;
323 void addPreEmitPass() override;
324 void addPreEmitPass2() override;
325 void addPreSched2() override;
328 class X86ExecutionDepsFix : public ExecutionDepsFix {
331 X86ExecutionDepsFix() : ExecutionDepsFix(ID, X86::VR128XRegClass) {}
332 StringRef getPassName() const override {
333 return "X86 Execution Dependency Fix";
336 char X86ExecutionDepsFix::ID;
338 } // end anonymous namespace
340 INITIALIZE_PASS(X86ExecutionDepsFix, "x86-execution-deps-fix",
341 "X86 Execution Dependency Fix", false, false)
343 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
344 return new X86PassConfig(*this, PM);
347 void X86PassConfig::addIRPasses() {
348 addPass(createAtomicExpandPass());
350 TargetPassConfig::addIRPasses();
352 if (TM->getOptLevel() != CodeGenOpt::None)
353 addPass(createInterleavedAccessPass());
355 // Add passes that handle indirect branch removal and insertion of a retpoline
356 // thunk. These will be a no-op unless a function subtarget has the retpoline
358 addPass(createIndirectBrExpandPass());
361 bool X86PassConfig::addInstSelector() {
362 // Install an instruction selector.
363 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
365 // For ELF, cleanup any local-dynamic TLS accesses.
366 if (TM->getTargetTriple().isOSBinFormatELF() &&
367 getOptLevel() != CodeGenOpt::None)
368 addPass(createCleanupLocalDynamicTLSPass());
370 addPass(createX86GlobalBaseRegPass());
374 bool X86PassConfig::addIRTranslator() {
375 addPass(new IRTranslator());
379 bool X86PassConfig::addLegalizeMachineIR() {
380 addPass(new Legalizer());
384 bool X86PassConfig::addRegBankSelect() {
385 addPass(new RegBankSelect());
389 bool X86PassConfig::addGlobalInstructionSelect() {
390 addPass(new InstructionSelect());
394 bool X86PassConfig::addILPOpts() {
395 addPass(&EarlyIfConverterID);
396 if (EnableMachineCombinerPass)
397 addPass(&MachineCombinerID);
398 addPass(createX86CmovConverterPass());
402 bool X86PassConfig::addPreISel() {
403 // Only add this pass for 32-bit x86 Windows.
404 const Triple &TT = TM->getTargetTriple();
405 if (TT.isOSWindows() && TT.getArch() == Triple::x86)
406 addPass(createX86WinEHStatePass());
410 void X86PassConfig::addPreRegAlloc() {
411 if (getOptLevel() != CodeGenOpt::None) {
412 addPass(&LiveRangeShrinkID);
413 addPass(createX86FixupSetCC());
414 addPass(createX86OptimizeLEAs());
415 addPass(createX86CallFrameOptimization());
418 addPass(createX86WinAllocaExpander());
420 void X86PassConfig::addMachineSSAOptimization() {
421 addPass(createX86DomainReassignmentPass());
422 TargetPassConfig::addMachineSSAOptimization();
425 void X86PassConfig::addPostRegAlloc() {
426 addPass(createX86FloatingPointStackifierPass());
429 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
431 void X86PassConfig::addPreEmitPass() {
432 if (getOptLevel() != CodeGenOpt::None)
433 addPass(new X86ExecutionDepsFix());
436 addPass(createX86IssueVZeroUpperPass());
438 if (getOptLevel() != CodeGenOpt::None) {
439 addPass(createX86FixupBWInsts());
440 addPass(createX86PadShortFunctions());
441 addPass(createX86FixupLEAs());
442 addPass(createX86EvexToVexInsts());
446 void X86PassConfig::addPreEmitPass2() {
447 addPass(createX86RetpolineThunksPass());