1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the XCoreTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreISelLowering.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "XCoreSubtarget.h"
18 #include "XCoreTargetMachine.h"
19 #include "XCoreTargetObjectFile.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/GlobalAlias.h"
33 #include "llvm/IR/GlobalVariable.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/KnownBits.h"
38 #include "llvm/Support/raw_ostream.h"
43 #define DEBUG_TYPE "xcore-lower"
45 const char *XCoreTargetLowering::
46 getTargetNodeName(unsigned Opcode) const
48 switch ((XCoreISD::NodeType)Opcode)
50 case XCoreISD::FIRST_NUMBER : break;
51 case XCoreISD::BL : return "XCoreISD::BL";
52 case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
53 case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
54 case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
55 case XCoreISD::LDWSP : return "XCoreISD::LDWSP";
56 case XCoreISD::STWSP : return "XCoreISD::STWSP";
57 case XCoreISD::RETSP : return "XCoreISD::RETSP";
58 case XCoreISD::LADD : return "XCoreISD::LADD";
59 case XCoreISD::LSUB : return "XCoreISD::LSUB";
60 case XCoreISD::LMUL : return "XCoreISD::LMUL";
61 case XCoreISD::MACCU : return "XCoreISD::MACCU";
62 case XCoreISD::MACCS : return "XCoreISD::MACCS";
63 case XCoreISD::CRC8 : return "XCoreISD::CRC8";
64 case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
65 case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32";
66 case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET";
67 case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN";
68 case XCoreISD::MEMBARRIER : return "XCoreISD::MEMBARRIER";
73 XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
74 const XCoreSubtarget &Subtarget)
75 : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
80 // Compute derived properties from the register classes
81 computeRegisterProperties(Subtarget.getRegisterInfo());
83 setStackPointerRegisterToSaveRestore(XCore::SP);
85 setSchedulingPreference(Sched::Source);
87 // Use i32 for setcc operations results (slt, sgt, ...).
88 setBooleanContents(ZeroOrOneBooleanContent);
89 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
91 // XCore does not have the NodeTypes below.
92 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
93 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
94 setOperationAction(ISD::ADDC, MVT::i32, Expand);
95 setOperationAction(ISD::ADDE, MVT::i32, Expand);
96 setOperationAction(ISD::SUBC, MVT::i32, Expand);
97 setOperationAction(ISD::SUBE, MVT::i32, Expand);
100 setOperationAction(ISD::ADD, MVT::i64, Custom);
101 setOperationAction(ISD::SUB, MVT::i64, Custom);
102 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
103 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
104 setOperationAction(ISD::MULHS, MVT::i32, Expand);
105 setOperationAction(ISD::MULHU, MVT::i32, Expand);
106 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
107 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
108 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
111 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
112 setOperationAction(ISD::ROTL , MVT::i32, Expand);
113 setOperationAction(ISD::ROTR , MVT::i32, Expand);
115 setOperationAction(ISD::TRAP, MVT::Other, Legal);
118 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
120 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
121 setOperationAction(ISD::BlockAddress, MVT::i32 , Custom);
123 // Conversion of i64 -> double produces constantpool nodes
124 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
127 for (MVT VT : MVT::integer_valuetypes()) {
128 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
129 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
130 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
132 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
133 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand);
136 // Custom expand misaligned loads / stores.
137 setOperationAction(ISD::LOAD, MVT::i32, Custom);
138 setOperationAction(ISD::STORE, MVT::i32, Custom);
141 setOperationAction(ISD::VAEND, MVT::Other, Expand);
142 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
143 setOperationAction(ISD::VAARG, MVT::Other, Custom);
144 setOperationAction(ISD::VASTART, MVT::Other, Custom);
147 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
148 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
149 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
151 // Exception handling
152 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
153 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
156 // We request a fence for ATOMIC_* instructions, to reduce them to Monotonic.
157 // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP.
158 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
159 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
160 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
162 // TRAMPOLINE is custom lowered.
163 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
164 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
166 // We want to custom lower some of our intrinsics.
167 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
169 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4;
170 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize
171 = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2;
173 // We have target-specific dag combine patterns for the following nodes:
174 setTargetDAGCombine(ISD::STORE);
175 setTargetDAGCombine(ISD::ADD);
176 setTargetDAGCombine(ISD::INTRINSIC_VOID);
177 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
179 setMinFunctionAlignment(1);
180 setPrefFunctionAlignment(2);
183 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
184 if (Val.getOpcode() != ISD::LOAD)
187 EVT VT1 = Val.getValueType();
188 if (!VT1.isSimple() || !VT1.isInteger() ||
189 !VT2.isSimple() || !VT2.isInteger())
192 switch (VT1.getSimpleVT().SimpleTy) {
201 SDValue XCoreTargetLowering::
202 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
203 switch (Op.getOpcode())
205 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
206 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
207 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
208 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
209 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
210 case ISD::LOAD: return LowerLOAD(Op, DAG);
211 case ISD::STORE: return LowerSTORE(Op, DAG);
212 case ISD::VAARG: return LowerVAARG(Op, DAG);
213 case ISD::VASTART: return LowerVASTART(Op, DAG);
214 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
215 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
216 // FIXME: Remove these when LegalizeDAGTypes lands.
218 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
219 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
220 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
221 case ISD::FRAME_TO_ARGS_OFFSET: return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
222 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
223 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
224 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
225 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
226 case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG);
227 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op, DAG);
229 llvm_unreachable("unimplemented operand");
233 /// ReplaceNodeResults - Replace the results of node with an illegal result
234 /// type with new values built out of custom code.
235 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
236 SmallVectorImpl<SDValue>&Results,
237 SelectionDAG &DAG) const {
238 switch (N->getOpcode()) {
240 llvm_unreachable("Don't know how to custom expand this!");
243 Results.push_back(ExpandADDSUB(N, DAG));
248 //===----------------------------------------------------------------------===//
249 // Misc Lower Operation implementation
250 //===----------------------------------------------------------------------===//
252 SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA,
253 const GlobalValue *GV,
254 SelectionDAG &DAG) const {
255 // FIXME there is no actual debug info here
258 if (GV->getValueType()->isFunctionTy())
259 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
261 const auto *GVar = dyn_cast<GlobalVariable>(GV);
262 if ((GV->hasSection() && GV->getSection().startswith(".cp.")) ||
263 (GVar && GVar->isConstant() && GV->hasLocalLinkage()))
264 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
266 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
269 static bool IsSmallObject(const GlobalValue *GV, const XCoreTargetLowering &XTL) {
270 if (XTL.getTargetMachine().getCodeModel() == CodeModel::Small)
273 Type *ObjType = GV->getValueType();
274 if (!ObjType->isSized())
277 auto &DL = GV->getParent()->getDataLayout();
278 unsigned ObjSize = DL.getTypeAllocSize(ObjType);
279 return ObjSize < CodeModelLargeSize && ObjSize != 0;
282 SDValue XCoreTargetLowering::
283 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
285 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
286 const GlobalValue *GV = GN->getGlobal();
288 int64_t Offset = GN->getOffset();
289 if (IsSmallObject(GV, *this)) {
290 // We can only fold positive offsets that are a multiple of the word size.
291 int64_t FoldedOffset = std::max(Offset & ~3, (int64_t)0);
292 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset);
293 GA = getGlobalAddressWrapper(GA, GV, DAG);
294 // Handle the rest of the offset.
295 if (Offset != FoldedOffset) {
296 SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, DL, MVT::i32);
297 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
301 // Ideally we would not fold in offset with an index <= 11.
302 Type *Ty = Type::getInt8PtrTy(*DAG.getContext());
303 Constant *GA = ConstantExpr::getBitCast(const_cast<GlobalValue*>(GV), Ty);
304 Ty = Type::getInt32Ty(*DAG.getContext());
305 Constant *Idx = ConstantInt::get(Ty, Offset);
306 Constant *GAI = ConstantExpr::getGetElementPtr(
307 Type::getInt8Ty(*DAG.getContext()), GA, Idx);
308 SDValue CP = DAG.getConstantPool(GAI, MVT::i32);
309 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL,
310 DAG.getEntryNode(), CP, MachinePointerInfo());
314 SDValue XCoreTargetLowering::
315 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
318 auto PtrVT = getPointerTy(DAG.getDataLayout());
319 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
320 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
322 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, PtrVT, Result);
325 SDValue XCoreTargetLowering::
326 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
328 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
329 // FIXME there isn't really debug info here
331 EVT PtrVT = Op.getValueType();
333 if (CP->isMachineConstantPoolEntry()) {
334 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
335 CP->getAlignment(), CP->getOffset());
337 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
338 CP->getAlignment(), CP->getOffset());
340 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
343 unsigned XCoreTargetLowering::getJumpTableEncoding() const {
344 return MachineJumpTableInfo::EK_Inline;
347 SDValue XCoreTargetLowering::
348 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
350 SDValue Chain = Op.getOperand(0);
351 SDValue Table = Op.getOperand(1);
352 SDValue Index = Op.getOperand(2);
354 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
355 unsigned JTI = JT->getIndex();
356 MachineFunction &MF = DAG.getMachineFunction();
357 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
358 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
360 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();
361 if (NumEntries <= 32) {
362 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
364 assert((NumEntries >> 31) == 0);
365 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
366 DAG.getConstant(1, dl, MVT::i32));
367 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
371 SDValue XCoreTargetLowering::lowerLoadWordFromAlignedBasePlusOffset(
372 const SDLoc &DL, SDValue Chain, SDValue Base, int64_t Offset,
373 SelectionDAG &DAG) const {
374 auto PtrVT = getPointerTy(DAG.getDataLayout());
375 if ((Offset & 0x3) == 0) {
376 return DAG.getLoad(PtrVT, DL, Chain, Base, MachinePointerInfo());
378 // Lower to pair of consecutive word aligned loads plus some bit shifting.
379 int32_t HighOffset = alignTo(Offset, 4);
380 int32_t LowOffset = HighOffset - 4;
381 SDValue LowAddr, HighAddr;
382 if (GlobalAddressSDNode *GASD =
383 dyn_cast<GlobalAddressSDNode>(Base.getNode())) {
384 LowAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(),
386 HighAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(),
389 LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
390 DAG.getConstant(LowOffset, DL, MVT::i32));
391 HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
392 DAG.getConstant(HighOffset, DL, MVT::i32));
394 SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, DL, MVT::i32);
395 SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, DL, MVT::i32);
397 SDValue Low = DAG.getLoad(PtrVT, DL, Chain, LowAddr, MachinePointerInfo());
398 SDValue High = DAG.getLoad(PtrVT, DL, Chain, HighAddr, MachinePointerInfo());
399 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
400 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
401 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
402 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
404 SDValue Ops[] = { Result, Chain };
405 return DAG.getMergeValues(Ops, DL);
408 static bool isWordAligned(SDValue Value, SelectionDAG &DAG)
411 DAG.computeKnownBits(Value, Known);
412 return Known.Zero.countTrailingOnes() >= 2;
415 SDValue XCoreTargetLowering::
416 LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
417 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
418 LoadSDNode *LD = cast<LoadSDNode>(Op);
419 assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
420 "Unexpected extension type");
421 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
422 if (allowsMisalignedMemoryAccesses(LD->getMemoryVT(),
423 LD->getAddressSpace(),
427 auto &TD = DAG.getDataLayout();
428 unsigned ABIAlignment = TD.getABITypeAlignment(
429 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
430 // Leave aligned load alone.
431 if (LD->getAlignment() >= ABIAlignment)
434 SDValue Chain = LD->getChain();
435 SDValue BasePtr = LD->getBasePtr();
438 if (!LD->isVolatile()) {
439 const GlobalValue *GV;
441 if (DAG.isBaseWithConstantOffset(BasePtr) &&
442 isWordAligned(BasePtr->getOperand(0), DAG)) {
443 SDValue NewBasePtr = BasePtr->getOperand(0);
444 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
445 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,
448 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) &&
449 MinAlign(GV->getAlignment(), 4) == 4) {
450 SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL,
451 BasePtr->getValueType(0));
452 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,
457 if (LD->getAlignment() == 2) {
459 DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr,
460 LD->getPointerInfo(), MVT::i16,
461 /* Alignment = */ 2, LD->getMemOperand()->getFlags());
462 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
463 DAG.getConstant(2, DL, MVT::i32));
465 DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr,
466 LD->getPointerInfo().getWithOffset(2), MVT::i16,
467 /* Alignment = */ 2, LD->getMemOperand()->getFlags());
468 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
469 DAG.getConstant(16, DL, MVT::i32));
470 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
471 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
473 SDValue Ops[] = { Result, Chain };
474 return DAG.getMergeValues(Ops, DL);
477 // Lower to a call to __misaligned_load(BasePtr).
478 Type *IntPtrTy = TD.getIntPtrType(*DAG.getContext());
479 TargetLowering::ArgListTy Args;
480 TargetLowering::ArgListEntry Entry;
483 Entry.Node = BasePtr;
484 Args.push_back(Entry);
486 TargetLowering::CallLoweringInfo CLI(DAG);
487 CLI.setDebugLoc(DL).setChain(Chain).setLibCallee(
488 CallingConv::C, IntPtrTy,
489 DAG.getExternalSymbol("__misaligned_load",
490 getPointerTy(DAG.getDataLayout())),
493 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
494 SDValue Ops[] = { CallResult.first, CallResult.second };
495 return DAG.getMergeValues(Ops, DL);
498 SDValue XCoreTargetLowering::
499 LowerSTORE(SDValue Op, SelectionDAG &DAG) const
501 StoreSDNode *ST = cast<StoreSDNode>(Op);
502 assert(!ST->isTruncatingStore() && "Unexpected store type");
503 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
504 if (allowsMisalignedMemoryAccesses(ST->getMemoryVT(),
505 ST->getAddressSpace(),
506 ST->getAlignment())) {
509 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(
510 ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
511 // Leave aligned store alone.
512 if (ST->getAlignment() >= ABIAlignment) {
515 SDValue Chain = ST->getChain();
516 SDValue BasePtr = ST->getBasePtr();
517 SDValue Value = ST->getValue();
520 if (ST->getAlignment() == 2) {
522 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
523 DAG.getConstant(16, dl, MVT::i32));
524 SDValue StoreLow = DAG.getTruncStore(
525 Chain, dl, Low, BasePtr, ST->getPointerInfo(), MVT::i16,
526 /* Alignment = */ 2, ST->getMemOperand()->getFlags());
527 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
528 DAG.getConstant(2, dl, MVT::i32));
529 SDValue StoreHigh = DAG.getTruncStore(
530 Chain, dl, High, HighAddr, ST->getPointerInfo().getWithOffset(2),
531 MVT::i16, /* Alignment = */ 2, ST->getMemOperand()->getFlags());
532 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
535 // Lower to a call to __misaligned_store(BasePtr, Value).
536 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
537 TargetLowering::ArgListTy Args;
538 TargetLowering::ArgListEntry Entry;
541 Entry.Node = BasePtr;
542 Args.push_back(Entry);
545 Args.push_back(Entry);
547 TargetLowering::CallLoweringInfo CLI(DAG);
548 CLI.setDebugLoc(dl).setChain(Chain).setCallee(
549 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
550 DAG.getExternalSymbol("__misaligned_store",
551 getPointerTy(DAG.getDataLayout())),
554 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
555 return CallResult.second;
558 SDValue XCoreTargetLowering::
559 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
561 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
562 "Unexpected operand to lower!");
564 SDValue LHS = Op.getOperand(0);
565 SDValue RHS = Op.getOperand(1);
566 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
567 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
568 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
570 SDValue Lo(Hi.getNode(), 1);
571 SDValue Ops[] = { Lo, Hi };
572 return DAG.getMergeValues(Ops, dl);
575 SDValue XCoreTargetLowering::
576 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
578 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
579 "Unexpected operand to lower!");
581 SDValue LHS = Op.getOperand(0);
582 SDValue RHS = Op.getOperand(1);
583 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
584 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
585 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
587 SDValue Lo(Hi.getNode(), 1);
588 SDValue Ops[] = { Lo, Hi };
589 return DAG.getMergeValues(Ops, dl);
592 /// isADDADDMUL - Return whether Op is in a form that is equivalent to
593 /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then
594 /// each intermediate result in the calculation must also have a single use.
595 /// If the Op is in the correct form the constituent parts are written to Mul0,
596 /// Mul1, Addend0 and Addend1.
598 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
599 SDValue &Addend1, bool requireIntermediatesHaveOneUse)
601 if (Op.getOpcode() != ISD::ADD)
603 SDValue N0 = Op.getOperand(0);
604 SDValue N1 = Op.getOperand(1);
607 if (N0.getOpcode() == ISD::ADD) {
610 } else if (N1.getOpcode() == ISD::ADD) {
616 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
618 if (OtherOp.getOpcode() == ISD::MUL) {
619 // add(add(a,b),mul(x,y))
620 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())
622 Mul0 = OtherOp.getOperand(0);
623 Mul1 = OtherOp.getOperand(1);
624 Addend0 = AddOp.getOperand(0);
625 Addend1 = AddOp.getOperand(1);
628 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
629 // add(add(mul(x,y),a),b)
630 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse())
632 Mul0 = AddOp.getOperand(0).getOperand(0);
633 Mul1 = AddOp.getOperand(0).getOperand(1);
634 Addend0 = AddOp.getOperand(1);
638 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
639 // add(add(a,mul(x,y)),b)
640 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse())
642 Mul0 = AddOp.getOperand(1).getOperand(0);
643 Mul1 = AddOp.getOperand(1).getOperand(1);
644 Addend0 = AddOp.getOperand(0);
651 SDValue XCoreTargetLowering::
652 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
656 if (N->getOperand(0).getOpcode() == ISD::MUL) {
657 Mul = N->getOperand(0);
658 Other = N->getOperand(1);
659 } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
660 Mul = N->getOperand(1);
661 Other = N->getOperand(0);
666 SDValue LL, RL, AddendL, AddendH;
667 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
668 Mul.getOperand(0), DAG.getConstant(0, dl, MVT::i32));
669 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
670 Mul.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
671 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
672 Other, DAG.getConstant(0, dl, MVT::i32));
673 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
674 Other, DAG.getConstant(1, dl, MVT::i32));
675 APInt HighMask = APInt::getHighBitsSet(64, 32);
676 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
677 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
678 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
679 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
680 // The inputs are both zero-extended.
681 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
682 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
684 SDValue Lo(Hi.getNode(), 1);
685 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
687 if (LHSSB > 32 && RHSSB > 32) {
688 // The inputs are both sign-extended.
689 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
690 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
692 SDValue Lo(Hi.getNode(), 1);
693 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
696 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
697 Mul.getOperand(0), DAG.getConstant(1, dl, MVT::i32));
698 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
699 Mul.getOperand(1), DAG.getConstant(1, dl, MVT::i32));
700 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
701 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
703 SDValue Lo(Hi.getNode(), 1);
704 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
705 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
706 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
707 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
708 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
711 SDValue XCoreTargetLowering::
712 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
714 assert(N->getValueType(0) == MVT::i64 &&
715 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
716 "Unknown operand to lower!");
718 if (N->getOpcode() == ISD::ADD)
719 if (SDValue Result = TryExpandADDWithMul(N, DAG))
724 // Extract components
725 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
727 DAG.getConstant(0, dl, MVT::i32));
728 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
730 DAG.getConstant(1, dl, MVT::i32));
731 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
733 DAG.getConstant(0, dl, MVT::i32));
734 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
736 DAG.getConstant(1, dl, MVT::i32));
739 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
741 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
742 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
744 SDValue Carry(Lo.getNode(), 1);
746 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
748 SDValue Ignored(Hi.getNode(), 1);
750 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
753 SDValue XCoreTargetLowering::
754 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
756 // Whist llvm does not support aggregate varargs we can ignore
757 // the possibility of the ValueType being an implicit byVal vararg.
758 SDNode *Node = Op.getNode();
759 EVT VT = Node->getValueType(0); // not an aggregate
760 SDValue InChain = Node->getOperand(0);
761 SDValue VAListPtr = Node->getOperand(1);
762 EVT PtrVT = VAListPtr.getValueType();
763 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
766 DAG.getLoad(PtrVT, dl, InChain, VAListPtr, MachinePointerInfo(SV));
767 // Increment the pointer, VAList, to the next vararg
768 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,
769 DAG.getIntPtrConstant(VT.getSizeInBits() / 8,
771 // Store the incremented VAList to the legalized pointer
772 InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,
773 MachinePointerInfo(SV));
774 // Load the actual argument out of the pointer VAList
775 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo());
778 SDValue XCoreTargetLowering::
779 LowerVASTART(SDValue Op, SelectionDAG &DAG) const
782 // vastart stores the address of the VarArgsFrameIndex slot into the
783 // memory location argument
784 MachineFunction &MF = DAG.getMachineFunction();
785 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
786 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
787 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),
788 MachinePointerInfo());
791 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
792 SelectionDAG &DAG) const {
793 // This nodes represent llvm.frameaddress on the DAG.
794 // It takes one operand, the index of the frame address to return.
795 // An index of zero corresponds to the current function's frame address.
796 // An index of one to the parent's frame address, and so on.
797 // Depths > 0 not supported yet!
798 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
801 MachineFunction &MF = DAG.getMachineFunction();
802 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
803 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op),
804 RegInfo->getFrameRegister(MF), MVT::i32);
807 SDValue XCoreTargetLowering::
808 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
809 // This nodes represent llvm.returnaddress on the DAG.
810 // It takes one operand, the index of the return address to return.
811 // An index of zero corresponds to the current function's return address.
812 // An index of one to the parent's return address, and so on.
813 // Depths > 0 not supported yet!
814 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
817 MachineFunction &MF = DAG.getMachineFunction();
818 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
819 int FI = XFI->createLRSpillSlot(MF);
820 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
821 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op),
822 DAG.getEntryNode(), FIN,
823 MachinePointerInfo::getFixedStack(MF, FI));
826 SDValue XCoreTargetLowering::
827 LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const {
828 // This node represents offset from frame pointer to first on-stack argument.
829 // This is needed for correct stack adjustment during unwind.
830 // However, we don't know the offset until after the frame has be finalised.
831 // This is done during the XCoreFTAOElim pass.
832 return DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, SDLoc(Op), MVT::i32);
835 SDValue XCoreTargetLowering::
836 LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
837 // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER)
838 // This node represents 'eh_return' gcc dwarf builtin, which is used to
839 // return from exception. The general meaning is: adjust stack by OFFSET and
840 // pass execution to HANDLER.
841 MachineFunction &MF = DAG.getMachineFunction();
842 SDValue Chain = Op.getOperand(0);
843 SDValue Offset = Op.getOperand(1);
844 SDValue Handler = Op.getOperand(2);
847 // Absolute SP = (FP + FrameToArgs) + Offset
848 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
849 SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
850 RegInfo->getFrameRegister(MF), MVT::i32);
851 SDValue FrameToArgs = DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl,
853 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, FrameToArgs);
854 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, Offset);
856 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
857 // which leaves 2 caller saved registers, R2 & R3 for us to use.
858 unsigned StackReg = XCore::R2;
859 unsigned HandlerReg = XCore::R3;
861 SDValue OutChains[] = {
862 DAG.getCopyToReg(Chain, dl, StackReg, Stack),
863 DAG.getCopyToReg(Chain, dl, HandlerReg, Handler)
866 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
868 return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain,
869 DAG.getRegister(StackReg, MVT::i32),
870 DAG.getRegister(HandlerReg, MVT::i32));
874 SDValue XCoreTargetLowering::
875 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
876 return Op.getOperand(0);
879 SDValue XCoreTargetLowering::
880 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
881 SDValue Chain = Op.getOperand(0);
882 SDValue Trmp = Op.getOperand(1); // trampoline
883 SDValue FPtr = Op.getOperand(2); // nested function
884 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
886 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
889 // LDAPF_u10 r11, nest
890 // LDW_2rus r11, r11[0]
891 // STWSP_ru6 r11, sp[0]
892 // LDAPF_u10 r11, fptr
893 // LDW_2rus r11, r11[0]
899 SDValue OutChains[5];
905 DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, dl, MVT::i32), Addr,
906 MachinePointerInfo(TrmpAddr));
908 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
909 DAG.getConstant(4, dl, MVT::i32));
911 DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, dl, MVT::i32), Addr,
912 MachinePointerInfo(TrmpAddr, 4));
914 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
915 DAG.getConstant(8, dl, MVT::i32));
917 DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, dl, MVT::i32), Addr,
918 MachinePointerInfo(TrmpAddr, 8));
920 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
921 DAG.getConstant(12, dl, MVT::i32));
923 DAG.getStore(Chain, dl, Nest, Addr, MachinePointerInfo(TrmpAddr, 12));
925 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
926 DAG.getConstant(16, dl, MVT::i32));
928 DAG.getStore(Chain, dl, FPtr, Addr, MachinePointerInfo(TrmpAddr, 16));
930 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
933 SDValue XCoreTargetLowering::
934 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
936 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
938 case Intrinsic::xcore_crc8:
939 EVT VT = Op.getValueType();
941 DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT),
942 Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3));
943 SDValue Crc(Data.getNode(), 1);
944 SDValue Results[] = { Crc, Data };
945 return DAG.getMergeValues(Results, DL);
950 SDValue XCoreTargetLowering::
951 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const {
953 return DAG.getNode(XCoreISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
956 SDValue XCoreTargetLowering::
957 LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const {
958 AtomicSDNode *N = cast<AtomicSDNode>(Op);
959 assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP");
960 assert((N->getOrdering() == AtomicOrdering::Unordered ||
961 N->getOrdering() == AtomicOrdering::Monotonic) &&
962 "setInsertFencesForAtomic(true) expects unordered / monotonic");
963 if (N->getMemoryVT() == MVT::i32) {
964 if (N->getAlignment() < 4)
965 report_fatal_error("atomic load must be aligned");
966 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op),
967 N->getChain(), N->getBasePtr(), N->getPointerInfo(),
968 N->getAlignment(), N->getMemOperand()->getFlags(),
969 N->getAAInfo(), N->getRanges());
971 if (N->getMemoryVT() == MVT::i16) {
972 if (N->getAlignment() < 2)
973 report_fatal_error("atomic load must be aligned");
974 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
975 N->getBasePtr(), N->getPointerInfo(), MVT::i16,
976 N->getAlignment(), N->getMemOperand()->getFlags(),
979 if (N->getMemoryVT() == MVT::i8)
980 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
981 N->getBasePtr(), N->getPointerInfo(), MVT::i8,
982 N->getAlignment(), N->getMemOperand()->getFlags(),
987 SDValue XCoreTargetLowering::
988 LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const {
989 AtomicSDNode *N = cast<AtomicSDNode>(Op);
990 assert(N->getOpcode() == ISD::ATOMIC_STORE && "Bad Atomic OP");
991 assert((N->getOrdering() == AtomicOrdering::Unordered ||
992 N->getOrdering() == AtomicOrdering::Monotonic) &&
993 "setInsertFencesForAtomic(true) expects unordered / monotonic");
994 if (N->getMemoryVT() == MVT::i32) {
995 if (N->getAlignment() < 4)
996 report_fatal_error("atomic store must be aligned");
997 return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(), N->getBasePtr(),
998 N->getPointerInfo(), N->getAlignment(),
999 N->getMemOperand()->getFlags(), N->getAAInfo());
1001 if (N->getMemoryVT() == MVT::i16) {
1002 if (N->getAlignment() < 2)
1003 report_fatal_error("atomic store must be aligned");
1004 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(),
1005 N->getBasePtr(), N->getPointerInfo(), MVT::i16,
1006 N->getAlignment(), N->getMemOperand()->getFlags(),
1009 if (N->getMemoryVT() == MVT::i8)
1010 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(),
1011 N->getBasePtr(), N->getPointerInfo(), MVT::i8,
1012 N->getAlignment(), N->getMemOperand()->getFlags(),
1017 //===----------------------------------------------------------------------===//
1018 // Calling Convention Implementation
1019 //===----------------------------------------------------------------------===//
1021 #include "XCoreGenCallingConv.inc"
1023 //===----------------------------------------------------------------------===//
1024 // Call Calling Convention Implementation
1025 //===----------------------------------------------------------------------===//
1027 /// XCore call implementation
1029 XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1030 SmallVectorImpl<SDValue> &InVals) const {
1031 SelectionDAG &DAG = CLI.DAG;
1033 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1034 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1035 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1036 SDValue Chain = CLI.Chain;
1037 SDValue Callee = CLI.Callee;
1038 bool &isTailCall = CLI.IsTailCall;
1039 CallingConv::ID CallConv = CLI.CallConv;
1040 bool isVarArg = CLI.IsVarArg;
1042 // XCore target does not yet support tail call optimization.
1045 // For now, only CallingConv::C implemented
1049 llvm_unreachable("Unsupported calling convention");
1050 case CallingConv::Fast:
1051 case CallingConv::C:
1052 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
1053 Outs, OutVals, Ins, dl, DAG, InVals);
1057 /// LowerCallResult - Lower the result values of a call into the
1058 /// appropriate copies out of appropriate physical registers / memory locations.
1059 static SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1060 const SmallVectorImpl<CCValAssign> &RVLocs,
1061 const SDLoc &dl, SelectionDAG &DAG,
1062 SmallVectorImpl<SDValue> &InVals) {
1063 SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs;
1064 // Copy results out of physical registers.
1065 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1066 const CCValAssign &VA = RVLocs[i];
1067 if (VA.isRegLoc()) {
1068 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),
1069 InFlag).getValue(1);
1070 InFlag = Chain.getValue(2);
1071 InVals.push_back(Chain.getValue(0));
1073 assert(VA.isMemLoc());
1074 ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(),
1076 // Reserve space for this result.
1077 InVals.push_back(SDValue());
1081 // Copy results out of memory.
1082 SmallVector<SDValue, 4> MemOpChains;
1083 for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) {
1084 int offset = ResultMemLocs[i].first;
1085 unsigned index = ResultMemLocs[i].second;
1086 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1087 SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, dl, MVT::i32) };
1088 SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);
1089 InVals[index] = load;
1090 MemOpChains.push_back(load.getValue(1));
1093 // Transform all loads nodes into one single node because
1094 // all load nodes are independent of each other.
1095 if (!MemOpChains.empty())
1096 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1101 /// LowerCCCCallTo - functions arguments are copied from virtual
1102 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
1103 /// CALLSEQ_END are emitted.
1104 /// TODO: isTailCall, sret.
1105 SDValue XCoreTargetLowering::LowerCCCCallTo(
1106 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
1107 bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
1108 const SmallVectorImpl<SDValue> &OutVals,
1109 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1110 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1112 // Analyze operands of the call, assigning locations to each operand.
1113 SmallVector<CCValAssign, 16> ArgLocs;
1114 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1117 // The ABI dictates there should be one stack slot available to the callee
1118 // on function entry (for saving lr).
1119 CCInfo.AllocateStack(4, 4);
1121 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1123 SmallVector<CCValAssign, 16> RVLocs;
1124 // Analyze return values to determine the number of bytes of stack required.
1125 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1127 RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4);
1128 RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1130 // Get a count of how many bytes are to be pushed on the stack.
1131 unsigned NumBytes = RetCCInfo.getNextStackOffset();
1132 auto PtrVT = getPointerTy(DAG.getDataLayout());
1134 Chain = DAG.getCALLSEQ_START(Chain,
1135 DAG.getConstant(NumBytes, dl, PtrVT, true), dl);
1137 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
1138 SmallVector<SDValue, 12> MemOpChains;
1140 // Walk the register/memloc assignments, inserting copies/loads.
1141 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1142 CCValAssign &VA = ArgLocs[i];
1143 SDValue Arg = OutVals[i];
1145 // Promote the value if needed.
1146 switch (VA.getLocInfo()) {
1147 default: llvm_unreachable("Unknown loc info!");
1148 case CCValAssign::Full: break;
1149 case CCValAssign::SExt:
1150 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1152 case CCValAssign::ZExt:
1153 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1155 case CCValAssign::AExt:
1156 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1160 // Arguments that can be passed on register must be kept at
1161 // RegsToPass vector
1162 if (VA.isRegLoc()) {
1163 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1165 assert(VA.isMemLoc());
1167 int Offset = VA.getLocMemOffset();
1169 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
1171 DAG.getConstant(Offset/4, dl,
1176 // Transform all store nodes into one single node because
1177 // all store nodes are independent of each other.
1178 if (!MemOpChains.empty())
1179 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1181 // Build a sequence of copy-to-reg nodes chained together with token
1182 // chain and flag operands which copy the outgoing args into registers.
1183 // The InFlag in necessary since all emitted instructions must be
1186 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1187 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1188 RegsToPass[i].second, InFlag);
1189 InFlag = Chain.getValue(1);
1192 // If the callee is a GlobalAddress node (quite common, every direct call is)
1193 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1194 // Likewise ExternalSymbol -> TargetExternalSymbol.
1195 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1196 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
1197 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1198 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
1200 // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
1201 // = Chain, Callee, Reg#1, Reg#2, ...
1203 // Returns a chain & a flag for retval copy to use.
1204 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1205 SmallVector<SDValue, 8> Ops;
1206 Ops.push_back(Chain);
1207 Ops.push_back(Callee);
1209 // Add argument registers to the end of the list so that they are
1210 // known live into the call.
1211 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1212 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1213 RegsToPass[i].second.getValueType()));
1215 if (InFlag.getNode())
1216 Ops.push_back(InFlag);
1218 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, Ops);
1219 InFlag = Chain.getValue(1);
1221 // Create the CALLSEQ_END node.
1222 Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
1223 DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
1224 InFlag = Chain.getValue(1);
1226 // Handle result values, copying them out of physregs into vregs that we
1228 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
1231 //===----------------------------------------------------------------------===//
1232 // Formal Arguments Calling Convention Implementation
1233 //===----------------------------------------------------------------------===//
1236 struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; };
1239 /// XCore formal arguments implementation
1240 SDValue XCoreTargetLowering::LowerFormalArguments(
1241 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1242 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1243 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1247 llvm_unreachable("Unsupported calling convention");
1248 case CallingConv::C:
1249 case CallingConv::Fast:
1250 return LowerCCCArguments(Chain, CallConv, isVarArg,
1251 Ins, dl, DAG, InVals);
1255 /// LowerCCCArguments - transform physical registers into
1256 /// virtual registers and generate load operations for
1257 /// arguments places on the stack.
1259 SDValue XCoreTargetLowering::LowerCCCArguments(
1260 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1261 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1262 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1263 MachineFunction &MF = DAG.getMachineFunction();
1264 MachineFrameInfo &MFI = MF.getFrameInfo();
1265 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1266 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1268 // Assign locations to all of the incoming arguments.
1269 SmallVector<CCValAssign, 16> ArgLocs;
1270 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1273 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1275 unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize();
1277 unsigned LRSaveSize = StackSlotSize;
1280 XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize);
1282 // All getCopyFromReg ops must precede any getMemcpys to prevent the
1283 // scheduler clobbering a register before it has been copied.
1285 // 1. CopyFromReg (and load) arg & vararg registers.
1286 // 2. Chain CopyFromReg nodes into a TokenFactor.
1287 // 3. Memcpy 'byVal' args & push final InVals.
1288 // 4. Chain mem ops nodes into a TokenFactor.
1289 SmallVector<SDValue, 4> CFRegNode;
1290 SmallVector<ArgDataPair, 4> ArgData;
1291 SmallVector<SDValue, 4> MemOps;
1293 // 1a. CopyFromReg (and load) arg registers.
1294 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1296 CCValAssign &VA = ArgLocs[i];
1299 if (VA.isRegLoc()) {
1300 // Arguments passed in registers
1301 EVT RegVT = VA.getLocVT();
1302 switch (RegVT.getSimpleVT().SimpleTy) {
1306 errs() << "LowerFormalArguments Unhandled argument type: "
1307 << RegVT.getEVTString() << "\n";
1309 llvm_unreachable(nullptr);
1312 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1313 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1314 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1315 CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1));
1319 assert(VA.isMemLoc());
1320 // Load the argument to a virtual register
1321 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
1322 if (ObjSize > StackSlotSize) {
1323 errs() << "LowerFormalArguments Unhandled argument type: "
1324 << EVT(VA.getLocVT()).getEVTString()
1327 // Create the frame index object for this incoming parameter...
1328 int FI = MFI.CreateFixedObject(ObjSize,
1329 LRSaveSize + VA.getLocMemOffset(),
1332 // Create the SelectionDAG nodes corresponding to a load
1333 //from this parameter
1334 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1335 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1336 MachinePointerInfo::getFixedStack(MF, FI));
1338 const ArgDataPair ADP = { ArgIn, Ins[i].Flags };
1339 ArgData.push_back(ADP);
1342 // 1b. CopyFromReg vararg registers.
1344 // Argument registers
1345 static const MCPhysReg ArgRegs[] = {
1346 XCore::R0, XCore::R1, XCore::R2, XCore::R3
1348 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1349 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
1350 if (FirstVAReg < array_lengthof(ArgRegs)) {
1352 // Save remaining registers, storing higher register numbers at a higher
1354 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
1355 // Create a stack slot
1356 int FI = MFI.CreateFixedObject(4, offset, true);
1357 if (i == (int)FirstVAReg) {
1358 XFI->setVarArgsFrameIndex(FI);
1360 offset -= StackSlotSize;
1361 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1362 // Move argument from phys reg -> virt reg
1363 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1364 RegInfo.addLiveIn(ArgRegs[i], VReg);
1365 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1366 CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1));
1367 // Move argument from virt reg -> stack
1369 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
1370 MemOps.push_back(Store);
1373 // This will point to the next argument passed via stack.
1374 XFI->setVarArgsFrameIndex(
1375 MFI.CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
1380 // 2. chain CopyFromReg nodes into a TokenFactor.
1381 if (!CFRegNode.empty())
1382 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, CFRegNode);
1384 // 3. Memcpy 'byVal' args & push final InVals.
1385 // Aggregates passed "byVal" need to be copied by the callee.
1386 // The callee will use a pointer to this copy, rather than the original
1388 for (SmallVectorImpl<ArgDataPair>::const_iterator ArgDI = ArgData.begin(),
1389 ArgDE = ArgData.end();
1390 ArgDI != ArgDE; ++ArgDI) {
1391 if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) {
1392 unsigned Size = ArgDI->Flags.getByValSize();
1393 unsigned Align = std::max(StackSlotSize, ArgDI->Flags.getByValAlign());
1394 // Create a new object on the stack and copy the pointee into it.
1395 int FI = MFI.CreateStackObject(Size, Align, false);
1396 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1397 InVals.push_back(FIN);
1398 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,
1399 DAG.getConstant(Size, dl, MVT::i32),
1400 Align, false, false, false,
1401 MachinePointerInfo(),
1402 MachinePointerInfo()));
1404 InVals.push_back(ArgDI->SDV);
1408 // 4, chain mem ops nodes into a TokenFactor.
1409 if (!MemOps.empty()) {
1410 MemOps.push_back(Chain);
1411 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1417 //===----------------------------------------------------------------------===//
1418 // Return Value Calling Convention Implementation
1419 //===----------------------------------------------------------------------===//
1421 bool XCoreTargetLowering::
1422 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1424 const SmallVectorImpl<ISD::OutputArg> &Outs,
1425 LLVMContext &Context) const {
1426 SmallVector<CCValAssign, 16> RVLocs;
1427 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1428 if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
1430 if (CCInfo.getNextStackOffset() != 0 && isVarArg)
1436 XCoreTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1438 const SmallVectorImpl<ISD::OutputArg> &Outs,
1439 const SmallVectorImpl<SDValue> &OutVals,
1440 const SDLoc &dl, SelectionDAG &DAG) const {
1442 XCoreFunctionInfo *XFI =
1443 DAG.getMachineFunction().getInfo<XCoreFunctionInfo>();
1444 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1446 // CCValAssign - represent the assignment of
1447 // the return value to a location
1448 SmallVector<CCValAssign, 16> RVLocs;
1450 // CCState - Info about the registers and stack slot.
1451 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1454 // Analyze return values.
1456 CCInfo.AllocateStack(XFI->getReturnStackOffset(), 4);
1458 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1461 SmallVector<SDValue, 4> RetOps(1, Chain);
1463 // Return on XCore is always a "retsp 0"
1464 RetOps.push_back(DAG.getConstant(0, dl, MVT::i32));
1466 SmallVector<SDValue, 4> MemOpChains;
1467 // Handle return values that must be copied to memory.
1468 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1469 CCValAssign &VA = RVLocs[i];
1472 assert(VA.isMemLoc());
1474 report_fatal_error("Can't return value from vararg function in memory");
1477 int Offset = VA.getLocMemOffset();
1478 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
1479 // Create the frame index object for the memory location.
1480 int FI = MFI.CreateFixedObject(ObjSize, Offset, false);
1482 // Create a SelectionDAG node corresponding to a store
1483 // to this memory location.
1484 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1485 MemOpChains.push_back(DAG.getStore(
1486 Chain, dl, OutVals[i], FIN,
1487 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
1490 // Transform all store nodes into one single node because
1491 // all stores are independent of each other.
1492 if (!MemOpChains.empty())
1493 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1495 // Now handle return values copied to registers.
1496 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1497 CCValAssign &VA = RVLocs[i];
1500 // Copy the result values into the output registers.
1501 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1503 // guarantee that all emitted copies are
1504 // stuck together, avoiding something bad
1505 Flag = Chain.getValue(1);
1506 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1509 RetOps[0] = Chain; // Update chain.
1511 // Add the flag if we have it.
1513 RetOps.push_back(Flag);
1515 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, RetOps);
1518 //===----------------------------------------------------------------------===//
1519 // Other Lowering Code
1520 //===----------------------------------------------------------------------===//
1523 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1524 MachineBasicBlock *BB) const {
1525 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1526 DebugLoc dl = MI.getDebugLoc();
1527 assert((MI.getOpcode() == XCore::SELECT_CC) &&
1528 "Unexpected instr type to insert");
1530 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1531 // control-flow pattern. The incoming instruction knows the destination vreg
1532 // to set, the condition code register to branch on, the true/false values to
1533 // select between, and a branch opcode to use.
1534 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1535 MachineFunction::iterator It = ++BB->getIterator();
1540 // cmpTY ccX, r1, r2
1542 // fallthrough --> copy0MBB
1543 MachineBasicBlock *thisMBB = BB;
1544 MachineFunction *F = BB->getParent();
1545 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1546 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1547 F->insert(It, copy0MBB);
1548 F->insert(It, sinkMBB);
1550 // Transfer the remainder of BB and its successor edges to sinkMBB.
1551 sinkMBB->splice(sinkMBB->begin(), BB,
1552 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1553 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1555 // Next, add the true and fallthrough blocks as its successors.
1556 BB->addSuccessor(copy0MBB);
1557 BB->addSuccessor(sinkMBB);
1559 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1560 .addReg(MI.getOperand(1).getReg())
1564 // %FalseValue = ...
1565 // # fallthrough to sinkMBB
1568 // Update machine-CFG edges
1569 BB->addSuccessor(sinkMBB);
1572 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1575 BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg())
1576 .addReg(MI.getOperand(3).getReg())
1578 .addReg(MI.getOperand(2).getReg())
1581 MI.eraseFromParent(); // The pseudo instruction is gone now.
1585 //===----------------------------------------------------------------------===//
1586 // Target Optimization Hooks
1587 //===----------------------------------------------------------------------===//
1589 SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
1590 DAGCombinerInfo &DCI) const {
1591 SelectionDAG &DAG = DCI.DAG;
1593 switch (N->getOpcode()) {
1595 case ISD::INTRINSIC_VOID:
1596 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
1597 case Intrinsic::xcore_outt:
1598 case Intrinsic::xcore_outct:
1599 case Intrinsic::xcore_chkct: {
1600 SDValue OutVal = N->getOperand(3);
1601 // These instructions ignore the high bits.
1602 if (OutVal.hasOneUse()) {
1603 unsigned BitWidth = OutVal.getValueSizeInBits();
1604 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 8);
1606 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1607 !DCI.isBeforeLegalizeOps());
1608 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1609 if (TLI.ShrinkDemandedConstant(OutVal, DemandedMask, TLO) ||
1610 TLI.SimplifyDemandedBits(OutVal, DemandedMask, Known, TLO))
1611 DCI.CommitTargetLoweringOpt(TLO);
1615 case Intrinsic::xcore_setpt: {
1616 SDValue Time = N->getOperand(3);
1617 // This instruction ignores the high bits.
1618 if (Time.hasOneUse()) {
1619 unsigned BitWidth = Time.getValueSizeInBits();
1620 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16);
1622 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1623 !DCI.isBeforeLegalizeOps());
1624 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1625 if (TLI.ShrinkDemandedConstant(Time, DemandedMask, TLO) ||
1626 TLI.SimplifyDemandedBits(Time, DemandedMask, Known, TLO))
1627 DCI.CommitTargetLoweringOpt(TLO);
1633 case XCoreISD::LADD: {
1634 SDValue N0 = N->getOperand(0);
1635 SDValue N1 = N->getOperand(1);
1636 SDValue N2 = N->getOperand(2);
1637 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1638 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1639 EVT VT = N0.getValueType();
1641 // canonicalize constant to RHS
1643 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1645 // fold (ladd 0, 0, x) -> 0, x & 1
1646 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1647 SDValue Carry = DAG.getConstant(0, dl, VT);
1648 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1649 DAG.getConstant(1, dl, VT));
1650 SDValue Ops[] = { Result, Carry };
1651 return DAG.getMergeValues(Ops, dl);
1654 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
1656 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) {
1658 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1659 VT.getSizeInBits() - 1);
1660 DAG.computeKnownBits(N2, Known);
1661 if ((Known.Zero & Mask) == Mask) {
1662 SDValue Carry = DAG.getConstant(0, dl, VT);
1663 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1664 SDValue Ops[] = { Result, Carry };
1665 return DAG.getMergeValues(Ops, dl);
1670 case XCoreISD::LSUB: {
1671 SDValue N0 = N->getOperand(0);
1672 SDValue N1 = N->getOperand(1);
1673 SDValue N2 = N->getOperand(2);
1674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1676 EVT VT = N0.getValueType();
1678 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
1679 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1681 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1682 VT.getSizeInBits() - 1);
1683 DAG.computeKnownBits(N2, Known);
1684 if ((Known.Zero & Mask) == Mask) {
1685 SDValue Borrow = N2;
1686 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1687 DAG.getConstant(0, dl, VT), N2);
1688 SDValue Ops[] = { Result, Borrow };
1689 return DAG.getMergeValues(Ops, dl);
1693 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1695 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) {
1697 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1698 VT.getSizeInBits() - 1);
1699 DAG.computeKnownBits(N2, Known);
1700 if ((Known.Zero & Mask) == Mask) {
1701 SDValue Borrow = DAG.getConstant(0, dl, VT);
1702 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1703 SDValue Ops[] = { Result, Borrow };
1704 return DAG.getMergeValues(Ops, dl);
1709 case XCoreISD::LMUL: {
1710 SDValue N0 = N->getOperand(0);
1711 SDValue N1 = N->getOperand(1);
1712 SDValue N2 = N->getOperand(2);
1713 SDValue N3 = N->getOperand(3);
1714 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1715 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1716 EVT VT = N0.getValueType();
1717 // Canonicalize multiplicative constant to RHS. If both multiplicative
1718 // operands are constant canonicalize smallest to RHS.
1719 if ((N0C && !N1C) ||
1720 (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
1721 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
1725 if (N1C && N1C->isNullValue()) {
1726 // If the high result is unused fold to add(a, b)
1727 if (N->hasNUsesOfValue(0, 0)) {
1728 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1729 SDValue Ops[] = { Lo, Lo };
1730 return DAG.getMergeValues(Ops, dl);
1732 // Otherwise fold to ladd(a, b, 0)
1734 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1735 SDValue Carry(Result.getNode(), 1);
1736 SDValue Ops[] = { Carry, Result };
1737 return DAG.getMergeValues(Ops, dl);
1742 // Fold 32 bit expressions such as add(add(mul(x,y),a),b) ->
1743 // lmul(x, y, a, b). The high result of lmul will be ignored.
1744 // This is only profitable if the intermediate results are unused
1746 SDValue Mul0, Mul1, Addend0, Addend1;
1747 if (N->getValueType(0) == MVT::i32 &&
1748 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) {
1749 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1750 DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1751 Mul1, Addend0, Addend1);
1752 SDValue Result(Ignored.getNode(), 1);
1755 APInt HighMask = APInt::getHighBitsSet(64, 32);
1756 // Fold 64 bit expression such as add(add(mul(x,y),a),b) ->
1757 // lmul(x, y, a, b) if all operands are zero-extended. We do this
1758 // before type legalization as it is messy to match the operands after
1760 if (N->getValueType(0) == MVT::i64 &&
1761 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) &&
1762 DAG.MaskedValueIsZero(Mul0, HighMask) &&
1763 DAG.MaskedValueIsZero(Mul1, HighMask) &&
1764 DAG.MaskedValueIsZero(Addend0, HighMask) &&
1765 DAG.MaskedValueIsZero(Addend1, HighMask)) {
1766 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1767 Mul0, DAG.getConstant(0, dl, MVT::i32));
1768 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1769 Mul1, DAG.getConstant(0, dl, MVT::i32));
1770 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1771 Addend0, DAG.getConstant(0, dl, MVT::i32));
1772 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1773 Addend1, DAG.getConstant(0, dl, MVT::i32));
1774 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1775 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1776 Addend0L, Addend1L);
1777 SDValue Lo(Hi.getNode(), 1);
1778 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1783 // Replace unaligned store of unaligned load with memmove.
1784 StoreSDNode *ST = cast<StoreSDNode>(N);
1785 if (!DCI.isBeforeLegalize() ||
1786 allowsMisalignedMemoryAccesses(ST->getMemoryVT(),
1787 ST->getAddressSpace(),
1788 ST->getAlignment()) ||
1789 ST->isVolatile() || ST->isIndexed()) {
1792 SDValue Chain = ST->getChain();
1794 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
1795 assert((StoreBits % 8) == 0 &&
1796 "Store size in bits must be a multiple of 8");
1797 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(
1798 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
1799 unsigned Alignment = ST->getAlignment();
1800 if (Alignment >= ABIAlignment) {
1804 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) {
1805 if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
1806 LD->getAlignment() == Alignment &&
1807 !LD->isVolatile() && !LD->isIndexed() &&
1808 Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
1809 bool isTail = isInTailCallPosition(DAG, ST, Chain);
1810 return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1812 DAG.getConstant(StoreBits/8, dl, MVT::i32),
1813 Alignment, false, isTail, ST->getPointerInfo(),
1814 LD->getPointerInfo());
1823 void XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1825 const APInt &DemandedElts,
1826 const SelectionDAG &DAG,
1827 unsigned Depth) const {
1829 switch (Op.getOpcode()) {
1831 case XCoreISD::LADD:
1832 case XCoreISD::LSUB:
1833 if (Op.getResNo() == 1) {
1834 // Top bits of carry / borrow are clear.
1835 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1836 Known.getBitWidth() - 1);
1839 case ISD::INTRINSIC_W_CHAIN:
1841 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1843 case Intrinsic::xcore_getts:
1844 // High bits are known to be zero.
1845 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1846 Known.getBitWidth() - 16);
1848 case Intrinsic::xcore_int:
1849 case Intrinsic::xcore_inct:
1850 // High bits are known to be zero.
1851 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1852 Known.getBitWidth() - 8);
1854 case Intrinsic::xcore_testct:
1855 // Result is either 0 or 1.
1856 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1857 Known.getBitWidth() - 1);
1859 case Intrinsic::xcore_testwct:
1860 // Result is in the range 0 - 4.
1861 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1862 Known.getBitWidth() - 3);
1870 //===----------------------------------------------------------------------===//
1871 // Addressing mode description hooks
1872 //===----------------------------------------------------------------------===//
1874 static inline bool isImmUs(int64_t val)
1876 return (val >= 0 && val <= 11);
1879 static inline bool isImmUs2(int64_t val)
1881 return (val%2 == 0 && isImmUs(val/2));
1884 static inline bool isImmUs4(int64_t val)
1886 return (val%4 == 0 && isImmUs(val/4));
1889 /// isLegalAddressingMode - Return true if the addressing mode represented
1890 /// by AM is legal for this target, for a load/store of the specified type.
1891 bool XCoreTargetLowering::isLegalAddressingMode(const DataLayout &DL,
1892 const AddrMode &AM, Type *Ty,
1893 unsigned AS) const {
1894 if (Ty->getTypeID() == Type::VoidTyID)
1895 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1897 unsigned Size = DL.getTypeAllocSize(Ty);
1899 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1906 if (AM.Scale == 0) {
1907 return isImmUs(AM.BaseOffs);
1910 return AM.Scale == 1 && AM.BaseOffs == 0;
1914 if (AM.Scale == 0) {
1915 return isImmUs2(AM.BaseOffs);
1918 return AM.Scale == 2 && AM.BaseOffs == 0;
1921 if (AM.Scale == 0) {
1922 return isImmUs4(AM.BaseOffs);
1925 return AM.Scale == 4 && AM.BaseOffs == 0;
1929 //===----------------------------------------------------------------------===//
1930 // XCore Inline Assembly Support
1931 //===----------------------------------------------------------------------===//
1933 std::pair<unsigned, const TargetRegisterClass *>
1934 XCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1935 StringRef Constraint,
1937 if (Constraint.size() == 1) {
1938 switch (Constraint[0]) {
1941 return std::make_pair(0U, &XCore::GRRegsRegClass);
1944 // Use the default implementation in TargetLowering to convert the register
1945 // constraint into a member of a register class.
1946 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);