1 //===- InstCombineSimplifyDemanded.cpp ------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains logic for simplifying instructions based on information
11 // about how they are used.
13 //===----------------------------------------------------------------------===//
15 #include "InstCombineInternal.h"
16 #include "llvm/Analysis/ValueTracking.h"
17 #include "llvm/IR/IntrinsicInst.h"
18 #include "llvm/IR/PatternMatch.h"
21 using namespace llvm::PatternMatch;
23 #define DEBUG_TYPE "instcombine"
25 /// Check to see if the specified operand of the specified instruction is a
26 /// constant integer. If so, check to see if there are any bits set in the
27 /// constant that are not demanded. If so, shrink the constant and return true.
28 static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
30 assert(I && "No instruction?");
31 assert(OpNo < I->getNumOperands() && "Operand index too large");
33 // If the operand is not a constant integer, nothing to do.
34 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo));
35 if (!OpC) return false;
37 // If there are no bits set that aren't demanded, nothing to do.
38 Demanded = Demanded.zextOrTrunc(OpC->getValue().getBitWidth());
39 if ((~Demanded & OpC->getValue()) == 0)
42 // This instruction is producing bits that are not demanded. Shrink the RHS.
43 Demanded &= OpC->getValue();
44 I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
51 /// Inst is an integer instruction that SimplifyDemandedBits knows about. See if
52 /// the instruction has any properties that allow us to simplify its operands.
53 bool InstCombiner::SimplifyDemandedInstructionBits(Instruction &Inst) {
54 unsigned BitWidth = Inst.getType()->getScalarSizeInBits();
55 APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
56 APInt DemandedMask(APInt::getAllOnesValue(BitWidth));
58 Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, KnownZero, KnownOne,
61 if (V == &Inst) return true;
62 replaceInstUsesWith(Inst, V);
66 /// This form of SimplifyDemandedBits simplifies the specified instruction
67 /// operand if possible, updating it in place. It returns true if it made any
68 /// change and false otherwise.
69 bool InstCombiner::SimplifyDemandedBits(Use &U, const APInt &DemandedMask,
70 APInt &KnownZero, APInt &KnownOne,
72 auto *UserI = dyn_cast<Instruction>(U.getUser());
73 Value *NewVal = SimplifyDemandedUseBits(U.get(), DemandedMask, KnownZero,
74 KnownOne, Depth, UserI);
75 if (!NewVal) return false;
81 /// This function attempts to replace V with a simpler value based on the
82 /// demanded bits. When this function is called, it is known that only the bits
83 /// set in DemandedMask of the result of V are ever used downstream.
84 /// Consequently, depending on the mask and V, it may be possible to replace V
85 /// with a constant or one of its operands. In such cases, this function does
86 /// the replacement and returns true. In all other cases, it returns false after
87 /// analyzing the expression and setting KnownOne and known to be one in the
88 /// expression. KnownZero contains all the bits that are known to be zero in the
89 /// expression. These are provided to potentially allow the caller (which might
90 /// recursively be SimplifyDemandedBits itself) to simplify the expression.
91 /// KnownOne and KnownZero always follow the invariant that:
92 /// KnownOne & KnownZero == 0.
93 /// That is, a bit can't be both 1 and 0. Note that the bits in KnownOne and
94 /// KnownZero may only be accurate for those bits set in DemandedMask. Note also
95 /// that the bitwidth of V, DemandedMask, KnownZero and KnownOne must all be the
98 /// This returns null if it did not change anything and it permits no
99 /// simplification. This returns V itself if it did some simplification of V's
100 /// operands based on the information about what bits are demanded. This returns
101 /// some other non-null value if it found out that V is equal to another value
102 /// in the context where the specified bits are demanded, but not for all users.
103 Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
104 APInt &KnownZero, APInt &KnownOne,
107 assert(V != nullptr && "Null pointer of Value???");
108 assert(Depth <= 6 && "Limit Search Depth");
109 uint32_t BitWidth = DemandedMask.getBitWidth();
110 Type *VTy = V->getType();
112 (!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits() == BitWidth) &&
113 KnownZero.getBitWidth() == BitWidth &&
114 KnownOne.getBitWidth() == BitWidth &&
115 "Value *V, DemandedMask, KnownZero and KnownOne "
116 "must have same BitWidth");
117 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
118 // We know all of the bits for a constant!
119 KnownOne = CI->getValue() & DemandedMask;
120 KnownZero = ~KnownOne & DemandedMask;
123 if (isa<ConstantPointerNull>(V)) {
124 // We know all of the bits for a constant!
125 KnownOne.clearAllBits();
126 KnownZero = DemandedMask;
130 KnownZero.clearAllBits();
131 KnownOne.clearAllBits();
132 if (DemandedMask == 0) { // Not demanding any bits from V.
133 if (isa<UndefValue>(V))
135 return UndefValue::get(VTy);
138 if (Depth == 6) // Limit search depth.
141 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
142 APInt RHSKnownZero(BitWidth, 0), RHSKnownOne(BitWidth, 0);
144 Instruction *I = dyn_cast<Instruction>(V);
146 computeKnownBits(V, KnownZero, KnownOne, Depth, CxtI);
147 return nullptr; // Only analyze instructions.
150 // If there are multiple uses of this value and we aren't at the root, then
151 // we can't do any simplifications of the operands, because DemandedMask
152 // only reflects the bits demanded by *one* of the users.
153 if (Depth != 0 && !I->hasOneUse()) {
154 // Despite the fact that we can't simplify this instruction in all User's
155 // context, we can at least compute the knownzero/knownone bits, and we can
156 // do simplifications that apply to *just* the one user if we know that
157 // this instruction has a simpler value in that context.
158 if (I->getOpcode() == Instruction::And) {
159 // If either the LHS or the RHS are Zero, the result is zero.
160 computeKnownBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth + 1,
162 computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth + 1,
165 // If all of the demanded bits are known 1 on one side, return the other.
166 // These bits cannot contribute to the result of the 'and' in this
168 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) ==
169 (DemandedMask & ~LHSKnownZero))
170 return I->getOperand(0);
171 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) ==
172 (DemandedMask & ~RHSKnownZero))
173 return I->getOperand(1);
175 // If all of the demanded bits in the inputs are known zeros, return zero.
176 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask)
177 return Constant::getNullValue(VTy);
179 } else if (I->getOpcode() == Instruction::Or) {
180 // We can simplify (X|Y) -> X or Y in the user's context if we know that
181 // only bits from X or Y are demanded.
183 // If either the LHS or the RHS are One, the result is One.
184 computeKnownBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth + 1,
186 computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth + 1,
189 // If all of the demanded bits are known zero on one side, return the
190 // other. These bits cannot contribute to the result of the 'or' in this
192 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) ==
193 (DemandedMask & ~LHSKnownOne))
194 return I->getOperand(0);
195 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) ==
196 (DemandedMask & ~RHSKnownOne))
197 return I->getOperand(1);
199 // If all of the potentially set bits on one side are known to be set on
200 // the other side, just use the 'other' side.
201 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) ==
202 (DemandedMask & (~RHSKnownZero)))
203 return I->getOperand(0);
204 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) ==
205 (DemandedMask & (~LHSKnownZero)))
206 return I->getOperand(1);
207 } else if (I->getOpcode() == Instruction::Xor) {
208 // We can simplify (X^Y) -> X or Y in the user's context if we know that
209 // only bits from X or Y are demanded.
211 computeKnownBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth + 1,
213 computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth + 1,
216 // If all of the demanded bits are known zero on one side, return the
218 if ((DemandedMask & RHSKnownZero) == DemandedMask)
219 return I->getOperand(0);
220 if ((DemandedMask & LHSKnownZero) == DemandedMask)
221 return I->getOperand(1);
224 // Compute the KnownZero/KnownOne bits to simplify things downstream.
225 computeKnownBits(I, KnownZero, KnownOne, Depth, CxtI);
229 // If this is the root being simplified, allow it to have multiple uses,
230 // just set the DemandedMask to all bits so that we can try to simplify the
231 // operands. This allows visitTruncInst (for example) to simplify the
232 // operand of a trunc without duplicating all the logic below.
233 if (Depth == 0 && !V->hasOneUse())
234 DemandedMask = APInt::getAllOnesValue(BitWidth);
236 switch (I->getOpcode()) {
238 computeKnownBits(I, KnownZero, KnownOne, Depth, CxtI);
240 case Instruction::And:
241 // If either the LHS or the RHS are Zero, the result is zero.
242 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, RHSKnownZero,
243 RHSKnownOne, Depth + 1) ||
244 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownZero,
245 LHSKnownZero, LHSKnownOne, Depth + 1))
247 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
248 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
250 // If the client is only demanding bits that we know, return the known
252 if ((DemandedMask & ((RHSKnownZero | LHSKnownZero)|
253 (RHSKnownOne & LHSKnownOne))) == DemandedMask)
254 return Constant::getIntegerValue(VTy, RHSKnownOne & LHSKnownOne);
256 // If all of the demanded bits are known 1 on one side, return the other.
257 // These bits cannot contribute to the result of the 'and'.
258 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) ==
259 (DemandedMask & ~LHSKnownZero))
260 return I->getOperand(0);
261 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) ==
262 (DemandedMask & ~RHSKnownZero))
263 return I->getOperand(1);
265 // If all of the demanded bits in the inputs are known zeros, return zero.
266 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask)
267 return Constant::getNullValue(VTy);
269 // If the RHS is a constant, see if we can simplify it.
270 if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnownZero))
273 // Output known-1 bits are only known if set in both the LHS & RHS.
274 KnownOne = RHSKnownOne & LHSKnownOne;
275 // Output known-0 are known to be clear if zero in either the LHS | RHS.
276 KnownZero = RHSKnownZero | LHSKnownZero;
278 case Instruction::Or:
279 // If either the LHS or the RHS are One, the result is One.
280 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, RHSKnownZero,
281 RHSKnownOne, Depth + 1) ||
282 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownOne,
283 LHSKnownZero, LHSKnownOne, Depth + 1))
285 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
286 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
288 // If the client is only demanding bits that we know, return the known
290 if ((DemandedMask & ((RHSKnownZero & LHSKnownZero)|
291 (RHSKnownOne | LHSKnownOne))) == DemandedMask)
292 return Constant::getIntegerValue(VTy, RHSKnownOne | LHSKnownOne);
294 // If all of the demanded bits are known zero on one side, return the other.
295 // These bits cannot contribute to the result of the 'or'.
296 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) ==
297 (DemandedMask & ~LHSKnownOne))
298 return I->getOperand(0);
299 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) ==
300 (DemandedMask & ~RHSKnownOne))
301 return I->getOperand(1);
303 // If all of the potentially set bits on one side are known to be set on
304 // the other side, just use the 'other' side.
305 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) ==
306 (DemandedMask & (~RHSKnownZero)))
307 return I->getOperand(0);
308 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) ==
309 (DemandedMask & (~LHSKnownZero)))
310 return I->getOperand(1);
312 // If the RHS is a constant, see if we can simplify it.
313 if (ShrinkDemandedConstant(I, 1, DemandedMask))
316 // Output known-0 bits are only known if clear in both the LHS & RHS.
317 KnownZero = RHSKnownZero & LHSKnownZero;
318 // Output known-1 are known to be set if set in either the LHS | RHS.
319 KnownOne = RHSKnownOne | LHSKnownOne;
321 case Instruction::Xor: {
322 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, RHSKnownZero,
323 RHSKnownOne, Depth + 1) ||
324 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, LHSKnownZero,
325 LHSKnownOne, Depth + 1))
327 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
328 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
330 // Output known-0 bits are known if clear or set in both the LHS & RHS.
331 APInt IKnownZero = (RHSKnownZero & LHSKnownZero) |
332 (RHSKnownOne & LHSKnownOne);
333 // Output known-1 are known to be set if set in only one of the LHS, RHS.
334 APInt IKnownOne = (RHSKnownZero & LHSKnownOne) |
335 (RHSKnownOne & LHSKnownZero);
337 // If the client is only demanding bits that we know, return the known
339 if ((DemandedMask & (IKnownZero|IKnownOne)) == DemandedMask)
340 return Constant::getIntegerValue(VTy, IKnownOne);
342 // If all of the demanded bits are known zero on one side, return the other.
343 // These bits cannot contribute to the result of the 'xor'.
344 if ((DemandedMask & RHSKnownZero) == DemandedMask)
345 return I->getOperand(0);
346 if ((DemandedMask & LHSKnownZero) == DemandedMask)
347 return I->getOperand(1);
349 // If all of the demanded bits are known to be zero on one side or the
350 // other, turn this into an *inclusive* or.
351 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
352 if ((DemandedMask & ~RHSKnownZero & ~LHSKnownZero) == 0) {
354 BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1),
356 return InsertNewInstWith(Or, *I);
359 // If all of the demanded bits on one side are known, and all of the set
360 // bits on that side are also known to be set on the other side, turn this
361 // into an AND, as we know the bits will be cleared.
362 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
363 if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) {
365 if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) {
366 Constant *AndC = Constant::getIntegerValue(VTy,
367 ~RHSKnownOne & DemandedMask);
368 Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
369 return InsertNewInstWith(And, *I);
373 // If the RHS is a constant, see if we can simplify it.
374 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
375 if (ShrinkDemandedConstant(I, 1, DemandedMask))
378 // If our LHS is an 'and' and if it has one use, and if any of the bits we
379 // are flipping are known to be set, then the xor is just resetting those
380 // bits to zero. We can just knock out bits from the 'and' and the 'xor',
381 // simplifying both of them.
382 if (Instruction *LHSInst = dyn_cast<Instruction>(I->getOperand(0)))
383 if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
384 isa<ConstantInt>(I->getOperand(1)) &&
385 isa<ConstantInt>(LHSInst->getOperand(1)) &&
386 (LHSKnownOne & RHSKnownOne & DemandedMask) != 0) {
387 ConstantInt *AndRHS = cast<ConstantInt>(LHSInst->getOperand(1));
388 ConstantInt *XorRHS = cast<ConstantInt>(I->getOperand(1));
389 APInt NewMask = ~(LHSKnownOne & RHSKnownOne & DemandedMask);
392 ConstantInt::get(I->getType(), NewMask & AndRHS->getValue());
393 Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
394 InsertNewInstWith(NewAnd, *I);
397 ConstantInt::get(I->getType(), NewMask & XorRHS->getValue());
398 Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC);
399 return InsertNewInstWith(NewXor, *I);
402 // Output known-0 bits are known if clear or set in both the LHS & RHS.
403 KnownZero= (RHSKnownZero & LHSKnownZero) | (RHSKnownOne & LHSKnownOne);
404 // Output known-1 are known to be set if set in only one of the LHS, RHS.
405 KnownOne = (RHSKnownZero & LHSKnownOne) | (RHSKnownOne & LHSKnownZero);
408 case Instruction::Select:
409 // If this is a select as part of a min/max pattern, don't simplify any
410 // further in case we break the structure.
412 if (matchSelectPattern(I, LHS, RHS).Flavor != SPF_UNKNOWN)
415 if (SimplifyDemandedBits(I->getOperandUse(2), DemandedMask, RHSKnownZero,
416 RHSKnownOne, Depth + 1) ||
417 SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, LHSKnownZero,
418 LHSKnownOne, Depth + 1))
420 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
421 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
423 // If the operands are constants, see if we can simplify them.
424 if (ShrinkDemandedConstant(I, 1, DemandedMask) ||
425 ShrinkDemandedConstant(I, 2, DemandedMask))
428 // Only known if known in both the LHS and RHS.
429 KnownOne = RHSKnownOne & LHSKnownOne;
430 KnownZero = RHSKnownZero & LHSKnownZero;
432 case Instruction::Trunc: {
433 unsigned truncBf = I->getOperand(0)->getType()->getScalarSizeInBits();
434 DemandedMask = DemandedMask.zext(truncBf);
435 KnownZero = KnownZero.zext(truncBf);
436 KnownOne = KnownOne.zext(truncBf);
437 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, KnownZero,
438 KnownOne, Depth + 1))
440 DemandedMask = DemandedMask.trunc(BitWidth);
441 KnownZero = KnownZero.trunc(BitWidth);
442 KnownOne = KnownOne.trunc(BitWidth);
443 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
446 case Instruction::BitCast:
447 if (!I->getOperand(0)->getType()->isIntOrIntVectorTy())
448 return nullptr; // vector->int or fp->int?
450 if (VectorType *DstVTy = dyn_cast<VectorType>(I->getType())) {
451 if (VectorType *SrcVTy =
452 dyn_cast<VectorType>(I->getOperand(0)->getType())) {
453 if (DstVTy->getNumElements() != SrcVTy->getNumElements())
454 // Don't touch a bitcast between vectors of different element counts.
457 // Don't touch a scalar-to-vector bitcast.
459 } else if (I->getOperand(0)->getType()->isVectorTy())
460 // Don't touch a vector-to-scalar bitcast.
463 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, KnownZero,
464 KnownOne, Depth + 1))
466 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
468 case Instruction::ZExt: {
469 // Compute the bits in the result that are not present in the input.
470 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits();
472 DemandedMask = DemandedMask.trunc(SrcBitWidth);
473 KnownZero = KnownZero.trunc(SrcBitWidth);
474 KnownOne = KnownOne.trunc(SrcBitWidth);
475 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, KnownZero,
476 KnownOne, Depth + 1))
478 DemandedMask = DemandedMask.zext(BitWidth);
479 KnownZero = KnownZero.zext(BitWidth);
480 KnownOne = KnownOne.zext(BitWidth);
481 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
482 // The top bits are known to be zero.
483 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth);
486 case Instruction::SExt: {
487 // Compute the bits in the result that are not present in the input.
488 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits();
490 APInt InputDemandedBits = DemandedMask &
491 APInt::getLowBitsSet(BitWidth, SrcBitWidth);
493 APInt NewBits(APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth));
494 // If any of the sign extended bits are demanded, we know that the sign
496 if ((NewBits & DemandedMask) != 0)
497 InputDemandedBits.setBit(SrcBitWidth-1);
499 InputDemandedBits = InputDemandedBits.trunc(SrcBitWidth);
500 KnownZero = KnownZero.trunc(SrcBitWidth);
501 KnownOne = KnownOne.trunc(SrcBitWidth);
502 if (SimplifyDemandedBits(I->getOperandUse(0), InputDemandedBits, KnownZero,
503 KnownOne, Depth + 1))
505 InputDemandedBits = InputDemandedBits.zext(BitWidth);
506 KnownZero = KnownZero.zext(BitWidth);
507 KnownOne = KnownOne.zext(BitWidth);
508 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
510 // If the sign bit of the input is known set or clear, then we know the
511 // top bits of the result.
513 // If the input sign bit is known zero, or if the NewBits are not demanded
514 // convert this into a zero extension.
515 if (KnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) {
516 // Convert to ZExt cast
517 CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
518 return InsertNewInstWith(NewCast, *I);
519 } else if (KnownOne[SrcBitWidth-1]) { // Input sign bit known set
524 case Instruction::Add:
525 case Instruction::Sub: {
526 /// If the high-bits of an ADD/SUB are not demanded, then we do not care
527 /// about the high bits of the operands.
528 unsigned NLZ = DemandedMask.countLeadingZeros();
530 // Right fill the mask of bits for this ADD/SUB to demand the most
531 // significant bit and all those below it.
532 APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ));
533 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps,
534 LHSKnownZero, LHSKnownOne, Depth + 1) ||
535 ShrinkDemandedConstant(I, 1, DemandedFromOps) ||
536 SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps,
537 LHSKnownZero, LHSKnownOne, Depth + 1)) {
538 // Disable the nsw and nuw flags here: We can no longer guarantee that
539 // we won't wrap after simplification. Removing the nsw/nuw flags is
540 // legal here because the top bit is not demanded.
541 BinaryOperator &BinOP = *cast<BinaryOperator>(I);
542 BinOP.setHasNoSignedWrap(false);
543 BinOP.setHasNoUnsignedWrap(false);
548 // Otherwise just hand the add/sub off to computeKnownBits to fill in
549 // the known zeros and ones.
550 computeKnownBits(V, KnownZero, KnownOne, Depth, CxtI);
553 case Instruction::Shl:
554 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
556 Value *VarX; ConstantInt *C1;
557 if (match(I->getOperand(0), m_Shr(m_Value(VarX), m_ConstantInt(C1)))) {
558 Instruction *Shr = cast<Instruction>(I->getOperand(0));
559 Value *R = SimplifyShrShlDemandedBits(Shr, I, DemandedMask,
560 KnownZero, KnownOne);
566 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
567 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
569 // If the shift is NUW/NSW, then it does demand the high bits.
570 ShlOperator *IOp = cast<ShlOperator>(I);
571 if (IOp->hasNoSignedWrap())
572 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
573 else if (IOp->hasNoUnsignedWrap())
574 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
576 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, KnownZero,
577 KnownOne, Depth + 1))
579 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
580 KnownZero <<= ShiftAmt;
581 KnownOne <<= ShiftAmt;
582 // low bits known zero.
584 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
587 case Instruction::LShr:
588 // For a logical shift right
589 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
590 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
592 // Unsigned shift right.
593 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
595 // If the shift is exact, then it does demand the low bits (and knows that
597 if (cast<LShrOperator>(I)->isExact())
598 DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
600 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, KnownZero,
601 KnownOne, Depth + 1))
603 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
604 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
605 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
607 // Compute the new bits that are at the top now.
608 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
609 KnownZero |= HighBits; // high bits known zero.
613 case Instruction::AShr:
614 // If this is an arithmetic shift right and only the low-bit is set, we can
615 // always convert this into a logical shr, even if the shift amount is
616 // variable. The low bit of the shift cannot be an input sign bit unless
617 // the shift amount is >= the size of the datatype, which is undefined.
618 if (DemandedMask == 1) {
619 // Perform the logical shift right.
620 Instruction *NewVal = BinaryOperator::CreateLShr(
621 I->getOperand(0), I->getOperand(1), I->getName());
622 return InsertNewInstWith(NewVal, *I);
625 // If the sign bit is the only bit demanded by this ashr, then there is no
626 // need to do it, the shift doesn't change the high bit.
627 if (DemandedMask.isSignBit())
628 return I->getOperand(0);
630 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
631 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
633 // Signed shift right.
634 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
635 // If any of the "high bits" are demanded, we should set the sign bit as
637 if (DemandedMask.countLeadingZeros() <= ShiftAmt)
638 DemandedMaskIn.setBit(BitWidth-1);
640 // If the shift is exact, then it does demand the low bits (and knows that
642 if (cast<AShrOperator>(I)->isExact())
643 DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
645 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, KnownZero,
646 KnownOne, Depth + 1))
648 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
649 // Compute the new bits that are at the top now.
650 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
651 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
652 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
654 // Handle the sign bits.
655 APInt SignBit(APInt::getSignBit(BitWidth));
656 // Adjust to where it is now in the mask.
657 SignBit = APIntOps::lshr(SignBit, ShiftAmt);
659 // If the input sign bit is known to be zero, or if none of the top bits
660 // are demanded, turn this into an unsigned shift right.
661 if (BitWidth <= ShiftAmt || KnownZero[BitWidth-ShiftAmt-1] ||
662 (HighBits & ~DemandedMask) == HighBits) {
663 // Perform the logical shift right.
664 BinaryOperator *NewVal = BinaryOperator::CreateLShr(I->getOperand(0),
666 NewVal->setIsExact(cast<BinaryOperator>(I)->isExact());
667 return InsertNewInstWith(NewVal, *I);
668 } else if ((KnownOne & SignBit) != 0) { // New bits are known one.
669 KnownOne |= HighBits;
673 case Instruction::SRem:
674 if (ConstantInt *Rem = dyn_cast<ConstantInt>(I->getOperand(1))) {
675 // X % -1 demands all the bits because we don't want to introduce
676 // INT_MIN % -1 (== undef) by accident.
677 if (Rem->isAllOnesValue())
679 APInt RA = Rem->getValue().abs();
680 if (RA.isPowerOf2()) {
681 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
682 return I->getOperand(0);
684 APInt LowBits = RA - 1;
685 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
686 if (SimplifyDemandedBits(I->getOperandUse(0), Mask2, LHSKnownZero,
687 LHSKnownOne, Depth + 1))
690 // The low bits of LHS are unchanged by the srem.
691 KnownZero = LHSKnownZero & LowBits;
692 KnownOne = LHSKnownOne & LowBits;
694 // If LHS is non-negative or has all low bits zero, then the upper bits
696 if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits))
697 KnownZero |= ~LowBits;
699 // If LHS is negative and not all low bits are zero, then the upper bits
701 if (LHSKnownOne[BitWidth-1] && ((LHSKnownOne & LowBits) != 0))
702 KnownOne |= ~LowBits;
704 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
708 // The sign bit is the LHS's sign bit, except when the result of the
709 // remainder is zero.
710 if (DemandedMask.isNegative() && KnownZero.isNonNegative()) {
711 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
712 computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth + 1,
714 // If it's known zero, our sign bit is also zero.
715 if (LHSKnownZero.isNegative())
716 KnownZero.setBit(KnownZero.getBitWidth() - 1);
719 case Instruction::URem: {
720 APInt KnownZero2(BitWidth, 0), KnownOne2(BitWidth, 0);
721 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
722 if (SimplifyDemandedBits(I->getOperandUse(0), AllOnes, KnownZero2,
723 KnownOne2, Depth + 1) ||
724 SimplifyDemandedBits(I->getOperandUse(1), AllOnes, KnownZero2,
725 KnownOne2, Depth + 1))
728 unsigned Leaders = KnownZero2.countLeadingOnes();
729 Leaders = std::max(Leaders,
730 KnownZero2.countLeadingOnes());
731 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask;
734 case Instruction::Call:
735 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
736 switch (II->getIntrinsicID()) {
738 case Intrinsic::bswap: {
739 // If the only bits demanded come from one byte of the bswap result,
740 // just shift the input byte into position to eliminate the bswap.
741 unsigned NLZ = DemandedMask.countLeadingZeros();
742 unsigned NTZ = DemandedMask.countTrailingZeros();
744 // Round NTZ down to the next byte. If we have 11 trailing zeros, then
745 // we need all the bits down to bit 8. Likewise, round NLZ. If we
746 // have 14 leading zeros, round to 8.
749 // If we need exactly one byte, we can do this transformation.
750 if (BitWidth-NLZ-NTZ == 8) {
751 unsigned ResultBit = NTZ;
752 unsigned InputBit = BitWidth-NTZ-8;
754 // Replace this with either a left or right shift to get the byte into
757 if (InputBit > ResultBit)
758 NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0),
759 ConstantInt::get(I->getType(), InputBit-ResultBit));
761 NewVal = BinaryOperator::CreateShl(II->getArgOperand(0),
762 ConstantInt::get(I->getType(), ResultBit-InputBit));
764 return InsertNewInstWith(NewVal, *I);
767 // TODO: Could compute known zero/one bits based on the input.
770 case Intrinsic::x86_mmx_pmovmskb:
771 case Intrinsic::x86_sse_movmsk_ps:
772 case Intrinsic::x86_sse2_movmsk_pd:
773 case Intrinsic::x86_sse2_pmovmskb_128:
774 case Intrinsic::x86_avx_movmsk_ps_256:
775 case Intrinsic::x86_avx_movmsk_pd_256:
776 case Intrinsic::x86_avx2_pmovmskb: {
777 // MOVMSK copies the vector elements' sign bits to the low bits
778 // and zeros the high bits.
780 if (II->getIntrinsicID() == Intrinsic::x86_mmx_pmovmskb) {
781 ArgWidth = 8; // Arg is x86_mmx, but treated as <8 x i8>.
783 auto Arg = II->getArgOperand(0);
784 auto ArgType = cast<VectorType>(Arg->getType());
785 ArgWidth = ArgType->getNumElements();
788 // If we don't need any of low bits then return zero,
789 // we know that DemandedMask is non-zero already.
790 APInt DemandedElts = DemandedMask.zextOrTrunc(ArgWidth);
791 if (DemandedElts == 0)
792 return ConstantInt::getNullValue(VTy);
794 // We know that the upper bits are set to zero.
795 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - ArgWidth);
798 case Intrinsic::x86_sse42_crc32_64_64:
799 KnownZero = APInt::getHighBitsSet(64, 32);
803 computeKnownBits(V, KnownZero, KnownOne, Depth, CxtI);
807 // If the client is only demanding bits that we know, return the known
809 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
810 return Constant::getIntegerValue(VTy, KnownOne);
814 /// Helper routine of SimplifyDemandedUseBits. It tries to simplify
815 /// "E1 = (X lsr C1) << C2", where the C1 and C2 are constant, into
816 /// "E2 = X << (C2 - C1)" or "E2 = X >> (C1 - C2)", depending on the sign
819 /// Suppose E1 and E2 are generally different in bits S={bm, bm+1,
820 /// ..., bn}, without considering the specific value X is holding.
821 /// This transformation is legal iff one of following conditions is hold:
822 /// 1) All the bit in S are 0, in this case E1 == E2.
823 /// 2) We don't care those bits in S, per the input DemandedMask.
824 /// 3) Combination of 1) and 2). Some bits in S are 0, and we don't care the
827 /// Currently we only test condition 2).
829 /// As with SimplifyDemandedUseBits, it returns NULL if the simplification was
831 Value *InstCombiner::SimplifyShrShlDemandedBits(Instruction *Shr,
833 const APInt &DemandedMask,
837 const APInt &ShlOp1 = cast<ConstantInt>(Shl->getOperand(1))->getValue();
838 const APInt &ShrOp1 = cast<ConstantInt>(Shr->getOperand(1))->getValue();
839 if (!ShlOp1 || !ShrOp1)
840 return nullptr; // Noop.
842 Value *VarX = Shr->getOperand(0);
843 Type *Ty = VarX->getType();
844 unsigned BitWidth = Ty->getIntegerBitWidth();
845 if (ShlOp1.uge(BitWidth) || ShrOp1.uge(BitWidth))
846 return nullptr; // Undef.
848 unsigned ShlAmt = ShlOp1.getZExtValue();
849 unsigned ShrAmt = ShrOp1.getZExtValue();
851 KnownOne.clearAllBits();
852 KnownZero = APInt::getBitsSet(KnownZero.getBitWidth(), 0, ShlAmt-1);
853 KnownZero &= DemandedMask;
855 APInt BitMask1(APInt::getAllOnesValue(BitWidth));
856 APInt BitMask2(APInt::getAllOnesValue(BitWidth));
858 bool isLshr = (Shr->getOpcode() == Instruction::LShr);
859 BitMask1 = isLshr ? (BitMask1.lshr(ShrAmt) << ShlAmt) :
860 (BitMask1.ashr(ShrAmt) << ShlAmt);
862 if (ShrAmt <= ShlAmt) {
863 BitMask2 <<= (ShlAmt - ShrAmt);
865 BitMask2 = isLshr ? BitMask2.lshr(ShrAmt - ShlAmt):
866 BitMask2.ashr(ShrAmt - ShlAmt);
869 // Check if condition-2 (see the comment to this function) is satified.
870 if ((BitMask1 & DemandedMask) == (BitMask2 & DemandedMask)) {
871 if (ShrAmt == ShlAmt)
874 if (!Shr->hasOneUse())
878 if (ShrAmt < ShlAmt) {
879 Constant *Amt = ConstantInt::get(VarX->getType(), ShlAmt - ShrAmt);
880 New = BinaryOperator::CreateShl(VarX, Amt);
881 BinaryOperator *Orig = cast<BinaryOperator>(Shl);
882 New->setHasNoSignedWrap(Orig->hasNoSignedWrap());
883 New->setHasNoUnsignedWrap(Orig->hasNoUnsignedWrap());
885 Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
886 New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
887 BinaryOperator::CreateAShr(VarX, Amt);
888 if (cast<BinaryOperator>(Shr)->isExact())
889 New->setIsExact(true);
892 return InsertNewInstWith(New, *Shl);
898 /// The specified value produces a vector with any number of elements.
899 /// DemandedElts contains the set of elements that are actually used by the
900 /// caller. This method analyzes which elements of the operand are undef and
901 /// returns that information in UndefElts.
903 /// If the information about demanded elements can be used to simplify the
904 /// operation, the operation is simplified, then the resultant value is
905 /// returned. This returns null if no change was made.
906 Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
909 unsigned VWidth = V->getType()->getVectorNumElements();
910 APInt EltMask(APInt::getAllOnesValue(VWidth));
911 assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!");
913 if (isa<UndefValue>(V)) {
914 // If the entire vector is undefined, just return this info.
919 if (DemandedElts == 0) { // If nothing is demanded, provide undef.
921 return UndefValue::get(V->getType());
926 // Handle ConstantAggregateZero, ConstantVector, ConstantDataSequential.
927 if (Constant *C = dyn_cast<Constant>(V)) {
928 // Check if this is identity. If so, return 0 since we are not simplifying
930 if (DemandedElts.isAllOnesValue())
933 Type *EltTy = cast<VectorType>(V->getType())->getElementType();
934 Constant *Undef = UndefValue::get(EltTy);
936 SmallVector<Constant*, 16> Elts;
937 for (unsigned i = 0; i != VWidth; ++i) {
938 if (!DemandedElts[i]) { // If not demanded, set to undef.
939 Elts.push_back(Undef);
944 Constant *Elt = C->getAggregateElement(i);
945 if (!Elt) return nullptr;
947 if (isa<UndefValue>(Elt)) { // Already undef.
948 Elts.push_back(Undef);
950 } else { // Otherwise, defined.
955 // If we changed the constant, return it.
956 Constant *NewCV = ConstantVector::get(Elts);
957 return NewCV != C ? NewCV : nullptr;
960 // Limit search depth.
964 // If multiple users are using the root value, proceed with
965 // simplification conservatively assuming that all elements
967 if (!V->hasOneUse()) {
968 // Quit if we find multiple users of a non-root value though.
969 // They'll be handled when it's their turn to be visited by
970 // the main instcombine process.
972 // TODO: Just compute the UndefElts information recursively.
975 // Conservatively assume that all elements are needed.
976 DemandedElts = EltMask;
979 Instruction *I = dyn_cast<Instruction>(V);
980 if (!I) return nullptr; // Only analyze instructions.
982 bool MadeChange = false;
983 APInt UndefElts2(VWidth, 0);
984 APInt UndefElts3(VWidth, 0);
986 switch (I->getOpcode()) {
989 case Instruction::InsertElement: {
990 // If this is a variable index, we don't know which element it overwrites.
991 // demand exactly the same input as we produce.
992 ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2));
994 // Note that we can't propagate undef elt info, because we don't know
995 // which elt is getting updated.
996 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts,
997 UndefElts2, Depth + 1);
998 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1002 // If this is inserting an element that isn't demanded, remove this
1004 unsigned IdxNo = Idx->getZExtValue();
1005 if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
1007 return I->getOperand(0);
1010 // Otherwise, the element inserted overwrites whatever was there, so the
1011 // input demanded set is simpler than the output set.
1012 APInt DemandedElts2 = DemandedElts;
1013 DemandedElts2.clearBit(IdxNo);
1014 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts2,
1015 UndefElts, Depth + 1);
1016 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1018 // The inserted element is defined.
1019 UndefElts.clearBit(IdxNo);
1022 case Instruction::ShuffleVector: {
1023 ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1024 unsigned LHSVWidth =
1025 Shuffle->getOperand(0)->getType()->getVectorNumElements();
1026 APInt LeftDemanded(LHSVWidth, 0), RightDemanded(LHSVWidth, 0);
1027 for (unsigned i = 0; i < VWidth; i++) {
1028 if (DemandedElts[i]) {
1029 unsigned MaskVal = Shuffle->getMaskValue(i);
1030 if (MaskVal != -1u) {
1031 assert(MaskVal < LHSVWidth * 2 &&
1032 "shufflevector mask index out of range!");
1033 if (MaskVal < LHSVWidth)
1034 LeftDemanded.setBit(MaskVal);
1036 RightDemanded.setBit(MaskVal - LHSVWidth);
1041 APInt LHSUndefElts(LHSVWidth, 0);
1042 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), LeftDemanded,
1043 LHSUndefElts, Depth + 1);
1044 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1046 APInt RHSUndefElts(LHSVWidth, 0);
1047 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), RightDemanded,
1048 RHSUndefElts, Depth + 1);
1049 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
1051 bool NewUndefElts = false;
1052 unsigned LHSIdx = -1u, LHSValIdx = -1u;
1053 unsigned RHSIdx = -1u, RHSValIdx = -1u;
1054 bool LHSUniform = true;
1055 bool RHSUniform = true;
1056 for (unsigned i = 0; i < VWidth; i++) {
1057 unsigned MaskVal = Shuffle->getMaskValue(i);
1058 if (MaskVal == -1u) {
1059 UndefElts.setBit(i);
1060 } else if (!DemandedElts[i]) {
1061 NewUndefElts = true;
1062 UndefElts.setBit(i);
1063 } else if (MaskVal < LHSVWidth) {
1064 if (LHSUndefElts[MaskVal]) {
1065 NewUndefElts = true;
1066 UndefElts.setBit(i);
1068 LHSIdx = LHSIdx == -1u ? i : LHSVWidth;
1069 LHSValIdx = LHSValIdx == -1u ? MaskVal : LHSVWidth;
1070 LHSUniform = LHSUniform && (MaskVal == i);
1073 if (RHSUndefElts[MaskVal - LHSVWidth]) {
1074 NewUndefElts = true;
1075 UndefElts.setBit(i);
1077 RHSIdx = RHSIdx == -1u ? i : LHSVWidth;
1078 RHSValIdx = RHSValIdx == -1u ? MaskVal - LHSVWidth : LHSVWidth;
1079 RHSUniform = RHSUniform && (MaskVal - LHSVWidth == i);
1084 // Try to transform shuffle with constant vector and single element from
1085 // this constant vector to single insertelement instruction.
1086 // shufflevector V, C, <v1, v2, .., ci, .., vm> ->
1087 // insertelement V, C[ci], ci-n
1088 if (LHSVWidth == Shuffle->getType()->getNumElements()) {
1089 Value *Op = nullptr;
1090 Constant *Value = nullptr;
1093 // Find constant vector with the single element in shuffle (LHS or RHS).
1094 if (LHSIdx < LHSVWidth && RHSUniform) {
1095 if (auto *CV = dyn_cast<ConstantVector>(Shuffle->getOperand(0))) {
1096 Op = Shuffle->getOperand(1);
1097 Value = CV->getOperand(LHSValIdx);
1101 if (RHSIdx < LHSVWidth && LHSUniform) {
1102 if (auto *CV = dyn_cast<ConstantVector>(Shuffle->getOperand(1))) {
1103 Op = Shuffle->getOperand(0);
1104 Value = CV->getOperand(RHSValIdx);
1108 // Found constant vector with single element - convert to insertelement.
1110 Instruction *New = InsertElementInst::Create(
1111 Op, Value, ConstantInt::get(Type::getInt32Ty(I->getContext()), Idx),
1112 Shuffle->getName());
1113 InsertNewInstWith(New, *Shuffle);
1118 // Add additional discovered undefs.
1119 SmallVector<Constant*, 16> Elts;
1120 for (unsigned i = 0; i < VWidth; ++i) {
1122 Elts.push_back(UndefValue::get(Type::getInt32Ty(I->getContext())));
1124 Elts.push_back(ConstantInt::get(Type::getInt32Ty(I->getContext()),
1125 Shuffle->getMaskValue(i)));
1127 I->setOperand(2, ConstantVector::get(Elts));
1132 case Instruction::Select: {
1133 APInt LeftDemanded(DemandedElts), RightDemanded(DemandedElts);
1134 if (ConstantVector* CV = dyn_cast<ConstantVector>(I->getOperand(0))) {
1135 for (unsigned i = 0; i < VWidth; i++) {
1136 Constant *CElt = CV->getAggregateElement(i);
1137 // Method isNullValue always returns false when called on a
1138 // ConstantExpr. If CElt is a ConstantExpr then skip it in order to
1139 // to avoid propagating incorrect information.
1140 if (isa<ConstantExpr>(CElt))
1142 if (CElt->isNullValue())
1143 LeftDemanded.clearBit(i);
1145 RightDemanded.clearBit(i);
1149 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), LeftDemanded, UndefElts,
1151 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
1153 TmpV = SimplifyDemandedVectorElts(I->getOperand(2), RightDemanded,
1154 UndefElts2, Depth + 1);
1155 if (TmpV) { I->setOperand(2, TmpV); MadeChange = true; }
1157 // Output elements are undefined if both are undefined.
1158 UndefElts &= UndefElts2;
1161 case Instruction::BitCast: {
1162 // Vector->vector casts only.
1163 VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType());
1165 unsigned InVWidth = VTy->getNumElements();
1166 APInt InputDemandedElts(InVWidth, 0);
1167 UndefElts2 = APInt(InVWidth, 0);
1170 if (VWidth == InVWidth) {
1171 // If we are converting from <4 x i32> -> <4 x f32>, we demand the same
1172 // elements as are demanded of us.
1174 InputDemandedElts = DemandedElts;
1175 } else if ((VWidth % InVWidth) == 0) {
1176 // If the number of elements in the output is a multiple of the number of
1177 // elements in the input then an input element is live if any of the
1178 // corresponding output elements are live.
1179 Ratio = VWidth / InVWidth;
1180 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1181 if (DemandedElts[OutIdx])
1182 InputDemandedElts.setBit(OutIdx / Ratio);
1183 } else if ((InVWidth % VWidth) == 0) {
1184 // If the number of elements in the input is a multiple of the number of
1185 // elements in the output then an input element is live if the
1186 // corresponding output element is live.
1187 Ratio = InVWidth / VWidth;
1188 for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1189 if (DemandedElts[InIdx / Ratio])
1190 InputDemandedElts.setBit(InIdx);
1192 // Unsupported so far.
1196 // div/rem demand all inputs, because they don't want divide by zero.
1197 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), InputDemandedElts,
1198 UndefElts2, Depth + 1);
1200 I->setOperand(0, TmpV);
1204 if (VWidth == InVWidth) {
1205 UndefElts = UndefElts2;
1206 } else if ((VWidth % InVWidth) == 0) {
1207 // If the number of elements in the output is a multiple of the number of
1208 // elements in the input then an output element is undef if the
1209 // corresponding input element is undef.
1210 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1211 if (UndefElts2[OutIdx / Ratio])
1212 UndefElts.setBit(OutIdx);
1213 } else if ((InVWidth % VWidth) == 0) {
1214 // If the number of elements in the input is a multiple of the number of
1215 // elements in the output then an output element is undef if all of the
1216 // corresponding input elements are undef.
1217 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
1218 APInt SubUndef = UndefElts2.lshr(OutIdx * Ratio).zextOrTrunc(Ratio);
1219 if (SubUndef.countPopulation() == Ratio)
1220 UndefElts.setBit(OutIdx);
1223 llvm_unreachable("Unimp");
1227 case Instruction::And:
1228 case Instruction::Or:
1229 case Instruction::Xor:
1230 case Instruction::Add:
1231 case Instruction::Sub:
1232 case Instruction::Mul:
1233 // div/rem demand all inputs, because they don't want divide by zero.
1234 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, UndefElts,
1236 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1237 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), DemandedElts,
1238 UndefElts2, Depth + 1);
1239 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
1241 // Output elements are undefined if both are undefined. Consider things
1242 // like undef&0. The result is known zero, not undef.
1243 UndefElts &= UndefElts2;
1245 case Instruction::FPTrunc:
1246 case Instruction::FPExt:
1247 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, UndefElts,
1249 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1252 case Instruction::Call: {
1253 IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
1255 switch (II->getIntrinsicID()) {
1258 case Intrinsic::x86_xop_vfrcz_ss:
1259 case Intrinsic::x86_xop_vfrcz_sd:
1260 // The instructions for these intrinsics are speced to zero upper bits not
1261 // pass them through like other scalar intrinsics. So we shouldn't just
1262 // use Arg0 if DemandedElts[0] is clear like we do for other intrinsics.
1263 // Instead we should return a zero vector.
1264 if (!DemandedElts[0]) {
1266 return ConstantAggregateZero::get(II->getType());
1269 // Only the lower element is used.
1271 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1272 UndefElts, Depth + 1);
1273 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1275 // Only the lower element is undefined. The high elements are zero.
1276 UndefElts = UndefElts[0];
1279 // Unary scalar-as-vector operations that work column-wise.
1280 case Intrinsic::x86_sse_rcp_ss:
1281 case Intrinsic::x86_sse_rsqrt_ss:
1282 case Intrinsic::x86_sse_sqrt_ss:
1283 case Intrinsic::x86_sse2_sqrt_sd:
1284 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1285 UndefElts, Depth + 1);
1286 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1288 // If lowest element of a scalar op isn't used then use Arg0.
1289 if (!DemandedElts[0]) {
1291 return II->getArgOperand(0);
1293 // TODO: If only low elt lower SQRT to FSQRT (with rounding/exceptions
1297 // Binary scalar-as-vector operations that work column-wise. The high
1298 // elements come from operand 0. The low element is a function of both
1300 case Intrinsic::x86_sse_min_ss:
1301 case Intrinsic::x86_sse_max_ss:
1302 case Intrinsic::x86_sse_cmp_ss:
1303 case Intrinsic::x86_sse2_min_sd:
1304 case Intrinsic::x86_sse2_max_sd:
1305 case Intrinsic::x86_sse2_cmp_sd: {
1306 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1307 UndefElts, Depth + 1);
1308 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1310 // If lowest element of a scalar op isn't used then use Arg0.
1311 if (!DemandedElts[0]) {
1313 return II->getArgOperand(0);
1316 // Only lower element is used for operand 1.
1318 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
1319 UndefElts2, Depth + 1);
1320 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1322 // Lower element is undefined if both lower elements are undefined.
1323 // Consider things like undef&0. The result is known zero, not undef.
1325 UndefElts.clearBit(0);
1330 // Binary scalar-as-vector operations that work column-wise. The high
1331 // elements come from operand 0 and the low element comes from operand 1.
1332 case Intrinsic::x86_sse41_round_ss:
1333 case Intrinsic::x86_sse41_round_sd: {
1334 // Don't use the low element of operand 0.
1335 APInt DemandedElts2 = DemandedElts;
1336 DemandedElts2.clearBit(0);
1337 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts2,
1338 UndefElts, Depth + 1);
1339 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1341 // If lowest element of a scalar op isn't used then use Arg0.
1342 if (!DemandedElts[0]) {
1344 return II->getArgOperand(0);
1347 // Only lower element is used for operand 1.
1349 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
1350 UndefElts2, Depth + 1);
1351 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1353 // Take the high undef elements from operand 0 and take the lower element
1355 UndefElts.clearBit(0);
1356 UndefElts |= UndefElts2[0];
1360 // Three input scalar-as-vector operations that work column-wise. The high
1361 // elements come from operand 0 and the low element is a function of all
1363 case Intrinsic::x86_avx512_mask_add_ss_round:
1364 case Intrinsic::x86_avx512_mask_div_ss_round:
1365 case Intrinsic::x86_avx512_mask_mul_ss_round:
1366 case Intrinsic::x86_avx512_mask_sub_ss_round:
1367 case Intrinsic::x86_avx512_mask_max_ss_round:
1368 case Intrinsic::x86_avx512_mask_min_ss_round:
1369 case Intrinsic::x86_avx512_mask_add_sd_round:
1370 case Intrinsic::x86_avx512_mask_div_sd_round:
1371 case Intrinsic::x86_avx512_mask_mul_sd_round:
1372 case Intrinsic::x86_avx512_mask_sub_sd_round:
1373 case Intrinsic::x86_avx512_mask_max_sd_round:
1374 case Intrinsic::x86_avx512_mask_min_sd_round:
1375 case Intrinsic::x86_fma_vfmadd_ss:
1376 case Intrinsic::x86_fma_vfmsub_ss:
1377 case Intrinsic::x86_fma_vfnmadd_ss:
1378 case Intrinsic::x86_fma_vfnmsub_ss:
1379 case Intrinsic::x86_fma_vfmadd_sd:
1380 case Intrinsic::x86_fma_vfmsub_sd:
1381 case Intrinsic::x86_fma_vfnmadd_sd:
1382 case Intrinsic::x86_fma_vfnmsub_sd:
1383 case Intrinsic::x86_avx512_mask_vfmadd_ss:
1384 case Intrinsic::x86_avx512_mask_vfmadd_sd:
1385 case Intrinsic::x86_avx512_maskz_vfmadd_ss:
1386 case Intrinsic::x86_avx512_maskz_vfmadd_sd:
1387 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1388 UndefElts, Depth + 1);
1389 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1391 // If lowest element of a scalar op isn't used then use Arg0.
1392 if (!DemandedElts[0]) {
1394 return II->getArgOperand(0);
1397 // Only lower element is used for operand 1 and 2.
1399 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
1400 UndefElts2, Depth + 1);
1401 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1402 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(2), DemandedElts,
1403 UndefElts3, Depth + 1);
1404 if (TmpV) { II->setArgOperand(2, TmpV); MadeChange = true; }
1406 // Lower element is undefined if all three lower elements are undefined.
1407 // Consider things like undef&0. The result is known zero, not undef.
1408 if (!UndefElts2[0] || !UndefElts3[0])
1409 UndefElts.clearBit(0);
1413 case Intrinsic::x86_avx512_mask3_vfmadd_ss:
1414 case Intrinsic::x86_avx512_mask3_vfmadd_sd:
1415 case Intrinsic::x86_avx512_mask3_vfmsub_ss:
1416 case Intrinsic::x86_avx512_mask3_vfmsub_sd:
1417 case Intrinsic::x86_avx512_mask3_vfnmsub_ss:
1418 case Intrinsic::x86_avx512_mask3_vfnmsub_sd:
1419 // These intrinsics get the passthru bits from operand 2.
1420 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(2), DemandedElts,
1421 UndefElts, Depth + 1);
1422 if (TmpV) { II->setArgOperand(2, TmpV); MadeChange = true; }
1424 // If lowest element of a scalar op isn't used then use Arg2.
1425 if (!DemandedElts[0]) {
1427 return II->getArgOperand(2);
1430 // Only lower element is used for operand 0 and 1.
1432 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1433 UndefElts2, Depth + 1);
1434 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1435 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
1436 UndefElts3, Depth + 1);
1437 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1439 // Lower element is undefined if all three lower elements are undefined.
1440 // Consider things like undef&0. The result is known zero, not undef.
1441 if (!UndefElts2[0] || !UndefElts3[0])
1442 UndefElts.clearBit(0);
1446 case Intrinsic::x86_sse2_pmulu_dq:
1447 case Intrinsic::x86_sse41_pmuldq:
1448 case Intrinsic::x86_avx2_pmul_dq:
1449 case Intrinsic::x86_avx2_pmulu_dq:
1450 case Intrinsic::x86_avx512_pmul_dq_512:
1451 case Intrinsic::x86_avx512_pmulu_dq_512: {
1452 Value *Op0 = II->getArgOperand(0);
1453 Value *Op1 = II->getArgOperand(1);
1454 unsigned InnerVWidth = Op0->getType()->getVectorNumElements();
1455 assert((VWidth * 2) == InnerVWidth && "Unexpected input size");
1457 APInt InnerDemandedElts(InnerVWidth, 0);
1458 for (unsigned i = 0; i != VWidth; ++i)
1459 if (DemandedElts[i])
1460 InnerDemandedElts.setBit(i * 2);
1462 UndefElts2 = APInt(InnerVWidth, 0);
1463 TmpV = SimplifyDemandedVectorElts(Op0, InnerDemandedElts, UndefElts2,
1465 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1467 UndefElts3 = APInt(InnerVWidth, 0);
1468 TmpV = SimplifyDemandedVectorElts(Op1, InnerDemandedElts, UndefElts3,
1470 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1475 // SSE4A instructions leave the upper 64-bits of the 128-bit result
1476 // in an undefined state.
1477 case Intrinsic::x86_sse4a_extrq:
1478 case Intrinsic::x86_sse4a_extrqi:
1479 case Intrinsic::x86_sse4a_insertq:
1480 case Intrinsic::x86_sse4a_insertqi:
1481 UndefElts |= APInt::getHighBitsSet(VWidth, VWidth / 2);
1487 return MadeChange ? I : nullptr;