1 Pull in r198738 from upstream llvm trunk (by Venkatraman Govindaraju):
3 [Sparc] Add support for parsing branch instructions and conditional moves.
5 Introduced here: http://svn.freebsd.org/changeset/base/262261
7 Index: test/MC/Disassembler/Sparc/sparc.txt
8 ===================================================================
9 --- test/MC/Disassembler/Sparc/sparc.txt
10 +++ test/MC/Disassembler/Sparc/sparc.txt
13 # CHECK: subxcc %g1, %g2, %g3
40 +# CHECK: bleu 4194303
49 +# CHECK: bpos 4194303
52 +# CHECK: bneg 4194303
67 +# CHECK: fbug 4194303
73 +# CHECK: fbul 4194303
76 +# CHECK: fblg 4194303
79 +# CHECK: fbne 4194303
85 +# CHECK: fbue 4194303
88 +# CHECK: fbge 4194303
91 +# CHECK: fbuge 4194303
94 +# CHECK: fble 4194303
97 +# CHECK: fbule 4194303
100 +# CHECK: fbo 4194303
102 Index: test/MC/Sparc/sparc-ctrl-instructions.s
103 ===================================================================
104 --- test/MC/Sparc/sparc-ctrl-instructions.s
105 +++ test/MC/Sparc/sparc-ctrl-instructions.s
107 ! CHECK-NEXT: ! fixup A - offset: 0, value: %lo(sym), kind: fixup_sparc_lo10
110 + ! CHECK: ba .BB0 ! encoding: [0x10,0b10AAAAAA,A,A]
111 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
114 + ! CHECK: bne .BB0 ! encoding: [0x12,0b10AAAAAA,A,A]
115 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
118 + ! CHECK: be .BB0 ! encoding: [0x02,0b10AAAAAA,A,A]
119 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
122 + ! CHECK: bg .BB0 ! encoding: [0x14,0b10AAAAAA,A,A]
123 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
126 + ! CHECK: ble .BB0 ! encoding: [0x04,0b10AAAAAA,A,A]
127 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
130 + ! CHECK: bge .BB0 ! encoding: [0x16,0b10AAAAAA,A,A]
131 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
134 + ! CHECK: bl .BB0 ! encoding: [0x06,0b10AAAAAA,A,A]
135 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
138 + ! CHECK: bgu .BB0 ! encoding: [0x18,0b10AAAAAA,A,A]
139 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
142 + ! CHECK: bleu .BB0 ! encoding: [0x08,0b10AAAAAA,A,A]
143 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
146 + ! CHECK: bcc .BB0 ! encoding: [0x1a,0b10AAAAAA,A,A]
147 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
150 + ! CHECK: bcs .BB0 ! encoding: [0x0a,0b10AAAAAA,A,A]
151 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
154 + ! CHECK: bpos .BB0 ! encoding: [0x1c,0b10AAAAAA,A,A]
155 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
158 + ! CHECK: bneg .BB0 ! encoding: [0x0c,0b10AAAAAA,A,A]
159 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
162 + ! CHECK: bvc .BB0 ! encoding: [0x1e,0b10AAAAAA,A,A]
163 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
166 + ! CHECK: bvs .BB0 ! encoding: [0x0e,0b10AAAAAA,A,A]
167 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
170 + ! CHECK: fbu .BB0 ! encoding: [0x0f,0b10AAAAAA,A,A]
171 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
174 + ! CHECK: fbg .BB0 ! encoding: [0x0d,0b10AAAAAA,A,A]
175 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
177 + ! CHECK: fbug .BB0 ! encoding: [0x0b,0b10AAAAAA,A,A]
178 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
181 + ! CHECK: fbl .BB0 ! encoding: [0x09,0b10AAAAAA,A,A]
182 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
185 + ! CHECK: fbul .BB0 ! encoding: [0x07,0b10AAAAAA,A,A]
186 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
189 + ! CHECK: fblg .BB0 ! encoding: [0x05,0b10AAAAAA,A,A]
190 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
193 + ! CHECK: fbne .BB0 ! encoding: [0x03,0b10AAAAAA,A,A]
194 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
197 + ! CHECK: fbe .BB0 ! encoding: [0x13,0b10AAAAAA,A,A]
198 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
201 + ! CHECK: fbue .BB0 ! encoding: [0x15,0b10AAAAAA,A,A]
202 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
205 + ! CHECK: fbge .BB0 ! encoding: [0x17,0b10AAAAAA,A,A]
206 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
209 + ! CHECK: fbuge .BB0 ! encoding: [0x19,0b10AAAAAA,A,A]
210 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
213 + ! CHECK: fble .BB0 ! encoding: [0x1b,0b10AAAAAA,A,A]
214 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
217 + ! CHECK: fbule .BB0 ! encoding: [0x1d,0b10AAAAAA,A,A]
218 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
221 + ! CHECK: fbo .BB0 ! encoding: [0x1f,0b10AAAAAA,A,A]
222 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
224 Index: test/MC/Sparc/sparc64-ctrl-instructions.s
225 ===================================================================
226 --- test/MC/Sparc/sparc64-ctrl-instructions.s
227 +++ test/MC/Sparc/sparc64-ctrl-instructions.s
229 +! RUN: llvm-mc %s -triple=sparc64-unknown-linux-gnu -show-encoding | FileCheck %s
232 + ! CHECK: bne %xcc, .BB0 ! encoding: [0x12,0b01101AAA,A,A]
233 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
236 + ! CHECK: be %xcc, .BB0 ! encoding: [0x02,0b01101AAA,A,A]
237 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
240 + ! CHECK: bg %xcc, .BB0 ! encoding: [0x14,0b01101AAA,A,A]
241 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
244 + ! CHECK: ble %xcc, .BB0 ! encoding: [0x04,0b01101AAA,A,A]
245 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
248 + ! CHECK: bge %xcc, .BB0 ! encoding: [0x16,0b01101AAA,A,A]
249 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
252 + ! CHECK: bl %xcc, .BB0 ! encoding: [0x06,0b01101AAA,A,A]
253 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
256 + ! CHECK: bgu %xcc, .BB0 ! encoding: [0x18,0b01101AAA,A,A]
257 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
260 + ! CHECK: bleu %xcc, .BB0 ! encoding: [0x08,0b01101AAA,A,A]
261 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
264 + ! CHECK: bcc %xcc, .BB0 ! encoding: [0x1a,0b01101AAA,A,A]
265 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
268 + ! CHECK: bcs %xcc, .BB0 ! encoding: [0x0a,0b01101AAA,A,A]
269 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
272 + ! CHECK: bpos %xcc, .BB0 ! encoding: [0x1c,0b01101AAA,A,A]
273 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
276 + ! CHECK: bneg %xcc, .BB0 ! encoding: [0x0c,0b01101AAA,A,A]
277 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
280 + ! CHECK: bvc %xcc, .BB0 ! encoding: [0x1e,0b01101AAA,A,A]
281 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
284 + ! CHECK: bvs %xcc, .BB0 ! encoding: [0x0e,0b01101AAA,A,A]
285 + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
289 + ! CHECK: movne %icc, %g1, %g2 ! encoding: [0x85,0x66,0x40,0x01]
290 + ! CHECK: move %icc, %g1, %g2 ! encoding: [0x85,0x64,0x40,0x01]
291 + ! CHECK: movg %icc, %g1, %g2 ! encoding: [0x85,0x66,0x80,0x01]
292 + ! CHECK: movle %icc, %g1, %g2 ! encoding: [0x85,0x64,0x80,0x01]
293 + ! CHECK: movge %icc, %g1, %g2 ! encoding: [0x85,0x66,0xc0,0x01]
294 + ! CHECK: movl %icc, %g1, %g2 ! encoding: [0x85,0x64,0xc0,0x01]
295 + ! CHECK: movgu %icc, %g1, %g2 ! encoding: [0x85,0x67,0x00,0x01]
296 + ! CHECK: movleu %icc, %g1, %g2 ! encoding: [0x85,0x65,0x00,0x01]
297 + ! CHECK: movcc %icc, %g1, %g2 ! encoding: [0x85,0x67,0x40,0x01]
298 + ! CHECK: movcs %icc, %g1, %g2 ! encoding: [0x85,0x65,0x40,0x01]
299 + ! CHECK: movpos %icc, %g1, %g2 ! encoding: [0x85,0x67,0x80,0x01]
300 + ! CHECK: movneg %icc, %g1, %g2 ! encoding: [0x85,0x65,0x80,0x01]
301 + ! CHECK: movvc %icc, %g1, %g2 ! encoding: [0x85,0x67,0xc0,0x01]
302 + ! CHECK: movvs %icc, %g1, %g2 ! encoding: [0x85,0x65,0xc0,0x01]
303 + movne %icc, %g1, %g2
304 + move %icc, %g1, %g2
305 + movg %icc, %g1, %g2
306 + movle %icc, %g1, %g2
307 + movge %icc, %g1, %g2
308 + movl %icc, %g1, %g2
309 + movgu %icc, %g1, %g2
310 + movleu %icc, %g1, %g2
311 + movcc %icc, %g1, %g2
312 + movcs %icc, %g1, %g2
313 + movpos %icc, %g1, %g2
314 + movneg %icc, %g1, %g2
315 + movvc %icc, %g1, %g2
316 + movvs %icc, %g1, %g2
318 + ! CHECK: movne %xcc, %g1, %g2 ! encoding: [0x85,0x66,0x50,0x01]
319 + ! CHECK: move %xcc, %g1, %g2 ! encoding: [0x85,0x64,0x50,0x01]
320 + ! CHECK: movg %xcc, %g1, %g2 ! encoding: [0x85,0x66,0x90,0x01]
321 + ! CHECK: movle %xcc, %g1, %g2 ! encoding: [0x85,0x64,0x90,0x01]
322 + ! CHECK: movge %xcc, %g1, %g2 ! encoding: [0x85,0x66,0xd0,0x01]
323 + ! CHECK: movl %xcc, %g1, %g2 ! encoding: [0x85,0x64,0xd0,0x01]
324 + ! CHECK: movgu %xcc, %g1, %g2 ! encoding: [0x85,0x67,0x10,0x01]
325 + ! CHECK: movleu %xcc, %g1, %g2 ! encoding: [0x85,0x65,0x10,0x01]
326 + ! CHECK: movcc %xcc, %g1, %g2 ! encoding: [0x85,0x67,0x50,0x01]
327 + ! CHECK: movcs %xcc, %g1, %g2 ! encoding: [0x85,0x65,0x50,0x01]
328 + ! CHECK: movpos %xcc, %g1, %g2 ! encoding: [0x85,0x67,0x90,0x01]
329 + ! CHECK: movneg %xcc, %g1, %g2 ! encoding: [0x85,0x65,0x90,0x01]
330 + ! CHECK: movvc %xcc, %g1, %g2 ! encoding: [0x85,0x67,0xd0,0x01]
331 + ! CHECK: movvs %xcc, %g1, %g2 ! encoding: [0x85,0x65,0xd0,0x01]
332 + movne %xcc, %g1, %g2
333 + move %xcc, %g1, %g2
334 + movg %xcc, %g1, %g2
335 + movle %xcc, %g1, %g2
336 + movge %xcc, %g1, %g2
337 + movl %xcc, %g1, %g2
338 + movgu %xcc, %g1, %g2
339 + movleu %xcc, %g1, %g2
340 + movcc %xcc, %g1, %g2
341 + movcs %xcc, %g1, %g2
342 + movpos %xcc, %g1, %g2
343 + movneg %xcc, %g1, %g2
344 + movvc %xcc, %g1, %g2
345 + movvs %xcc, %g1, %g2
347 + ! CHECK: movu %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0xc0,0x01]
348 + ! CHECK: movg %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x80,0x01]
349 + ! CHECK: movug %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x40,0x01]
350 + ! CHECK: movl %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x00,0x01]
351 + ! CHECK: movul %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0xc0,0x01]
352 + ! CHECK: movlg %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0x80,0x01]
353 + ! CHECK: movne %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0x40,0x01]
354 + ! CHECK: move %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0x40,0x01]
355 + ! CHECK: movue %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0x80,0x01]
356 + ! CHECK: movge %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0xc0,0x01]
357 + ! CHECK: movuge %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0x00,0x01]
358 + ! CHECK: movle %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0x40,0x01]
359 + ! CHECK: movule %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0x80,0x01]
360 + ! CHECK: movo %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0xc0,0x01]
361 + movu %fcc0, %g1, %g2
362 + movg %fcc0, %g1, %g2
363 + movug %fcc0, %g1, %g2
364 + movl %fcc0, %g1, %g2
365 + movul %fcc0, %g1, %g2
366 + movlg %fcc0, %g1, %g2
367 + movne %fcc0, %g1, %g2
368 + move %fcc0, %g1, %g2
369 + movue %fcc0, %g1, %g2
370 + movge %fcc0, %g1, %g2
371 + movuge %fcc0, %g1, %g2
372 + movle %fcc0, %g1, %g2
373 + movule %fcc0, %g1, %g2
374 + movo %fcc0, %g1, %g2
377 + ! CHECK fmovsne %icc, %f1, %f2 ! encoding: [0x85,0xaa,0x60,0x21]
378 + ! CHECK fmovse %icc, %f1, %f2 ! encoding: [0x85,0xa8,0x60,0x21]
379 + ! CHECK fmovsg %icc, %f1, %f2 ! encoding: [0x85,0xaa,0xa0,0x21]
380 + ! CHECK fmovsle %icc, %f1, %f2 ! encoding: [0x85,0xa8,0xa0,0x21]
381 + ! CHECK fmovsge %icc, %f1, %f2 ! encoding: [0x85,0xaa,0xe0,0x21]
382 + ! CHECK fmovsl %icc, %f1, %f2 ! encoding: [0x85,0xa8,0xe0,0x21]
383 + ! CHECK fmovsgu %icc, %f1, %f2 ! encoding: [0x85,0xab,0x20,0x21]
384 + ! CHECK fmovsleu %icc, %f1, %f2 ! encoding: [0x85,0xa9,0x20,0x21]
385 + ! CHECK fmovscc %icc, %f1, %f2 ! encoding: [0x85,0xab,0x60,0x21]
386 + ! CHECK fmovscs %icc, %f1, %f2 ! encoding: [0x85,0xa9,0x60,0x21]
387 + ! CHECK fmovspos %icc, %f1, %f2 ! encoding: [0x85,0xab,0xa0,0x21]
388 + ! CHECK fmovsneg %icc, %f1, %f2 ! encoding: [0x85,0xa9,0xa0,0x21]
389 + ! CHECK fmovsvc %icc, %f1, %f2 ! encoding: [0x85,0xab,0xe0,0x21]
390 + ! CHECK fmovsvs %icc, %f1, %f2 ! encoding: [0x85,0xa9,0xe0,0x21]
391 + fmovsne %icc, %f1, %f2
392 + fmovse %icc, %f1, %f2
393 + fmovsg %icc, %f1, %f2
394 + fmovsle %icc, %f1, %f2
395 + fmovsge %icc, %f1, %f2
396 + fmovsl %icc, %f1, %f2
397 + fmovsgu %icc, %f1, %f2
398 + fmovsleu %icc, %f1, %f2
399 + fmovscc %icc, %f1, %f2
400 + fmovscs %icc, %f1, %f2
401 + fmovspos %icc, %f1, %f2
402 + fmovsneg %icc, %f1, %f2
403 + fmovsvc %icc, %f1, %f2
404 + fmovsvs %icc, %f1, %f2
406 + ! CHECK fmovsne %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0x70,0x21]
407 + ! CHECK fmovse %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0x70,0x21]
408 + ! CHECK fmovsg %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0xb0,0x21]
409 + ! CHECK fmovsle %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0xb0,0x21]
410 + ! CHECK fmovsge %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0xf0,0x21]
411 + ! CHECK fmovsl %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0xf0,0x21]
412 + ! CHECK fmovsgu %xcc, %f1, %f2 ! encoding: [0x85,0xab,0x30,0x21]
413 + ! CHECK fmovsleu %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0x30,0x21]
414 + ! CHECK fmovscc %xcc, %f1, %f2 ! encoding: [0x85,0xab,0x70,0x21]
415 + ! CHECK fmovscs %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0x70,0x21]
416 + ! CHECK fmovspos %xcc, %f1, %f2 ! encoding: [0x85,0xab,0xb0,0x21]
417 + ! CHECK fmovsneg %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0xb0,0x21]
418 + ! CHECK fmovsvc %xcc, %f1, %f2 ! encoding: [0x85,0xab,0xf0,0x21]
419 + ! CHECK fmovsvs %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0xf0,0x21]
420 + fmovsne %xcc, %f1, %f2
421 + fmovse %xcc, %f1, %f2
422 + fmovsg %xcc, %f1, %f2
423 + fmovsle %xcc, %f1, %f2
424 + fmovsge %xcc, %f1, %f2
425 + fmovsl %xcc, %f1, %f2
426 + fmovsgu %xcc, %f1, %f2
427 + fmovsleu %xcc, %f1, %f2
428 + fmovscc %xcc, %f1, %f2
429 + fmovscs %xcc, %f1, %f2
430 + fmovspos %xcc, %f1, %f2
431 + fmovsneg %xcc, %f1, %f2
432 + fmovsvc %xcc, %f1, %f2
433 + fmovsvs %xcc, %f1, %f2
435 + ! CHECK fmovsu %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0xc0,0x21]
436 + ! CHECK fmovsg %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x80,0x21]
437 + ! CHECK fmovsug %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x40,0x21]
438 + ! CHECK fmovsl %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x00,0x21]
439 + ! CHECK fmovsul %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0xc0,0x21]
440 + ! CHECK fmovslg %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0x80,0x21]
441 + ! CHECK fmovsne %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0x40,0x21]
442 + ! CHECK fmovse %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0x40,0x21]
443 + ! CHECK fmovsue %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0x80,0x21]
444 + ! CHECK fmovsge %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0xc0,0x21]
445 + ! CHECK fmovsuge %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x00,0x21]
446 + ! CHECK fmovsle %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x40,0x21]
447 + ! CHECK fmovsule %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x80,0x21]
448 + ! CHECK fmovso %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0xc0,0x21]
449 + fmovsu %fcc0, %f1, %f2
450 + fmovsg %fcc0, %f1, %f2
451 + fmovsug %fcc0, %f1, %f2
452 + fmovsl %fcc0, %f1, %f2
453 + fmovsul %fcc0, %f1, %f2
454 + fmovslg %fcc0, %f1, %f2
455 + fmovsne %fcc0, %f1, %f2
456 + fmovse %fcc0, %f1, %f2
457 + fmovsue %fcc0, %f1, %f2
458 + fmovsge %fcc0, %f1, %f2
459 + fmovsuge %fcc0, %f1, %f2
460 + fmovsle %fcc0, %f1, %f2
461 + fmovsule %fcc0, %f1, %f2
462 + fmovso %fcc0, %f1, %f2
464 Index: lib/Target/Sparc/SparcInstr64Bit.td
465 ===================================================================
466 --- lib/Target/Sparc/SparcInstr64Bit.td
467 +++ lib/Target/Sparc/SparcInstr64Bit.td
468 @@ -333,32 +333,42 @@ class XBranchSP<dag ins, string asmstr, list<dag>
469 let Predicates = [Is64Bit] in {
472 -def BPXCC : XBranchSP<(ins brtarget:$imm22, CCOp:$cond),
473 - "b$cond %xcc, $imm22",
474 - [(SPbrxcc bb:$imm22, imm:$cond)]>;
475 +def BPXCC : XBranchSP<(ins brtarget:$imm19, CCOp:$cond),
476 + "b$cond %xcc, $imm19",
477 + [(SPbrxcc bb:$imm19, imm:$cond)]>;
479 // Conditional moves on %xcc.
480 let Uses = [ICC], Constraints = "$f = $rd" in {
481 -def MOVXCCrr : Pseudo<(outs IntRegs:$rd),
483 +def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
484 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
485 "mov$cond %xcc, $rs2, $rd",
487 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>;
488 -def MOVXCCri : Pseudo<(outs IntRegs:$rd),
489 - (ins i32imm:$i, IntRegs:$f, CCOp:$cond),
490 - "mov$cond %xcc, $i, $rd",
491 +def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
492 + (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
493 + "mov$cond %xcc, $simm11, $rd",
495 - (SPselectxcc simm11:$i, i32:$f, imm:$cond))]>;
496 -def FMOVS_XCC : Pseudo<(outs FPRegs:$rd),
497 + (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>;
500 +let opf_cc = 0b110 in {
501 +def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
502 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
503 "fmovs$cond %xcc, $rs2, $rd",
505 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>;
506 -def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd),
507 +def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
508 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
509 "fmovd$cond %xcc, $rs2, $rd",
511 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
512 +def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
513 + (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
514 + "fmovq$cond %xcc, $rs2, $rd",
516 + (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>;
518 } // Uses, Constraints
520 //===----------------------------------------------------------------------===//
521 Index: lib/Target/Sparc/SparcInstrInfo.td
522 ===================================================================
523 --- lib/Target/Sparc/SparcInstrInfo.td
524 +++ lib/Target/Sparc/SparcInstrInfo.td
525 @@ -928,8 +928,9 @@ let Predicates = [HasV9], Constraints = "$f = $rd"
527 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
528 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
529 - "fmovd$cond %icc, $rs2, $rd",
530 - [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
531 + "fmovq$cond %icc, $rs2, $rd",
532 + [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
533 + Requires<[HasHardQuad]>;
536 let Uses = [FCC], opf_cc = 0b000 in {
537 @@ -946,8 +947,9 @@ let Predicates = [HasV9], Constraints = "$f = $rd"
539 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
540 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
541 - "fmovd$cond %fcc0, $rs2, $rd",
542 - [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
543 + "fmovq$cond %fcc0, $rs2, $rd",
544 + [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
545 + Requires<[HasHardQuad]>;
549 @@ -1092,3 +1094,4 @@ def : Pat<(atomic_store ADDRri:$dst, i32:$val), (S
552 include "SparcInstr64Bit.td"
553 +include "SparcInstrAliases.td"
554 Index: lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
555 ===================================================================
556 --- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
557 +++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
558 @@ -537,9 +537,29 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand
559 Parser.Lex(); // Eat the '%'.
561 if (matchRegisterName(Parser.getTok(), RegNo, false, false)) {
562 + StringRef name = Parser.getTok().getString();
563 Parser.Lex(); // Eat the identifier token.
564 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
565 - Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E);
568 + Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E);
571 + Op = SparcOperand::CreateToken("%y", S);
576 + Op = SparcOperand::CreateToken("%xcc", S);
578 + Op = SparcOperand::CreateToken("%icc", S);
582 + assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
583 + Op = SparcOperand::CreateToken("%fcc0", S);
588 if (matchSparcAsmModifiers(EVal, E)) {
589 Index: lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
590 ===================================================================
591 --- lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
592 +++ lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
593 @@ -83,6 +83,17 @@ void SparcInstPrinter::printCCOperand(const MCInst
596 int CC = (int)MI->getOperand(opNum).getImm();
597 + switch (MI->getOpcode()) {
602 + case SP::FMOVS_FCC:
603 + case SP::FMOVD_FCC:
604 + case SP::FMOVQ_FCC: // Make sure CC is a fp conditional flag.
605 + CC = (CC < 16) ? (CC + 16) : CC;
608 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
611 Index: lib/Target/Sparc/SparcInstrAliases.td
612 ===================================================================
613 --- lib/Target/Sparc/SparcInstrAliases.td
614 +++ lib/Target/Sparc/SparcInstrAliases.td
616 +//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
618 +// The LLVM Compiler Infrastructure
620 +// This file is distributed under the University of Illinois Open Source
621 +// License. See LICENSE.TXT for details.
623 +//===----------------------------------------------------------------------===//
625 +// This file contains instruction aliases for Sparc.
626 +//===----------------------------------------------------------------------===//
628 +// Instruction aliases for conditional moves.
630 +// mov<cond> <ccreg> rs2, rd
631 +multiclass cond_mov_alias<string cond, int condVal, string ccreg,
632 + Instruction movrr, Instruction movri,
633 + Instruction fmovs, Instruction fmovd> {
635 + // mov<cond> (%icc|%xcc|%fcc0), rs2, rd
636 + def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
638 + (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
640 + // mov<cond> (%icc|%xcc|%fcc0), simm11, rd
641 + def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
643 + (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
645 + // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd
646 + def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
648 + (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
650 + // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd
651 + def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
653 + (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
657 +// Instruction aliases for integer conditional branches and moves.
658 +multiclass int_cond_alias<string cond, int condVal> {
661 + def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
662 + (BCOND brtarget:$imm, condVal)>;
664 + // b<cond> %xcc, $imm
665 + def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
666 + (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
668 + defm : cond_mov_alias<cond, condVal, " %icc",
669 + MOVICCrr, MOVICCri,
670 + FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
672 + defm : cond_mov_alias<cond, condVal, " %xcc",
673 + MOVXCCrr, MOVXCCri,
674 + FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
676 + // fmovq<cond> (%icc|%xcc), $rs2, $rd
677 + def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
678 + (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
679 + Requires<[HasV9, HasHardQuad]>;
680 + def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
681 + (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
682 + Requires<[Is64Bit, HasHardQuad]>;
687 +// Instruction aliases for floating point conditional branches and moves.
688 +multiclass fp_cond_alias<string cond, int condVal> {
691 + def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
692 + (FBCOND brtarget:$imm, condVal), 0>;
694 + defm : cond_mov_alias<cond, condVal, " %fcc0",
695 + MOVFCCrr, MOVFCCri,
696 + FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>;
698 + // fmovq<cond> %fcc0, $rs2, $rd
699 + def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"),
700 + (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
701 + Requires<[HasV9, HasHardQuad]>;
704 +defm : int_cond_alias<"a", 0b1000>;
705 +defm : int_cond_alias<"n", 0b0000>;
706 +defm : int_cond_alias<"ne", 0b1001>;
707 +defm : int_cond_alias<"e", 0b0001>;
708 +defm : int_cond_alias<"g", 0b1010>;
709 +defm : int_cond_alias<"le", 0b0010>;
710 +defm : int_cond_alias<"ge", 0b1011>;
711 +defm : int_cond_alias<"l", 0b0011>;
712 +defm : int_cond_alias<"gu", 0b1100>;
713 +defm : int_cond_alias<"leu", 0b0100>;
714 +defm : int_cond_alias<"cc", 0b1101>;
715 +defm : int_cond_alias<"cs", 0b0101>;
716 +defm : int_cond_alias<"pos", 0b1110>;
717 +defm : int_cond_alias<"neg", 0b0110>;
718 +defm : int_cond_alias<"vc", 0b1111>;
719 +defm : int_cond_alias<"vs", 0b0111>;
721 +defm : fp_cond_alias<"u", 0b0111>;
722 +defm : fp_cond_alias<"g", 0b0110>;
723 +defm : fp_cond_alias<"ug", 0b0101>;
724 +defm : fp_cond_alias<"l", 0b0100>;
725 +defm : fp_cond_alias<"ul", 0b0011>;
726 +defm : fp_cond_alias<"lg", 0b0010>;
727 +defm : fp_cond_alias<"ne", 0b0001>;
728 +defm : fp_cond_alias<"e", 0b1001>;
729 +defm : fp_cond_alias<"ue", 0b1010>;
730 +defm : fp_cond_alias<"ge", 0b1011>;
731 +defm : fp_cond_alias<"uge", 0b1100>;
732 +defm : fp_cond_alias<"le", 0b1101>;
733 +defm : fp_cond_alias<"ule", 0b1110>;
734 +defm : fp_cond_alias<"o", 0b1111>;