1 //===-------------------- UnwindRegistersRestore.S ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is dual licensed under the MIT and the University of Illinois Open
6 // Source Licenses. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_x866jumptoEv)
17 # void libunwind::Registers_x86::jumpto()
21 # +-----------------------+
22 # + thread_state pointer +
23 # +-----------------------+
25 # +-----------------------+ <-- SP
28 # set up eax and ret on new stack location
29 movl 28(%eax), %edx # edx holds new stack pointer
36 # we now have ret and eax pushed onto where new stack will be
37 # restore all registers
47 pop %eax # eax was already pushed on new stack
48 ret # eip was already pushed on new stack
55 #elif defined(__x86_64__)
57 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind16Registers_x86_646jumptoEv)
59 # void libunwind::Registers_x86_64::jumpto()
61 # On entry, thread_state pointer is in rdi
63 movq 56(%rdi), %rax # rax holds new stack pointer
66 movq 32(%rdi), %rbx # store new rdi on new stack
68 movq 128(%rdi), %rbx # store new rip on new stack
70 # restore all registers
91 movq 56(%rdi), %rsp # cut back rsp to new location
92 pop %rdi # rdi was saved here earlier
93 ret # rip was saved here
96 #elif defined(__ppc__)
98 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv)
100 ; void libunwind::Registers_ppc::jumpto()
103 ; thread_state pointer is in r3
106 ; restore integral registerrs
140 ; restore float registers
174 ; restore vector registers if any are in use
175 lwz r5,156(r3) ; test VRsave
180 rlwinm r4,r4,0,0,27 ; mask low 4-bits
181 ; r4 is now a 16-byte aligned pointer into the red zone
182 ; the _vectorRegisters may not be 16-byte aligned so copy via red zone temp buffer
185 #define LOAD_VECTOR_UNALIGNEDl(_index) \
186 andis. r0,r5,(1<<(15-_index)) @\
187 beq Ldone ## _index @\
188 lwz r0, 424+_index*16(r3) @\
190 lwz r0, 424+_index*16+4(r3) @\
192 lwz r0, 424+_index*16+8(r3) @\
194 lwz r0, 424+_index*16+12(r3)@\
196 lvx v ## _index,0,r4 @\
199 #define LOAD_VECTOR_UNALIGNEDh(_index) \
200 andi. r0,r5,(1<<(31-_index)) @\
201 beq Ldone ## _index @\
202 lwz r0, 424+_index*16(r3) @\
204 lwz r0, 424+_index*16+4(r3) @\
206 lwz r0, 424+_index*16+8(r3) @\
208 lwz r0, 424+_index*16+12(r3)@\
210 lvx v ## _index,0,r4 @\
214 LOAD_VECTOR_UNALIGNEDl(0)
215 LOAD_VECTOR_UNALIGNEDl(1)
216 LOAD_VECTOR_UNALIGNEDl(2)
217 LOAD_VECTOR_UNALIGNEDl(3)
218 LOAD_VECTOR_UNALIGNEDl(4)
219 LOAD_VECTOR_UNALIGNEDl(5)
220 LOAD_VECTOR_UNALIGNEDl(6)
221 LOAD_VECTOR_UNALIGNEDl(7)
222 LOAD_VECTOR_UNALIGNEDl(8)
223 LOAD_VECTOR_UNALIGNEDl(9)
224 LOAD_VECTOR_UNALIGNEDl(10)
225 LOAD_VECTOR_UNALIGNEDl(11)
226 LOAD_VECTOR_UNALIGNEDl(12)
227 LOAD_VECTOR_UNALIGNEDl(13)
228 LOAD_VECTOR_UNALIGNEDl(14)
229 LOAD_VECTOR_UNALIGNEDl(15)
230 LOAD_VECTOR_UNALIGNEDh(16)
231 LOAD_VECTOR_UNALIGNEDh(17)
232 LOAD_VECTOR_UNALIGNEDh(18)
233 LOAD_VECTOR_UNALIGNEDh(19)
234 LOAD_VECTOR_UNALIGNEDh(20)
235 LOAD_VECTOR_UNALIGNEDh(21)
236 LOAD_VECTOR_UNALIGNEDh(22)
237 LOAD_VECTOR_UNALIGNEDh(23)
238 LOAD_VECTOR_UNALIGNEDh(24)
239 LOAD_VECTOR_UNALIGNEDh(25)
240 LOAD_VECTOR_UNALIGNEDh(26)
241 LOAD_VECTOR_UNALIGNEDh(27)
242 LOAD_VECTOR_UNALIGNEDh(28)
243 LOAD_VECTOR_UNALIGNEDh(29)
244 LOAD_VECTOR_UNALIGNEDh(30)
245 LOAD_VECTOR_UNALIGNEDh(31)
248 lwz r0, 136(r3) ; __cr
250 lwz r0, 148(r3) ; __ctr
252 lwz r0, 0(r3) ; __ssr0
254 lwz r0, 8(r3) ; do r0 now
255 lwz r5,28(r3) ; do r5 now
256 lwz r4,24(r3) ; do r4 now
257 lwz r1,12(r3) ; do sp now
258 lwz r3,20(r3) ; do r3 last
261 #elif defined(__arm64__) || defined(__aarch64__)
264 // void libunwind::Registers_arm64::jumpto()
267 // thread_state pointer is in x0
270 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind15Registers_arm646jumptoEv)
271 // skip restore of x0,x1 for now
272 ldp x2, x3, [x0, #0x010]
273 ldp x4, x5, [x0, #0x020]
274 ldp x6, x7, [x0, #0x030]
275 ldp x8, x9, [x0, #0x040]
276 ldp x10,x11, [x0, #0x050]
277 ldp x12,x13, [x0, #0x060]
278 ldp x14,x15, [x0, #0x070]
279 ldp x16,x17, [x0, #0x080]
280 ldp x18,x19, [x0, #0x090]
281 ldp x20,x21, [x0, #0x0A0]
282 ldp x22,x23, [x0, #0x0B0]
283 ldp x24,x25, [x0, #0x0C0]
284 ldp x26,x27, [x0, #0x0D0]
285 ldp x28,x29, [x0, #0x0E0]
286 ldr x30, [x0, #0x100] // restore pc into lr
288 mov sp,x1 // restore sp
290 ldp d0, d1, [x0, #0x110]
291 ldp d2, d3, [x0, #0x120]
292 ldp d4, d5, [x0, #0x130]
293 ldp d6, d7, [x0, #0x140]
294 ldp d8, d9, [x0, #0x150]
295 ldp d10,d11, [x0, #0x160]
296 ldp d12,d13, [x0, #0x170]
297 ldp d14,d15, [x0, #0x180]
298 ldp d16,d17, [x0, #0x190]
299 ldp d18,d19, [x0, #0x1A0]
300 ldp d20,d21, [x0, #0x1B0]
301 ldp d22,d23, [x0, #0x1C0]
302 ldp d24,d25, [x0, #0x1D0]
303 ldp d26,d27, [x0, #0x1E0]
304 ldp d28,d29, [x0, #0x1F0]
305 ldr d30, [x0, #0x200]
306 ldr d31, [x0, #0x208]
308 ldp x0, x1, [x0, #0x000] // restore x0,x1
309 ret x30 // jump to pc
311 #elif defined(__arm__) && !defined(__APPLE__)
313 #if !defined(__ARM_ARCH_ISA_ARM)
318 @ void libunwind::Registers_arm::restoreCoreAndJumpTo()
321 @ thread_state pointer is in r0
324 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
325 #if !defined(__ARM_ARCH_ISA_ARM)
329 mov lr, r3 @ restore pc into lr
332 @ Use lr as base so that r0 can be restored.
334 @ 32bit thumb-2 restrictions for ldm:
335 @ . the sp (r13) cannot be in the list
336 @ . the pc (r15) and lr (r14) cannot both be in the list in an LDM instruction
339 ldr lr, [lr, #60] @ restore pc into lr
344 @ static void libunwind::Registers_arm::restoreVFPWithFLDMD(unw_fpreg_t* values)
347 @ values pointer is in r0
351 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMDEPy)
352 @ VFP and iwMMX instructions are only available when compiling with the flags
353 @ that enable them. We do not want to do that in the library (because we do not
354 @ want the compiler to generate instructions that access those) but this is
355 @ only accessed if the personality routine needs these registers. Use of
356 @ these registers implies they are, actually, available on the target, so
357 @ it's ok to execute.
358 @ So, generate the instruction using the corresponding coprocessor mnemonic.
363 @ static void libunwind::Registers_arm::restoreVFPWithFLDMX(unw_fpreg_t* values)
366 @ values pointer is in r0
370 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMXEPy)
371 vldmia r0, {d0-d15} @ fldmiax is deprecated in ARMv7+ and now behaves like vldmia
375 @ static void libunwind::Registers_arm::restoreVFPv3(unw_fpreg_t* values)
378 @ values pointer is in r0
382 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm12restoreVFPv3EPy)
387 @ static void libunwind::Registers_arm::restoreiWMMX(unw_fpreg_t* values)
390 @ values pointer is in r0
393 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm12restoreiWMMXEPy)
394 #if (!defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_6SM__)) || defined(__ARM_WMMX)
395 ldcl p1, cr0, [r0], #8 @ wldrd wR0, [r0], #8
396 ldcl p1, cr1, [r0], #8 @ wldrd wR1, [r0], #8
397 ldcl p1, cr2, [r0], #8 @ wldrd wR2, [r0], #8
398 ldcl p1, cr3, [r0], #8 @ wldrd wR3, [r0], #8
399 ldcl p1, cr4, [r0], #8 @ wldrd wR4, [r0], #8
400 ldcl p1, cr5, [r0], #8 @ wldrd wR5, [r0], #8
401 ldcl p1, cr6, [r0], #8 @ wldrd wR6, [r0], #8
402 ldcl p1, cr7, [r0], #8 @ wldrd wR7, [r0], #8
403 ldcl p1, cr8, [r0], #8 @ wldrd wR8, [r0], #8
404 ldcl p1, cr9, [r0], #8 @ wldrd wR9, [r0], #8
405 ldcl p1, cr10, [r0], #8 @ wldrd wR10, [r0], #8
406 ldcl p1, cr11, [r0], #8 @ wldrd wR11, [r0], #8
407 ldcl p1, cr12, [r0], #8 @ wldrd wR12, [r0], #8
408 ldcl p1, cr13, [r0], #8 @ wldrd wR13, [r0], #8
409 ldcl p1, cr14, [r0], #8 @ wldrd wR14, [r0], #8
410 ldcl p1, cr15, [r0], #8 @ wldrd wR15, [r0], #8
415 @ static void libunwind::Registers_arm::restoreiWMMXControl(unw_uint32_t* values)
418 @ values pointer is in r0
421 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreiWMMXControlEPj)
422 #if (!defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_6SM__)) || defined(__ARM_WMMX)
423 ldc2 p1, cr8, [r0], #4 @ wldrw wCGR0, [r0], #4
424 ldc2 p1, cr9, [r0], #4 @ wldrw wCGR1, [r0], #4
425 ldc2 p1, cr10, [r0], #4 @ wldrw wCGR2, [r0], #4
426 ldc2 p1, cr11, [r0], #4 @ wldrw wCGR3, [r0], #4
430 #elif defined(__or1k__)
432 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind14Registers_or1k6jumptoEv)
434 # void libunwind::Registers_or1k::jumpto()
437 # thread_state pointer is in r3
440 # restore integral registerrs
474 # at last, restore r3
481 #elif defined(__riscv)
484 // void libunwind::Registers_riscv::jumpto()
487 // thread_state pointer is in a0
490 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind15Registers_riscv6jumptoEv)
491 #ifdef __riscv_float_abi_double
492 fld f0, (8 * 32 + 8 * 0)(a0)
493 fld f1, (8 * 32 + 8 * 1)(a0)
494 fld f2, (8 * 32 + 8 * 2)(a0)
495 fld f3, (8 * 32 + 8 * 3)(a0)
496 fld f4, (8 * 32 + 8 * 4)(a0)
497 fld f5, (8 * 32 + 8 * 5)(a0)
498 fld f6, (8 * 32 + 8 * 6)(a0)
499 fld f7, (8 * 32 + 8 * 7)(a0)
500 fld f8, (8 * 32 + 8 * 8)(a0)
501 fld f9, (8 * 32 + 8 * 9)(a0)
502 fld f10, (8 * 32 + 8 * 10)(a0)
503 fld f11, (8 * 32 + 8 * 11)(a0)
504 fld f12, (8 * 32 + 8 * 12)(a0)
505 fld f13, (8 * 32 + 8 * 13)(a0)
506 fld f14, (8 * 32 + 8 * 14)(a0)
507 fld f15, (8 * 32 + 8 * 15)(a0)
508 fld f16, (8 * 32 + 8 * 16)(a0)
509 fld f17, (8 * 32 + 8 * 17)(a0)
510 fld f18, (8 * 32 + 8 * 18)(a0)
511 fld f19, (8 * 32 + 8 * 19)(a0)
512 fld f20, (8 * 32 + 8 * 20)(a0)
513 fld f21, (8 * 32 + 8 * 21)(a0)
514 fld f22, (8 * 32 + 8 * 22)(a0)
515 fld f23, (8 * 32 + 8 * 23)(a0)
516 fld f24, (8 * 32 + 8 * 24)(a0)
517 fld f25, (8 * 32 + 8 * 25)(a0)
518 fld f26, (8 * 32 + 8 * 26)(a0)
519 fld f27, (8 * 32 + 8 * 27)(a0)
520 fld f28, (8 * 32 + 8 * 28)(a0)
521 fld f29, (8 * 32 + 8 * 29)(a0)
522 fld f30, (8 * 32 + 8 * 30)(a0)
523 fld f31, (8 * 32 + 8 * 31)(a0)
558 ld x10, (8 * 10)(a0) // restore a0
562 #elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32
565 // void libunwind::Registers_mips_o32::jumpto()
568 // thread state pointer is in a0 ($4)
570 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
575 #ifdef __mips_hard_float
577 ldc1 $f0, (4 * 36 + 8 * 0)($4)
578 ldc1 $f2, (4 * 36 + 8 * 2)($4)
579 ldc1 $f4, (4 * 36 + 8 * 4)($4)
580 ldc1 $f6, (4 * 36 + 8 * 6)($4)
581 ldc1 $f8, (4 * 36 + 8 * 8)($4)
582 ldc1 $f10, (4 * 36 + 8 * 10)($4)
583 ldc1 $f12, (4 * 36 + 8 * 12)($4)
584 ldc1 $f14, (4 * 36 + 8 * 14)($4)
585 ldc1 $f16, (4 * 36 + 8 * 16)($4)
586 ldc1 $f18, (4 * 36 + 8 * 18)($4)
587 ldc1 $f20, (4 * 36 + 8 * 20)($4)
588 ldc1 $f22, (4 * 36 + 8 * 22)($4)
589 ldc1 $f24, (4 * 36 + 8 * 24)($4)
590 ldc1 $f26, (4 * 36 + 8 * 26)($4)
591 ldc1 $f28, (4 * 36 + 8 * 28)($4)
592 ldc1 $f30, (4 * 36 + 8 * 30)($4)
594 ldc1 $f0, (4 * 36 + 8 * 0)($4)
595 ldc1 $f1, (4 * 36 + 8 * 1)($4)
596 ldc1 $f2, (4 * 36 + 8 * 2)($4)
597 ldc1 $f3, (4 * 36 + 8 * 3)($4)
598 ldc1 $f4, (4 * 36 + 8 * 4)($4)
599 ldc1 $f5, (4 * 36 + 8 * 5)($4)
600 ldc1 $f6, (4 * 36 + 8 * 6)($4)
601 ldc1 $f7, (4 * 36 + 8 * 7)($4)
602 ldc1 $f8, (4 * 36 + 8 * 8)($4)
603 ldc1 $f9, (4 * 36 + 8 * 9)($4)
604 ldc1 $f10, (4 * 36 + 8 * 10)($4)
605 ldc1 $f11, (4 * 36 + 8 * 11)($4)
606 ldc1 $f12, (4 * 36 + 8 * 12)($4)
607 ldc1 $f13, (4 * 36 + 8 * 13)($4)
608 ldc1 $f14, (4 * 36 + 8 * 14)($4)
609 ldc1 $f15, (4 * 36 + 8 * 15)($4)
610 ldc1 $f16, (4 * 36 + 8 * 16)($4)
611 ldc1 $f17, (4 * 36 + 8 * 17)($4)
612 ldc1 $f18, (4 * 36 + 8 * 18)($4)
613 ldc1 $f19, (4 * 36 + 8 * 19)($4)
614 ldc1 $f20, (4 * 36 + 8 * 20)($4)
615 ldc1 $f21, (4 * 36 + 8 * 21)($4)
616 ldc1 $f22, (4 * 36 + 8 * 22)($4)
617 ldc1 $f23, (4 * 36 + 8 * 23)($4)
618 ldc1 $f24, (4 * 36 + 8 * 24)($4)
619 ldc1 $f25, (4 * 36 + 8 * 25)($4)
620 ldc1 $f26, (4 * 36 + 8 * 26)($4)
621 ldc1 $f27, (4 * 36 + 8 * 27)($4)
622 ldc1 $f28, (4 * 36 + 8 * 28)($4)
623 ldc1 $f29, (4 * 36 + 8 * 29)($4)
624 ldc1 $f30, (4 * 36 + 8 * 30)($4)
625 ldc1 $f31, (4 * 36 + 8 * 31)($4)
664 // load new pc into ra
666 // jump to ra, load a0 in the delay slot
671 #elif defined(__mips64)
674 // void libunwind::Registers_mips_newabi::jumpto()
677 // thread state pointer is in a0 ($4)
679 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
684 #ifdef __mips_hard_float
685 ldc1 $f0, (8 * 35)($4)
686 ldc1 $f1, (8 * 36)($4)
687 ldc1 $f2, (8 * 37)($4)
688 ldc1 $f3, (8 * 38)($4)
689 ldc1 $f4, (8 * 39)($4)
690 ldc1 $f5, (8 * 40)($4)
691 ldc1 $f6, (8 * 41)($4)
692 ldc1 $f7, (8 * 42)($4)
693 ldc1 $f8, (8 * 43)($4)
694 ldc1 $f9, (8 * 44)($4)
695 ldc1 $f10, (8 * 45)($4)
696 ldc1 $f11, (8 * 46)($4)
697 ldc1 $f12, (8 * 47)($4)
698 ldc1 $f13, (8 * 48)($4)
699 ldc1 $f14, (8 * 49)($4)
700 ldc1 $f15, (8 * 50)($4)
701 ldc1 $f16, (8 * 51)($4)
702 ldc1 $f17, (8 * 52)($4)
703 ldc1 $f18, (8 * 53)($4)
704 ldc1 $f19, (8 * 54)($4)
705 ldc1 $f20, (8 * 55)($4)
706 ldc1 $f21, (8 * 56)($4)
707 ldc1 $f22, (8 * 57)($4)
708 ldc1 $f23, (8 * 58)($4)
709 ldc1 $f24, (8 * 59)($4)
710 ldc1 $f25, (8 * 60)($4)
711 ldc1 $f26, (8 * 61)($4)
712 ldc1 $f27, (8 * 62)($4)
713 ldc1 $f28, (8 * 63)($4)
714 ldc1 $f29, (8 * 64)($4)
715 ldc1 $f30, (8 * 65)($4)
716 ldc1 $f31, (8 * 66)($4)
754 // load new pc into ra
756 // jump to ra, load a0 in the delay slot
763 NO_EXEC_STACK_DIRECTIVE