1 //===--- arm_neon.td - ARM NEON compiler interface ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TableGen definitions from which the ARM NEON header
11 // file will be generated. See ARM document DUI0348B.
13 //===----------------------------------------------------------------------===//
40 def OP_QDMULL_LN : Op;
41 def OP_QDMLAL_LN : Op;
42 def OP_QDMLSL_LN : Op;
43 def OP_QDMULH_LN : Op;
44 def OP_QRDMULH_LN : Op;
72 class Inst <string n, string p, string t, Op o> {
81 // Used to generate Builtins.def:
82 // SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8")
83 // IInst: Instruction with generic integer suffix (e.g., "i8")
84 // WInst: Instruction with only bit size suffix (e.g., "8")
85 class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
86 class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
87 class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
89 // prototype: return (arg, arg, ...)
91 // t: best-fit integer (int/poly args)
92 // x: signed integer (int/float args)
93 // u: unsigned integer (int/float args)
94 // f: float (int args)
96 // g: default, ignore 'Q' size modifier.
97 // w: double width elements, same num elts
98 // n: double width elements, half num elts
99 // h: half width elements, double num elts
100 // e: half width elements, double num elts, unsigned
102 // l: constant uint64
103 // s: scalar of element type
104 // a: scalar of element type (splat to vector type)
105 // k: default elt width, double num elts
106 // #: array of default vectors
108 // c: const pointer type
123 ////////////////////////////////////////////////////////////////////////////////
125 def VADD : Inst<"vadd", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
126 def VADDL : Inst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>;
127 def VADDW : Inst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>;
128 def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
129 def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
130 def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
131 def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">;
132 def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">;
134 ////////////////////////////////////////////////////////////////////////////////
135 // E.3.2 Multiplication
136 def VMUL : Inst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>;
137 def VMULP : SInst<"vmul", "ddd", "PcQPc">;
138 def VMLA : Inst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
139 def VMLAL : Inst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>;
140 def VMLS : Inst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
141 def VMLSL : Inst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>;
142 def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">;
143 def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">;
144 def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">;
145 def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">;
146 def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">;
147 def VQDMULL : SInst<"vqdmull", "wdd", "si">;
149 ////////////////////////////////////////////////////////////////////////////////
151 def VSUB : Inst<"vsub", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
152 def VSUBL : Inst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>;
153 def VSUBW : Inst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>;
154 def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
155 def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
156 def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">;
157 def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">;
159 ////////////////////////////////////////////////////////////////////////////////
161 def VCEQ : Inst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
162 def VCGE : Inst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
163 def VCLE : Inst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
164 def VCGT : Inst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
165 def VCLT : Inst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
166 def VCAGE : IInst<"vcage", "udd", "fQf">;
167 def VCALE : IInst<"vcale", "udd", "fQf">;
168 def VCAGT : IInst<"vcagt", "udd", "fQf">;
169 def VCALT : IInst<"vcalt", "udd", "fQf">;
170 def VTST : WInst<"vtst", "udd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">;
172 ////////////////////////////////////////////////////////////////////////////////
173 // E.3.5 Absolute Difference
174 def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
175 def VABDL : Inst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>;
176 def VABA : Inst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>;
177 def VABAL : Inst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>;
179 ////////////////////////////////////////////////////////////////////////////////
181 def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
182 def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
184 ////////////////////////////////////////////////////////////////////////////////
185 // E.3.7 Pairwise Addition
186 def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">;
187 def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
188 def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
190 ////////////////////////////////////////////////////////////////////////////////
191 // E.3.8-9 Folding Max/Min
192 def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">;
193 def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">;
195 ////////////////////////////////////////////////////////////////////////////////
196 // E.3.10 Reciprocal/Sqrt
197 def VRECPS : IInst<"vrecps", "ddd", "fQf">;
198 def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">;
200 ////////////////////////////////////////////////////////////////////////////////
201 // E.3.11 Shifts by signed variable
202 def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
203 def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
204 def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
205 def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
207 ////////////////////////////////////////////////////////////////////////////////
208 // E.3.12 Shifts by constant
210 def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
211 def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
212 def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
213 def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
214 def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
215 def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
216 def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">;
217 def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">;
218 def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">;
219 def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">;
220 def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">;
221 def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">;
222 def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">;
223 def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">;
225 ////////////////////////////////////////////////////////////////////////////////
226 // E.3.13 Shifts with insert
227 def VSRI_N : WInst<"vsri_n", "dddi",
228 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
229 def VSLI_N : WInst<"vsli_n", "dddi",
230 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
233 ////////////////////////////////////////////////////////////////////////////////
234 // E.3.14 Loads and stores of a single vector
235 def VLD1 : WInst<"vld1", "dc",
236 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
237 def VLD1_LANE : WInst<"vld1_lane", "dcdi",
238 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
239 def VLD1_DUP : WInst<"vld1_dup", "dc",
240 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
241 def VST1 : WInst<"vst1", "vpd",
242 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
243 def VST1_LANE : WInst<"vst1_lane", "vpdi",
244 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
246 ////////////////////////////////////////////////////////////////////////////////
247 // E.3.15 Loads and stores of an N-element structure
248 def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
249 def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
250 def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
251 def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">;
252 def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">;
253 def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">;
254 def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
255 def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
256 def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
257 def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
258 def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
259 def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
260 def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
261 def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
262 def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
264 ////////////////////////////////////////////////////////////////////////////////
265 // E.3.16 Extract lanes from a vector
266 def VGET_LANE : IInst<"vget_lane", "sdi",
267 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
269 ////////////////////////////////////////////////////////////////////////////////
270 // E.3.17 Set lanes within a vector
271 def VSET_LANE : IInst<"vset_lane", "dsdi",
272 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
274 ////////////////////////////////////////////////////////////////////////////////
275 // E.3.18 Initialize a vector from bit pattern
276 def VCREATE: Inst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST>;
278 ////////////////////////////////////////////////////////////////////////////////
279 // E.3.19 Set all lanes to same value
280 def VDUP_N : Inst<"vdup_n", "ds",
281 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
282 def VMOV_N : Inst<"vmov_n", "ds",
283 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
284 def VDUP_LANE : Inst<"vdup_lane", "dgi",
285 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl",OP_DUP_LN>;
287 ////////////////////////////////////////////////////////////////////////////////
288 // E.3.20 Combining vectors
289 def VCOMBINE : Inst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>;
291 ////////////////////////////////////////////////////////////////////////////////
292 // E.3.21 Splitting vectors
293 def VGET_HIGH : Inst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
294 def VGET_LOW : Inst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
296 ////////////////////////////////////////////////////////////////////////////////
297 // E.3.22 Converting vectors
298 def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">;
299 def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">;
300 def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">;
301 def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">;
302 def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">;
303 let isVCVT_N = 1 in {
304 def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">;
305 def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">;
306 def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">;
308 def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">;
309 def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">;
310 def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">;
311 def VQMOVUN : SInst<"vqmovun", "ek", "sil">;
313 ////////////////////////////////////////////////////////////////////////////////
314 // E.3.23-24 Table lookup, Extended table lookup
315 def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">;
316 def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">;
317 def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">;
318 def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">;
319 def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">;
320 def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">;
321 def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">;
322 def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">;
324 ////////////////////////////////////////////////////////////////////////////////
325 // E.3.25 Operations with a scalar value
326 def VMLA_LANE : Inst<"vmla_lane", "dddgi", "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
327 def VMLAL_LANE : Inst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>;
328 def VQDMLAL_LANE : Inst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>;
329 def VMLS_LANE : Inst<"vmls_lane", "dddgi", "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
330 def VMLSL_LANE : Inst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>;
331 def VQDMLSL_LANE : Inst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>;
332 def VMUL_N : Inst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
333 def VMUL_LANE : Inst<"vmul_lane", "ddgi", "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
334 def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">;
335 def VMULL_LANE : Inst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>;
336 def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">;
337 def VQDMULL_LANE : Inst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>;
338 def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">;
339 def VQDMULH_LANE : Inst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>;
340 def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">;
341 def VQRDMULH_LANE : Inst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>;
342 def VMLA_N : Inst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
343 def VMLAL_N : Inst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>;
344 def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">;
345 def VMLS_N : Inst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>;
346 def VMLSL_N : Inst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>;
347 def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">;
349 ////////////////////////////////////////////////////////////////////////////////
350 // E.3.26 Vector Extract
351 def VEXT : WInst<"vext", "dddi",
352 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">;
354 ////////////////////////////////////////////////////////////////////////////////
355 // E.3.27 Reverse vector elements
356 def VREV64 : Inst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
358 def VREV32 : Inst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
359 def VREV16 : Inst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>;
361 ////////////////////////////////////////////////////////////////////////////////
362 // E.3.28 Other single operand arithmetic
363 def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">;
364 def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">;
365 def VNEG : Inst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>;
366 def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">;
367 def VCLS : SInst<"vcls", "dd", "csiQcQsQi">;
368 def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
369 def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">;
370 def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">;
371 def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">;
373 ////////////////////////////////////////////////////////////////////////////////
374 // E.3.29 Logical operations
375 def VMVN : Inst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
376 def VAND : Inst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
377 def VORR : Inst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
378 def VEOR : Inst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
379 def VBIC : Inst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
380 def VORN : Inst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
381 def VBSL : Inst<"vbsl", "dudd",
382 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs", OP_SEL>;
384 ////////////////////////////////////////////////////////////////////////////////
385 // E.3.30 Transposition operations
386 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
387 def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
388 def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
390 ////////////////////////////////////////////////////////////////////////////////
391 // E.3.31 Vector reinterpret cast operations
393 : Inst<"vreinterpret", "dd",
394 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT>;