1 //===--- arm_neon.td - ARM NEON compiler interface ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TableGen definitions from which the ARM NEON header
11 // file will be generated. See ARM document DUI0348B.
13 //===----------------------------------------------------------------------===//
15 include "arm_neon_incl.td"
17 def OP_ADD : Op<(op "+", $p0, $p1)>;
18 def OP_ADDL : Op<(op "+", (call "vmovl", $p0), (call "vmovl", $p1))>;
19 def OP_ADDLHi : Op<(op "+", (call "vmovl_high", $p0),
20 (call "vmovl_high", $p1))>;
21 def OP_ADDW : Op<(op "+", $p0, (call "vmovl", $p1))>;
22 def OP_ADDWHi : Op<(op "+", $p0, (call "vmovl_high", $p1))>;
23 def OP_SUB : Op<(op "-", $p0, $p1)>;
24 def OP_SUBL : Op<(op "-", (call "vmovl", $p0), (call "vmovl", $p1))>;
25 def OP_SUBLHi : Op<(op "-", (call "vmovl_high", $p0),
26 (call "vmovl_high", $p1))>;
27 def OP_SUBW : Op<(op "-", $p0, (call "vmovl", $p1))>;
28 def OP_SUBWHi : Op<(op "-", $p0, (call "vmovl_high", $p1))>;
29 def OP_MUL : Op<(op "*", $p0, $p1)>;
30 def OP_MLA : Op<(op "+", $p0, (op "*", $p1, $p2))>;
31 def OP_MLAL : Op<(op "+", $p0, (call "vmull", $p1, $p2))>;
32 def OP_MULLHi : Op<(call "vmull", (call "vget_high", $p0),
33 (call "vget_high", $p1))>;
34 def OP_MULLHi_P64 : Op<(call "vmull",
35 (cast "poly64_t", (call "vget_high", $p0)),
36 (cast "poly64_t", (call "vget_high", $p1)))>;
37 def OP_MULLHi_N : Op<(call "vmull_n", (call "vget_high", $p0), $p1)>;
38 def OP_MLALHi : Op<(call "vmlal", $p0, (call "vget_high", $p1),
39 (call "vget_high", $p2))>;
40 def OP_MLALHi_N : Op<(call "vmlal_n", $p0, (call "vget_high", $p1), $p2)>;
41 def OP_MLS : Op<(op "-", $p0, (op "*", $p1, $p2))>;
42 def OP_FMLS : Op<(call "vfma", $p0, (op "-", $p1), $p2)>;
43 def OP_MLSL : Op<(op "-", $p0, (call "vmull", $p1, $p2))>;
44 def OP_MLSLHi : Op<(call "vmlsl", $p0, (call "vget_high", $p1),
45 (call "vget_high", $p2))>;
46 def OP_MLSLHi_N : Op<(call "vmlsl_n", $p0, (call "vget_high", $p1), $p2)>;
47 def OP_MUL_N : Op<(op "*", $p0, (dup $p1))>;
48 def OP_MULX_N : Op<(call "vmulx", $p0, (dup $p1))>;
49 def OP_MLA_N : Op<(op "+", $p0, (op "*", $p1, (dup $p2)))>;
50 def OP_MLS_N : Op<(op "-", $p0, (op "*", $p1, (dup $p2)))>;
51 def OP_FMLA_N : Op<(call "vfma", $p0, $p1, (dup $p2))>;
52 def OP_FMLS_N : Op<(call "vfma", $p0, (op "-", $p1), (dup $p2))>;
53 def OP_MLAL_N : Op<(op "+", $p0, (call "vmull", $p1, (dup $p2)))>;
54 def OP_MLSL_N : Op<(op "-", $p0, (call "vmull", $p1, (dup $p2)))>;
55 def OP_MUL_LN : Op<(op "*", $p0, (splat $p1, $p2))>;
56 def OP_MULX_LN : Op<(call "vmulx", $p0, (splat $p1, $p2))>;
57 def OP_MULL_LN : Op<(call "vmull", $p0, (splat $p1, $p2))>;
58 def OP_MULLHi_LN: Op<(call "vmull", (call "vget_high", $p0), (splat $p1, $p2))>;
59 def OP_MLA_LN : Op<(op "+", $p0, (op "*", $p1, (splat $p2, $p3)))>;
60 def OP_MLS_LN : Op<(op "-", $p0, (op "*", $p1, (splat $p2, $p3)))>;
61 def OP_MLAL_LN : Op<(op "+", $p0, (call "vmull", $p1, (splat $p2, $p3)))>;
62 def OP_MLALHi_LN: Op<(op "+", $p0, (call "vmull", (call "vget_high", $p1),
64 def OP_MLSL_LN : Op<(op "-", $p0, (call "vmull", $p1, (splat $p2, $p3)))>;
65 def OP_MLSLHi_LN : Op<(op "-", $p0, (call "vmull", (call "vget_high", $p1),
67 def OP_QDMULL_LN : Op<(call "vqdmull", $p0, (splat $p1, $p2))>;
68 def OP_QDMULLHi_LN : Op<(call "vqdmull", (call "vget_high", $p0),
70 def OP_QDMLAL_LN : Op<(call "vqdmlal", $p0, $p1, (splat $p2, $p3))>;
71 def OP_QDMLALHi_LN : Op<(call "vqdmlal", $p0, (call "vget_high", $p1),
73 def OP_QDMLSL_LN : Op<(call "vqdmlsl", $p0, $p1, (splat $p2, $p3))>;
74 def OP_QDMLSLHi_LN : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1),
76 def OP_QDMULH_LN : Op<(call "vqdmulh", $p0, (splat $p1, $p2))>;
77 def OP_QRDMULH_LN : Op<(call "vqrdmulh", $p0, (splat $p1, $p2))>;
78 def OP_QRDMLAH : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, $p2))>;
79 def OP_QRDMLSH : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, $p2))>;
80 def OP_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>;
81 def OP_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>;
82 def OP_FMS_LN : Op<(call "vfma_lane", $p0, (op "-", $p1), $p2, $p3)>;
83 def OP_FMS_LNQ : Op<(call "vfma_laneq", $p0, (op "-", $p1), $p2, $p3)>;
84 def OP_TRN1 : Op<(shuffle $p0, $p1, (interleave (decimate mask0, 2),
85 (decimate mask1, 2)))>;
86 def OP_ZIP1 : Op<(shuffle $p0, $p1, (lowhalf (interleave mask0, mask1)))>;
87 def OP_UZP1 : Op<(shuffle $p0, $p1, (add (decimate mask0, 2),
88 (decimate mask1, 2)))>;
89 def OP_TRN2 : Op<(shuffle $p0, $p1, (interleave
90 (decimate (rotl mask0, 1), 2),
91 (decimate (rotl mask1, 1), 2)))>;
92 def OP_ZIP2 : Op<(shuffle $p0, $p1, (highhalf (interleave mask0, mask1)))>;
93 def OP_UZP2 : Op<(shuffle $p0, $p1, (add (decimate (rotl mask0, 1), 2),
94 (decimate (rotl mask1, 1), 2)))>;
95 def OP_EQ : Op<(cast "R", (op "==", $p0, $p1))>;
96 def OP_GE : Op<(cast "R", (op ">=", $p0, $p1))>;
97 def OP_LE : Op<(cast "R", (op "<=", $p0, $p1))>;
98 def OP_GT : Op<(cast "R", (op ">", $p0, $p1))>;
99 def OP_LT : Op<(cast "R", (op "<", $p0, $p1))>;
100 def OP_NEG : Op<(op "-", $p0)>;
101 def OP_NOT : Op<(op "~", $p0)>;
102 def OP_AND : Op<(op "&", $p0, $p1)>;
103 def OP_OR : Op<(op "|", $p0, $p1)>;
104 def OP_XOR : Op<(op "^", $p0, $p1)>;
105 def OP_ANDN : Op<(op "&", $p0, (op "~", $p1))>;
106 def OP_ORN : Op<(op "|", $p0, (op "~", $p1))>;
107 def OP_CAST : Op<(cast "R", $p0)>;
108 def OP_HI : Op<(shuffle $p0, $p0, (highhalf mask0))>;
109 def OP_LO : Op<(shuffle $p0, $p0, (lowhalf mask0))>;
110 def OP_CONC : Op<(shuffle $p0, $p1, (add mask0, mask1))>;
111 def OP_DUP : Op<(dup $p0)>;
112 def OP_DUP_LN : Op<(splat $p0, $p1)>;
113 def OP_SEL : Op<(cast "R", (op "|",
114 (op "&", $p0, (cast $p0, $p1)),
115 (op "&", (op "~", $p0), (cast $p0, $p2))))>;
116 def OP_REV16 : Op<(shuffle $p0, $p0, (rev 16, mask0))>;
117 def OP_REV32 : Op<(shuffle $p0, $p0, (rev 32, mask0))>;
118 def OP_REV64 : Op<(shuffle $p0, $p0, (rev 64, mask0))>;
119 def OP_XTN : Op<(call "vcombine", $p0, (call "vmovn", $p1))>;
120 def OP_SQXTUN : Op<(call "vcombine", (cast $p0, "U", $p0),
121 (call "vqmovun", $p1))>;
122 def OP_QXTN : Op<(call "vcombine", $p0, (call "vqmovn", $p1))>;
123 def OP_VCVT_NA_HI_F16 : Op<(call "vcombine", $p0, (call "vcvt_f16_f32", $p1))>;
124 def OP_VCVT_NA_HI_F32 : Op<(call "vcombine", $p0, (call "vcvt_f32_f64", $p1))>;
125 def OP_VCVT_EX_HI_F32 : Op<(call "vcvt_f32_f16", (call "vget_high", $p0))>;
126 def OP_VCVT_EX_HI_F64 : Op<(call "vcvt_f64_f32", (call "vget_high", $p0))>;
127 def OP_VCVTX_HI : Op<(call "vcombine", $p0, (call "vcvtx_f32", $p1))>;
128 def OP_REINT : Op<(cast "R", $p0)>;
129 def OP_ADDHNHi : Op<(call "vcombine", $p0, (call "vaddhn", $p1, $p2))>;
130 def OP_RADDHNHi : Op<(call "vcombine", $p0, (call "vraddhn", $p1, $p2))>;
131 def OP_SUBHNHi : Op<(call "vcombine", $p0, (call "vsubhn", $p1, $p2))>;
132 def OP_RSUBHNHi : Op<(call "vcombine", $p0, (call "vrsubhn", $p1, $p2))>;
133 def OP_ABDL : Op<(cast "R", (call "vmovl", (cast $p0, "U",
134 (call "vabd", $p0, $p1))))>;
135 def OP_ABDLHi : Op<(call "vabdl", (call "vget_high", $p0),
136 (call "vget_high", $p1))>;
137 def OP_ABA : Op<(op "+", $p0, (call "vabd", $p1, $p2))>;
138 def OP_ABAL : Op<(op "+", $p0, (call "vabdl", $p1, $p2))>;
139 def OP_ABALHi : Op<(call "vabal", $p0, (call "vget_high", $p1),
140 (call "vget_high", $p2))>;
141 def OP_QDMULLHi : Op<(call "vqdmull", (call "vget_high", $p0),
142 (call "vget_high", $p1))>;
143 def OP_QDMULLHi_N : Op<(call "vqdmull_n", (call "vget_high", $p0), $p1)>;
144 def OP_QDMLALHi : Op<(call "vqdmlal", $p0, (call "vget_high", $p1),
145 (call "vget_high", $p2))>;
146 def OP_QDMLALHi_N : Op<(call "vqdmlal_n", $p0, (call "vget_high", $p1), $p2)>;
147 def OP_QDMLSLHi : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1),
148 (call "vget_high", $p2))>;
149 def OP_QDMLSLHi_N : Op<(call "vqdmlsl_n", $p0, (call "vget_high", $p1), $p2)>;
150 def OP_DIV : Op<(op "/", $p0, $p1)>;
151 def OP_LONG_HI : Op<(cast "R", (call (name_replace "_high_", "_"),
152 (call "vget_high", $p0), $p1))>;
153 def OP_NARROW_HI : Op<(cast "R", (call "vcombine",
154 (cast "R", "H", $p0),
156 (call (name_replace "_high_", "_"),
158 def OP_MOVL_HI : LOp<[(save_temp $a1, (call "vget_high", $p0)),
160 (call "vshll_n", $a1, (literal "int32_t", "0")))]>;
161 def OP_COPY_LN : Op<(call "vset_lane", (call "vget_lane", $p2, $p3), $p0, $p1)>;
162 def OP_SCALAR_MUL_LN : Op<(op "*", $p0, (call "vget_lane", $p1, $p2))>;
163 def OP_SCALAR_MULX_LN : Op<(call "vmulx", $p0, (call "vget_lane", $p1, $p2))>;
164 def OP_SCALAR_VMULX_LN : LOp<[(save_temp $x, (call "vget_lane", $p0,
165 (literal "int32_t", "0"))),
166 (save_temp $y, (call "vget_lane", $p1, $p2)),
167 (save_temp $z, (call "vmulx", $x, $y)),
168 (call "vset_lane", $z, $p0, $p2)]>;
169 def OP_SCALAR_VMULX_LNQ : LOp<[(save_temp $x, (call "vget_lane", $p0,
170 (literal "int32_t", "0"))),
171 (save_temp $y, (call "vget_lane", $p1, $p2)),
172 (save_temp $z, (call "vmulx", $x, $y)),
173 (call "vset_lane", $z, $p0, (literal "int32_t",
175 class ScalarMulOp<string opname> :
176 Op<(call opname, $p0, (call "vget_lane", $p1, $p2))>;
178 def OP_SCALAR_QDMULL_LN : ScalarMulOp<"vqdmull">;
179 def OP_SCALAR_QDMULH_LN : ScalarMulOp<"vqdmulh">;
180 def OP_SCALAR_QRDMULH_LN : ScalarMulOp<"vqrdmulh">;
182 def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1,
183 (call "vget_lane", $p2, $p3)))>;
184 def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1,
185 (call "vget_lane", $p2, $p3)))>;
187 def OP_SCALAR_HALF_GET_LN : Op<(bitcast "float16_t",
189 (bitcast "int16x4_t", $p0), $p1))>;
190 def OP_SCALAR_HALF_GET_LNQ : Op<(bitcast "float16_t",
192 (bitcast "int16x8_t", $p0), $p1))>;
193 def OP_SCALAR_HALF_SET_LN : Op<(bitcast "float16x4_t",
195 (bitcast "int16_t", $p0),
196 (bitcast "int16x4_t", $p1), $p2))>;
197 def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast "float16x8_t",
199 (bitcast "int16_t", $p0),
200 (bitcast "int16x8_t", $p1), $p2))>;
203 : Op<(call "vdot", $p0, $p1,
204 (bitcast $p1, (splat(bitcast "uint32x2_t", $p2), $p3)))>;
206 : Op<(call "vdot", $p0, $p1,
207 (bitcast $p1, (splat(bitcast "uint32x4_t", $p2), $p3)))>;
209 //===----------------------------------------------------------------------===//
211 //===----------------------------------------------------------------------===//
213 ////////////////////////////////////////////////////////////////////////////////
215 def VADD : IOpInst<"vadd", "ddd",
216 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
217 def VADDL : SOpInst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>;
218 def VADDW : SOpInst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>;
219 def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
220 def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
221 def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
222 def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">;
223 def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">;
225 ////////////////////////////////////////////////////////////////////////////////
226 // E.3.2 Multiplication
227 def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>;
228 def VMULP : SInst<"vmul", "ddd", "PcQPc">;
229 def VMLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
230 def VMLAL : SOpInst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>;
231 def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
232 def VMLSL : SOpInst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>;
233 def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">;
234 def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">;
236 let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in {
237 def VQRDMLAH : SOpInst<"vqrdmlah", "dddd", "siQsQi", OP_QRDMLAH>;
238 def VQRDMLSH : SOpInst<"vqrdmlsh", "dddd", "siQsQi", OP_QRDMLSH>;
241 def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">;
242 def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">;
243 def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">;
244 def VQDMULL : SInst<"vqdmull", "wdd", "si">;
246 ////////////////////////////////////////////////////////////////////////////////
248 def VSUB : IOpInst<"vsub", "ddd",
249 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
250 def VSUBL : SOpInst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>;
251 def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>;
252 def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
253 def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
254 def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">;
255 def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">;
257 ////////////////////////////////////////////////////////////////////////////////
259 def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
260 def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
261 let InstName = "vcge" in
262 def VCLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
263 def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
264 let InstName = "vcgt" in
265 def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
266 let InstName = "vacge" in {
267 def VCAGE : IInst<"vcage", "udd", "fQf">;
268 def VCALE : IInst<"vcale", "udd", "fQf">;
270 let InstName = "vacgt" in {
271 def VCAGT : IInst<"vcagt", "udd", "fQf">;
272 def VCALT : IInst<"vcalt", "udd", "fQf">;
274 def VTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">;
276 ////////////////////////////////////////////////////////////////////////////////
277 // E.3.5 Absolute Difference
278 def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
279 def VABDL : SOpInst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>;
280 def VABA : SOpInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>;
281 def VABAL : SOpInst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>;
283 ////////////////////////////////////////////////////////////////////////////////
285 def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
286 def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
288 ////////////////////////////////////////////////////////////////////////////////
289 // E.3.7 Pairwise Addition
290 def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">;
291 def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
292 def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
294 ////////////////////////////////////////////////////////////////////////////////
295 // E.3.8-9 Folding Max/Min
296 def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">;
297 def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">;
299 ////////////////////////////////////////////////////////////////////////////////
300 // E.3.10 Reciprocal/Sqrt
301 def VRECPS : IInst<"vrecps", "ddd", "fQf">;
302 def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">;
304 ////////////////////////////////////////////////////////////////////////////////
305 // E.3.11 Shifts by signed variable
306 def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
307 def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
308 def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
309 def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
311 ////////////////////////////////////////////////////////////////////////////////
312 // E.3.12 Shifts by constant
314 def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
315 def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
316 def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
317 def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
318 def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
319 def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
320 def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">;
321 def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">;
322 def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">;
323 def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">;
324 def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">;
325 def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">;
326 def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">;
327 def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">;
329 ////////////////////////////////////////////////////////////////////////////////
330 // E.3.13 Shifts with insert
331 def VSRI_N : WInst<"vsri_n", "dddi",
332 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
333 def VSLI_N : WInst<"vsli_n", "dddi",
334 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
337 ////////////////////////////////////////////////////////////////////////////////
338 // E.3.14 Loads and stores of a single vector
339 def VLD1 : WInst<"vld1", "dc",
340 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
341 def VLD1_X2 : WInst<"vld1_x2", "2c",
342 "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
343 def VLD1_X3 : WInst<"vld1_x3", "3c",
344 "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
345 def VLD1_X4 : WInst<"vld1_x4", "4c",
346 "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
347 def VLD1_LANE : WInst<"vld1_lane", "dcdi",
348 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
349 def VLD1_DUP : WInst<"vld1_dup", "dc",
350 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
351 def VST1 : WInst<"vst1", "vpd",
352 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
353 def VST1_X2 : WInst<"vst1_x2", "vp2",
354 "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
355 def VST1_X3 : WInst<"vst1_x3", "vp3",
356 "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
357 def VST1_X4 : WInst<"vst1_x4", "vp4",
358 "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
359 def VST1_LANE : WInst<"vst1_lane", "vpdi",
360 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
362 ////////////////////////////////////////////////////////////////////////////////
363 // E.3.15 Loads and stores of an N-element structure
364 def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
365 def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
366 def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
367 def VLD2_DUP : WInst<"vld2_dup", "2c",
368 "UcUsUiUlcsilhfPcPsQcQfQhQiQlQsQPcQPsQUcQUiQUlQUs">;
369 def VLD3_DUP : WInst<"vld3_dup", "3c",
370 "UcUsUiUlcsilhfPcPsQcQfQhQiQlQsQPcQPsQUcQUiQUlQUs">;
371 def VLD4_DUP : WInst<"vld4_dup", "4c",
372 "UcUsUiUlcsilhfPcPsQcQfQhQiQlQsQPcQPsQUcQUiQUlQUs">;
373 def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
374 def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
375 def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
376 def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
377 def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
378 def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
379 def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
380 def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
381 def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
383 ////////////////////////////////////////////////////////////////////////////////
384 // E.3.16 Extract lanes from a vector
385 let InstName = "vmov" in
386 def VGET_LANE : IInst<"vget_lane", "sdi",
387 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
389 ////////////////////////////////////////////////////////////////////////////////
390 // E.3.17 Set lanes within a vector
391 let InstName = "vmov" in
392 def VSET_LANE : IInst<"vset_lane", "dsdi",
393 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
395 ////////////////////////////////////////////////////////////////////////////////
396 // E.3.18 Initialize a vector from bit pattern
397 def VCREATE : NoTestOpInst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST> {
398 let BigEndianSafe = 1;
401 ////////////////////////////////////////////////////////////////////////////////
402 // E.3.19 Set all lanes to same value
403 let InstName = "vmov" in {
404 def VDUP_N : WOpInst<"vdup_n", "ds",
405 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl",
407 def VMOV_N : WOpInst<"vmov_n", "ds",
408 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl",
412 def VDUP_LANE: WOpInst<"vdup_lane", "dgi",
413 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl",
416 ////////////////////////////////////////////////////////////////////////////////
417 // E.3.20 Combining vectors
418 def VCOMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>;
420 ////////////////////////////////////////////////////////////////////////////////
421 // E.3.21 Splitting vectors
422 // Note that the ARM NEON Reference 2.0 mistakenly document the vget_high_f16()
423 // and vget_low_f16() intrinsics as AArch64-only. We (and GCC) support all
424 // versions of these intrinsics in both AArch32 and AArch64 architectures. See
425 // D45668 for more details.
426 let InstName = "vmov" in {
427 def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
428 def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
431 ////////////////////////////////////////////////////////////////////////////////
432 // E.3.22 Converting vectors
434 let ArchGuard = "(__ARM_FP & 2)" in {
435 def VCVT_F16_F32 : SInst<"vcvt_f16_f32", "md", "Hf">;
436 def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "wd", "h">;
439 def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">;
440 def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">;
441 def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">;
442 let isVCVT_N = 1 in {
443 def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">;
444 def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">;
445 def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">;
448 def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">;
449 def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">;
450 def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">;
451 def VQMOVUN : SInst<"vqmovun", "ek", "sil">;
453 ////////////////////////////////////////////////////////////////////////////////
454 // E.3.23-24 Table lookup, Extended table lookup
455 let InstName = "vtbl" in {
456 def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">;
457 def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">;
458 def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">;
459 def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">;
461 let InstName = "vtbx" in {
462 def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">;
463 def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">;
464 def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">;
465 def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">;
468 ////////////////////////////////////////////////////////////////////////////////
469 // E.3.25 Operations with a scalar value
470 def VMLA_LANE : IOpInst<"vmla_lane", "dddgi",
471 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
472 def VMLAL_LANE : SOpInst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>;
473 def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>;
474 def VMLS_LANE : IOpInst<"vmls_lane", "dddgi",
475 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
476 def VMLSL_LANE : SOpInst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>;
477 def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>;
478 def VMUL_N : IOpInst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
479 def VMUL_LANE : IOpInst<"vmul_lane", "ddgi",
480 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
481 def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">;
482 def VMULL_LANE : SOpInst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>;
483 def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">;
484 def VQDMULL_LANE : SOpInst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>;
485 def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">;
486 def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>;
487 def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">;
488 def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>;
490 let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in {
491 def VQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "dddgi", "siQsQi", OP_QRDMLAH_LN>;
492 def VQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "dddgi", "siQsQi", OP_QRDMLSH_LN>;
495 def VMLA_N : IOpInst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
496 def VMLAL_N : SOpInst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>;
497 def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">;
498 def VMLS_N : IOpInst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>;
499 def VMLSL_N : SOpInst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>;
500 def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">;
502 ////////////////////////////////////////////////////////////////////////////////
503 // E.3.26 Vector Extract
504 def VEXT : WInst<"vext", "dddi",
505 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">;
507 ////////////////////////////////////////////////////////////////////////////////
508 // E.3.27 Reverse vector elements
509 def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
511 def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
512 def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>;
514 ////////////////////////////////////////////////////////////////////////////////
515 // E.3.28 Other single operand arithmetic
516 def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">;
517 def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">;
518 def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>;
519 def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">;
520 def VCLS : SInst<"vcls", "dd", "csiQcQsQi">;
521 def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
522 def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">;
523 def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">;
524 def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">;
526 ////////////////////////////////////////////////////////////////////////////////
527 // E.3.29 Logical operations
528 def VMVN : LOpInst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
529 def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
530 def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
531 def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
532 def VBIC : LOpInst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
533 def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
534 let isHiddenLInst = 1 in
535 def VBSL : SInst<"vbsl", "dudd",
536 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">;
538 ////////////////////////////////////////////////////////////////////////////////
539 // E.3.30 Transposition operations
540 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
541 def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
542 def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
544 ////////////////////////////////////////////////////////////////////////////////
545 // E.3.31 Vector reinterpret cast operations
547 : NoTestOpInst<"vreinterpret", "dd",
548 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT> {
549 let CartesianProductOfTypes = 1;
550 let ArchGuard = "!defined(__aarch64__)";
551 let BigEndianSafe = 1;
554 ////////////////////////////////////////////////////////////////////////////////
555 // Vector fused multiply-add operations
557 let ArchGuard = "defined(__ARM_FEATURE_FMA)" in {
558 def VFMA : SInst<"vfma", "dddd", "fQf">;
559 def VFMS : SOpInst<"vfms", "dddd", "fQf", OP_FMLS>;
560 def FMLA_N_F32 : SOpInst<"vfma_n", "ddds", "fQf", OP_FMLA_N>;
563 ////////////////////////////////////////////////////////////////////////////////
564 // fp16 vector operations
565 def SCALAR_HALF_GET_LANE : IOpInst<"vget_lane", "sdi", "h", OP_SCALAR_HALF_GET_LN>;
566 def SCALAR_HALF_SET_LANE : IOpInst<"vset_lane", "dsdi", "h", OP_SCALAR_HALF_SET_LN>;
567 def SCALAR_HALF_GET_LANEQ : IOpInst<"vget_lane", "sdi", "Qh", OP_SCALAR_HALF_GET_LNQ>;
568 def SCALAR_HALF_SET_LANEQ : IOpInst<"vset_lane", "dsdi", "Qh", OP_SCALAR_HALF_SET_LNQ>;
570 ////////////////////////////////////////////////////////////////////////////////
571 // AArch64 Intrinsics
573 let ArchGuard = "defined(__aarch64__)" in {
575 ////////////////////////////////////////////////////////////////////////////////
577 def LD1 : WInst<"vld1", "dc", "dQdPlQPl">;
578 def LD2 : WInst<"vld2", "2c", "QUlQldQdPlQPl">;
579 def LD3 : WInst<"vld3", "3c", "QUlQldQdPlQPl">;
580 def LD4 : WInst<"vld4", "4c", "QUlQldQdPlQPl">;
581 def ST1 : WInst<"vst1", "vpd", "dQdPlQPl">;
582 def ST2 : WInst<"vst2", "vp2", "QUlQldQdPlQPl">;
583 def ST3 : WInst<"vst3", "vp3", "QUlQldQdPlQPl">;
584 def ST4 : WInst<"vst4", "vp4", "QUlQldQdPlQPl">;
586 def LD1_X2 : WInst<"vld1_x2", "2c",
588 def LD1_X3 : WInst<"vld1_x3", "3c",
590 def LD1_X4 : WInst<"vld1_x4", "4c",
593 def ST1_X2 : WInst<"vst1_x2", "vp2", "dQdPlQPl">;
594 def ST1_X3 : WInst<"vst1_x3", "vp3", "dQdPlQPl">;
595 def ST1_X4 : WInst<"vst1_x4", "vp4", "dQdPlQPl">;
597 def LD1_LANE : WInst<"vld1_lane", "dcdi", "dQdPlQPl">;
598 def LD2_LANE : WInst<"vld2_lane", "2c2i", "lUlQcQUcQPcQlQUldQdPlQPl">;
599 def LD3_LANE : WInst<"vld3_lane", "3c3i", "lUlQcQUcQPcQlQUldQdPlQPl">;
600 def LD4_LANE : WInst<"vld4_lane", "4c4i", "lUlQcQUcQPcQlQUldQdPlQPl">;
601 def ST1_LANE : WInst<"vst1_lane", "vpdi", "dQdPlQPl">;
602 def ST2_LANE : WInst<"vst2_lane", "vp2i", "lUlQcQUcQPcQlQUldQdPlQPl">;
603 def ST3_LANE : WInst<"vst3_lane", "vp3i", "lUlQcQUcQPcQlQUldQdPlQPl">;
604 def ST4_LANE : WInst<"vst4_lane", "vp4i", "lUlQcQUcQPcQlQUldQdPlQPl">;
606 def LD1_DUP : WInst<"vld1_dup", "dc", "dQdPlQPl">;
607 def LD2_DUP : WInst<"vld2_dup", "2c", "dQdPlQPl">;
608 def LD3_DUP : WInst<"vld3_dup", "3c", "dQdPlQPl">;
609 def LD4_DUP : WInst<"vld4_dup", "4c", "dQdPlQPl">;
611 def VLDRQ : WInst<"vldrq", "sc", "Pk">;
612 def VSTRQ : WInst<"vstrq", "vps", "Pk">;
614 ////////////////////////////////////////////////////////////////////////////////
616 def ADD : IOpInst<"vadd", "ddd", "dQd", OP_ADD>;
618 ////////////////////////////////////////////////////////////////////////////////
620 def SUB : IOpInst<"vsub", "ddd", "dQd", OP_SUB>;
622 ////////////////////////////////////////////////////////////////////////////////
624 def MUL : IOpInst<"vmul", "ddd", "dQd", OP_MUL>;
625 def MLA : IOpInst<"vmla", "dddd", "dQd", OP_MLA>;
626 def MLS : IOpInst<"vmls", "dddd", "dQd", OP_MLS>;
628 ////////////////////////////////////////////////////////////////////////////////
629 // Multiplication Extended
630 def MULX : SInst<"vmulx", "ddd", "fdQfQd">;
632 ////////////////////////////////////////////////////////////////////////////////
634 def FDIV : IOpInst<"vdiv", "ddd", "fdQfQd", OP_DIV>;
636 ////////////////////////////////////////////////////////////////////////////////
637 // Vector fused multiply-add operations
638 def FMLA : SInst<"vfma", "dddd", "dQd">;
639 def FMLS : SOpInst<"vfms", "dddd", "dQd", OP_FMLS>;
641 ////////////////////////////////////////////////////////////////////////////////
642 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
643 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
645 def FMLA_N : SOpInst<"vfma_n", "ddds", "dQd", OP_FMLA_N>;
646 def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>;
648 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>;
649 def MLS_N : SOpInst<"vmls_n", "ddds", "Qd", OP_MLS_N>;
651 ////////////////////////////////////////////////////////////////////////////////
652 // Logical operations
653 def BSL : SInst<"vbsl", "dudd", "dPlQdQPl">;
655 ////////////////////////////////////////////////////////////////////////////////
656 // Absolute Difference
657 def ABD : SInst<"vabd", "ddd", "dQd">;
659 ////////////////////////////////////////////////////////////////////////////////
660 // saturating absolute/negate
661 def ABS : SInst<"vabs", "dd", "dQdlQl">;
662 def QABS : SInst<"vqabs", "dd", "lQl">;
663 def NEG : SOpInst<"vneg", "dd", "dlQdQl", OP_NEG>;
664 def QNEG : SInst<"vqneg", "dd", "lQl">;
666 ////////////////////////////////////////////////////////////////////////////////
667 // Signed Saturating Accumulated of Unsigned Value
668 def SUQADD : SInst<"vuqadd", "ddd", "csilQcQsQiQl">;
670 ////////////////////////////////////////////////////////////////////////////////
671 // Unsigned Saturating Accumulated of Signed Value
672 def USQADD : SInst<"vsqadd", "ddd", "UcUsUiUlQUcQUsQUiQUl">;
674 ////////////////////////////////////////////////////////////////////////////////
676 def FRECPS : IInst<"vrecps", "ddd", "dQd">;
677 def FRSQRTS : IInst<"vrsqrts", "ddd", "dQd">;
678 def FRECPE : SInst<"vrecpe", "dd", "dQd">;
679 def FRSQRTE : SInst<"vrsqrte", "dd", "dQd">;
680 def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">;
682 ////////////////////////////////////////////////////////////////////////////////
684 def RBIT : IInst<"vrbit", "dd", "cUcPcQcQUcQPc">;
686 ////////////////////////////////////////////////////////////////////////////////
687 // Integer extract and narrow to high
688 def XTN2 : SOpInst<"vmovn_high", "qhk", "silUsUiUl", OP_XTN>;
690 ////////////////////////////////////////////////////////////////////////////////
691 // Signed integer saturating extract and unsigned narrow to high
692 def SQXTUN2 : SOpInst<"vqmovun_high", "emd", "HsHiHl", OP_SQXTUN>;
694 ////////////////////////////////////////////////////////////////////////////////
695 // Integer saturating extract and narrow to high
696 def QXTN2 : SOpInst<"vqmovn_high", "qhk", "silUsUiUl", OP_QXTN>;
698 ////////////////////////////////////////////////////////////////////////////////
699 // Converting vectors
701 def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "md", "Qd">;
702 def VCVT_F64_F32 : SInst<"vcvt_f64_f32", "wd", "f">;
704 def VCVT_S64 : SInst<"vcvt_s64", "xd", "dQd">;
705 def VCVT_U64 : SInst<"vcvt_u64", "ud", "dQd">;
706 def VCVT_F64 : SInst<"vcvt_f64", "Fd", "lUlQlQUl">;
708 def VCVT_HIGH_F16_F32 : SOpInst<"vcvt_high_f16", "hmj", "Hf", OP_VCVT_NA_HI_F16>;
709 def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "wk", "h", OP_VCVT_EX_HI_F32>;
710 def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "qfj", "d", OP_VCVT_NA_HI_F32>;
711 def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "wj", "f", OP_VCVT_EX_HI_F64>;
713 def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">;
714 def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "qfj", "d", OP_VCVTX_HI>;
716 ////////////////////////////////////////////////////////////////////////////////
718 def FCAGE : IInst<"vcage", "udd", "dQd">;
719 def FCAGT : IInst<"vcagt", "udd", "dQd">;
720 def FCALE : IInst<"vcale", "udd", "dQd">;
721 def FCALT : IInst<"vcalt", "udd", "dQd">;
722 def CMTST : WInst<"vtst", "udd", "lUlPlQlQUlQPl">;
723 def CFMEQ : SOpInst<"vceq", "udd", "lUldQdQlQUlPlQPl", OP_EQ>;
724 def CFMGE : SOpInst<"vcge", "udd", "lUldQdQlQUl", OP_GE>;
725 def CFMLE : SOpInst<"vcle", "udd", "lUldQdQlQUl", OP_LE>;
726 def CFMGT : SOpInst<"vcgt", "udd", "lUldQdQlQUl", OP_GT>;
727 def CFMLT : SOpInst<"vclt", "udd", "lUldQdQlQUl", OP_LT>;
729 def CMEQ : SInst<"vceqz", "ud",
730 "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">;
731 def CMGE : SInst<"vcgez", "ud", "csilfdQcQsQiQlQfQd">;
732 def CMLE : SInst<"vclez", "ud", "csilfdQcQsQiQlQfQd">;
733 def CMGT : SInst<"vcgtz", "ud", "csilfdQcQsQiQlQfQd">;
734 def CMLT : SInst<"vcltz", "ud", "csilfdQcQsQiQlQfQd">;
736 ////////////////////////////////////////////////////////////////////////////////
738 def MAX : SInst<"vmax", "ddd", "dQd">;
739 def MIN : SInst<"vmin", "ddd", "dQd">;
741 ////////////////////////////////////////////////////////////////////////////////
743 def MAXP : SInst<"vpmax", "ddd", "QcQsQiQUcQUsQUiQfQd">;
744 def MINP : SInst<"vpmin", "ddd", "QcQsQiQUcQUsQUiQfQd">;
746 ////////////////////////////////////////////////////////////////////////////////
747 // Pairwise MaxNum/MinNum Floating Point
748 def FMAXNMP : SInst<"vpmaxnm", "ddd", "fQfQd">;
749 def FMINNMP : SInst<"vpminnm", "ddd", "fQfQd">;
751 ////////////////////////////////////////////////////////////////////////////////
753 def ADDP : IInst<"vpadd", "ddd", "QcQsQiQlQUcQUsQUiQUlQfQd">;
755 ////////////////////////////////////////////////////////////////////////////////
756 // Shifts by constant
758 // Left shift long high
759 def SHLL_HIGH_N : SOpInst<"vshll_high_n", "ndi", "HcHsHiHUcHUsHUi",
762 ////////////////////////////////////////////////////////////////////////////////
763 def SRI_N : WInst<"vsri_n", "dddi", "PlQPl">;
764 def SLI_N : WInst<"vsli_n", "dddi", "PlQPl">;
766 // Right shift narrow high
767 def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "hmdi",
768 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
769 def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "hmdi",
770 "HsHiHl", OP_NARROW_HI>;
771 def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "hmdi",
772 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
773 def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "hmdi",
774 "HsHiHl", OP_NARROW_HI>;
775 def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "hmdi",
776 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
777 def QRSHRN_HIGH_N : SOpInst<"vqrshrn_high_n", "hmdi",
778 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
781 ////////////////////////////////////////////////////////////////////////////////
782 // Converting vectors
783 def VMOVL_HIGH : SOpInst<"vmovl_high", "nd", "HcHsHiHUcHUsHUi", OP_MOVL_HI>;
785 let isVCVT_N = 1 in {
786 def CVTF_N_F64 : SInst<"vcvt_n_f64", "Fdi", "lUlQlQUl">;
787 def FCVTZS_N_S64 : SInst<"vcvt_n_s64", "xdi", "dQd">;
788 def FCVTZS_N_U64 : SInst<"vcvt_n_u64", "udi", "dQd">;
791 ////////////////////////////////////////////////////////////////////////////////
792 // 3VDiff class using high 64-bit in operands
793 def VADDL_HIGH : SOpInst<"vaddl_high", "wkk", "csiUcUsUi", OP_ADDLHi>;
794 def VADDW_HIGH : SOpInst<"vaddw_high", "wwk", "csiUcUsUi", OP_ADDWHi>;
795 def VSUBL_HIGH : SOpInst<"vsubl_high", "wkk", "csiUcUsUi", OP_SUBLHi>;
796 def VSUBW_HIGH : SOpInst<"vsubw_high", "wwk", "csiUcUsUi", OP_SUBWHi>;
798 def VABDL_HIGH : SOpInst<"vabdl_high", "wkk", "csiUcUsUi", OP_ABDLHi>;
799 def VABAL_HIGH : SOpInst<"vabal_high", "wwkk", "csiUcUsUi", OP_ABALHi>;
801 def VMULL_HIGH : SOpInst<"vmull_high", "wkk", "csiUcUsUiPc", OP_MULLHi>;
802 def VMULL_HIGH_N : SOpInst<"vmull_high_n", "wks", "siUsUi", OP_MULLHi_N>;
803 def VMLAL_HIGH : SOpInst<"vmlal_high", "wwkk", "csiUcUsUi", OP_MLALHi>;
804 def VMLAL_HIGH_N : SOpInst<"vmlal_high_n", "wwks", "siUsUi", OP_MLALHi_N>;
805 def VMLSL_HIGH : SOpInst<"vmlsl_high", "wwkk", "csiUcUsUi", OP_MLSLHi>;
806 def VMLSL_HIGH_N : SOpInst<"vmlsl_high_n", "wwks", "siUsUi", OP_MLSLHi_N>;
808 def VADDHN_HIGH : SOpInst<"vaddhn_high", "qhkk", "silUsUiUl", OP_ADDHNHi>;
809 def VRADDHN_HIGH : SOpInst<"vraddhn_high", "qhkk", "silUsUiUl", OP_RADDHNHi>;
810 def VSUBHN_HIGH : SOpInst<"vsubhn_high", "qhkk", "silUsUiUl", OP_SUBHNHi>;
811 def VRSUBHN_HIGH : SOpInst<"vrsubhn_high", "qhkk", "silUsUiUl", OP_RSUBHNHi>;
813 def VQDMULL_HIGH : SOpInst<"vqdmull_high", "wkk", "si", OP_QDMULLHi>;
814 def VQDMULL_HIGH_N : SOpInst<"vqdmull_high_n", "wks", "si", OP_QDMULLHi_N>;
815 def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "wwkk", "si", OP_QDMLALHi>;
816 def VQDMLAL_HIGH_N : SOpInst<"vqdmlal_high_n", "wwks", "si", OP_QDMLALHi_N>;
817 def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "wwkk", "si", OP_QDMLSLHi>;
818 def VQDMLSL_HIGH_N : SOpInst<"vqdmlsl_high_n", "wwks", "si", OP_QDMLSLHi_N>;
819 def VMULL_P64 : SInst<"vmull", "rss", "Pl">;
820 def VMULL_HIGH_P64 : SOpInst<"vmull_high", "rdd", "HPl", OP_MULLHi_P64>;
823 ////////////////////////////////////////////////////////////////////////////////
824 // Extract or insert element from vector
825 def GET_LANE : IInst<"vget_lane", "sdi", "dQdPlQPl">;
826 def SET_LANE : IInst<"vset_lane", "dsdi", "dQdPlQPl">;
827 def COPY_LANE : IOpInst<"vcopy_lane", "ddidi",
828 "csilUcUsUiUlPcPsPlfd", OP_COPY_LN>;
829 def COPYQ_LANE : IOpInst<"vcopy_lane", "ddigi",
830 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>;
831 def COPY_LANEQ : IOpInst<"vcopy_laneq", "ddiki",
832 "csilPcPsPlUcUsUiUlfd", OP_COPY_LN>;
833 def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "ddidi",
834 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>;
836 ////////////////////////////////////////////////////////////////////////////////
837 // Set all lanes to same value
838 def VDUP_LANE1: WOpInst<"vdup_lane", "dgi", "hdQhQdPlQPl", OP_DUP_LN>;
839 def VDUP_LANE2: WOpInst<"vdup_laneq", "dji",
840 "csilUcUsUiUlPcPshfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl",
842 def DUP_N : WOpInst<"vdup_n", "ds", "dQdPlQPl", OP_DUP>;
843 def MOV_N : WOpInst<"vmov_n", "ds", "dQdPlQPl", OP_DUP>;
845 ////////////////////////////////////////////////////////////////////////////////
846 def COMBINE : NoTestOpInst<"vcombine", "kdd", "dPl", OP_CONC>;
848 ////////////////////////////////////////////////////////////////////////////////
849 //Initialize a vector from bit pattern
850 def CREATE : NoTestOpInst<"vcreate", "dl", "dPl", OP_CAST> {
851 let BigEndianSafe = 1;
854 ////////////////////////////////////////////////////////////////////////////////
856 def VMLA_LANEQ : IOpInst<"vmla_laneq", "dddji",
857 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
858 def VMLS_LANEQ : IOpInst<"vmls_laneq", "dddji",
859 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
861 def VFMA_LANE : IInst<"vfma_lane", "dddgi", "fdQfQd">;
862 def VFMA_LANEQ : IInst<"vfma_laneq", "dddji", "fdQfQd"> {
865 def VFMS_LANE : IOpInst<"vfms_lane", "dddgi", "fdQfQd", OP_FMS_LN>;
866 def VFMS_LANEQ : IOpInst<"vfms_laneq", "dddji", "fdQfQd", OP_FMS_LNQ>;
868 def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "wwdki", "siUsUi", OP_MLAL_LN>;
869 def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "wwkdi", "siUsUi",
871 def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "wwkki", "siUsUi",
873 def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "wwdki", "siUsUi", OP_MLSL_LN>;
874 def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "wwkdi", "siUsUi",
876 def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "wwkki", "siUsUi",
879 def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "wwdki", "si", OP_QDMLAL_LN>;
880 def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "wwkdi", "si",
882 def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "wwkki", "si",
884 def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "wwdki", "si", OP_QDMLSL_LN>;
885 def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "wwkdi", "si",
887 def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "wwkki", "si",
890 // Newly add double parameter for vmul_lane in aarch64
891 // Note: d type is handled by SCALAR_VMUL_LANE
892 def VMUL_LANE_A64 : IOpInst<"vmul_lane", "ddgi", "Qd", OP_MUL_LN>;
894 // Note: d type is handled by SCALAR_VMUL_LANEQ
895 def VMUL_LANEQ : IOpInst<"vmul_laneq", "ddji",
896 "sifUsUiQsQiQUsQUiQfQd", OP_MUL_LN>;
897 def VMULL_LANEQ : SOpInst<"vmull_laneq", "wdki", "siUsUi", OP_MULL_LN>;
898 def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "wkdi", "siUsUi",
900 def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "wkki", "siUsUi",
903 def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "wdki", "si", OP_QDMULL_LN>;
904 def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "wkdi", "si",
906 def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "wkki", "si",
909 def VQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ddji", "siQsQi", OP_QDMULH_LN>;
910 def VQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ddji", "siQsQi", OP_QRDMULH_LN>;
912 let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in {
913 def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "dddji", "siQsQi", OP_QRDMLAH_LN>;
914 def VQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "dddji", "siQsQi", OP_QRDMLSH_LN>;
917 // Note: d type implemented by SCALAR_VMULX_LANE
918 def VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "fQfQd", OP_MULX_LN>;
919 // Note: d type is implemented by SCALAR_VMULX_LANEQ
920 def VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "fQfQd", OP_MULX_LN>;
922 ////////////////////////////////////////////////////////////////////////////////
923 // Across vectors class
924 def VADDLV : SInst<"vaddlv", "rd", "csiUcUsUiQcQsQiQUcQUsQUi">;
925 def VMAXV : SInst<"vmaxv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
926 def VMINV : SInst<"vminv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
927 def VADDV : SInst<"vaddv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">;
928 def FMAXNMV : SInst<"vmaxnmv", "sd", "fQfQd">;
929 def FMINNMV : SInst<"vminnmv", "sd", "fQfQd">;
931 ////////////////////////////////////////////////////////////////////////////////
932 // Newly added Vector Extract for f64
933 def VEXT_A64 : WInst<"vext", "dddi", "dQdPlQPl">;
935 ////////////////////////////////////////////////////////////////////////////////
937 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_CRYPTO)" in {
938 def AESE : SInst<"vaese", "ddd", "QUc">;
939 def AESD : SInst<"vaesd", "ddd", "QUc">;
940 def AESMC : SInst<"vaesmc", "dd", "QUc">;
941 def AESIMC : SInst<"vaesimc", "dd", "QUc">;
943 def SHA1H : SInst<"vsha1h", "ss", "Ui">;
944 def SHA1SU1 : SInst<"vsha1su1", "ddd", "QUi">;
945 def SHA256SU0 : SInst<"vsha256su0", "ddd", "QUi">;
947 def SHA1C : SInst<"vsha1c", "ddsd", "QUi">;
948 def SHA1P : SInst<"vsha1p", "ddsd", "QUi">;
949 def SHA1M : SInst<"vsha1m", "ddsd", "QUi">;
950 def SHA1SU0 : SInst<"vsha1su0", "dddd", "QUi">;
951 def SHA256H : SInst<"vsha256h", "dddd", "QUi">;
952 def SHA256H2 : SInst<"vsha256h2", "dddd", "QUi">;
953 def SHA256SU1 : SInst<"vsha256su1", "dddd", "QUi">;
956 ////////////////////////////////////////////////////////////////////////////////
957 // Float -> Int conversions with explicit rounding mode
959 let ArchGuard = "__ARM_ARCH >= 8" in {
960 def FCVTNS_S32 : SInst<"vcvtn_s32", "xd", "fQf">;
961 def FCVTNU_S32 : SInst<"vcvtn_u32", "ud", "fQf">;
962 def FCVTPS_S32 : SInst<"vcvtp_s32", "xd", "fQf">;
963 def FCVTPU_S32 : SInst<"vcvtp_u32", "ud", "fQf">;
964 def FCVTMS_S32 : SInst<"vcvtm_s32", "xd", "fQf">;
965 def FCVTMU_S32 : SInst<"vcvtm_u32", "ud", "fQf">;
966 def FCVTAS_S32 : SInst<"vcvta_s32", "xd", "fQf">;
967 def FCVTAU_S32 : SInst<"vcvta_u32", "ud", "fQf">;
970 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
971 def FCVTNS_S64 : SInst<"vcvtn_s64", "xd", "dQd">;
972 def FCVTNU_S64 : SInst<"vcvtn_u64", "ud", "dQd">;
973 def FCVTPS_S64 : SInst<"vcvtp_s64", "xd", "dQd">;
974 def FCVTPU_S64 : SInst<"vcvtp_u64", "ud", "dQd">;
975 def FCVTMS_S64 : SInst<"vcvtm_s64", "xd", "dQd">;
976 def FCVTMU_S64 : SInst<"vcvtm_u64", "ud", "dQd">;
977 def FCVTAS_S64 : SInst<"vcvta_s64", "xd", "dQd">;
978 def FCVTAU_S64 : SInst<"vcvta_u64", "ud", "dQd">;
981 ////////////////////////////////////////////////////////////////////////////////
984 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
985 def FRINTN_S32 : SInst<"vrndn", "dd", "fQf">;
986 def FRINTA_S32 : SInst<"vrnda", "dd", "fQf">;
987 def FRINTP_S32 : SInst<"vrndp", "dd", "fQf">;
988 def FRINTM_S32 : SInst<"vrndm", "dd", "fQf">;
989 def FRINTX_S32 : SInst<"vrndx", "dd", "fQf">;
990 def FRINTZ_S32 : SInst<"vrnd", "dd", "fQf">;
991 def FRINTI_S32 : SInst<"vrndi", "dd", "fQf">;
994 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
995 def FRINTN_S64 : SInst<"vrndn", "dd", "dQd">;
996 def FRINTA_S64 : SInst<"vrnda", "dd", "dQd">;
997 def FRINTP_S64 : SInst<"vrndp", "dd", "dQd">;
998 def FRINTM_S64 : SInst<"vrndm", "dd", "dQd">;
999 def FRINTX_S64 : SInst<"vrndx", "dd", "dQd">;
1000 def FRINTZ_S64 : SInst<"vrnd", "dd", "dQd">;
1001 def FRINTI_S64 : SInst<"vrndi", "dd", "dQd">;
1004 ////////////////////////////////////////////////////////////////////////////////
1005 // MaxNum/MinNum Floating Point
1007 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in {
1008 def FMAXNM_S32 : SInst<"vmaxnm", "ddd", "fQf">;
1009 def FMINNM_S32 : SInst<"vminnm", "ddd", "fQf">;
1012 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in {
1013 def FMAXNM_S64 : SInst<"vmaxnm", "ddd", "dQd">;
1014 def FMINNM_S64 : SInst<"vminnm", "ddd", "dQd">;
1017 ////////////////////////////////////////////////////////////////////////////////
1019 def VTRN1 : SOpInst<"vtrn1", "ddd",
1020 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN1>;
1021 def VZIP1 : SOpInst<"vzip1", "ddd",
1022 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP1>;
1023 def VUZP1 : SOpInst<"vuzp1", "ddd",
1024 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP1>;
1025 def VTRN2 : SOpInst<"vtrn2", "ddd",
1026 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN2>;
1027 def VZIP2 : SOpInst<"vzip2", "ddd",
1028 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP2>;
1029 def VUZP2 : SOpInst<"vuzp2", "ddd",
1030 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP2>;
1032 ////////////////////////////////////////////////////////////////////////////////
1034 let InstName = "vtbl" in {
1035 def VQTBL1_A64 : WInst<"vqtbl1", "djt", "UccPcQUcQcQPc">;
1036 def VQTBL2_A64 : WInst<"vqtbl2", "dBt", "UccPcQUcQcQPc">;
1037 def VQTBL3_A64 : WInst<"vqtbl3", "dCt", "UccPcQUcQcQPc">;
1038 def VQTBL4_A64 : WInst<"vqtbl4", "dDt", "UccPcQUcQcQPc">;
1040 let InstName = "vtbx" in {
1041 def VQTBX1_A64 : WInst<"vqtbx1", "ddjt", "UccPcQUcQcQPc">;
1042 def VQTBX2_A64 : WInst<"vqtbx2", "ddBt", "UccPcQUcQcQPc">;
1043 def VQTBX3_A64 : WInst<"vqtbx3", "ddCt", "UccPcQUcQcQPc">;
1044 def VQTBX4_A64 : WInst<"vqtbx4", "ddDt", "UccPcQUcQcQPc">;
1047 ////////////////////////////////////////////////////////////////////////////////
1048 // Vector reinterpret cast operations
1050 // NeonEmitter implicitly takes the cartesian product of the type string with
1051 // itself during generation so, unlike all other intrinsics, this one should
1052 // include *all* types, not just additional ones.
1054 : NoTestOpInst<"vreinterpret", "dd",
1055 "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", OP_REINT> {
1056 let CartesianProductOfTypes = 1;
1057 let BigEndianSafe = 1;
1058 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)";
1061 ////////////////////////////////////////////////////////////////////////////////
1062 // Scalar Intrinsics
1063 // Scalar Arithmetic
1066 def SCALAR_ADD : SInst<"vadd", "sss", "SlSUl">;
1067 // Scalar Saturating Add
1068 def SCALAR_QADD : SInst<"vqadd", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1070 // Scalar Subtraction
1071 def SCALAR_SUB : SInst<"vsub", "sss", "SlSUl">;
1072 // Scalar Saturating Sub
1073 def SCALAR_QSUB : SInst<"vqsub", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1075 let InstName = "vmov" in {
1076 def VGET_HIGH_A64 : NoTestOpInst<"vget_high", "dk", "dPl", OP_HI>;
1077 def VGET_LOW_A64 : NoTestOpInst<"vget_low", "dk", "dPl", OP_LO>;
1080 ////////////////////////////////////////////////////////////////////////////////
1082 // Scalar Shift Left
1083 def SCALAR_SHL: SInst<"vshl", "sss", "SlSUl">;
1084 // Scalar Saturating Shift Left
1085 def SCALAR_QSHL: SInst<"vqshl", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1086 // Scalar Saturating Rounding Shift Left
1087 def SCALAR_QRSHL: SInst<"vqrshl", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1088 // Scalar Shift Rounding Left
1089 def SCALAR_RSHL: SInst<"vrshl", "sss", "SlSUl">;
1091 ////////////////////////////////////////////////////////////////////////////////
1092 // Scalar Shift (Immediate)
1093 let isScalarShift = 1 in {
1094 // Signed/Unsigned Shift Right (Immediate)
1095 def SCALAR_SSHR_N: SInst<"vshr_n", "ssi", "SlSUl">;
1096 // Signed/Unsigned Rounding Shift Right (Immediate)
1097 def SCALAR_SRSHR_N: SInst<"vrshr_n", "ssi", "SlSUl">;
1099 // Signed/Unsigned Shift Right and Accumulate (Immediate)
1100 def SCALAR_SSRA_N: SInst<"vsra_n", "sssi", "SlSUl">;
1101 // Signed/Unsigned Rounding Shift Right and Accumulate (Immediate)
1102 def SCALAR_SRSRA_N: SInst<"vrsra_n", "sssi", "SlSUl">;
1104 // Shift Left (Immediate)
1105 def SCALAR_SHL_N: SInst<"vshl_n", "ssi", "SlSUl">;
1106 // Signed/Unsigned Saturating Shift Left (Immediate)
1107 def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">;
1108 // Signed Saturating Shift Left Unsigned (Immediate)
1109 def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">;
1111 // Shift Right And Insert (Immediate)
1112 def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">;
1113 // Shift Left And Insert (Immediate)
1114 def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">;
1116 let isScalarNarrowShift = 1 in {
1117 // Signed/Unsigned Saturating Shift Right Narrow (Immediate)
1118 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">;
1119 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)
1120 def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "zsi", "SsSiSlSUsSUiSUl">;
1121 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
1122 def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "zsi", "SsSiSl">;
1123 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
1124 def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "zsi", "SsSiSl">;
1127 ////////////////////////////////////////////////////////////////////////////////
1128 // Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate)
1129 def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "ysi", "SiSUi">;
1130 def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "osi", "SlSUl">;
1132 ////////////////////////////////////////////////////////////////////////////////
1133 // Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate)
1134 def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "$si", "Sf">;
1135 def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "bsi", "Sf">;
1136 def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "$si", "Sd">;
1137 def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "bsi", "Sd">;
1140 ////////////////////////////////////////////////////////////////////////////////
1141 // Scalar Floating-point Round to Integral
1142 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
1143 def SCALAR_FRINTN_S32 : SInst<"vrndn", "ss", "Sf">;
1146 ////////////////////////////////////////////////////////////////////////////////
1147 // Scalar Reduce Pairwise Addition (Scalar and Floating Point)
1148 def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHdSHUl">;
1150 ////////////////////////////////////////////////////////////////////////////////
1151 // Scalar Reduce Floating Point Pairwise Max/Min
1152 def SCALAR_FMAXP : SInst<"vpmax", "sd", "SfSQd">;
1154 def SCALAR_FMINP : SInst<"vpmin", "sd", "SfSQd">;
1156 ////////////////////////////////////////////////////////////////////////////////
1157 // Scalar Reduce Floating Point Pairwise maxNum/minNum
1158 def SCALAR_FMAXNMP : SInst<"vpmaxnm", "sd", "SfSQd">;
1159 def SCALAR_FMINNMP : SInst<"vpminnm", "sd", "SfSQd">;
1161 ////////////////////////////////////////////////////////////////////////////////
1162 // Scalar Integer Saturating Doubling Multiply Half High
1163 def SCALAR_SQDMULH : SInst<"vqdmulh", "sss", "SsSi">;
1165 ////////////////////////////////////////////////////////////////////////////////
1166 // Scalar Integer Saturating Rounding Doubling Multiply Half High
1167 def SCALAR_SQRDMULH : SInst<"vqrdmulh", "sss", "SsSi">;
1169 let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in {
1170 ////////////////////////////////////////////////////////////////////////////////
1171 // Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half
1172 def SCALAR_SQRDMLAH : SOpInst<"vqrdmlah", "ssss", "SsSi", OP_QRDMLAH>;
1174 ////////////////////////////////////////////////////////////////////////////////
1175 // Signed Saturating Rounding Doubling Multiply Subtract Returning High Half
1176 def SCALAR_SQRDMLSH : SOpInst<"vqrdmlsh", "ssss", "SsSi", OP_QRDMLSH>;
1179 ////////////////////////////////////////////////////////////////////////////////
1180 // Scalar Floating-point Multiply Extended
1181 def SCALAR_FMULX : IInst<"vmulx", "sss", "SfSd">;
1183 ////////////////////////////////////////////////////////////////////////////////
1184 // Scalar Floating-point Reciprocal Step
1185 def SCALAR_FRECPS : IInst<"vrecps", "sss", "SfSd">;
1187 ////////////////////////////////////////////////////////////////////////////////
1188 // Scalar Floating-point Reciprocal Square Root Step
1189 def SCALAR_FRSQRTS : IInst<"vrsqrts", "sss", "SfSd">;
1191 ////////////////////////////////////////////////////////////////////////////////
1192 // Scalar Signed Integer Convert To Floating-point
1193 def SCALAR_SCVTFS : SInst<"vcvt_f32", "ys", "Si">;
1194 def SCALAR_SCVTFD : SInst<"vcvt_f64", "os", "Sl">;
1196 ////////////////////////////////////////////////////////////////////////////////
1197 // Scalar Unsigned Integer Convert To Floating-point
1198 def SCALAR_UCVTFS : SInst<"vcvt_f32", "ys", "SUi">;
1199 def SCALAR_UCVTFD : SInst<"vcvt_f64", "os", "SUl">;
1201 ////////////////////////////////////////////////////////////////////////////////
1202 // Scalar Floating-point Converts
1203 def SCALAR_FCVTXN : IInst<"vcvtx_f32", "ys", "Sd">;
1204 def SCALAR_FCVTNSS : SInst<"vcvtn_s32", "$s", "Sf">;
1205 def SCALAR_FCVTNUS : SInst<"vcvtn_u32", "bs", "Sf">;
1206 def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "$s", "Sd">;
1207 def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "bs", "Sd">;
1208 def SCALAR_FCVTMSS : SInst<"vcvtm_s32", "$s", "Sf">;
1209 def SCALAR_FCVTMUS : SInst<"vcvtm_u32", "bs", "Sf">;
1210 def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "$s", "Sd">;
1211 def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "bs", "Sd">;
1212 def SCALAR_FCVTASS : SInst<"vcvta_s32", "$s", "Sf">;
1213 def SCALAR_FCVTAUS : SInst<"vcvta_u32", "bs", "Sf">;
1214 def SCALAR_FCVTASD : SInst<"vcvta_s64", "$s", "Sd">;
1215 def SCALAR_FCVTAUD : SInst<"vcvta_u64", "bs", "Sd">;
1216 def SCALAR_FCVTPSS : SInst<"vcvtp_s32", "$s", "Sf">;
1217 def SCALAR_FCVTPUS : SInst<"vcvtp_u32", "bs", "Sf">;
1218 def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "$s", "Sd">;
1219 def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "bs", "Sd">;
1220 def SCALAR_FCVTZSS : SInst<"vcvt_s32", "$s", "Sf">;
1221 def SCALAR_FCVTZUS : SInst<"vcvt_u32", "bs", "Sf">;
1222 def SCALAR_FCVTZSD : SInst<"vcvt_s64", "$s", "Sd">;
1223 def SCALAR_FCVTZUD : SInst<"vcvt_u64", "bs", "Sd">;
1225 ////////////////////////////////////////////////////////////////////////////////
1226 // Scalar Floating-point Reciprocal Estimate
1227 def SCALAR_FRECPE : IInst<"vrecpe", "ss", "SfSd">;
1229 ////////////////////////////////////////////////////////////////////////////////
1230 // Scalar Floating-point Reciprocal Exponent
1231 def SCALAR_FRECPX : IInst<"vrecpx", "ss", "SfSd">;
1233 ////////////////////////////////////////////////////////////////////////////////
1234 // Scalar Floating-point Reciprocal Square Root Estimate
1235 def SCALAR_FRSQRTE : IInst<"vrsqrte", "ss", "SfSd">;
1237 ////////////////////////////////////////////////////////////////////////////////
1238 // Scalar Integer Comparison
1239 def SCALAR_CMEQ : SInst<"vceq", "sss", "SlSUl">;
1240 def SCALAR_CMEQZ : SInst<"vceqz", "ss", "SlSUl">;
1241 def SCALAR_CMGE : SInst<"vcge", "sss", "Sl">;
1242 def SCALAR_CMGEZ : SInst<"vcgez", "ss", "Sl">;
1243 def SCALAR_CMHS : SInst<"vcge", "sss", "SUl">;
1244 def SCALAR_CMLE : SInst<"vcle", "sss", "SlSUl">;
1245 def SCALAR_CMLEZ : SInst<"vclez", "ss", "Sl">;
1246 def SCALAR_CMLT : SInst<"vclt", "sss", "SlSUl">;
1247 def SCALAR_CMLTZ : SInst<"vcltz", "ss", "Sl">;
1248 def SCALAR_CMGT : SInst<"vcgt", "sss", "Sl">;
1249 def SCALAR_CMGTZ : SInst<"vcgtz", "ss", "Sl">;
1250 def SCALAR_CMHI : SInst<"vcgt", "sss", "SUl">;
1251 def SCALAR_CMTST : SInst<"vtst", "sss", "SlSUl">;
1253 ////////////////////////////////////////////////////////////////////////////////
1254 // Scalar Floating-point Comparison
1255 def SCALAR_FCMEQ : IInst<"vceq", "bss", "SfSd">;
1256 def SCALAR_FCMEQZ : IInst<"vceqz", "bs", "SfSd">;
1257 def SCALAR_FCMGE : IInst<"vcge", "bss", "SfSd">;
1258 def SCALAR_FCMGEZ : IInst<"vcgez", "bs", "SfSd">;
1259 def SCALAR_FCMGT : IInst<"vcgt", "bss", "SfSd">;
1260 def SCALAR_FCMGTZ : IInst<"vcgtz", "bs", "SfSd">;
1261 def SCALAR_FCMLE : IInst<"vcle", "bss", "SfSd">;
1262 def SCALAR_FCMLEZ : IInst<"vclez", "bs", "SfSd">;
1263 def SCALAR_FCMLT : IInst<"vclt", "bss", "SfSd">;
1264 def SCALAR_FCMLTZ : IInst<"vcltz", "bs", "SfSd">;
1266 ////////////////////////////////////////////////////////////////////////////////
1267 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
1268 def SCALAR_FACGE : IInst<"vcage", "bss", "SfSd">;
1269 def SCALAR_FACLE : IInst<"vcale", "bss", "SfSd">;
1271 ////////////////////////////////////////////////////////////////////////////////
1272 // Scalar Floating-point Absolute Compare Mask Greater Than
1273 def SCALAR_FACGT : IInst<"vcagt", "bss", "SfSd">;
1274 def SCALAR_FACLT : IInst<"vcalt", "bss", "SfSd">;
1276 ////////////////////////////////////////////////////////////////////////////////
1277 // Scalar Absolute Value
1278 def SCALAR_ABS : SInst<"vabs", "ss", "Sl">;
1280 ////////////////////////////////////////////////////////////////////////////////
1281 // Scalar Absolute Difference
1282 def SCALAR_ABD : IInst<"vabd", "sss", "SfSd">;
1284 ////////////////////////////////////////////////////////////////////////////////
1285 // Scalar Signed Saturating Absolute Value
1286 def SCALAR_SQABS : SInst<"vqabs", "ss", "ScSsSiSl">;
1288 ////////////////////////////////////////////////////////////////////////////////
1290 def SCALAR_NEG : SInst<"vneg", "ss", "Sl">;
1292 ////////////////////////////////////////////////////////////////////////////////
1293 // Scalar Signed Saturating Negate
1294 def SCALAR_SQNEG : SInst<"vqneg", "ss", "ScSsSiSl">;
1296 ////////////////////////////////////////////////////////////////////////////////
1297 // Scalar Signed Saturating Accumulated of Unsigned Value
1298 def SCALAR_SUQADD : SInst<"vuqadd", "sss", "ScSsSiSl">;
1300 ////////////////////////////////////////////////////////////////////////////////
1301 // Scalar Unsigned Saturating Accumulated of Signed Value
1302 def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">;
1304 ////////////////////////////////////////////////////////////////////////////////
1305 // Signed Saturating Doubling Multiply-Add Long
1306 def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">;
1308 ////////////////////////////////////////////////////////////////////////////////
1309 // Signed Saturating Doubling Multiply-Subtract Long
1310 def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">;
1312 ////////////////////////////////////////////////////////////////////////////////
1313 // Signed Saturating Doubling Multiply Long
1314 def SCALAR_SQDMULL : SInst<"vqdmull", "rss", "SsSi">;
1316 ////////////////////////////////////////////////////////////////////////////////
1317 // Scalar Signed Saturating Extract Unsigned Narrow
1318 def SCALAR_SQXTUN : SInst<"vqmovun", "zs", "SsSiSl">;
1320 ////////////////////////////////////////////////////////////////////////////////
1321 // Scalar Signed Saturating Extract Narrow
1322 def SCALAR_SQXTN : SInst<"vqmovn", "zs", "SsSiSl">;
1324 ////////////////////////////////////////////////////////////////////////////////
1325 // Scalar Unsigned Saturating Extract Narrow
1326 def SCALAR_UQXTN : SInst<"vqmovn", "zs", "SUsSUiSUl">;
1328 // Scalar Floating Point multiply (scalar, by element)
1329 def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "ssdi", "SfSd", OP_SCALAR_MUL_LN>;
1330 def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "ssji", "SfSd", OP_SCALAR_MUL_LN>;
1332 // Scalar Floating Point multiply extended (scalar, by element)
1333 def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "ssdi", "SfSd", OP_SCALAR_MULX_LN>;
1334 def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "ssji", "SfSd", OP_SCALAR_MULX_LN>;
1336 def SCALAR_VMUL_N : IInst<"vmul_n", "dds", "d">;
1338 // VMUL_LANE_A64 d type implemented using scalar mul lane
1339 def SCALAR_VMUL_LANE : IInst<"vmul_lane", "ddgi", "d">;
1341 // VMUL_LANEQ d type implemented using scalar mul lane
1342 def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "ddji", "d"> {
1346 // VMULX_LANE d type implemented using scalar vmulx_lane
1347 def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "d", OP_SCALAR_VMULX_LN>;
1349 // VMULX_LANEQ d type implemented using scalar vmulx_laneq
1350 def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "d", OP_SCALAR_VMULX_LNQ>;
1352 // Scalar Floating Point fused multiply-add (scalar, by element)
1353 def SCALAR_FMLA_LANE : IInst<"vfma_lane", "sssdi", "SfSd">;
1354 def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "sssji", "SfSd">;
1356 // Scalar Floating Point fused multiply-subtract (scalar, by element)
1357 def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "sssdi", "SfSd", OP_FMS_LN>;
1358 def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "sssji", "SfSd", OP_FMS_LNQ>;
1360 // Signed Saturating Doubling Multiply Long (scalar by element)
1361 def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "rsdi", "SsSi", OP_SCALAR_QDMULL_LN>;
1362 def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "rsji", "SsSi", OP_SCALAR_QDMULL_LN>;
1364 // Signed Saturating Doubling Multiply-Add Long (scalar by element)
1365 def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "rrsdi", "SsSi">;
1366 def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "rrsji", "SsSi">;
1368 // Signed Saturating Doubling Multiply-Subtract Long (scalar by element)
1369 def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "rrsdi", "SsSi">;
1370 def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "rrsji", "SsSi">;
1372 // Scalar Integer Saturating Doubling Multiply Half High (scalar by element)
1373 def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QDMULH_LN>;
1374 def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QDMULH_LN>;
1376 // Scalar Integer Saturating Rounding Doubling Multiply Half High
1377 def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QRDMULH_LN>;
1378 def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QRDMULH_LN>;
1380 let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in {
1381 // Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half
1382 def SCALAR_SQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "sssdi", "SsSi", OP_SCALAR_QRDMLAH_LN>;
1383 def SCALAR_SQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "sssji", "SsSi", OP_SCALAR_QRDMLAH_LN>;
1385 // Signed Saturating Rounding Doubling Multiply Subtract Returning High Half
1386 def SCALAR_SQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "sssdi", "SsSi", OP_SCALAR_QRDMLSH_LN>;
1387 def SCALAR_SQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "sssji", "SsSi", OP_SCALAR_QRDMLSH_LN>;
1390 def SCALAR_VDUP_LANE : IInst<"vdup_lane", "sdi", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;
1391 def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "sji", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;
1394 // ARMv8.2-A FP16 vector intrinsics for A32/A64.
1395 let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
1397 // ARMv8.2-A FP16 one-operand vector intrinsics.
1400 def CMEQH : SInst<"vceqz", "ud", "hQh">;
1401 def CMGEH : SInst<"vcgez", "ud", "hQh">;
1402 def CMGTH : SInst<"vcgtz", "ud", "hQh">;
1403 def CMLEH : SInst<"vclez", "ud", "hQh">;
1404 def CMLTH : SInst<"vcltz", "ud", "hQh">;
1406 // Vector conversion
1407 def VCVT_F16 : SInst<"vcvt_f16", "Hd", "sUsQsQUs">;
1408 def VCVT_S16 : SInst<"vcvt_s16", "xd", "hQh">;
1409 def VCVT_U16 : SInst<"vcvt_u16", "ud", "hQh">;
1410 def VCVTA_S16 : SInst<"vcvta_s16", "xd", "hQh">;
1411 def VCVTA_U16 : SInst<"vcvta_u16", "ud", "hQh">;
1412 def VCVTM_S16 : SInst<"vcvtm_s16", "xd", "hQh">;
1413 def VCVTM_U16 : SInst<"vcvtm_u16", "ud", "hQh">;
1414 def VCVTN_S16 : SInst<"vcvtn_s16", "xd", "hQh">;
1415 def VCVTN_U16 : SInst<"vcvtn_u16", "ud", "hQh">;
1416 def VCVTP_S16 : SInst<"vcvtp_s16", "xd", "hQh">;
1417 def VCVTP_U16 : SInst<"vcvtp_u16", "ud", "hQh">;
1420 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
1421 def FRINTZH : SInst<"vrnd", "dd", "hQh">;
1422 def FRINTNH : SInst<"vrndn", "dd", "hQh">;
1423 def FRINTAH : SInst<"vrnda", "dd", "hQh">;
1424 def FRINTPH : SInst<"vrndp", "dd", "hQh">;
1425 def FRINTMH : SInst<"vrndm", "dd", "hQh">;
1426 def FRINTXH : SInst<"vrndx", "dd", "hQh">;
1430 def VABSH : SInst<"vabs", "dd", "hQh">;
1431 def VNEGH : SOpInst<"vneg", "dd", "hQh", OP_NEG>;
1432 def VRECPEH : SInst<"vrecpe", "dd", "hQh">;
1433 def FRSQRTEH : SInst<"vrsqrte", "dd", "hQh">;
1435 // ARMv8.2-A FP16 two-operands vector intrinsics.
1438 def VADDH : SOpInst<"vadd", "ddd", "hQh", OP_ADD>;
1439 def VABDH : SInst<"vabd", "ddd", "hQh">;
1440 def VSUBH : SOpInst<"vsub", "ddd", "hQh", OP_SUB>;
1443 let InstName = "vacge" in {
1444 def VCAGEH : SInst<"vcage", "udd", "hQh">;
1445 def VCALEH : SInst<"vcale", "udd", "hQh">;
1447 let InstName = "vacgt" in {
1448 def VCAGTH : SInst<"vcagt", "udd", "hQh">;
1449 def VCALTH : SInst<"vcalt", "udd", "hQh">;
1451 def VCEQH : SOpInst<"vceq", "udd", "hQh", OP_EQ>;
1452 def VCGEH : SOpInst<"vcge", "udd", "hQh", OP_GE>;
1453 def VCGTH : SOpInst<"vcgt", "udd", "hQh", OP_GT>;
1454 let InstName = "vcge" in
1455 def VCLEH : SOpInst<"vcle", "udd", "hQh", OP_LE>;
1456 let InstName = "vcgt" in
1457 def VCLTH : SOpInst<"vclt", "udd", "hQh", OP_LT>;
1459 // Vector conversion
1460 let isVCVT_N = 1 in {
1461 def VCVT_N_F16 : SInst<"vcvt_n_f16", "Hdi", "sUsQsQUs">;
1462 def VCVT_N_S16 : SInst<"vcvt_n_s16", "xdi", "hQh">;
1463 def VCVT_N_U16 : SInst<"vcvt_n_u16", "udi", "hQh">;
1467 def VMAXH : SInst<"vmax", "ddd", "hQh">;
1468 def VMINH : SInst<"vmin", "ddd", "hQh">;
1469 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
1470 def FMAXNMH : SInst<"vmaxnm", "ddd", "hQh">;
1471 def FMINNMH : SInst<"vminnm", "ddd", "hQh">;
1474 // Multiplication/Division
1475 def VMULH : SOpInst<"vmul", "ddd", "hQh", OP_MUL>;
1477 // Pairwise addition
1478 def VPADDH : SInst<"vpadd", "ddd", "h">;
1481 def VPMAXH : SInst<"vpmax", "ddd", "h">;
1482 def VPMINH : SInst<"vpmin", "ddd", "h">;
1485 def VRECPSH : SInst<"vrecps", "ddd", "hQh">;
1486 def VRSQRTSH : SInst<"vrsqrts", "ddd", "hQh">;
1488 // ARMv8.2-A FP16 three-operands vector intrinsics.
1490 // Vector fused multiply-add operations
1491 def VFMAH : SInst<"vfma", "dddd", "hQh">;
1492 def VFMSH : SOpInst<"vfms", "dddd", "hQh", OP_FMLS>;
1494 // ARMv8.2-A FP16 lane vector intrinsics.
1497 def VMUL_LANEH : IOpInst<"vmul_lane", "ddgi", "hQh", OP_MUL_LN>;
1498 def VMUL_NH : IOpInst<"vmul_n", "dds", "hQh", OP_MUL_N>;
1500 // Data processing intrinsics - section 5
1502 // Logical operations
1503 let isHiddenLInst = 1 in
1504 def VBSLH : SInst<"vbsl", "dudd", "hQh">;
1506 // Transposition operations
1507 def VZIPH : WInst<"vzip", "2dd", "hQh">;
1508 def VUZPH : WInst<"vuzp", "2dd", "hQh">;
1509 def VTRNH : WInst<"vtrn", "2dd", "hQh">;
1512 let ArchGuard = "!defined(__aarch64__)" in {
1513 // Set all lanes to same value.
1514 // Already implemented prior to ARMv8.2-A.
1515 def VMOV_NH : WOpInst<"vmov_n", "ds", "hQh", OP_DUP>;
1516 def VDUP_NH : WOpInst<"vdup_n", "ds", "hQh", OP_DUP>;
1517 def VDUP_LANE1H : WOpInst<"vdup_lane", "dgi", "hQh", OP_DUP_LN>;
1521 def VEXTH : WInst<"vext", "dddi", "hQh">;
1523 // Reverse vector elements
1524 def VREV64H : WOpInst<"vrev64", "dd", "hQh", OP_REV64>;
1527 // ARMv8.2-A FP16 vector intrinsics for A64 only.
1528 let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(__aarch64__)" in {
1531 def FRINTIH : SInst<"vrndi", "dd", "hQh">;
1534 def FSQRTH : SInst<"vsqrt", "dd", "hQh">;
1536 // Multiplication/Division
1537 def MULXH : SInst<"vmulx", "ddd", "hQh">;
1538 def FDIVH : IOpInst<"vdiv", "ddd", "hQh", OP_DIV>;
1540 // Pairwise addition
1541 def VPADDH1 : SInst<"vpadd", "ddd", "Qh">;
1544 def VPMAXH1 : SInst<"vpmax", "ddd", "Qh">;
1545 def VPMINH1 : SInst<"vpmin", "ddd", "Qh">;
1547 // Pairwise MaxNum/MinNum
1548 def FMAXNMPH : SInst<"vpmaxnm", "ddd", "hQh">;
1549 def FMINNMPH : SInst<"vpminnm", "ddd", "hQh">;
1551 // ARMv8.2-A FP16 lane vector intrinsics.
1554 def VFMA_LANEH : IInst<"vfma_lane", "dddgi", "hQh">;
1555 def VFMA_LANEQH : IInst<"vfma_laneq", "dddji", "hQh">;
1557 // FMA lane with scalar argument
1558 def FMLA_NH : SOpInst<"vfma_n", "ddds", "hQh", OP_FMLA_N>;
1559 // Scalar floating point fused multiply-add (scalar, by element)
1560 def SCALAR_FMLA_LANEH : IInst<"vfma_lane", "sssdi", "Sh">;
1561 def SCALAR_FMLA_LANEQH : IInst<"vfma_laneq", "sssji", "Sh">;
1564 def VFMS_LANEH : IOpInst<"vfms_lane", "dddgi", "hQh", OP_FMS_LN>;
1565 def VFMS_LANEQH : IOpInst<"vfms_laneq", "dddji", "hQh", OP_FMS_LNQ>;
1566 // FMS lane with scalar argument
1567 def FMLS_NH : SOpInst<"vfms_n", "ddds", "hQh", OP_FMLS_N>;
1568 // Scalar floating foint fused multiply-subtract (scalar, by element)
1569 def SCALAR_FMLS_LANEH : IOpInst<"vfms_lane", "sssdi", "Sh", OP_FMS_LN>;
1570 def SCALAR_FMLS_LANEQH : IOpInst<"vfms_laneq", "sssji", "Sh", OP_FMS_LNQ>;
1573 def VMUL_LANEQH : IOpInst<"vmul_laneq", "ddji", "hQh", OP_MUL_LN>;
1574 // Scalar floating point multiply (scalar, by element)
1575 def SCALAR_FMUL_LANEH : IOpInst<"vmul_lane", "ssdi", "Sh", OP_SCALAR_MUL_LN>;
1576 def SCALAR_FMUL_LANEQH : IOpInst<"vmul_laneq", "ssji", "Sh", OP_SCALAR_MUL_LN>;
1579 def VMULX_LANEH : IOpInst<"vmulx_lane", "ddgi", "hQh", OP_MULX_LN>;
1580 def VMULX_LANEQH : IOpInst<"vmulx_laneq", "ddji", "hQh", OP_MULX_LN>;
1581 def VMULX_NH : IOpInst<"vmulx_n", "dds", "hQh", OP_MULX_N>;
1582 // Scalar floating point mulx (scalar, by element)
1583 def SCALAR_FMULX_LANEH : IInst<"vmulx_lane", "ssdi", "Sh">;
1584 def SCALAR_FMULX_LANEQH : IInst<"vmulx_laneq", "ssji", "Sh">;
1586 // ARMv8.2-A FP16 reduction vector intrinsics.
1587 def VMAXVH : SInst<"vmaxv", "sd", "hQh">;
1588 def VMINVH : SInst<"vminv", "sd", "hQh">;
1589 def FMAXNMVH : SInst<"vmaxnmv", "sd", "hQh">;
1590 def FMINNMVH : SInst<"vminnmv", "sd", "hQh">;
1593 def VTRN1H : SOpInst<"vtrn1", "ddd", "hQh", OP_TRN1>;
1594 def VZIP1H : SOpInst<"vzip1", "ddd", "hQh", OP_ZIP1>;
1595 def VUZP1H : SOpInst<"vuzp1", "ddd", "hQh", OP_UZP1>;
1596 def VTRN2H : SOpInst<"vtrn2", "ddd", "hQh", OP_TRN2>;
1597 def VZIP2H : SOpInst<"vzip2", "ddd", "hQh", OP_ZIP2>;
1598 def VUZP2H : SOpInst<"vuzp2", "ddd", "hQh", OP_UZP2>;
1600 def SCALAR_VDUP_LANEH : IInst<"vdup_lane", "sdi", "Sh">;
1601 def SCALAR_VDUP_LANEQH : IInst<"vdup_laneq", "sji", "Sh">;
1604 // v8.2-A dot product instructions.
1605 let ArchGuard = "defined(__ARM_FEATURE_DOTPROD)" in {
1606 def DOT : SInst<"vdot", "dd88", "iQiUiQUi">;
1607 def DOT_LANE : SOpInst<"vdot_lane", "dd87i", "iUiQiQUi", OP_DOT_LN>;
1609 let ArchGuard = "defined(__ARM_FEATURE_DOTPROD) && defined(__aarch64__)" in {
1610 // Variants indexing into a 128-bit vector are A64 only.
1611 def UDOT_LANEQ : SOpInst<"vdot_laneq", "dd89i", "iUiQiQUi", OP_DOT_LNQ>;