1 //===--- arm_neon.td - ARM NEON compiler interface ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TableGen definitions from which the ARM NEON header
11 // file will be generated. See ARM document DUI0348B.
13 //===----------------------------------------------------------------------===//
15 // Each intrinsic is a subclass of the Inst class. An intrinsic can either
16 // generate a __builtin_* call or it can expand to a set of generic operations.
18 // The operations are subclasses of Operation providing a list of DAGs, the
19 // last of which is the return value. The available DAG nodes are documented
22 //===----------------------------------------------------------------------===//
24 // The base Operation class. All operations must subclass this.
25 class Operation<list<dag> ops=[]> {
29 // An operation that only contains a single DAG.
30 class Op<dag op> : Operation<[op]>;
31 // A shorter version of Operation - takes a list of DAGs. The last of these will
32 // be the return value.
33 class LOp<list<dag> ops> : Operation<ops>;
35 // These defs and classes are used internally to implement the SetTheory
36 // expansion and should be ignored.
37 foreach Index = 0-63 in
41 //===----------------------------------------------------------------------===//
42 // Available operations
43 //===----------------------------------------------------------------------===//
45 // DAG arguments can either be operations (documented below) or variables.
46 // Variables are prefixed with '$'. There are variables for each input argument,
47 // with the name $pN, where N starts at zero. So the zero'th argument will be
48 // $p0, the first $p1 etc.
50 // op - Binary or unary operator, depending on the number of arguments. The
51 // operator itself is just treated as a raw string and is not checked.
52 // example: (op "+", $p0, $p1) -> "__p0 + __p1".
53 // (op "-", $p0) -> "-__p0"
55 // call - Invoke another intrinsic. The input types are type checked and
56 // disambiguated. If there is no intrinsic defined that takes
57 // the given types (or if there is a type ambiguity) an error is
58 // generated at tblgen time. The name of the intrinsic is the raw
59 // name as given to the Inst class (not mangled).
60 // example: (call "vget_high", $p0) -> "vgetq_high_s16(__p0)"
61 // (assuming $p0 has type int16x8_t).
63 // cast - Perform a cast to a different type. This gets emitted as a static
64 // C-style cast. For a pure reinterpret cast (T x = *(T*)&y), use
67 // The syntax is (cast MOD* VAL). The last argument is the value to
68 // cast, preceded by a sequence of type modifiers. The target type
69 // starts off as the type of VAL, and is modified by MOD in sequence.
70 // The available modifiers are:
71 // - $X - Take the type of parameter/variable X. For example:
72 // (cast $p0, $p1) would cast $p1 to the type of $p0.
73 // - "R" - The type of the return type.
74 // - A typedef string - A NEON or stdint.h type that is then parsed.
75 // for example: (cast "uint32x4_t", $p0).
76 // - "U" - Make the type unsigned.
77 // - "S" - Make the type signed.
78 // - "H" - Halve the number of lanes in the type.
79 // - "D" - Double the number of lanes in the type.
80 // - "8" - Convert type to an equivalent vector of 8-bit signed
82 // example: (cast "R", "U", $p0) -> "(uint32x4_t)__p0" (assuming the return
83 // value is of type "int32x4_t".
84 // (cast $p0, "D", "8", $p1) -> "(int8x16_t)__p1" (assuming __p0
85 // has type float64x1_t or any other vector type of 64 bits).
86 // (cast "int32_t", $p2) -> "(int32_t)__p2"
88 // bitcast - Same as "cast", except a reinterpret-cast is produced:
89 // (bitcast "T", $p0) -> "*(T*)&__p0".
90 // The VAL argument is saved to a temporary so it can be used
93 // dup - Take a scalar argument and create a vector by duplicating it into
94 // all lanes. The type of the vector is the base type of the intrinsic.
95 // example: (dup $p1) -> "(uint32x2_t) {__p1, __p1}" (assuming the base type
98 // splat - Take a vector and a lane index, and return a vector of the same type
99 // containing repeated instances of the source vector at the lane index.
100 // example: (splat $p0, $p1) ->
101 // "__builtin_shufflevector(__p0, __p0, __p1, __p1, __p1, __p1)"
102 // (assuming __p0 has four elements).
104 // save_temp - Create a temporary (local) variable. The variable takes a name
105 // based on the zero'th parameter and can be referenced using
106 // using that name in subsequent DAGs in the same
107 // operation. The scope of a temp is the operation. If a variable
108 // with the given name already exists, an error will be given at
110 // example: [(save_temp $var, (call "foo", $p0)),
111 // (op "+", $var, $p1)] ->
112 // "int32x2_t __var = foo(__p0); return __var + __p1;"
114 // name_replace - Return the name of the current intrinsic with the first
115 // argument replaced by the second argument. Raises an error if
116 // the first argument does not exist in the intrinsic name.
117 // example: (call (name_replace "_high_", "_"), $p0) (to call the non-high
118 // version of this intrinsic).
120 // literal - Create a literal piece of code. The code is treated as a raw
121 // string, and must be given a type. The type is a stdint.h or
122 // NEON intrinsic type as given to (cast).
123 // example: (literal "int32_t", "0")
125 // shuffle - Create a vector shuffle. The syntax is (shuffle ARG0, ARG1, MASK).
126 // The MASK argument is a set of elements. The elements are generated
127 // from the two special defs "mask0" and "mask1". "mask0" expands to
128 // the lane indices in sequence for ARG0, and "mask1" expands to
129 // the lane indices in sequence for ARG1. They can be used as-is, e.g.
131 // (shuffle $p0, $p1, mask0) -> $p0
132 // (shuffle $p0, $p1, mask1) -> $p1
134 // or, more usefully, they can be manipulated using the SetTheory
135 // operators plus some extra operators defined in the NEON emitter.
136 // The operators are described below.
137 // example: (shuffle $p0, $p1, (add (highhalf mask0), (highhalf mask1))) ->
138 // A concatenation of the high halves of the input vectors.
141 // add, interleave, decimate: These set operators are vanilla SetTheory
142 // operators and take their normal definition.
146 // rotl - Rotate set left by a number of elements.
147 // example: (rotl mask0, 3) -> [3, 4, 5, 6, 0, 1, 2]
149 // rotl - Rotate set right by a number of elements.
150 // example: (rotr mask0, 3) -> [4, 5, 6, 0, 1, 2, 3]
152 // highhalf - Take only the high half of the input.
153 // example: (highhalf mask0) -> [4, 5, 6, 7] (assuming mask0 had 8 elements)
155 // highhalf - Take only the low half of the input.
156 // example: (lowhalf mask0) -> [0, 1, 2, 3] (assuming mask0 had 8 elements)
158 // rev - Perform a variable-width reversal of the elements. The zero'th argument
159 // is a width in bits to reverse. The lanes this maps to is determined
160 // based on the element width of the underlying type.
161 // example: (rev 32, mask0) -> [3, 2, 1, 0, 7, 6, 5, 4] (if 8-bit elements)
162 // example: (rev 32, mask0) -> [1, 0, 3, 2] (if 16-bit elements)
164 // mask0 - The initial sequence of lanes for shuffle ARG0
165 def mask0 : MaskExpand;
166 // mask0 - The initial sequence of lanes for shuffle ARG1
167 def mask1 : MaskExpand;
169 def OP_NONE : Operation;
170 def OP_UNAVAILABLE : Operation {
174 //===----------------------------------------------------------------------===//
175 // Instruction definitions
176 //===----------------------------------------------------------------------===//
178 // Every intrinsic subclasses "Inst". An intrinsic has a name, a prototype and
179 // a sequence of typespecs.
181 // The name is the base name of the intrinsic, for example "vget_lane". This is
182 // then mangled by the tblgen backend to add type information ("vget_lane_s16").
184 // A typespec is a sequence of uppercase characters (modifiers) followed by one
185 // lowercase character. A typespec encodes a particular "base type" of the
188 // An example typespec is "Qs" - quad-size short - uint16x8_t. The available
189 // typespec codes are given below.
191 // The string given to an Inst class is a sequence of typespecs. The intrinsic
192 // is instantiated for every typespec in the sequence. For example "sdQsQd".
194 // The prototype is a string that defines the return type of the intrinsic
195 // and the type of each argument. The return type and every argument gets a
196 // "modifier" that can change in some way the "base type" of the intrinsic.
198 // The modifier 'd' means "default" and does not modify the base type in any
199 // way. The available modifiers are given below.
212 // Typespec modifiers
213 // ------------------
214 // S: scalar, only used for function mangling.
217 // H: 128b without mangling 'q'
220 // Prototype modifiers
221 // -------------------
222 // prototype: return (arg, arg, ...)
225 // t: best-fit integer (int/poly args)
226 // x: signed integer (int/float args)
227 // u: unsigned integer (int/float args)
228 // f: float (int args)
229 // F: double (int args)
231 // g: default, ignore 'Q' size modifier.
232 // j: default, force 'Q' size modifier.
233 // w: double width elements, same num elts
234 // n: double width elements, half num elts
235 // h: half width elements, double num elts
236 // q: half width elements, quad num elts
237 // e: half width elements, double num elts, unsigned
238 // m: half width elements, same num elts
240 // l: constant uint64
241 // s: scalar of element type
242 // z: scalar of half width element type, signed
243 // r: scalar of double width element type, signed
244 // a: scalar of element type (splat to vector type)
245 // b: scalar of unsigned integer/long type (int/float args)
246 // $: scalar of signed integer/long type (int/float args)
247 // y: scalar of float
248 // o: scalar of double
249 // k: default elt width, double num elts
250 // 2,3,4: array of default vectors
251 // B,C,D: array of default elts, force 'Q' size modifier.
253 // c: const pointer type
255 // Every intrinsic subclasses Inst.
256 class Inst <string n, string p, string t, Operation o> {
258 string Prototype = p;
260 string ArchGuard = "";
262 Operation Operation = o;
263 bit CartesianProductOfTypes = 0;
264 bit BigEndianSafe = 0;
266 bit isScalarShift = 0;
267 bit isScalarNarrowShift = 0;
269 // For immediate checks: the immediate will be assumed to specify the lane of
270 // a Q register. Only used for intrinsics which end up calling polymorphic
274 // Certain intrinsics have different names than their representative
275 // instructions. This field allows us to handle this correctly when we
276 // are generating tests.
277 string InstName = "";
279 // Certain intrinsics even though they are not a WOpInst or LOpInst,
280 // generate a WOpInst/LOpInst instruction (see below for definition
281 // of a WOpInst/LOpInst). For testing purposes we need to know
282 // this. Ex: vset_lane which outputs vmov instructions.
283 bit isHiddenWInst = 0;
284 bit isHiddenLInst = 0;
287 // The following instruction classes are implemented via builtins.
288 // These declarations are used to generate Builtins.def:
290 // SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8")
291 // IInst: Instruction with generic integer suffix (e.g., "i8")
292 // WInst: Instruction with only bit size suffix (e.g., "8")
293 class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
294 class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
295 class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
297 // The following instruction classes are implemented via operators
298 // instead of builtins. As such these declarations are only used for
299 // the purpose of generating tests.
301 // SOpInst: Instruction with signed/unsigned suffix (e.g., "s8",
303 // IOpInst: Instruction with generic integer suffix (e.g., "i8").
304 // WOpInst: Instruction with bit size only suffix (e.g., "8").
305 // LOpInst: Logical instruction with no bit size suffix.
306 // NoTestOpInst: Intrinsic that has no corresponding instruction.
307 class SOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {}
308 class IOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {}
309 class WOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {}
310 class LOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {}
311 class NoTestOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {}
313 //===----------------------------------------------------------------------===//
315 //===----------------------------------------------------------------------===//
317 def OP_ADD : Op<(op "+", $p0, $p1)>;
318 def OP_ADDL : Op<(op "+", (call "vmovl", $p0), (call "vmovl", $p1))>;
319 def OP_ADDLHi : Op<(op "+", (call "vmovl_high", $p0),
320 (call "vmovl_high", $p1))>;
321 def OP_ADDW : Op<(op "+", $p0, (call "vmovl", $p1))>;
322 def OP_ADDWHi : Op<(op "+", $p0, (call "vmovl_high", $p1))>;
323 def OP_SUB : Op<(op "-", $p0, $p1)>;
324 def OP_SUBL : Op<(op "-", (call "vmovl", $p0), (call "vmovl", $p1))>;
325 def OP_SUBLHi : Op<(op "-", (call "vmovl_high", $p0),
326 (call "vmovl_high", $p1))>;
327 def OP_SUBW : Op<(op "-", $p0, (call "vmovl", $p1))>;
328 def OP_SUBWHi : Op<(op "-", $p0, (call "vmovl_high", $p1))>;
329 def OP_MUL : Op<(op "*", $p0, $p1)>;
330 def OP_MLA : Op<(op "+", $p0, (op "*", $p1, $p2))>;
331 def OP_MLAL : Op<(op "+", $p0, (call "vmull", $p1, $p2))>;
332 def OP_MULLHi : Op<(call "vmull", (call "vget_high", $p0),
333 (call "vget_high", $p1))>;
334 def OP_MULLHi_P64 : Op<(call "vmull",
335 (cast "poly64_t", (call "vget_high", $p0)),
336 (cast "poly64_t", (call "vget_high", $p1)))>;
337 def OP_MULLHi_N : Op<(call "vmull_n", (call "vget_high", $p0), $p1)>;
338 def OP_MLALHi : Op<(call "vmlal", $p0, (call "vget_high", $p1),
339 (call "vget_high", $p2))>;
340 def OP_MLALHi_N : Op<(call "vmlal_n", $p0, (call "vget_high", $p1), $p2)>;
341 def OP_MLS : Op<(op "-", $p0, (op "*", $p1, $p2))>;
342 def OP_MLSL : Op<(op "-", $p0, (call "vmull", $p1, $p2))>;
343 def OP_MLSLHi : Op<(call "vmlsl", $p0, (call "vget_high", $p1),
344 (call "vget_high", $p2))>;
345 def OP_MLSLHi_N : Op<(call "vmlsl_n", $p0, (call "vget_high", $p1), $p2)>;
346 def OP_MUL_N : Op<(op "*", $p0, (dup $p1))>;
347 def OP_MLA_N : Op<(op "+", $p0, (op "*", $p1, (dup $p2)))>;
348 def OP_MLS_N : Op<(op "-", $p0, (op "*", $p1, (dup $p2)))>;
349 def OP_FMLA_N : Op<(call "vfma", $p0, $p1, (dup $p2))>;
350 def OP_FMLS_N : Op<(call "vfms", $p0, $p1, (dup $p2))>;
351 def OP_MLAL_N : Op<(op "+", $p0, (call "vmull", $p1, (dup $p2)))>;
352 def OP_MLSL_N : Op<(op "-", $p0, (call "vmull", $p1, (dup $p2)))>;
353 def OP_MUL_LN : Op<(op "*", $p0, (splat $p1, $p2))>;
354 def OP_MULX_LN : Op<(call "vmulx", $p0, (splat $p1, $p2))>;
355 def OP_MULL_LN : Op<(call "vmull", $p0, (splat $p1, $p2))>;
356 def OP_MULLHi_LN: Op<(call "vmull", (call "vget_high", $p0), (splat $p1, $p2))>;
357 def OP_MLA_LN : Op<(op "+", $p0, (op "*", $p1, (splat $p2, $p3)))>;
358 def OP_MLS_LN : Op<(op "-", $p0, (op "*", $p1, (splat $p2, $p3)))>;
359 def OP_MLAL_LN : Op<(op "+", $p0, (call "vmull", $p1, (splat $p2, $p3)))>;
360 def OP_MLALHi_LN: Op<(op "+", $p0, (call "vmull", (call "vget_high", $p1),
362 def OP_MLSL_LN : Op<(op "-", $p0, (call "vmull", $p1, (splat $p2, $p3)))>;
363 def OP_MLSLHi_LN : Op<(op "-", $p0, (call "vmull", (call "vget_high", $p1),
365 def OP_QDMULL_LN : Op<(call "vqdmull", $p0, (splat $p1, $p2))>;
366 def OP_QDMULLHi_LN : Op<(call "vqdmull", (call "vget_high", $p0),
368 def OP_QDMLAL_LN : Op<(call "vqdmlal", $p0, $p1, (splat $p2, $p3))>;
369 def OP_QDMLALHi_LN : Op<(call "vqdmlal", $p0, (call "vget_high", $p1),
371 def OP_QDMLSL_LN : Op<(call "vqdmlsl", $p0, $p1, (splat $p2, $p3))>;
372 def OP_QDMLSLHi_LN : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1),
374 def OP_QDMULH_LN : Op<(call "vqdmulh", $p0, (splat $p1, $p2))>;
375 def OP_QRDMULH_LN : Op<(call "vqrdmulh", $p0, (splat $p1, $p2))>;
376 def OP_FMS_LN : Op<(call "vfma_lane", $p0, $p1, (op "-", $p2), $p3)>;
377 def OP_FMS_LNQ : Op<(call "vfma_laneq", $p0, $p1, (op "-", $p2), $p3)>;
378 def OP_TRN1 : Op<(shuffle $p0, $p1, (interleave (decimate mask0, 2),
379 (decimate mask1, 2)))>;
380 def OP_ZIP1 : Op<(shuffle $p0, $p1, (lowhalf (interleave mask0, mask1)))>;
381 def OP_UZP1 : Op<(shuffle $p0, $p1, (add (decimate mask0, 2),
382 (decimate mask1, 2)))>;
383 def OP_TRN2 : Op<(shuffle $p0, $p1, (interleave
384 (decimate (rotl mask0, 1), 2),
385 (decimate (rotl mask1, 1), 2)))>;
386 def OP_ZIP2 : Op<(shuffle $p0, $p1, (highhalf (interleave mask0, mask1)))>;
387 def OP_UZP2 : Op<(shuffle $p0, $p1, (add (decimate (rotl mask0, 1), 2),
388 (decimate (rotl mask1, 1), 2)))>;
389 def OP_EQ : Op<(cast "R", (op "==", $p0, $p1))>;
390 def OP_GE : Op<(cast "R", (op ">=", $p0, $p1))>;
391 def OP_LE : Op<(cast "R", (op "<=", $p0, $p1))>;
392 def OP_GT : Op<(cast "R", (op ">", $p0, $p1))>;
393 def OP_LT : Op<(cast "R", (op "<", $p0, $p1))>;
394 def OP_NEG : Op<(op "-", $p0)>;
395 def OP_NOT : Op<(op "~", $p0)>;
396 def OP_AND : Op<(op "&", $p0, $p1)>;
397 def OP_OR : Op<(op "|", $p0, $p1)>;
398 def OP_XOR : Op<(op "^", $p0, $p1)>;
399 def OP_ANDN : Op<(op "&", $p0, (op "~", $p1))>;
400 def OP_ORN : Op<(op "|", $p0, (op "~", $p1))>;
401 def OP_CAST : Op<(cast "R", $p0)>;
402 def OP_HI : Op<(shuffle $p0, $p0, (highhalf mask0))>;
403 def OP_LO : Op<(shuffle $p0, $p0, (lowhalf mask0))>;
404 def OP_CONC : Op<(shuffle $p0, $p1, (add mask0, mask1))>;
405 def OP_DUP : Op<(dup $p0)>;
406 def OP_DUP_LN : Op<(splat $p0, $p1)>;
407 def OP_SEL : Op<(cast "R", (op "|",
408 (op "&", $p0, (cast $p0, $p1)),
409 (op "&", (op "~", $p0), (cast $p0, $p2))))>;
410 def OP_REV16 : Op<(shuffle $p0, $p0, (rev 16, mask0))>;
411 def OP_REV32 : Op<(shuffle $p0, $p0, (rev 32, mask0))>;
412 def OP_REV64 : Op<(shuffle $p0, $p0, (rev 64, mask0))>;
413 def OP_XTN : Op<(call "vcombine", $p0, (call "vmovn", $p1))>;
414 def OP_SQXTUN : Op<(call "vcombine", (cast $p0, "U", $p0),
415 (call "vqmovun", $p1))>;
416 def OP_QXTN : Op<(call "vcombine", $p0, (call "vqmovn", $p1))>;
417 def OP_VCVT_NA_HI_F16 : Op<(call "vcombine", $p0, (call "vcvt_f16", $p1))>;
418 def OP_VCVT_NA_HI_F32 : Op<(call "vcombine", $p0, (call "vcvt_f32_f64", $p1))>;
419 def OP_VCVT_EX_HI_F32 : Op<(call "vcvt_f32_f16", (call "vget_high", $p0))>;
420 def OP_VCVT_EX_HI_F64 : Op<(call "vcvt_f64_f32", (call "vget_high", $p0))>;
421 def OP_VCVTX_HI : Op<(call "vcombine", $p0, (call "vcvtx_f32", $p1))>;
422 def OP_REINT : Op<(cast "R", $p0)>;
423 def OP_ADDHNHi : Op<(call "vcombine", $p0, (call "vaddhn", $p1, $p2))>;
424 def OP_RADDHNHi : Op<(call "vcombine", $p0, (call "vraddhn", $p1, $p2))>;
425 def OP_SUBHNHi : Op<(call "vcombine", $p0, (call "vsubhn", $p1, $p2))>;
426 def OP_RSUBHNHi : Op<(call "vcombine", $p0, (call "vrsubhn", $p1, $p2))>;
427 def OP_ABDL : Op<(cast "R", (call "vmovl", (cast $p0, "U",
428 (call "vabd", $p0, $p1))))>;
429 def OP_ABDLHi : Op<(call "vabdl", (call "vget_high", $p0),
430 (call "vget_high", $p1))>;
431 def OP_ABA : Op<(op "+", $p0, (call "vabd", $p1, $p2))>;
432 def OP_ABAL : Op<(op "+", $p0, (call "vabdl", $p1, $p2))>;
433 def OP_ABALHi : Op<(call "vabal", $p0, (call "vget_high", $p1),
434 (call "vget_high", $p2))>;
435 def OP_QDMULLHi : Op<(call "vqdmull", (call "vget_high", $p0),
436 (call "vget_high", $p1))>;
437 def OP_QDMULLHi_N : Op<(call "vqdmull_n", (call "vget_high", $p0), $p1)>;
438 def OP_QDMLALHi : Op<(call "vqdmlal", $p0, (call "vget_high", $p1),
439 (call "vget_high", $p2))>;
440 def OP_QDMLALHi_N : Op<(call "vqdmlal_n", $p0, (call "vget_high", $p1), $p2)>;
441 def OP_QDMLSLHi : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1),
442 (call "vget_high", $p2))>;
443 def OP_QDMLSLHi_N : Op<(call "vqdmlsl_n", $p0, (call "vget_high", $p1), $p2)>;
444 def OP_DIV : Op<(op "/", $p0, $p1)>;
445 def OP_LONG_HI : Op<(cast "R", (call (name_replace "_high_", "_"),
446 (call "vget_high", $p0), $p1))>;
447 def OP_NARROW_HI : Op<(cast "R", (call "vcombine",
448 (cast "R", "H", $p0),
450 (call (name_replace "_high_", "_"),
452 def OP_MOVL_HI : LOp<[(save_temp $a1, (call "vget_high", $p0)),
454 (call "vshll_n", $a1, (literal "int32_t", "0")))]>;
455 def OP_COPY_LN : Op<(call "vset_lane", (call "vget_lane", $p2, $p3), $p0, $p1)>;
456 def OP_SCALAR_MUL_LN : Op<(op "*", $p0, (call "vget_lane", $p1, $p2))>;
457 def OP_SCALAR_MULX_LN : Op<(call "vmulx", $p0, (call "vget_lane", $p1, $p2))>;
458 def OP_SCALAR_VMULX_LN : LOp<[(save_temp $x, (call "vget_lane", $p0,
459 (literal "int32_t", "0"))),
460 (save_temp $y, (call "vget_lane", $p1, $p2)),
461 (save_temp $z, (call "vmulx", $x, $y)),
462 (call "vset_lane", $z, $p0, $p2)]>;
463 def OP_SCALAR_VMULX_LNQ : LOp<[(save_temp $x, (call "vget_lane", $p0,
464 (literal "int32_t", "0"))),
465 (save_temp $y, (call "vget_lane", $p1, $p2)),
466 (save_temp $z, (call "vmulx", $x, $y)),
467 (call "vset_lane", $z, $p0, (literal "int32_t",
469 class ScalarMulOp<string opname> :
470 Op<(call opname, $p0, (call "vget_lane", $p1, $p2))>;
472 def OP_SCALAR_QDMULL_LN : ScalarMulOp<"vqdmull">;
473 def OP_SCALAR_QDMULH_LN : ScalarMulOp<"vqdmulh">;
474 def OP_SCALAR_QRDMULH_LN : ScalarMulOp<"vqrdmulh">;
476 def OP_SCALAR_HALF_GET_LN : Op<(bitcast "float16_t",
478 (bitcast "int16x4_t", $p0), $p1))>;
479 def OP_SCALAR_HALF_GET_LNQ : Op<(bitcast "float16_t",
481 (bitcast "int16x8_t", $p0), $p1))>;
482 def OP_SCALAR_HALF_SET_LN : Op<(bitcast "float16x4_t",
484 (bitcast "int16_t", $p0),
485 (bitcast "int16x4_t", $p1), $p2))>;
486 def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast "float16x8_t",
488 (bitcast "int16_t", $p0),
489 (bitcast "int16x8_t", $p1), $p2))>;
491 //===----------------------------------------------------------------------===//
493 //===----------------------------------------------------------------------===//
495 ////////////////////////////////////////////////////////////////////////////////
497 def VADD : IOpInst<"vadd", "ddd",
498 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
499 def VADDL : SOpInst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>;
500 def VADDW : SOpInst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>;
501 def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
502 def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
503 def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
504 def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">;
505 def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">;
507 ////////////////////////////////////////////////////////////////////////////////
508 // E.3.2 Multiplication
509 def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>;
510 def VMULP : SInst<"vmul", "ddd", "PcQPc">;
511 def VMLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
512 def VMLAL : SOpInst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>;
513 def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
514 def VMLSL : SOpInst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>;
515 def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">;
516 def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">;
517 def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">;
518 def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">;
519 def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">;
520 def VQDMULL : SInst<"vqdmull", "wdd", "si">;
522 ////////////////////////////////////////////////////////////////////////////////
524 def VSUB : IOpInst<"vsub", "ddd",
525 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
526 def VSUBL : SOpInst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>;
527 def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>;
528 def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
529 def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
530 def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">;
531 def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">;
533 ////////////////////////////////////////////////////////////////////////////////
535 def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
536 def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
537 let InstName = "vcge" in
538 def VCLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
539 def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
540 let InstName = "vcgt" in
541 def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
542 let InstName = "vacge" in {
543 def VCAGE : IInst<"vcage", "udd", "fQf">;
544 def VCALE : IInst<"vcale", "udd", "fQf">;
546 let InstName = "vacgt" in {
547 def VCAGT : IInst<"vcagt", "udd", "fQf">;
548 def VCALT : IInst<"vcalt", "udd", "fQf">;
550 def VTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">;
552 ////////////////////////////////////////////////////////////////////////////////
553 // E.3.5 Absolute Difference
554 def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
555 def VABDL : SOpInst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>;
556 def VABA : SOpInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>;
557 def VABAL : SOpInst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>;
559 ////////////////////////////////////////////////////////////////////////////////
561 def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
562 def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
564 ////////////////////////////////////////////////////////////////////////////////
565 // E.3.7 Pairwise Addition
566 def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">;
567 def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
568 def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
570 ////////////////////////////////////////////////////////////////////////////////
571 // E.3.8-9 Folding Max/Min
572 def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">;
573 def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">;
575 ////////////////////////////////////////////////////////////////////////////////
576 // E.3.10 Reciprocal/Sqrt
577 def VRECPS : IInst<"vrecps", "ddd", "fQf">;
578 def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">;
580 ////////////////////////////////////////////////////////////////////////////////
581 // E.3.11 Shifts by signed variable
582 def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
583 def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
584 def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
585 def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
587 ////////////////////////////////////////////////////////////////////////////////
588 // E.3.12 Shifts by constant
590 def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
591 def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
592 def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
593 def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
594 def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
595 def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
596 def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">;
597 def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">;
598 def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">;
599 def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">;
600 def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">;
601 def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">;
602 def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">;
603 def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">;
605 ////////////////////////////////////////////////////////////////////////////////
606 // E.3.13 Shifts with insert
607 def VSRI_N : WInst<"vsri_n", "dddi",
608 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
609 def VSLI_N : WInst<"vsli_n", "dddi",
610 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
613 ////////////////////////////////////////////////////////////////////////////////
614 // E.3.14 Loads and stores of a single vector
615 def VLD1 : WInst<"vld1", "dc",
616 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
617 def VLD1_LANE : WInst<"vld1_lane", "dcdi",
618 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
619 def VLD1_DUP : WInst<"vld1_dup", "dc",
620 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
621 def VST1 : WInst<"vst1", "vpd",
622 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
623 def VST1_LANE : WInst<"vst1_lane", "vpdi",
624 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
626 ////////////////////////////////////////////////////////////////////////////////
627 // E.3.15 Loads and stores of an N-element structure
628 def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
629 def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
630 def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
631 def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">;
632 def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">;
633 def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">;
634 def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
635 def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
636 def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
637 def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
638 def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
639 def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
640 def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
641 def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
642 def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
644 ////////////////////////////////////////////////////////////////////////////////
645 // E.3.16 Extract lanes from a vector
646 let InstName = "vmov" in
647 def VGET_LANE : IInst<"vget_lane", "sdi",
648 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
650 ////////////////////////////////////////////////////////////////////////////////
651 // E.3.17 Set lanes within a vector
652 let InstName = "vmov" in
653 def VSET_LANE : IInst<"vset_lane", "dsdi",
654 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
656 ////////////////////////////////////////////////////////////////////////////////
657 // E.3.18 Initialize a vector from bit pattern
658 def VCREATE : NoTestOpInst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST> {
659 let BigEndianSafe = 1;
662 ////////////////////////////////////////////////////////////////////////////////
663 // E.3.19 Set all lanes to same value
664 let InstName = "vmov" in {
665 def VDUP_N : WOpInst<"vdup_n", "ds",
666 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl",
668 def VMOV_N : WOpInst<"vmov_n", "ds",
669 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl",
673 def VDUP_LANE: WOpInst<"vdup_lane", "dgi",
674 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl",
677 ////////////////////////////////////////////////////////////////////////////////
678 // E.3.20 Combining vectors
679 def VCOMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>;
681 ////////////////////////////////////////////////////////////////////////////////
682 // E.3.21 Splitting vectors
683 let InstName = "vmov" in {
684 def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
685 def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
688 ////////////////////////////////////////////////////////////////////////////////
689 // E.3.22 Converting vectors
690 def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">;
691 def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">;
692 def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">;
693 def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">;
694 def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">;
695 let isVCVT_N = 1 in {
696 def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">;
697 def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">;
698 def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">;
700 def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">;
701 def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">;
702 def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">;
703 def VQMOVUN : SInst<"vqmovun", "ek", "sil">;
705 ////////////////////////////////////////////////////////////////////////////////
706 // E.3.23-24 Table lookup, Extended table lookup
707 let InstName = "vtbl" in {
708 def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">;
709 def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">;
710 def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">;
711 def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">;
713 let InstName = "vtbx" in {
714 def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">;
715 def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">;
716 def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">;
717 def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">;
720 ////////////////////////////////////////////////////////////////////////////////
721 // E.3.25 Operations with a scalar value
722 def VMLA_LANE : IOpInst<"vmla_lane", "dddgi",
723 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
724 def VMLAL_LANE : SOpInst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>;
725 def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>;
726 def VMLS_LANE : IOpInst<"vmls_lane", "dddgi",
727 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
728 def VMLSL_LANE : SOpInst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>;
729 def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>;
730 def VMUL_N : IOpInst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
731 def VMUL_LANE : IOpInst<"vmul_lane", "ddgi",
732 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
733 def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">;
734 def VMULL_LANE : SOpInst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>;
735 def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">;
736 def VQDMULL_LANE : SOpInst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>;
737 def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">;
738 def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>;
739 def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">;
740 def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>;
741 def VMLA_N : IOpInst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
742 def VMLAL_N : SOpInst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>;
743 def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">;
744 def VMLS_N : IOpInst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>;
745 def VMLSL_N : SOpInst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>;
746 def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">;
748 ////////////////////////////////////////////////////////////////////////////////
749 // E.3.26 Vector Extract
750 def VEXT : WInst<"vext", "dddi",
751 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">;
753 ////////////////////////////////////////////////////////////////////////////////
754 // E.3.27 Reverse vector elements
755 def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
757 def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
758 def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>;
760 ////////////////////////////////////////////////////////////////////////////////
761 // E.3.28 Other single operand arithmetic
762 def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">;
763 def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">;
764 def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>;
765 def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">;
766 def VCLS : SInst<"vcls", "dd", "csiQcQsQi">;
767 def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
768 def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">;
769 def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">;
770 def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">;
772 ////////////////////////////////////////////////////////////////////////////////
773 // E.3.29 Logical operations
774 def VMVN : LOpInst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
775 def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
776 def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
777 def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
778 def VBIC : LOpInst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
779 def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
780 let isHiddenLInst = 1 in
781 def VBSL : SInst<"vbsl", "dudd",
782 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">;
784 ////////////////////////////////////////////////////////////////////////////////
785 // E.3.30 Transposition operations
786 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
787 def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
788 def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
790 ////////////////////////////////////////////////////////////////////////////////
791 // E.3.31 Vector reinterpret cast operations
793 : NoTestOpInst<"vreinterpret", "dd",
794 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT> {
795 let CartesianProductOfTypes = 1;
796 let ArchGuard = "!defined(__aarch64__)";
797 let BigEndianSafe = 1;
800 ////////////////////////////////////////////////////////////////////////////////
801 // Vector fused multiply-add operations
803 def VFMA : SInst<"vfma", "dddd", "fQf">;
805 ////////////////////////////////////////////////////////////////////////////////
806 // fp16 vector operations
807 def SCALAR_HALF_GET_LANE : IOpInst<"vget_lane", "sdi", "h", OP_SCALAR_HALF_GET_LN>;
808 def SCALAR_HALF_SET_LANE : IOpInst<"vset_lane", "dsdi", "h", OP_SCALAR_HALF_SET_LN>;
809 def SCALAR_HALF_GET_LANEQ : IOpInst<"vget_lane", "sdi", "Qh", OP_SCALAR_HALF_GET_LNQ>;
810 def SCALAR_HALF_SET_LANEQ : IOpInst<"vset_lane", "dsdi", "Qh", OP_SCALAR_HALF_SET_LNQ>;
812 ////////////////////////////////////////////////////////////////////////////////
813 // AArch64 Intrinsics
815 let ArchGuard = "defined(__aarch64__)" in {
817 ////////////////////////////////////////////////////////////////////////////////
819 def LD1 : WInst<"vld1", "dc", "dQdPlQPl">;
820 def LD2 : WInst<"vld2", "2c", "QUlQldQdPlQPl">;
821 def LD3 : WInst<"vld3", "3c", "QUlQldQdPlQPl">;
822 def LD4 : WInst<"vld4", "4c", "QUlQldQdPlQPl">;
823 def ST1 : WInst<"vst1", "vpd", "dQdPlQPl">;
824 def ST2 : WInst<"vst2", "vp2", "QUlQldQdPlQPl">;
825 def ST3 : WInst<"vst3", "vp3", "QUlQldQdPlQPl">;
826 def ST4 : WInst<"vst4", "vp4", "QUlQldQdPlQPl">;
828 def LD1_X2 : WInst<"vld1_x2", "2c",
829 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">;
830 def LD3_x3 : WInst<"vld1_x3", "3c",
831 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">;
832 def LD4_x4 : WInst<"vld1_x4", "4c",
833 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">;
835 def ST1_X2 : WInst<"vst1_x2", "vp2",
836 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">;
837 def ST1_X3 : WInst<"vst1_x3", "vp3",
838 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">;
839 def ST1_X4 : WInst<"vst1_x4", "vp4",
840 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">;
842 def LD1_LANE : WInst<"vld1_lane", "dcdi", "dQdPlQPl">;
843 def LD2_LANE : WInst<"vld2_lane", "2c2i", "lUlQcQUcQPcQlQUldQdPlQPl">;
844 def LD3_LANE : WInst<"vld3_lane", "3c3i", "lUlQcQUcQPcQlQUldQdPlQPl">;
845 def LD4_LANE : WInst<"vld4_lane", "4c4i", "lUlQcQUcQPcQlQUldQdPlQPl">;
846 def ST1_LANE : WInst<"vst1_lane", "vpdi", "dQdPlQPl">;
847 def ST2_LANE : WInst<"vst2_lane", "vp2i", "lUlQcQUcQPcQlQUldQdPlQPl">;
848 def ST3_LANE : WInst<"vst3_lane", "vp3i", "lUlQcQUcQPcQlQUldQdPlQPl">;
849 def ST4_LANE : WInst<"vst4_lane", "vp4i", "lUlQcQUcQPcQlQUldQdPlQPl">;
851 def LD1_DUP : WInst<"vld1_dup", "dc", "dQdPlQPl">;
852 def LD2_DUP : WInst<"vld2_dup", "2c",
853 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">;
854 def LD3_DUP : WInst<"vld3_dup", "3c",
855 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">;
856 def LD4_DUP : WInst<"vld4_dup", "4c",
857 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">;
859 def VLDRQ : WInst<"vldrq", "sc", "Pk">;
860 def VSTRQ : WInst<"vstrq", "vps", "Pk">;
862 ////////////////////////////////////////////////////////////////////////////////
864 def ADD : IOpInst<"vadd", "ddd", "dQd", OP_ADD>;
866 ////////////////////////////////////////////////////////////////////////////////
868 def SUB : IOpInst<"vsub", "ddd", "dQd", OP_SUB>;
870 ////////////////////////////////////////////////////////////////////////////////
872 def MUL : IOpInst<"vmul", "ddd", "dQd", OP_MUL>;
873 def MLA : IOpInst<"vmla", "dddd", "dQd", OP_MLA>;
874 def MLS : IOpInst<"vmls", "dddd", "dQd", OP_MLS>;
876 ////////////////////////////////////////////////////////////////////////////////
877 // Multiplication Extended
878 def MULX : SInst<"vmulx", "ddd", "fdQfQd">;
880 ////////////////////////////////////////////////////////////////////////////////
882 def FDIV : IOpInst<"vdiv", "ddd", "fdQfQd", OP_DIV>;
884 ////////////////////////////////////////////////////////////////////////////////
885 // Vector fused multiply-add operations
886 def FMLA : SInst<"vfma", "dddd", "dQd">;
887 def FMLS : SInst<"vfms", "dddd", "fdQfQd">;
889 ////////////////////////////////////////////////////////////////////////////////
890 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
891 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
893 def FMLA_N : SOpInst<"vfma_n", "ddds", "fQfQd", OP_FMLA_N>;
894 def FMLS_N : SOpInst<"vfms_n", "ddds", "fQfQd", OP_FMLS_N>;
896 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>;
897 def MLS_N : SOpInst<"vmls_n", "ddds", "Qd", OP_MLS_N>;
899 ////////////////////////////////////////////////////////////////////////////////
900 // Logical operations
901 def BSL : SInst<"vbsl", "dudd", "dPlQdQPl">;
903 ////////////////////////////////////////////////////////////////////////////////
904 // Absolute Difference
905 def ABD : SInst<"vabd", "ddd", "dQd">;
907 ////////////////////////////////////////////////////////////////////////////////
908 // saturating absolute/negate
909 def ABS : SInst<"vabs", "dd", "dQdlQl">;
910 def QABS : SInst<"vqabs", "dd", "lQl">;
911 def NEG : SOpInst<"vneg", "dd", "dlQdQl", OP_NEG>;
912 def QNEG : SInst<"vqneg", "dd", "lQl">;
914 ////////////////////////////////////////////////////////////////////////////////
915 // Signed Saturating Accumulated of Unsigned Value
916 def SUQADD : SInst<"vuqadd", "ddd", "csilQcQsQiQl">;
918 ////////////////////////////////////////////////////////////////////////////////
919 // Unsigned Saturating Accumulated of Signed Value
920 def USQADD : SInst<"vsqadd", "ddd", "UcUsUiUlQUcQUsQUiQUl">;
922 ////////////////////////////////////////////////////////////////////////////////
924 def FRECPS : IInst<"vrecps", "ddd", "dQd">;
925 def FRSQRTS : IInst<"vrsqrts", "ddd", "dQd">;
927 ////////////////////////////////////////////////////////////////////////////////
929 def RBIT : IInst<"vrbit", "dd", "cUcPcQcQUcQPc">;
931 ////////////////////////////////////////////////////////////////////////////////
932 // Integer extract and narrow to high
933 def XTN2 : SOpInst<"vmovn_high", "qhk", "silUsUiUl", OP_XTN>;
935 ////////////////////////////////////////////////////////////////////////////////
936 // Signed integer saturating extract and unsigned narrow to high
937 def SQXTUN2 : SOpInst<"vqmovun_high", "qhk", "sil", OP_SQXTUN>;
939 ////////////////////////////////////////////////////////////////////////////////
940 // Integer saturating extract and narrow to high
941 def QXTN2 : SOpInst<"vqmovn_high", "qhk", "silUsUiUl", OP_QXTN>;
943 ////////////////////////////////////////////////////////////////////////////////
944 // Converting vectors
945 def VCVT_HIGH_F16 : SOpInst<"vcvt_high_f16", "qhj", "f", OP_VCVT_NA_HI_F16>;
946 def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "wk", "h", OP_VCVT_EX_HI_F32>;
947 def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "md", "Qd">;
948 def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "qfj", "d", OP_VCVT_NA_HI_F32>;
949 def VCVT_F64_F32 : SInst<"vcvt_f64_f32", "wd", "f">;
950 def VCVT_F64 : SInst<"vcvt_f64", "Fd", "lUlQlQUl">;
951 def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "wj", "f", OP_VCVT_EX_HI_F64>;
952 def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">;
953 def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "qfj", "d", OP_VCVTX_HI>;
954 def VCVT_S64 : SInst<"vcvt_s64", "xd", "dQd">;
955 def VCVT_U64 : SInst<"vcvt_u64", "ud", "dQd">;
956 def FRECPE : SInst<"vrecpe", "dd", "dQd">;
957 def FRSQRTE : SInst<"vrsqrte", "dd", "dQd">;
958 def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">;
960 ////////////////////////////////////////////////////////////////////////////////
962 def FCAGE : IInst<"vcage", "udd", "dQd">;
963 def FCAGT : IInst<"vcagt", "udd", "dQd">;
964 def FCALE : IInst<"vcale", "udd", "dQd">;
965 def FCALT : IInst<"vcalt", "udd", "dQd">;
966 def CMTST : WInst<"vtst", "udd", "lUlPlQlQUlQPl">;
967 def CFMEQ : SOpInst<"vceq", "udd", "lUldQdQlQUlPlQPl", OP_EQ>;
968 def CFMGE : SOpInst<"vcge", "udd", "lUldQdQlQUl", OP_GE>;
969 def CFMLE : SOpInst<"vcle", "udd", "lUldQdQlQUl", OP_LE>;
970 def CFMGT : SOpInst<"vcgt", "udd", "lUldQdQlQUl", OP_GT>;
971 def CFMLT : SOpInst<"vclt", "udd", "lUldQdQlQUl", OP_LT>;
973 def CMEQ : SInst<"vceqz", "ud",
974 "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">;
975 def CMGE : SInst<"vcgez", "ud", "csilfdQcQsQiQlQfQd">;
976 def CMLE : SInst<"vclez", "ud", "csilfdQcQsQiQlQfQd">;
977 def CMGT : SInst<"vcgtz", "ud", "csilfdQcQsQiQlQfQd">;
978 def CMLT : SInst<"vcltz", "ud", "csilfdQcQsQiQlQfQd">;
980 ////////////////////////////////////////////////////////////////////////////////
982 def MAX : SInst<"vmax", "ddd", "dQd">;
983 def MIN : SInst<"vmin", "ddd", "dQd">;
985 ////////////////////////////////////////////////////////////////////////////////
987 def MAXP : SInst<"vpmax", "ddd", "QcQsQiQUcQUsQUiQfQd">;
988 def MINP : SInst<"vpmin", "ddd", "QcQsQiQUcQUsQUiQfQd">;
990 ////////////////////////////////////////////////////////////////////////////////
991 // Pairwise MaxNum/MinNum Floating Point
992 def FMAXNMP : SInst<"vpmaxnm", "ddd", "fQfQd">;
993 def FMINNMP : SInst<"vpminnm", "ddd", "fQfQd">;
995 ////////////////////////////////////////////////////////////////////////////////
997 def ADDP : IInst<"vpadd", "ddd", "QcQsQiQlQUcQUsQUiQUlQfQd">;
999 ////////////////////////////////////////////////////////////////////////////////
1000 // Shifts by constant
1001 let isShift = 1 in {
1002 // Left shift long high
1003 def SHLL_HIGH_N : SOpInst<"vshll_high_n", "ndi", "HcHsHiHUcHUsHUi",
1006 ////////////////////////////////////////////////////////////////////////////////
1007 def SRI_N : WInst<"vsri_n", "dddi", "PlQPl">;
1008 def SLI_N : WInst<"vsli_n", "dddi", "PlQPl">;
1010 // Right shift narrow high
1011 def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "hmdi",
1012 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
1013 def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "hmdi",
1014 "HsHiHl", OP_NARROW_HI>;
1015 def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "hmdi",
1016 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
1017 def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "hmdi",
1018 "HsHiHl", OP_NARROW_HI>;
1019 def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "hmdi",
1020 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
1021 def QRSHRN_HIGH_N : SOpInst<"vqrshrn_high_n", "hmdi",
1022 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
1025 ////////////////////////////////////////////////////////////////////////////////
1026 // Converting vectors
1027 def VMOVL_HIGH : SOpInst<"vmovl_high", "nd", "HcHsHiHUcHUsHUi", OP_MOVL_HI>;
1029 let isVCVT_N = 1 in {
1030 def CVTF_N_F64 : SInst<"vcvt_n_f64", "Fdi", "lUlQlQUl">;
1031 def FCVTZS_N_S64 : SInst<"vcvt_n_s64", "xdi", "dQd">;
1032 def FCVTZS_N_U64 : SInst<"vcvt_n_u64", "udi", "dQd">;
1035 ////////////////////////////////////////////////////////////////////////////////
1036 // 3VDiff class using high 64-bit in operands
1037 def VADDL_HIGH : SOpInst<"vaddl_high", "wkk", "csiUcUsUi", OP_ADDLHi>;
1038 def VADDW_HIGH : SOpInst<"vaddw_high", "wwk", "csiUcUsUi", OP_ADDWHi>;
1039 def VSUBL_HIGH : SOpInst<"vsubl_high", "wkk", "csiUcUsUi", OP_SUBLHi>;
1040 def VSUBW_HIGH : SOpInst<"vsubw_high", "wwk", "csiUcUsUi", OP_SUBWHi>;
1042 def VABDL_HIGH : SOpInst<"vabdl_high", "wkk", "csiUcUsUi", OP_ABDLHi>;
1043 def VABAL_HIGH : SOpInst<"vabal_high", "wwkk", "csiUcUsUi", OP_ABALHi>;
1045 def VMULL_HIGH : SOpInst<"vmull_high", "wkk", "csiUcUsUiPc", OP_MULLHi>;
1046 def VMULL_HIGH_N : SOpInst<"vmull_high_n", "wks", "siUsUi", OP_MULLHi_N>;
1047 def VMLAL_HIGH : SOpInst<"vmlal_high", "wwkk", "csiUcUsUi", OP_MLALHi>;
1048 def VMLAL_HIGH_N : SOpInst<"vmlal_high_n", "wwks", "siUsUi", OP_MLALHi_N>;
1049 def VMLSL_HIGH : SOpInst<"vmlsl_high", "wwkk", "csiUcUsUi", OP_MLSLHi>;
1050 def VMLSL_HIGH_N : SOpInst<"vmlsl_high_n", "wwks", "siUsUi", OP_MLSLHi_N>;
1052 def VADDHN_HIGH : SOpInst<"vaddhn_high", "qhkk", "silUsUiUl", OP_ADDHNHi>;
1053 def VRADDHN_HIGH : SOpInst<"vraddhn_high", "qhkk", "silUsUiUl", OP_RADDHNHi>;
1054 def VSUBHN_HIGH : SOpInst<"vsubhn_high", "qhkk", "silUsUiUl", OP_SUBHNHi>;
1055 def VRSUBHN_HIGH : SOpInst<"vrsubhn_high", "qhkk", "silUsUiUl", OP_RSUBHNHi>;
1057 def VQDMULL_HIGH : SOpInst<"vqdmull_high", "wkk", "si", OP_QDMULLHi>;
1058 def VQDMULL_HIGH_N : SOpInst<"vqdmull_high_n", "wks", "si", OP_QDMULLHi_N>;
1059 def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "wwkk", "si", OP_QDMLALHi>;
1060 def VQDMLAL_HIGH_N : SOpInst<"vqdmlal_high_n", "wwks", "si", OP_QDMLALHi_N>;
1061 def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "wwkk", "si", OP_QDMLSLHi>;
1062 def VQDMLSL_HIGH_N : SOpInst<"vqdmlsl_high_n", "wwks", "si", OP_QDMLSLHi_N>;
1063 def VMULL_P64 : SInst<"vmull", "rss", "Pl">;
1064 def VMULL_HIGH_P64 : SOpInst<"vmull_high", "rdd", "HPl", OP_MULLHi_P64>;
1067 ////////////////////////////////////////////////////////////////////////////////
1068 // Extract or insert element from vector
1069 def GET_LANE : IInst<"vget_lane", "sdi", "dQdPlQPl">;
1070 def SET_LANE : IInst<"vset_lane", "dsdi", "dQdPlQPl">;
1071 def COPY_LANE : IOpInst<"vcopy_lane", "ddidi",
1072 "csilUcUsUiUlPcPsPlfd", OP_COPY_LN>;
1073 def COPYQ_LANE : IOpInst<"vcopy_lane", "ddigi",
1074 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>;
1075 def COPY_LANEQ : IOpInst<"vcopy_laneq", "ddiki",
1076 "csilPcPsPlUcUsUiUlfd", OP_COPY_LN>;
1077 def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "ddidi",
1078 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>;
1080 ////////////////////////////////////////////////////////////////////////////////
1081 // Set all lanes to same value
1082 def VDUP_LANE1: WOpInst<"vdup_lane", "dgi", "hdQhQdPlQPl", OP_DUP_LN>;
1083 def VDUP_LANE2: WOpInst<"vdup_laneq", "dji",
1084 "csilUcUsUiUlPcPshfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl",
1086 def DUP_N : WOpInst<"vdup_n", "ds", "dQdPlQPl", OP_DUP>;
1087 def MOV_N : WOpInst<"vmov_n", "ds", "dQdPlQPl", OP_DUP>;
1089 ////////////////////////////////////////////////////////////////////////////////
1090 def COMBINE : NoTestOpInst<"vcombine", "kdd", "dPl", OP_CONC>;
1092 ////////////////////////////////////////////////////////////////////////////////
1093 //Initialize a vector from bit pattern
1094 def CREATE : NoTestOpInst<"vcreate", "dl", "dPl", OP_CAST> {
1095 let BigEndianSafe = 1;
1098 ////////////////////////////////////////////////////////////////////////////////
1100 def VMLA_LANEQ : IOpInst<"vmla_laneq", "dddji",
1101 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
1102 def VMLS_LANEQ : IOpInst<"vmls_laneq", "dddji",
1103 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
1105 def VFMA_LANE : IInst<"vfma_lane", "dddgi", "fdQfQd">;
1106 def VFMA_LANEQ : IInst<"vfma_laneq", "dddji", "fdQfQd"> {
1109 def VFMS_LANE : IOpInst<"vfms_lane", "dddgi", "fdQfQd", OP_FMS_LN>;
1110 def VFMS_LANEQ : IOpInst<"vfms_laneq", "dddji", "fdQfQd", OP_FMS_LNQ>;
1112 def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "wwdki", "siUsUi", OP_MLAL_LN>;
1113 def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "wwkdi", "siUsUi",
1115 def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "wwkki", "siUsUi",
1117 def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "wwdki", "siUsUi", OP_MLSL_LN>;
1118 def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "wwkdi", "siUsUi",
1120 def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "wwkki", "siUsUi",
1123 def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "wwdki", "si", OP_QDMLAL_LN>;
1124 def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "wwkdi", "si",
1126 def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "wwkki", "si",
1128 def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "wwdki", "si", OP_QDMLSL_LN>;
1129 def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "wwkdi", "si",
1131 def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "wwkki", "si",
1134 // Newly add double parameter for vmul_lane in aarch64
1135 // Note: d type is handled by SCALAR_VMUL_LANE
1136 def VMUL_LANE_A64 : IOpInst<"vmul_lane", "ddgi", "Qd", OP_MUL_LN>;
1138 // Note: d type is handled by SCALAR_VMUL_LANEQ
1139 def VMUL_LANEQ : IOpInst<"vmul_laneq", "ddji",
1140 "sifUsUiQsQiQUsQUiQfQd", OP_MUL_LN>;
1141 def VMULL_LANEQ : SOpInst<"vmull_laneq", "wdki", "siUsUi", OP_MULL_LN>;
1142 def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "wkdi", "siUsUi",
1144 def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "wkki", "siUsUi",
1147 def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "wdki", "si", OP_QDMULL_LN>;
1148 def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "wkdi", "si",
1150 def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "wkki", "si",
1153 def VQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ddji", "siQsQi", OP_QDMULH_LN>;
1154 def VQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ddji", "siQsQi", OP_QRDMULH_LN>;
1156 // Note: d type implemented by SCALAR_VMULX_LANE
1157 def VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "fQfQd", OP_MULX_LN>;
1158 // Note: d type is implemented by SCALAR_VMULX_LANEQ
1159 def VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "fQfQd", OP_MULX_LN>;
1161 ////////////////////////////////////////////////////////////////////////////////
1162 // Across vectors class
1163 def VADDLV : SInst<"vaddlv", "rd", "csiUcUsUiQcQsQiQUcQUsQUi">;
1164 def VMAXV : SInst<"vmaxv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
1165 def VMINV : SInst<"vminv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
1166 def VADDV : SInst<"vaddv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">;
1167 def FMAXNMV : SInst<"vmaxnmv", "sd", "fQfQd">;
1168 def FMINNMV : SInst<"vminnmv", "sd", "fQfQd">;
1170 ////////////////////////////////////////////////////////////////////////////////
1171 // Newly added Vector Extract for f64
1172 def VEXT_A64 : WInst<"vext", "dddi", "dQdPlQPl">;
1174 ////////////////////////////////////////////////////////////////////////////////
1176 let ArchGuard = "__ARM_FEATURE_CRYPTO" in {
1177 def AESE : SInst<"vaese", "ddd", "QUc">;
1178 def AESD : SInst<"vaesd", "ddd", "QUc">;
1179 def AESMC : SInst<"vaesmc", "dd", "QUc">;
1180 def AESIMC : SInst<"vaesimc", "dd", "QUc">;
1182 def SHA1H : SInst<"vsha1h", "ss", "Ui">;
1183 def SHA1SU1 : SInst<"vsha1su1", "ddd", "QUi">;
1184 def SHA256SU0 : SInst<"vsha256su0", "ddd", "QUi">;
1186 def SHA1C : SInst<"vsha1c", "ddsd", "QUi">;
1187 def SHA1P : SInst<"vsha1p", "ddsd", "QUi">;
1188 def SHA1M : SInst<"vsha1m", "ddsd", "QUi">;
1189 def SHA1SU0 : SInst<"vsha1su0", "dddd", "QUi">;
1190 def SHA256H : SInst<"vsha256h", "dddd", "QUi">;
1191 def SHA256H2 : SInst<"vsha256h2", "dddd", "QUi">;
1192 def SHA256SU1 : SInst<"vsha256su1", "dddd", "QUi">;
1195 ////////////////////////////////////////////////////////////////////////////////
1196 // Float -> Int conversions with explicit rounding mode
1198 let ArchGuard = "__ARM_ARCH >= 8" in {
1199 def FCVTNS_S32 : SInst<"vcvtn_s32", "xd", "fQf">;
1200 def FCVTNU_S32 : SInst<"vcvtn_u32", "ud", "fQf">;
1201 def FCVTPS_S32 : SInst<"vcvtp_s32", "xd", "fQf">;
1202 def FCVTPU_S32 : SInst<"vcvtp_u32", "ud", "fQf">;
1203 def FCVTMS_S32 : SInst<"vcvtm_s32", "xd", "fQf">;
1204 def FCVTMU_S32 : SInst<"vcvtm_u32", "ud", "fQf">;
1205 def FCVTAS_S32 : SInst<"vcvta_s32", "xd", "fQf">;
1206 def FCVTAU_S32 : SInst<"vcvta_u32", "ud", "fQf">;
1209 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
1210 def FCVTNS_S64 : SInst<"vcvtn_s64", "xd", "dQd">;
1211 def FCVTNU_S64 : SInst<"vcvtn_u64", "ud", "dQd">;
1212 def FCVTPS_S64 : SInst<"vcvtp_s64", "xd", "dQd">;
1213 def FCVTPU_S64 : SInst<"vcvtp_u64", "ud", "dQd">;
1214 def FCVTMS_S64 : SInst<"vcvtm_s64", "xd", "dQd">;
1215 def FCVTMU_S64 : SInst<"vcvtm_u64", "ud", "dQd">;
1216 def FCVTAS_S64 : SInst<"vcvta_s64", "xd", "dQd">;
1217 def FCVTAU_S64 : SInst<"vcvta_u64", "ud", "dQd">;
1220 ////////////////////////////////////////////////////////////////////////////////
1221 // Round to Integral
1223 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
1224 def FRINTN_S32 : SInst<"vrndn", "dd", "fQf">;
1225 def FRINTA_S32 : SInst<"vrnda", "dd", "fQf">;
1226 def FRINTP_S32 : SInst<"vrndp", "dd", "fQf">;
1227 def FRINTM_S32 : SInst<"vrndm", "dd", "fQf">;
1228 def FRINTX_S32 : SInst<"vrndx", "dd", "fQf">;
1229 def FRINTZ_S32 : SInst<"vrnd", "dd", "fQf">;
1232 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
1233 def FRINTN_S64 : SInst<"vrndn", "dd", "dQd">;
1234 def FRINTA_S64 : SInst<"vrnda", "dd", "dQd">;
1235 def FRINTP_S64 : SInst<"vrndp", "dd", "dQd">;
1236 def FRINTM_S64 : SInst<"vrndm", "dd", "dQd">;
1237 def FRINTX_S64 : SInst<"vrndx", "dd", "dQd">;
1238 def FRINTZ_S64 : SInst<"vrnd", "dd", "dQd">;
1239 def FRINTI_S64 : SInst<"vrndi", "dd", "fdQfQd">;
1242 ////////////////////////////////////////////////////////////////////////////////
1243 // MaxNum/MinNum Floating Point
1245 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in {
1246 def FMAXNM_S32 : SInst<"vmaxnm", "ddd", "fQf">;
1247 def FMINNM_S32 : SInst<"vminnm", "ddd", "fQf">;
1250 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in {
1251 def FMAXNM_S64 : SInst<"vmaxnm", "ddd", "dQd">;
1252 def FMINNM_S64 : SInst<"vminnm", "ddd", "dQd">;
1255 ////////////////////////////////////////////////////////////////////////////////
1257 def VTRN1 : SOpInst<"vtrn1", "ddd",
1258 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN1>;
1259 def VZIP1 : SOpInst<"vzip1", "ddd",
1260 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP1>;
1261 def VUZP1 : SOpInst<"vuzp1", "ddd",
1262 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP1>;
1263 def VTRN2 : SOpInst<"vtrn2", "ddd",
1264 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN2>;
1265 def VZIP2 : SOpInst<"vzip2", "ddd",
1266 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP2>;
1267 def VUZP2 : SOpInst<"vuzp2", "ddd",
1268 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP2>;
1270 ////////////////////////////////////////////////////////////////////////////////
1272 let InstName = "vtbl" in {
1273 def VQTBL1_A64 : WInst<"vqtbl1", "djt", "UccPcQUcQcQPc">;
1274 def VQTBL2_A64 : WInst<"vqtbl2", "dBt", "UccPcQUcQcQPc">;
1275 def VQTBL3_A64 : WInst<"vqtbl3", "dCt", "UccPcQUcQcQPc">;
1276 def VQTBL4_A64 : WInst<"vqtbl4", "dDt", "UccPcQUcQcQPc">;
1278 let InstName = "vtbx" in {
1279 def VQTBX1_A64 : WInst<"vqtbx1", "ddjt", "UccPcQUcQcQPc">;
1280 def VQTBX2_A64 : WInst<"vqtbx2", "ddBt", "UccPcQUcQcQPc">;
1281 def VQTBX3_A64 : WInst<"vqtbx3", "ddCt", "UccPcQUcQcQPc">;
1282 def VQTBX4_A64 : WInst<"vqtbx4", "ddDt", "UccPcQUcQcQPc">;
1285 ////////////////////////////////////////////////////////////////////////////////
1286 // Vector reinterpret cast operations
1288 // NeonEmitter implicitly takes the cartesian product of the type string with
1289 // itself during generation so, unlike all other intrinsics, this one should
1290 // include *all* types, not just additional ones.
1292 : NoTestOpInst<"vreinterpret", "dd",
1293 "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", OP_REINT> {
1294 let CartesianProductOfTypes = 1;
1295 let BigEndianSafe = 1;
1296 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)";
1299 ////////////////////////////////////////////////////////////////////////////////
1300 // Scalar Intrinsics
1301 // Scalar Arithmetic
1304 def SCALAR_ADD : SInst<"vadd", "sss", "SlSUl">;
1305 // Scalar Saturating Add
1306 def SCALAR_QADD : SInst<"vqadd", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1308 // Scalar Subtraction
1309 def SCALAR_SUB : SInst<"vsub", "sss", "SlSUl">;
1310 // Scalar Saturating Sub
1311 def SCALAR_QSUB : SInst<"vqsub", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1313 let InstName = "vmov" in {
1314 def VGET_HIGH_A64 : NoTestOpInst<"vget_high", "dk", "dPl", OP_HI>;
1315 def VGET_LOW_A64 : NoTestOpInst<"vget_low", "dk", "dPl", OP_LO>;
1318 ////////////////////////////////////////////////////////////////////////////////
1320 // Scalar Shift Left
1321 def SCALAR_SHL: SInst<"vshl", "sss", "SlSUl">;
1322 // Scalar Saturating Shift Left
1323 def SCALAR_QSHL: SInst<"vqshl", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1324 // Scalar Saturating Rounding Shift Left
1325 def SCALAR_QRSHL: SInst<"vqrshl", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1326 // Scalar Shift Rouding Left
1327 def SCALAR_RSHL: SInst<"vrshl", "sss", "SlSUl">;
1329 ////////////////////////////////////////////////////////////////////////////////
1330 // Scalar Shift (Immediate)
1331 let isScalarShift = 1 in {
1332 // Signed/Unsigned Shift Right (Immediate)
1333 def SCALAR_SSHR_N: SInst<"vshr_n", "ssi", "SlSUl">;
1334 // Signed/Unsigned Rounding Shift Right (Immediate)
1335 def SCALAR_SRSHR_N: SInst<"vrshr_n", "ssi", "SlSUl">;
1337 // Signed/Unsigned Shift Right and Accumulate (Immediate)
1338 def SCALAR_SSRA_N: SInst<"vsra_n", "sssi", "SlSUl">;
1339 // Signed/Unsigned Rounding Shift Right and Accumulate (Immediate)
1340 def SCALAR_SRSRA_N: SInst<"vrsra_n", "sssi", "SlSUl">;
1342 // Shift Left (Immediate)
1343 def SCALAR_SHL_N: SInst<"vshl_n", "ssi", "SlSUl">;
1344 // Signed/Unsigned Saturating Shift Left (Immediate)
1345 def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">;
1346 // Signed Saturating Shift Left Unsigned (Immediate)
1347 def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">;
1349 // Shift Right And Insert (Immediate)
1350 def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">;
1351 // Shift Left And Insert (Immediate)
1352 def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">;
1354 let isScalarNarrowShift = 1 in {
1355 // Signed/Unsigned Saturating Shift Right Narrow (Immediate)
1356 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">;
1357 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)
1358 def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "zsi", "SsSiSlSUsSUiSUl">;
1359 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
1360 def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "zsi", "SsSiSl">;
1361 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
1362 def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "zsi", "SsSiSl">;
1365 ////////////////////////////////////////////////////////////////////////////////
1366 // Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate)
1367 def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "ysi", "SiSUi">;
1368 def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "osi", "SlSUl">;
1370 ////////////////////////////////////////////////////////////////////////////////
1371 // Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate)
1372 def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "$si", "Sf">;
1373 def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "bsi", "Sf">;
1374 def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "$si", "Sd">;
1375 def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "bsi", "Sd">;
1378 ////////////////////////////////////////////////////////////////////////////////
1379 // Scalar Reduce Pairwise Addition (Scalar and Floating Point)
1380 def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHdSHUl">;
1382 ////////////////////////////////////////////////////////////////////////////////
1383 // Scalar Reduce Floating Point Pairwise Max/Min
1384 def SCALAR_FMAXP : SInst<"vpmax", "sd", "SfSQd">;
1386 def SCALAR_FMINP : SInst<"vpmin", "sd", "SfSQd">;
1388 ////////////////////////////////////////////////////////////////////////////////
1389 // Scalar Reduce Floating Point Pairwise maxNum/minNum
1390 def SCALAR_FMAXNMP : SInst<"vpmaxnm", "sd", "SfSQd">;
1391 def SCALAR_FMINNMP : SInst<"vpminnm", "sd", "SfSQd">;
1393 ////////////////////////////////////////////////////////////////////////////////
1394 // Scalar Integer Saturating Doubling Multiply Half High
1395 def SCALAR_SQDMULH : SInst<"vqdmulh", "sss", "SsSi">;
1397 ////////////////////////////////////////////////////////////////////////////////
1398 // Scalar Integer Saturating Rounding Doubling Multiply Half High
1399 def SCALAR_SQRDMULH : SInst<"vqrdmulh", "sss", "SsSi">;
1401 ////////////////////////////////////////////////////////////////////////////////
1402 // Scalar Floating-point Multiply Extended
1403 def SCALAR_FMULX : IInst<"vmulx", "sss", "SfSd">;
1405 ////////////////////////////////////////////////////////////////////////////////
1406 // Scalar Floating-point Reciprocal Step
1407 def SCALAR_FRECPS : IInst<"vrecps", "sss", "SfSd">;
1409 ////////////////////////////////////////////////////////////////////////////////
1410 // Scalar Floating-point Reciprocal Square Root Step
1411 def SCALAR_FRSQRTS : IInst<"vrsqrts", "sss", "SfSd">;
1413 ////////////////////////////////////////////////////////////////////////////////
1414 // Scalar Signed Integer Convert To Floating-point
1415 def SCALAR_SCVTFS : SInst<"vcvt_f32", "ys", "Si">;
1416 def SCALAR_SCVTFD : SInst<"vcvt_f64", "os", "Sl">;
1418 ////////////////////////////////////////////////////////////////////////////////
1419 // Scalar Unsigned Integer Convert To Floating-point
1420 def SCALAR_UCVTFS : SInst<"vcvt_f32", "ys", "SUi">;
1421 def SCALAR_UCVTFD : SInst<"vcvt_f64", "os", "SUl">;
1423 ////////////////////////////////////////////////////////////////////////////////
1424 // Scalar Floating-point Converts
1425 def SCALAR_FCVTXN : IInst<"vcvtx_f32", "ys", "Sd">;
1426 def SCALAR_FCVTNSS : SInst<"vcvtn_s32", "$s", "Sf">;
1427 def SCALAR_FCVTNUS : SInst<"vcvtn_u32", "bs", "Sf">;
1428 def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "$s", "Sd">;
1429 def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "bs", "Sd">;
1430 def SCALAR_FCVTMSS : SInst<"vcvtm_s32", "$s", "Sf">;
1431 def SCALAR_FCVTMUS : SInst<"vcvtm_u32", "bs", "Sf">;
1432 def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "$s", "Sd">;
1433 def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "bs", "Sd">;
1434 def SCALAR_FCVTASS : SInst<"vcvta_s32", "$s", "Sf">;
1435 def SCALAR_FCVTAUS : SInst<"vcvta_u32", "bs", "Sf">;
1436 def SCALAR_FCVTASD : SInst<"vcvta_s64", "$s", "Sd">;
1437 def SCALAR_FCVTAUD : SInst<"vcvta_u64", "bs", "Sd">;
1438 def SCALAR_FCVTPSS : SInst<"vcvtp_s32", "$s", "Sf">;
1439 def SCALAR_FCVTPUS : SInst<"vcvtp_u32", "bs", "Sf">;
1440 def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "$s", "Sd">;
1441 def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "bs", "Sd">;
1442 def SCALAR_FCVTZSS : SInst<"vcvt_s32", "$s", "Sf">;
1443 def SCALAR_FCVTZUS : SInst<"vcvt_u32", "bs", "Sf">;
1444 def SCALAR_FCVTZSD : SInst<"vcvt_s64", "$s", "Sd">;
1445 def SCALAR_FCVTZUD : SInst<"vcvt_u64", "bs", "Sd">;
1447 ////////////////////////////////////////////////////////////////////////////////
1448 // Scalar Floating-point Reciprocal Estimate
1449 def SCALAR_FRECPE : IInst<"vrecpe", "ss", "SfSd">;
1451 ////////////////////////////////////////////////////////////////////////////////
1452 // Scalar Floating-point Reciprocal Exponent
1453 def SCALAR_FRECPX : IInst<"vrecpx", "ss", "SfSd">;
1455 ////////////////////////////////////////////////////////////////////////////////
1456 // Scalar Floating-point Reciprocal Square Root Estimate
1457 def SCALAR_FRSQRTE : IInst<"vrsqrte", "ss", "SfSd">;
1459 ////////////////////////////////////////////////////////////////////////////////
1460 // Scalar Integer Comparison
1461 def SCALAR_CMEQ : SInst<"vceq", "sss", "SlSUl">;
1462 def SCALAR_CMEQZ : SInst<"vceqz", "ss", "SlSUl">;
1463 def SCALAR_CMGE : SInst<"vcge", "sss", "Sl">;
1464 def SCALAR_CMGEZ : SInst<"vcgez", "ss", "Sl">;
1465 def SCALAR_CMHS : SInst<"vcge", "sss", "SUl">;
1466 def SCALAR_CMLE : SInst<"vcle", "sss", "SlSUl">;
1467 def SCALAR_CMLEZ : SInst<"vclez", "ss", "Sl">;
1468 def SCALAR_CMLT : SInst<"vclt", "sss", "SlSUl">;
1469 def SCALAR_CMLTZ : SInst<"vcltz", "ss", "Sl">;
1470 def SCALAR_CMGT : SInst<"vcgt", "sss", "Sl">;
1471 def SCALAR_CMGTZ : SInst<"vcgtz", "ss", "Sl">;
1472 def SCALAR_CMHI : SInst<"vcgt", "sss", "SUl">;
1473 def SCALAR_CMTST : SInst<"vtst", "sss", "SlSUl">;
1475 ////////////////////////////////////////////////////////////////////////////////
1476 // Scalar Floating-point Comparison
1477 def SCALAR_FCMEQ : IInst<"vceq", "bss", "SfSd">;
1478 def SCALAR_FCMEQZ : IInst<"vceqz", "bs", "SfSd">;
1479 def SCALAR_FCMGE : IInst<"vcge", "bss", "SfSd">;
1480 def SCALAR_FCMGEZ : IInst<"vcgez", "bs", "SfSd">;
1481 def SCALAR_FCMGT : IInst<"vcgt", "bss", "SfSd">;
1482 def SCALAR_FCMGTZ : IInst<"vcgtz", "bs", "SfSd">;
1483 def SCALAR_FCMLE : IInst<"vcle", "bss", "SfSd">;
1484 def SCALAR_FCMLEZ : IInst<"vclez", "bs", "SfSd">;
1485 def SCALAR_FCMLT : IInst<"vclt", "bss", "SfSd">;
1486 def SCALAR_FCMLTZ : IInst<"vcltz", "bs", "SfSd">;
1488 ////////////////////////////////////////////////////////////////////////////////
1489 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
1490 def SCALAR_FACGE : IInst<"vcage", "bss", "SfSd">;
1491 def SCALAR_FACLE : IInst<"vcale", "bss", "SfSd">;
1493 ////////////////////////////////////////////////////////////////////////////////
1494 // Scalar Floating-point Absolute Compare Mask Greater Than
1495 def SCALAR_FACGT : IInst<"vcagt", "bss", "SfSd">;
1496 def SCALAR_FACLT : IInst<"vcalt", "bss", "SfSd">;
1498 ////////////////////////////////////////////////////////////////////////////////
1499 // Scalar Absolute Value
1500 def SCALAR_ABS : SInst<"vabs", "ss", "Sl">;
1502 ////////////////////////////////////////////////////////////////////////////////
1503 // Scalar Absolute Difference
1504 def SCALAR_ABD : IInst<"vabd", "sss", "SfSd">;
1506 ////////////////////////////////////////////////////////////////////////////////
1507 // Scalar Signed Saturating Absolute Value
1508 def SCALAR_SQABS : SInst<"vqabs", "ss", "ScSsSiSl">;
1510 ////////////////////////////////////////////////////////////////////////////////
1512 def SCALAR_NEG : SInst<"vneg", "ss", "Sl">;
1514 ////////////////////////////////////////////////////////////////////////////////
1515 // Scalar Signed Saturating Negate
1516 def SCALAR_SQNEG : SInst<"vqneg", "ss", "ScSsSiSl">;
1518 ////////////////////////////////////////////////////////////////////////////////
1519 // Scalar Signed Saturating Accumulated of Unsigned Value
1520 def SCALAR_SUQADD : SInst<"vuqadd", "sss", "ScSsSiSl">;
1522 ////////////////////////////////////////////////////////////////////////////////
1523 // Scalar Unsigned Saturating Accumulated of Signed Value
1524 def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">;
1526 ////////////////////////////////////////////////////////////////////////////////
1527 // Signed Saturating Doubling Multiply-Add Long
1528 def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">;
1530 ////////////////////////////////////////////////////////////////////////////////
1531 // Signed Saturating Doubling Multiply-Subtract Long
1532 def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">;
1534 ////////////////////////////////////////////////////////////////////////////////
1535 // Signed Saturating Doubling Multiply Long
1536 def SCALAR_SQDMULL : SInst<"vqdmull", "rss", "SsSi">;
1538 ////////////////////////////////////////////////////////////////////////////////
1539 // Scalar Signed Saturating Extract Unsigned Narrow
1540 def SCALAR_SQXTUN : SInst<"vqmovun", "zs", "SsSiSl">;
1542 ////////////////////////////////////////////////////////////////////////////////
1543 // Scalar Signed Saturating Extract Narrow
1544 def SCALAR_SQXTN : SInst<"vqmovn", "zs", "SsSiSl">;
1546 ////////////////////////////////////////////////////////////////////////////////
1547 // Scalar Unsigned Saturating Extract Narrow
1548 def SCALAR_UQXTN : SInst<"vqmovn", "zs", "SUsSUiSUl">;
1550 // Scalar Floating Point multiply (scalar, by element)
1551 def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "ssdi", "SfSd", OP_SCALAR_MUL_LN>;
1552 def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "ssji", "SfSd", OP_SCALAR_MUL_LN>;
1554 // Scalar Floating Point multiply extended (scalar, by element)
1555 def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "ssdi", "SfSd", OP_SCALAR_MULX_LN>;
1556 def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "ssji", "SfSd", OP_SCALAR_MULX_LN>;
1558 def SCALAR_VMUL_N : IInst<"vmul_n", "dds", "d">;
1560 // VMUL_LANE_A64 d type implemented using scalar mul lane
1561 def SCALAR_VMUL_LANE : IInst<"vmul_lane", "ddgi", "d">;
1563 // VMUL_LANEQ d type implemented using scalar mul lane
1564 def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "ddji", "d"> {
1568 // VMULX_LANE d type implemented using scalar vmulx_lane
1569 def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "d", OP_SCALAR_VMULX_LN>;
1571 // VMULX_LANEQ d type implemented using scalar vmulx_laneq
1572 def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "d", OP_SCALAR_VMULX_LNQ>;
1574 // Scalar Floating Point fused multiply-add (scalar, by element)
1575 def SCALAR_FMLA_LANE : IInst<"vfma_lane", "sssdi", "SfSd">;
1576 def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "sssji", "SfSd">;
1578 // Scalar Floating Point fused multiply-subtract (scalar, by element)
1579 def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "sssdi", "SfSd", OP_FMS_LN>;
1580 def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "sssji", "SfSd", OP_FMS_LNQ>;
1582 // Signed Saturating Doubling Multiply Long (scalar by element)
1583 def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "rsdi", "SsSi", OP_SCALAR_QDMULL_LN>;
1584 def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "rsji", "SsSi", OP_SCALAR_QDMULL_LN>;
1586 // Signed Saturating Doubling Multiply-Add Long (scalar by element)
1587 def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "rrsdi", "SsSi">;
1588 def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "rrsji", "SsSi">;
1590 // Signed Saturating Doubling Multiply-Subtract Long (scalar by element)
1591 def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "rrsdi", "SsSi">;
1592 def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "rrsji", "SsSi">;
1594 // Scalar Integer Saturating Doubling Multiply Half High (scalar by element)
1595 def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QDMULH_LN>;
1596 def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QDMULH_LN>;
1598 // Scalar Integer Saturating Rounding Doubling Multiply Half High
1599 def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QRDMULH_LN>;
1600 def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QRDMULH_LN>;
1602 def SCALAR_VDUP_LANE : IInst<"vdup_lane", "sdi", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;
1603 def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "sji", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;