1 //===--- arm_neon.td - ARM NEON compiler interface ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TableGen definitions from which the ARM NEON header
11 // file will be generated. See ARM document DUI0348B.
13 //===----------------------------------------------------------------------===//
18 def OP_UNAVAILABLE : Op;
50 def OP_MULLHi_LN : Op;
54 def OP_MLALHi_LN : Op;
56 def OP_MLSLHi_LN : Op;
57 def OP_QDMULL_LN : Op;
58 def OP_QDMULLHi_LN : Op;
59 def OP_QDMLAL_LN : Op;
60 def OP_QDMLALHi_LN : Op;
61 def OP_QDMLSL_LN : Op;
62 def OP_QDMLSLHi_LN : Op;
63 def OP_QDMULH_LN : Op;
64 def OP_QRDMULH_LN : Op;
98 def OP_VCVT_NA_HI : Op;
99 def OP_VCVT_EX_HI : Op;
100 def OP_VCVTX_HI : Op;
103 def OP_RADDHNHi : Op;
105 def OP_RSUBHNHi : Op;
111 def OP_QDMULLHi : Op;
112 def OP_QDMULLHi_N : Op;
113 def OP_QDMLALHi : Op;
114 def OP_QDMLALHi_N : Op;
115 def OP_QDMLSLHi : Op;
116 def OP_QDMLSLHi_N : Op;
119 def OP_NARROW_HI : Op;
122 def OP_COPYQ_LN : Op;
123 def OP_COPY_LNQ : Op;
124 def OP_SCALAR_MUL_LN : Op;
125 def OP_SCALAR_MUL_LNQ : Op;
126 def OP_SCALAR_MULX_LN : Op;
127 def OP_SCALAR_MULX_LNQ : Op;
128 def OP_SCALAR_VMULX_LN : Op;
129 def OP_SCALAR_VMULX_LNQ : Op;
130 def OP_SCALAR_QDMULL_LN : Op;
131 def OP_SCALAR_QDMULL_LNQ : Op;
132 def OP_SCALAR_QDMULH_LN : Op;
133 def OP_SCALAR_QDMULH_LNQ : Op;
134 def OP_SCALAR_QRDMULH_LN : Op;
135 def OP_SCALAR_QRDMULH_LNQ : Op;
136 def OP_SCALAR_GET_LN : Op;
137 def OP_SCALAR_SET_LN : Op;
139 class Inst <string n, string p, string t, Op o> {
141 string Prototype = p;
145 bit isScalarShift = 0;
146 bit isScalarNarrowShift = 0;
151 // Certain intrinsics have different names than their representative
152 // instructions. This field allows us to handle this correctly when we
153 // are generating tests.
154 string InstName = "";
156 // Certain intrinsics even though they are not a WOpInst or LOpInst,
157 // generate a WOpInst/LOpInst instruction (see below for definition
158 // of a WOpInst/LOpInst). For testing purposes we need to know
159 // this. Ex: vset_lane which outputs vmov instructions.
160 bit isHiddenWInst = 0;
161 bit isHiddenLInst = 0;
164 // The following instruction classes are implemented via builtins.
165 // These declarations are used to generate Builtins.def:
167 // SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8")
168 // IInst: Instruction with generic integer suffix (e.g., "i8")
169 // WInst: Instruction with only bit size suffix (e.g., "8")
170 class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
171 class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
172 class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
174 // The following instruction classes are implemented via operators
175 // instead of builtins. As such these declarations are only used for
176 // the purpose of generating tests.
178 // SOpInst: Instruction with signed/unsigned suffix (e.g., "s8",
180 // IOpInst: Instruction with generic integer suffix (e.g., "i8").
181 // WOpInst: Instruction with bit size only suffix (e.g., "8").
182 // LOpInst: Logical instruction with no bit size suffix.
183 // NoTestOpInst: Intrinsic that has no corresponding instruction.
184 class SOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
185 class IOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
186 class WOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
187 class LOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
188 class NoTestOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
190 // prototype: return (arg, arg, ...)
192 // t: best-fit integer (int/poly args)
193 // x: signed integer (int/float args)
194 // u: unsigned integer (int/float args)
195 // f: float (int args)
196 // F: double (int args)
198 // g: default, ignore 'Q' size modifier.
199 // j: default, force 'Q' size modifier.
200 // w: double width elements, same num elts
201 // n: double width elements, half num elts
202 // h: half width elements, double num elts
203 // q: half width elements, quad num elts
204 // e: half width elements, double num elts, unsigned
205 // m: half width elements, same num elts
207 // l: constant uint64
208 // s: scalar of element type
209 // z: scalar of half width element type, signed
210 // r: scalar of double width element type, signed
211 // a: scalar of element type (splat to vector type)
212 // b: scalar of unsigned integer/long type (int/float args)
213 // $: scalar of signed integer/long type (int/float args)
214 // y: scalar of float
215 // o: scalar of double
216 // k: default elt width, double num elts
217 // 2,3,4: array of default vectors
218 // B,C,D: array of default elts, force 'Q' size modifier.
220 // c: const pointer type
232 // S: scalar, only used for function mangling.
235 // H: 128b without mangling 'q'
238 ////////////////////////////////////////////////////////////////////////////////
240 def VADD : IOpInst<"vadd", "ddd",
241 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
242 def VADDL : SOpInst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>;
243 def VADDW : SOpInst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>;
244 def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
245 def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
246 def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
247 def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">;
248 def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">;
250 ////////////////////////////////////////////////////////////////////////////////
251 // E.3.2 Multiplication
252 def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>;
253 def VMULP : SInst<"vmul", "ddd", "PcQPc">;
254 def VMLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
255 def VMLAL : SOpInst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>;
256 def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
257 def VMLSL : SOpInst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>;
258 def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">;
259 def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">;
260 def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">;
261 def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">;
262 def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">;
263 def VQDMULL : SInst<"vqdmull", "wdd", "si">;
265 ////////////////////////////////////////////////////////////////////////////////
267 def VSUB : IOpInst<"vsub", "ddd",
268 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
269 def VSUBL : SOpInst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>;
270 def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>;
271 def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
272 def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
273 def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">;
274 def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">;
276 ////////////////////////////////////////////////////////////////////////////////
278 def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
279 def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
280 let InstName = "vcge" in
281 def VCLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
282 def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
283 let InstName = "vcgt" in
284 def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
285 let InstName = "vacge" in {
286 def VCAGE : IInst<"vcage", "udd", "fQf">;
287 def VCALE : IInst<"vcale", "udd", "fQf">;
289 let InstName = "vacgt" in {
290 def VCAGT : IInst<"vcagt", "udd", "fQf">;
291 def VCALT : IInst<"vcalt", "udd", "fQf">;
293 def VTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">;
295 ////////////////////////////////////////////////////////////////////////////////
296 // E.3.5 Absolute Difference
297 def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
298 def VABDL : SOpInst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>;
299 def VABA : SOpInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>;
300 def VABAL : SOpInst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>;
302 ////////////////////////////////////////////////////////////////////////////////
304 def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
305 def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
307 ////////////////////////////////////////////////////////////////////////////////
308 // E.3.7 Pairwise Addition
309 def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">;
310 def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
311 def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
313 ////////////////////////////////////////////////////////////////////////////////
314 // E.3.8-9 Folding Max/Min
315 def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">;
316 def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">;
318 ////////////////////////////////////////////////////////////////////////////////
319 // E.3.10 Reciprocal/Sqrt
320 def VRECPS : IInst<"vrecps", "ddd", "fQf">;
321 def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">;
323 ////////////////////////////////////////////////////////////////////////////////
324 // E.3.11 Shifts by signed variable
325 def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
326 def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
327 def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
328 def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
330 ////////////////////////////////////////////////////////////////////////////////
331 // E.3.12 Shifts by constant
333 def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
334 def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
335 def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
336 def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
337 def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
338 def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
339 def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">;
340 def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">;
341 def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">;
342 def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">;
343 def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">;
344 def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">;
345 def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">;
346 def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">;
348 ////////////////////////////////////////////////////////////////////////////////
349 // E.3.13 Shifts with insert
350 def VSRI_N : WInst<"vsri_n", "dddi",
351 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
352 def VSLI_N : WInst<"vsli_n", "dddi",
353 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
356 ////////////////////////////////////////////////////////////////////////////////
357 // E.3.14 Loads and stores of a single vector
358 def VLD1 : WInst<"vld1", "dc",
359 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
360 def VLD1_LANE : WInst<"vld1_lane", "dcdi",
361 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
362 def VLD1_DUP : WInst<"vld1_dup", "dc",
363 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
364 def VST1 : WInst<"vst1", "vpd",
365 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
366 def VST1_LANE : WInst<"vst1_lane", "vpdi",
367 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
369 ////////////////////////////////////////////////////////////////////////////////
370 // E.3.15 Loads and stores of an N-element structure
371 def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
372 def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
373 def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
374 def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">;
375 def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">;
376 def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">;
377 def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
378 def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
379 def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
380 def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
381 def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
382 def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
383 def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
384 def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
385 def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
387 ////////////////////////////////////////////////////////////////////////////////
388 // E.3.16 Extract lanes from a vector
389 let InstName = "vmov" in
390 def VGET_LANE : IInst<"vget_lane", "sdi",
391 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
393 ////////////////////////////////////////////////////////////////////////////////
394 // E.3.17 Set lanes within a vector
395 let InstName = "vmov" in
396 def VSET_LANE : IInst<"vset_lane", "dsdi",
397 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
399 ////////////////////////////////////////////////////////////////////////////////
400 // E.3.18 Initialize a vector from bit pattern
401 def VCREATE : NoTestOpInst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST>;
403 ////////////////////////////////////////////////////////////////////////////////
404 // E.3.19 Set all lanes to same value
405 let InstName = "vmov" in {
406 def VDUP_N : WOpInst<"vdup_n", "ds",
407 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
408 def VMOV_N : WOpInst<"vmov_n", "ds",
409 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
412 def VDUP_LANE: WOpInst<"vdup_lane", "dgi",
413 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl",
416 ////////////////////////////////////////////////////////////////////////////////
417 // E.3.20 Combining vectors
418 def VCOMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>;
420 ////////////////////////////////////////////////////////////////////////////////
421 // E.3.21 Splitting vectors
422 let InstName = "vmov" in {
423 def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
424 def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
427 ////////////////////////////////////////////////////////////////////////////////
428 // E.3.22 Converting vectors
429 def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">;
430 def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">;
431 def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">;
432 def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">;
433 def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">;
434 let isVCVT_N = 1 in {
435 def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">;
436 def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">;
437 def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">;
439 def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">;
440 def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">;
441 def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">;
442 def VQMOVUN : SInst<"vqmovun", "ek", "sil">;
444 ////////////////////////////////////////////////////////////////////////////////
445 // E.3.23-24 Table lookup, Extended table lookup
446 let InstName = "vtbl" in {
447 def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">;
448 def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">;
449 def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">;
450 def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">;
452 let InstName = "vtbx" in {
453 def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">;
454 def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">;
455 def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">;
456 def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">;
459 ////////////////////////////////////////////////////////////////////////////////
460 // E.3.25 Operations with a scalar value
461 def VMLA_LANE : IOpInst<"vmla_lane", "dddgi",
462 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
463 def VMLAL_LANE : SOpInst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>;
464 def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>;
465 def VMLS_LANE : IOpInst<"vmls_lane", "dddgi",
466 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
467 def VMLSL_LANE : SOpInst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>;
468 def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>;
469 def VMUL_N : IOpInst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
470 def VMUL_LANE : IOpInst<"vmul_lane", "ddgi",
471 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
472 def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">;
473 def VMULL_LANE : SOpInst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>;
474 def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">;
475 def VQDMULL_LANE : SOpInst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>;
476 def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">;
477 def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>;
478 def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">;
479 def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>;
480 def VMLA_N : IOpInst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
481 def VMLAL_N : SOpInst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>;
482 def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">;
483 def VMLS_N : IOpInst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>;
484 def VMLSL_N : SOpInst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>;
485 def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">;
487 ////////////////////////////////////////////////////////////////////////////////
488 // E.3.26 Vector Extract
489 def VEXT : WInst<"vext", "dddi",
490 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">;
492 ////////////////////////////////////////////////////////////////////////////////
493 // E.3.27 Reverse vector elements
494 def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
496 def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
497 def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>;
499 ////////////////////////////////////////////////////////////////////////////////
500 // E.3.28 Other single operand arithmetic
501 def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">;
502 def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">;
503 def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>;
504 def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">;
505 def VCLS : SInst<"vcls", "dd", "csiQcQsQi">;
506 def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
507 def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">;
508 def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">;
509 def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">;
511 ////////////////////////////////////////////////////////////////////////////////
512 // E.3.29 Logical operations
513 def VMVN : LOpInst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
514 def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
515 def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
516 def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
517 def VBIC : LOpInst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
518 def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
519 let isHiddenLInst = 1 in
520 def VBSL : SInst<"vbsl", "dudd",
521 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">;
523 ////////////////////////////////////////////////////////////////////////////////
524 // E.3.30 Transposition operations
525 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
526 def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
527 def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
529 ////////////////////////////////////////////////////////////////////////////////
530 // E.3.31 Vector reinterpret cast operations
532 : NoTestOpInst<"vreinterpret", "dd",
533 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT>;
535 ////////////////////////////////////////////////////////////////////////////////
536 // Vector fused multiply-add operations
538 def VFMA : SInst<"vfma", "dddd", "fQf">;
540 ////////////////////////////////////////////////////////////////////////////////
541 // AArch64 Intrinsics
545 ////////////////////////////////////////////////////////////////////////////////
547 // With additional QUl, Ql, d, Qd, Pl, QPl type.
548 def LD1 : WInst<"vld1", "dc",
549 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">;
550 def LD2 : WInst<"vld2", "2c",
551 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">;
552 def LD3 : WInst<"vld3", "3c",
553 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">;
554 def LD4 : WInst<"vld4", "4c",
555 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">;
556 def ST1 : WInst<"vst1", "vpd",
557 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">;
558 def ST2 : WInst<"vst2", "vp2",
559 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">;
560 def ST3 : WInst<"vst3", "vp3",
561 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">;
562 def ST4 : WInst<"vst4", "vp4",
563 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">;
565 def LD1_X2 : WInst<"vld1_x2", "2c",
566 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
567 def LD3_x3 : WInst<"vld1_x3", "3c",
568 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
569 def LD4_x4 : WInst<"vld1_x4", "4c",
570 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
572 def ST1_X2 : WInst<"vst1_x2", "vp2",
573 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
574 def ST1_X3 : WInst<"vst1_x3", "vp3",
575 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
576 def ST1_X4 : WInst<"vst1_x4", "vp4",
577 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
579 // With additional QUl, Ql, d, Qd, Pl, QPl type.
580 def LD1_LANE : WInst<"vld1_lane", "dcdi",
581 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
582 def LD2_LANE : WInst<"vld2_lane", "2c2i",
583 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
584 def LD3_LANE : WInst<"vld3_lane", "3c3i",
585 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
586 def LD4_LANE : WInst<"vld4_lane", "4c4i",
587 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
588 def ST1_LANE : WInst<"vst1_lane", "vpdi",
589 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
590 def ST2_LANE : WInst<"vst2_lane", "vp2i",
591 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
592 def ST3_LANE : WInst<"vst3_lane", "vp3i",
593 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
594 def ST4_LANE : WInst<"vst4_lane", "vp4i",
595 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
597 def LD1_DUP : WInst<"vld1_dup", "dc",
598 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
599 def LD2_DUP : WInst<"vld2_dup", "2c",
600 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
601 def LD3_DUP : WInst<"vld3_dup", "3c",
602 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
603 def LD4_DUP : WInst<"vld4_dup", "4c",
604 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">;
606 ////////////////////////////////////////////////////////////////////////////////
608 // With additional d, Qd type.
609 def ADD : IOpInst<"vadd", "ddd", "csilfdUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd",
612 ////////////////////////////////////////////////////////////////////////////////
614 // With additional Qd type.
615 def SUB : IOpInst<"vsub", "ddd", "csildfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd",
618 ////////////////////////////////////////////////////////////////////////////////
620 // With additional Qd type.
621 def MUL : IOpInst<"vmul", "ddd", "csifdUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MUL>;
622 def MLA : IOpInst<"vmla", "dddd", "csifdUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLA>;
623 def MLS : IOpInst<"vmls", "dddd", "csifdUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLS>;
625 ////////////////////////////////////////////////////////////////////////////////
626 // Multiplication Extended
627 def MULX : SInst<"vmulx", "ddd", "fdQfQd">;
629 ////////////////////////////////////////////////////////////////////////////////
631 def FDIV : IOpInst<"vdiv", "ddd", "fdQfQd", OP_DIV>;
633 ////////////////////////////////////////////////////////////////////////////////
634 // Vector fused multiply-add operations
635 // With additional d, Qd type.
636 def FMLA : SInst<"vfma", "dddd", "fdQfQd">;
637 def FMLS : SInst<"vfms", "dddd", "fdQfQd">;
639 ////////////////////////////////////////////////////////////////////////////////
640 // MUL, FMA, FMS definitions with scalar argument
641 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
642 def FMLA_N : SOpInst<"vfma_n", "ddds", "fQf", OP_FMLA_N>;
643 def FMLS_N : SOpInst<"vfms_n", "ddds", "fQf", OP_FMLS_N>;
645 ////////////////////////////////////////////////////////////////////////////////
646 // Logical operations
647 // With additional Qd, Ql, QPl type.
648 def BSL : SInst<"vbsl", "dudd",
649 "csilUcUsUiUlfdPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPsQdPlQPl">;
651 ////////////////////////////////////////////////////////////////////////////////
652 // Absolute Difference
653 // With additional Qd type.
654 def ABD : SInst<"vabd", "ddd", "csiUcUsUifdQcQsQiQUcQUsQUiQfQd">;
656 ////////////////////////////////////////////////////////////////////////////////
657 // saturating absolute/negate
658 // With additional Qd/Ql type.
659 def ABS : SInst<"vabs", "dd", "csilfdQcQsQiQfQlQd">;
660 def QABS : SInst<"vqabs", "dd", "csilQcQsQiQl">;
661 def NEG : SOpInst<"vneg", "dd", "csilfdQcQsQiQfQdQl", OP_NEG>;
662 def QNEG : SInst<"vqneg", "dd", "csilQcQsQiQl">;
664 ////////////////////////////////////////////////////////////////////////////////
665 // Signed Saturating Accumulated of Unsigned Value
666 def SUQADD : SInst<"vuqadd", "ddd", "csilQcQsQiQl">;
668 ////////////////////////////////////////////////////////////////////////////////
669 // Unsigned Saturating Accumulated of Signed Value
670 def USQADD : SInst<"vsqadd", "ddd", "UcUsUiUlQUcQUsQUiQUl">;
672 ////////////////////////////////////////////////////////////////////////////////
674 // With additional d, Qd type.
675 def FRECPS : IInst<"vrecps", "ddd", "fdQfQd">;
676 def FRSQRTS : IInst<"vrsqrts", "ddd", "fdQfQd">;
678 ////////////////////////////////////////////////////////////////////////////////
680 def RBIT : IInst<"vrbit", "dd", "cUcPcQcQUcQPc">;
682 ////////////////////////////////////////////////////////////////////////////////
683 // Integer extract and narrow to high
684 def XTN2 : SOpInst<"vmovn_high", "qhk", "silUsUiUl", OP_XTN>;
686 ////////////////////////////////////////////////////////////////////////////////
687 // Signed integer saturating extract and unsigned narrow to high
688 def SQXTUN2 : SOpInst<"vqmovun_high", "qhk", "sil", OP_SQXTUN>;
690 ////////////////////////////////////////////////////////////////////////////////
691 // Integer saturating extract and narrow to high
692 def QXTN2 : SOpInst<"vqmovn_high", "qhk", "silUsUiUl", OP_QXTN>;
694 ////////////////////////////////////////////////////////////////////////////////
695 // Converting vectors
696 def VCVT_HIGH_F16 : SOpInst<"vcvt_high_f16", "qhj", "f", OP_VCVT_NA_HI>;
697 def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "wk", "h", OP_VCVT_EX_HI>;
698 def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "fj", "d">;
699 def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "qfj", "d", OP_VCVT_NA_HI>;
700 def VCVT_F64_F32 : SInst<"vcvt_f64_f32", "wd", "f">;
701 def VCVT_F64 : SInst<"vcvt_f64", "Fd", "lUlQlQUl">;
702 def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "wj", "f", OP_VCVT_EX_HI>;
703 def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">;
704 def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "qfj", "d", OP_VCVTX_HI>;
705 def FRINTN : SInst<"vrndn", "dd", "fdQfQd">;
706 def FRINTA : SInst<"vrnda", "dd", "fdQfQd">;
707 def FRINTP : SInst<"vrndp", "dd", "fdQfQd">;
708 def FRINTM : SInst<"vrndm", "dd", "fdQfQd">;
709 def FRINTX : SInst<"vrndx", "dd", "fdQfQd">;
710 def FRINTZ : SInst<"vrnd", "dd", "fdQfQd">;
711 def FRINTI : SInst<"vrndi", "dd", "fdQfQd">;
712 def VCVT_S64 : SInst<"vcvt_s64", "xd", "dQd">;
713 def VCVT_U64 : SInst<"vcvt_u64", "ud", "dQd">;
714 def FCVTNS_S32 : SInst<"vcvtn_s32", "xd", "fQf">;
715 def FCVTNS_S64 : SInst<"vcvtn_s64", "xd", "dQd">;
716 def FCVTNU_S32 : SInst<"vcvtn_u32", "ud", "fQf">;
717 def FCVTNU_S64 : SInst<"vcvtn_u64", "ud", "dQd">;
718 def FCVTPS_S32 : SInst<"vcvtp_s32", "xd", "fQf">;
719 def FCVTPS_S64 : SInst<"vcvtp_s64", "xd", "dQd">;
720 def FCVTPU_S32 : SInst<"vcvtp_u32", "ud", "fQf">;
721 def FCVTPU_S64 : SInst<"vcvtp_u64", "ud", "dQd">;
722 def FCVTMS_S32 : SInst<"vcvtm_s32", "xd", "fQf">;
723 def FCVTMS_S64 : SInst<"vcvtm_s64", "xd", "dQd">;
724 def FCVTMU_S32 : SInst<"vcvtm_u32", "ud", "fQf">;
725 def FCVTMU_S64 : SInst<"vcvtm_u64", "ud", "dQd">;
726 def FCVTAS_S32 : SInst<"vcvta_s32", "xd", "fQf">;
727 def FCVTAS_S64 : SInst<"vcvta_s64", "xd", "dQd">;
728 def FCVTAU_S32 : SInst<"vcvta_u32", "ud", "fQf">;
729 def FCVTAU_S64 : SInst<"vcvta_u64", "ud", "dQd">;
730 def FRECPE : SInst<"vrecpe", "dd", "fdUiQfQUiQd">;
731 def FRSQRTE : SInst<"vrsqrte", "dd", "fdUiQfQUiQd">;
732 def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">;
734 ////////////////////////////////////////////////////////////////////////////////
736 // With additional Qd, Ql, QPl type.
737 def FCAGE : IInst<"vcage", "udd", "fdQfQd">;
738 def FCAGT : IInst<"vcagt", "udd", "fdQfQd">;
739 def FCALE : IInst<"vcale", "udd", "fdQfQd">;
740 def FCALT : IInst<"vcalt", "udd", "fdQfQd">;
741 // With additional Ql, QUl, Qd types.
742 def CMTST : WInst<"vtst", "udd",
743 "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPslUlQlQUlPlQPl">;
744 // With additional l, Ul,d, Qd, Ql, QUl, Qd types.
745 def CFMEQ : SOpInst<"vceq", "udd",
746 "csilfUcUsUiUlPcQcdQdQsQiQfQUcQUsQUiQUlQlQPcPlQPl", OP_EQ>;
747 def CFMGE : SOpInst<"vcge", "udd",
748 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_GE>;
749 def CFMLE : SOpInst<"vcle", "udd",
750 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_LE>;
751 def CFMGT : SOpInst<"vcgt", "udd",
752 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_GT>;
753 def CFMLT : SOpInst<"vclt", "udd",
754 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_LT>;
756 def CMEQ : SInst<"vceqz", "ud",
757 "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">;
758 def CMGE : SInst<"vcgez", "ud", "csilfdQcQsQiQlQfQd">;
759 def CMLE : SInst<"vclez", "ud", "csilfdQcQsQiQlQfQd">;
760 def CMGT : SInst<"vcgtz", "ud", "csilfdQcQsQiQlQfQd">;
761 def CMLT : SInst<"vcltz", "ud", "csilfdQcQsQiQlQfQd">;
763 ////////////////////////////////////////////////////////////////////////////////
765 // With additional Qd type.
766 def MAX : SInst<"vmax", "ddd", "csiUcUsUifdQcQsQiQUcQUsQUiQfQd">;
767 def MIN : SInst<"vmin", "ddd", "csiUcUsUifdQcQsQiQUcQUsQUiQfQd">;
769 ////////////////////////////////////////////////////////////////////////////////
770 // MaxNum/MinNum Floating Point
771 def FMAXNM : SInst<"vmaxnm", "ddd", "fdQfQd">;
772 def FMINNM : SInst<"vminnm", "ddd", "fdQfQd">;
774 ////////////////////////////////////////////////////////////////////////////////
776 // With additional Qc Qs Qi QUc QUs QUi Qf Qd types.
777 def MAXP : SInst<"vpmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">;
778 def MINP : SInst<"vpmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">;
780 ////////////////////////////////////////////////////////////////////////////////
781 // Pairwise MaxNum/MinNum Floating Point
782 def FMAXNMP : SInst<"vpmaxnm", "ddd", "fQfQd">;
783 def FMINNMP : SInst<"vpminnm", "ddd", "fQfQd">;
785 ////////////////////////////////////////////////////////////////////////////////
787 // With additional Qc Qs Qi QUc QUs QUi Qf Qd types.
788 def ADDP : IInst<"vpadd", "ddd", "csiUcUsUifQcQsQiQlQUcQUsQUiQUlQfQd">;
790 ////////////////////////////////////////////////////////////////////////////////
791 // Shifts by constant
793 // Left shift long high
794 def SHLL_HIGH_N : SOpInst<"vshll_high_n", "ndi", "HcHsHiHUcHUsHUi",
797 ////////////////////////////////////////////////////////////////////////////////
798 // Shifts with insert, with additional Ql, QPl type.
799 def SRI_N : WInst<"vsri_n", "dddi",
800 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPsPlQPl">;
801 def SLI_N : WInst<"vsli_n", "dddi",
802 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPsPlQPl">;
804 // Right shift narrow high
805 def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "hmdi",
806 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
807 def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "hmdi",
808 "HsHiHl", OP_NARROW_HI>;
809 def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "hmdi",
810 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
811 def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "hmdi",
812 "HsHiHl", OP_NARROW_HI>;
813 def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "hmdi",
814 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
815 def QRSHRN_HIGH_N : SOpInst<"vqrshrn_high_n", "hmdi",
816 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
819 ////////////////////////////////////////////////////////////////////////////////
820 // Converting vectors
821 def VMOVL_HIGH : SOpInst<"vmovl_high", "nd", "HcHsHiHUcHUsHUi", OP_MOVL_HI>;
823 let isVCVT_N = 1 in {
824 def CVTF_N_F64 : SInst<"vcvt_n_f64", "Fdi", "lUlQlQUl">;
825 def FCVTZS_N_S64 : SInst<"vcvt_n_s64", "xdi", "dQd">;
826 def FCVTZS_N_U64 : SInst<"vcvt_n_u64", "udi", "dQd">;
829 ////////////////////////////////////////////////////////////////////////////////
830 // 3VDiff class using high 64-bit in operands
831 def VADDL_HIGH : SOpInst<"vaddl_high", "wkk", "csiUcUsUi", OP_ADDLHi>;
832 def VADDW_HIGH : SOpInst<"vaddw_high", "wwk", "csiUcUsUi", OP_ADDWHi>;
833 def VSUBL_HIGH : SOpInst<"vsubl_high", "wkk", "csiUcUsUi", OP_SUBLHi>;
834 def VSUBW_HIGH : SOpInst<"vsubw_high", "wwk", "csiUcUsUi", OP_SUBWHi>;
836 def VABDL_HIGH : SOpInst<"vabdl_high", "wkk", "csiUcUsUi", OP_ABDLHi>;
837 def VABAL_HIGH : SOpInst<"vabal_high", "wwkk", "csiUcUsUi", OP_ABALHi>;
839 def VMULL_HIGH : SOpInst<"vmull_high", "wkk", "csiUcUsUiPc", OP_MULLHi>;
840 def VMULL_HIGH_N : SOpInst<"vmull_high_n", "wks", "siUsUi", OP_MULLHi_N>;
841 def VMLAL_HIGH : SOpInst<"vmlal_high", "wwkk", "csiUcUsUi", OP_MLALHi>;
842 def VMLAL_HIGH_N : SOpInst<"vmlal_high_n", "wwks", "siUsUi", OP_MLALHi_N>;
843 def VMLSL_HIGH : SOpInst<"vmlsl_high", "wwkk", "csiUcUsUi", OP_MLSLHi>;
844 def VMLSL_HIGH_N : SOpInst<"vmlsl_high_n", "wwks", "siUsUi", OP_MLSLHi_N>;
846 def VADDHN_HIGH : SOpInst<"vaddhn_high", "qhkk", "silUsUiUl", OP_ADDHNHi>;
847 def VRADDHN_HIGH : SOpInst<"vraddhn_high", "qhkk", "silUsUiUl", OP_RADDHNHi>;
848 def VSUBHN_HIGH : SOpInst<"vsubhn_high", "qhkk", "silUsUiUl", OP_SUBHNHi>;
849 def VRSUBHN_HIGH : SOpInst<"vrsubhn_high", "qhkk", "silUsUiUl", OP_RSUBHNHi>;
851 def VQDMULL_HIGH : SOpInst<"vqdmull_high", "wkk", "si", OP_QDMULLHi>;
852 def VQDMULL_HIGH_N : SOpInst<"vqdmull_high_n", "wks", "si", OP_QDMULLHi_N>;
853 def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "wwkk", "si", OP_QDMLALHi>;
854 def VQDMLAL_HIGH_N : SOpInst<"vqdmlal_high_n", "wwks", "si", OP_QDMLALHi_N>;
855 def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "wwkk", "si", OP_QDMLSLHi>;
856 def VQDMLSL_HIGH_N : SOpInst<"vqdmlsl_high_n", "wwks", "si", OP_QDMLSLHi_N>;
858 ////////////////////////////////////////////////////////////////////////////////
859 // Extract or insert element from vector
860 def GET_LANE : IInst<"vget_lane", "sdi",
861 "csilPcPsUcUsUiUlQcQsQiQlQUcQUsQUiQUlPcPsQPcQPsfdQfQdPlQPl">;
862 def SET_LANE : IInst<"vset_lane", "dsdi",
863 "csilPcPsUcUsUiUlQcQsQiQlQUcQUsQUiQUlPcPsQPcQPsfdQfQdPlQPl">;
864 def COPY_LANE : IOpInst<"vcopy_lane", "ddidi",
865 "csilPcPsUcUsUiUlPcPsPlfd", OP_COPY_LN>;
866 def COPYQ_LANE : IOpInst<"vcopy_lane", "ddigi",
867 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPYQ_LN>;
868 def COPY_LANEQ : IOpInst<"vcopy_laneq", "ddiki",
869 "csilPcPsPlUcUsUiUlfd", OP_COPY_LNQ>;
870 def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "ddidi",
871 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>;
873 ////////////////////////////////////////////////////////////////////////////////
874 // Set all lanes to same value
875 def VDUP_LANE1: WOpInst<"vdup_lane", "dgi",
876 "csilPcPsUcUsUiUlhfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl",
878 def VDUP_LANE2: WOpInst<"vdup_laneq", "dki",
879 "csilPcPsUcUsUiUlhfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl",
881 def DUP_N : WOpInst<"vdup_n", "ds",
882 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUldQdPlQPl",
884 def MOV_N : WOpInst<"vmov_n", "ds",
885 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUldQd",
888 ////////////////////////////////////////////////////////////////////////////////
889 // Combining vectors, with additional Pl
890 def COMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfdUcUsUiUlPcPsPl", OP_CONC>;
892 ////////////////////////////////////////////////////////////////////////////////
893 //Initialize a vector from bit pattern, with additional Pl
894 def CREATE : NoTestOpInst<"vcreate", "dl", "csihfdUcUsUiUlPcPslPl", OP_CAST>;
896 ////////////////////////////////////////////////////////////////////////////////
898 def VMLA_LANEQ : IOpInst<"vmla_laneq", "dddji",
899 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
900 def VMLS_LANEQ : IOpInst<"vmls_laneq", "dddji",
901 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
903 def VFMA_LANE : IInst<"vfma_lane", "dddgi", "fdQfQd">;
904 def VFMA_LANEQ : IInst<"vfma_laneq", "dddji", "fdQfQd">;
905 def VFMS_LANE : IOpInst<"vfms_lane", "dddgi", "fdQfQd", OP_FMS_LN>;
906 def VFMS_LANEQ : IOpInst<"vfms_laneq", "dddji", "fdQfQd", OP_FMS_LNQ>;
908 def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "wwdki", "siUsUi", OP_MLAL_LN>;
909 def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "wwkdi", "siUsUi",
911 def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "wwkki", "siUsUi",
913 def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "wwdki", "siUsUi", OP_MLSL_LN>;
914 def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "wwkdi", "siUsUi",
916 def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "wwkki", "siUsUi",
919 def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "wwdki", "si", OP_QDMLAL_LN>;
920 def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "wwkdi", "si",
922 def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "wwkki", "si",
924 def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "wwdki", "si", OP_QDMLSL_LN>;
925 def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "wwkdi", "si",
927 def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "wwkki", "si",
930 // Newly add double parameter for vmul_lane in aarch64
931 // Note: d type is handled by SCALAR_VMUL_LANE
932 def VMUL_LANE_A64 : IOpInst<"vmul_lane", "ddgi", "Qd", OP_MUL_LN>;
934 // Note: d type is handled by SCALAR_VMUL_LANEQ
935 def VMUL_LANEQ : IOpInst<"vmul_laneq", "ddji",
936 "sifUsUiQsQiQfQUsQUiQfQd", OP_MUL_LN>;
937 def VMULL_LANEQ : SOpInst<"vmull_laneq", "wdki", "siUsUi", OP_MULL_LN>;
938 def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "wkdi", "siUsUi",
940 def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "wkki", "siUsUi",
943 def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "wdki", "si", OP_QDMULL_LN>;
944 def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "wkdi", "si",
946 def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "wkki", "si",
949 def VQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ddji", "siQsQi", OP_QDMULH_LN>;
950 def VQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ddji", "siQsQi", OP_QRDMULH_LN>;
952 // Note: d type implemented by SCALAR_VMULX_LANE
953 def VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "fQfQd", OP_MULX_LN>;
954 // Note: d type is implemented by SCALAR_VMULX_LANEQ
955 def VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "fQfQd", OP_MULX_LN>;
957 ////////////////////////////////////////////////////////////////////////////////
958 // Across vectors class
959 def VADDLV : SInst<"vaddlv", "rd", "csiUcUsUiQcQsQiQUcQUsQUi">;
960 def VMAXV : SInst<"vmaxv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
961 def VMINV : SInst<"vminv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
962 def VADDV : SInst<"vaddv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">;
963 def FMAXNMV : SInst<"vmaxnmv", "sd", "fQfQd">;
964 def FMINNMV : SInst<"vminnmv", "sd", "fQfQd">;
966 ////////////////////////////////////////////////////////////////////////////////
967 // Newly added Vector Extract for f64
968 def VEXT_A64 : WInst<"vext", "dddi",
969 "cUcPcsUsPsiUilUlfdQcQUcQPcQsQUsQPsQiQUiQlQUlQfQdPlQPl">;
971 ////////////////////////////////////////////////////////////////////////////////
973 let isCrypto = 1 in {
974 def AESE : SInst<"vaese", "ddd", "QUc">;
975 def AESD : SInst<"vaesd", "ddd", "QUc">;
976 def AESMC : SInst<"vaesmc", "dd", "QUc">;
977 def AESIMC : SInst<"vaesimc", "dd", "QUc">;
979 def SHA1H : SInst<"vsha1h", "ss", "Ui">;
980 def SHA1SU1 : SInst<"vsha1su1", "ddd", "QUi">;
981 def SHA256SU0 : SInst<"vsha256su0", "ddd", "QUi">;
983 def SHA1C : SInst<"vsha1c", "ddsd", "QUi">;
984 def SHA1P : SInst<"vsha1p", "ddsd", "QUi">;
985 def SHA1M : SInst<"vsha1m", "ddsd", "QUi">;
986 def SHA1SU0 : SInst<"vsha1su0", "dddd", "QUi">;
987 def SHA256H : SInst<"vsha256h", "dddd", "QUi">;
988 def SHA256H2 : SInst<"vsha256h2", "dddd", "QUi">;
989 def SHA256SU1 : SInst<"vsha256su1", "dddd", "QUi">;
992 ////////////////////////////////////////////////////////////////////////////////
994 def VTRN1 : SOpInst<"vtrn1", "ddd",
995 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN1>;
996 def VZIP1 : SOpInst<"vzip1", "ddd",
997 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP1>;
998 def VUZP1 : SOpInst<"vuzp1", "ddd",
999 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP1>;
1000 def VTRN2 : SOpInst<"vtrn2", "ddd",
1001 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN2>;
1002 def VZIP2 : SOpInst<"vzip2", "ddd",
1003 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP2>;
1004 def VUZP2 : SOpInst<"vuzp2", "ddd",
1005 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP2>;
1007 ////////////////////////////////////////////////////////////////////////////////
1009 let InstName = "vtbl" in {
1010 def VQTBL1_A64 : WInst<"vqtbl1", "djt", "UccPcQUcQcQPc">;
1011 def VQTBL2_A64 : WInst<"vqtbl2", "dBt", "UccPcQUcQcQPc">;
1012 def VQTBL3_A64 : WInst<"vqtbl3", "dCt", "UccPcQUcQcQPc">;
1013 def VQTBL4_A64 : WInst<"vqtbl4", "dDt", "UccPcQUcQcQPc">;
1015 let InstName = "vtbx" in {
1016 def VQTBX1_A64 : WInst<"vqtbx1", "ddjt", "UccPcQUcQcQPc">;
1017 def VQTBX2_A64 : WInst<"vqtbx2", "ddBt", "UccPcQUcQcQPc">;
1018 def VQTBX3_A64 : WInst<"vqtbx3", "ddCt", "UccPcQUcQcQPc">;
1019 def VQTBX4_A64 : WInst<"vqtbx4", "ddDt", "UccPcQUcQcQPc">;
1022 ////////////////////////////////////////////////////////////////////////////////
1023 // Vector reinterpret cast operations
1024 // With additional d, Qd, pl, Qpl types
1026 : NoTestOpInst<"vreinterpret", "dd",
1027 "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPl", OP_REINT>;
1030 ////////////////////////////////////////////////////////////////////////////////
1031 // Scalar Intrinsics
1032 // Scalar Arithmetic
1035 def SCALAR_ADD : SInst<"vadd", "sss", "SlSUl">;
1036 // Scalar Saturating Add
1037 def SCALAR_QADD : SInst<"vqadd", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1039 // Scalar Subtraction
1040 def SCALAR_SUB : SInst<"vsub", "sss", "SlSUl">;
1041 // Scalar Saturating Sub
1042 def SCALAR_QSUB : SInst<"vqsub", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1044 let InstName = "vmov" in {
1045 def VGET_HIGH_A64 : NoTestOpInst<"vget_high", "dk", "csilhfdUcUsUiUlPcPsPl",
1047 def VGET_LOW_A64 : NoTestOpInst<"vget_low", "dk", "csilhfdUcUsUiUlPcPsPl",
1051 ////////////////////////////////////////////////////////////////////////////////
1053 // Scalar Shift Left
1054 def SCALAR_SHL: SInst<"vshl", "sss", "SlSUl">;
1055 // Scalar Saturating Shift Left
1056 def SCALAR_QSHL: SInst<"vqshl", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1057 // Scalar Saturating Rounding Shift Left
1058 def SCALAR_QRSHL: SInst<"vqrshl", "sss", "ScSsSiSlSUcSUsSUiSUl">;
1059 // Scalar Shift Rouding Left
1060 def SCALAR_RSHL: SInst<"vrshl", "sss", "SlSUl">;
1062 ////////////////////////////////////////////////////////////////////////////////
1063 // Scalar Shift (Immediate)
1064 let isScalarShift = 1 in {
1065 // Signed/Unsigned Shift Right (Immediate)
1066 def SCALAR_SSHR_N: SInst<"vshr_n", "ssi", "SlSUl">;
1067 // Signed/Unsigned Rounding Shift Right (Immediate)
1068 def SCALAR_SRSHR_N: SInst<"vrshr_n", "ssi", "SlSUl">;
1070 // Signed/Unsigned Shift Right and Accumulate (Immediate)
1071 def SCALAR_SSRA_N: SInst<"vsra_n", "sssi", "SlSUl">;
1072 // Signed/Unsigned Rounding Shift Right and Accumulate (Immediate)
1073 def SCALAR_SRSRA_N: SInst<"vrsra_n", "sssi", "SlSUl">;
1075 // Shift Left (Immediate)
1076 def SCALAR_SHL_N: SInst<"vshl_n", "ssi", "SlSUl">;
1077 // Signed/Unsigned Saturating Shift Left (Immediate)
1078 def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">;
1079 // Signed Saturating Shift Left Unsigned (Immediate)
1080 def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">;
1082 // Shift Right And Insert (Immediate)
1083 def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">;
1084 // Shift Left And Insert (Immediate)
1085 def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">;
1087 let isScalarNarrowShift = 1 in {
1088 // Signed/Unsigned Saturating Shift Right Narrow (Immediate)
1089 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">;
1090 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)
1091 def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "zsi", "SsSiSlSUsSUiSUl">;
1092 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
1093 def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "zsi", "SsSiSl">;
1094 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
1095 def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "zsi", "SsSiSl">;
1098 ////////////////////////////////////////////////////////////////////////////////
1099 // Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate)
1100 def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "ysi", "SiSUi">;
1101 def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "osi", "SlSUl">;
1103 ////////////////////////////////////////////////////////////////////////////////
1104 // Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate)
1105 def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "$si", "Sf">;
1106 def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "bsi", "Sf">;
1107 def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "$si", "Sd">;
1108 def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "bsi", "Sd">;
1111 ////////////////////////////////////////////////////////////////////////////////
1112 // Scalar Reduce Pairwise Addition (Scalar and Floating Point)
1113 def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHdSHUl">;
1115 ////////////////////////////////////////////////////////////////////////////////
1116 // Scalar Reduce Floating Point Pairwise Max/Min
1117 def SCALAR_FMAXP : SInst<"vpmax", "sd", "SfSQd">;
1119 def SCALAR_FMINP : SInst<"vpmin", "sd", "SfSQd">;
1121 ////////////////////////////////////////////////////////////////////////////////
1122 // Scalar Reduce Floating Point Pairwise maxNum/minNum
1123 def SCALAR_FMAXNMP : SInst<"vpmaxnm", "sd", "SfSQd">;
1124 def SCALAR_FMINNMP : SInst<"vpminnm", "sd", "SfSQd">;
1126 ////////////////////////////////////////////////////////////////////////////////
1127 // Scalar Integer Saturating Doubling Multiply Half High
1128 def SCALAR_SQDMULH : SInst<"vqdmulh", "sss", "SsSi">;
1130 ////////////////////////////////////////////////////////////////////////////////
1131 // Scalar Integer Saturating Rounding Doubling Multiply Half High
1132 def SCALAR_SQRDMULH : SInst<"vqrdmulh", "sss", "SsSi">;
1134 ////////////////////////////////////////////////////////////////////////////////
1135 // Scalar Floating-point Multiply Extended
1136 def SCALAR_FMULX : IInst<"vmulx", "sss", "SfSd">;
1138 ////////////////////////////////////////////////////////////////////////////////
1139 // Scalar Floating-point Reciprocal Step
1140 def SCALAR_FRECPS : IInst<"vrecps", "sss", "SfSd">;
1142 ////////////////////////////////////////////////////////////////////////////////
1143 // Scalar Floating-point Reciprocal Square Root Step
1144 def SCALAR_FRSQRTS : IInst<"vrsqrts", "sss", "SfSd">;
1146 ////////////////////////////////////////////////////////////////////////////////
1147 // Scalar Signed Integer Convert To Floating-point
1148 def SCALAR_SCVTFS : SInst<"vcvt_f32", "ys", "Si">;
1149 def SCALAR_SCVTFD : SInst<"vcvt_f64", "os", "Sl">;
1151 ////////////////////////////////////////////////////////////////////////////////
1152 // Scalar Unsigned Integer Convert To Floating-point
1153 def SCALAR_UCVTFS : SInst<"vcvt_f32", "ys", "SUi">;
1154 def SCALAR_UCVTFD : SInst<"vcvt_f64", "os", "SUl">;
1156 ////////////////////////////////////////////////////////////////////////////////
1157 // Scalar Floating-point Converts
1158 def SCALAR_FCVTXN : IInst<"vcvtx_f32", "ys", "Sd">;
1159 def SCALAR_FCVTNSS : SInst<"vcvtn_s32", "$s", "Sf">;
1160 def SCALAR_FCVTNUS : SInst<"vcvtn_u32", "bs", "Sf">;
1161 def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "$s", "Sd">;
1162 def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "bs", "Sd">;
1163 def SCALAR_FCVTMSS : SInst<"vcvtm_s32", "$s", "Sf">;
1164 def SCALAR_FCVTMUS : SInst<"vcvtm_u32", "bs", "Sf">;
1165 def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "$s", "Sd">;
1166 def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "bs", "Sd">;
1167 def SCALAR_FCVTASS : SInst<"vcvta_s32", "$s", "Sf">;
1168 def SCALAR_FCVTAUS : SInst<"vcvta_u32", "bs", "Sf">;
1169 def SCALAR_FCVTASD : SInst<"vcvta_s64", "$s", "Sd">;
1170 def SCALAR_FCVTAUD : SInst<"vcvta_u64", "bs", "Sd">;
1171 def SCALAR_FCVTPSS : SInst<"vcvtp_s32", "$s", "Sf">;
1172 def SCALAR_FCVTPUS : SInst<"vcvtp_u32", "bs", "Sf">;
1173 def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "$s", "Sd">;
1174 def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "bs", "Sd">;
1175 def SCALAR_FCVTZSS : SInst<"vcvt_s32", "$s", "Sf">;
1176 def SCALAR_FCVTZUS : SInst<"vcvt_u32", "bs", "Sf">;
1177 def SCALAR_FCVTZSD : SInst<"vcvt_s64", "$s", "Sd">;
1178 def SCALAR_FCVTZUD : SInst<"vcvt_u64", "bs", "Sd">;
1180 ////////////////////////////////////////////////////////////////////////////////
1181 // Scalar Floating-point Reciprocal Estimate
1182 def SCALAR_FRECPE : IInst<"vrecpe", "ss", "SfSd">;
1184 ////////////////////////////////////////////////////////////////////////////////
1185 // Scalar Floating-point Reciprocal Exponent
1186 def SCALAR_FRECPX : IInst<"vrecpx", "ss", "SfSd">;
1188 ////////////////////////////////////////////////////////////////////////////////
1189 // Scalar Floating-point Reciprocal Square Root Estimate
1190 def SCALAR_FRSQRTE : IInst<"vrsqrte", "ss", "SfSd">;
1192 ////////////////////////////////////////////////////////////////////////////////
1193 // Scalar Integer Comparison
1194 def SCALAR_CMEQ : SInst<"vceq", "sss", "SlSUl">;
1195 def SCALAR_CMEQZ : SInst<"vceqz", "ss", "SlSUl">;
1196 def SCALAR_CMGE : SInst<"vcge", "sss", "Sl">;
1197 def SCALAR_CMGEZ : SInst<"vcgez", "ss", "Sl">;
1198 def SCALAR_CMHS : SInst<"vcge", "sss", "SUl">;
1199 def SCALAR_CMLE : SInst<"vcle", "sss", "SlSUl">;
1200 def SCALAR_CMLEZ : SInst<"vclez", "ss", "Sl">;
1201 def SCALAR_CMLT : SInst<"vclt", "sss", "SlSUl">;
1202 def SCALAR_CMLTZ : SInst<"vcltz", "ss", "Sl">;
1203 def SCALAR_CMGT : SInst<"vcgt", "sss", "Sl">;
1204 def SCALAR_CMGTZ : SInst<"vcgtz", "ss", "Sl">;
1205 def SCALAR_CMHI : SInst<"vcgt", "sss", "SUl">;
1206 def SCALAR_CMTST : SInst<"vtst", "sss", "SlSUl">;
1208 ////////////////////////////////////////////////////////////////////////////////
1209 // Scalar Floating-point Comparison
1210 def SCALAR_FCMEQ : IInst<"vceq", "bss", "SfSd">;
1211 def SCALAR_FCMEQZ : IInst<"vceqz", "bs", "SfSd">;
1212 def SCALAR_FCMGE : IInst<"vcge", "bss", "SfSd">;
1213 def SCALAR_FCMGEZ : IInst<"vcgez", "bs", "SfSd">;
1214 def SCALAR_FCMGT : IInst<"vcgt", "bss", "SfSd">;
1215 def SCALAR_FCMGTZ : IInst<"vcgtz", "bs", "SfSd">;
1216 def SCALAR_FCMLE : IInst<"vcle", "bss", "SfSd">;
1217 def SCALAR_FCMLEZ : IInst<"vclez", "bs", "SfSd">;
1218 def SCALAR_FCMLT : IInst<"vclt", "bss", "SfSd">;
1219 def SCALAR_FCMLTZ : IInst<"vcltz", "bs", "SfSd">;
1221 ////////////////////////////////////////////////////////////////////////////////
1222 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
1223 def SCALAR_FACGE : IInst<"vcage", "bss", "SfSd">;
1224 def SCALAR_FACLE : IInst<"vcale", "bss", "SfSd">;
1226 ////////////////////////////////////////////////////////////////////////////////
1227 // Scalar Floating-point Absolute Compare Mask Greater Than
1228 def SCALAR_FACGT : IInst<"vcagt", "bss", "SfSd">;
1229 def SCALAR_FACLT : IInst<"vcalt", "bss", "SfSd">;
1231 ////////////////////////////////////////////////////////////////////////////////
1232 // Scalar Absolute Value
1233 def SCALAR_ABS : SInst<"vabs", "ss", "Sl">;
1235 ////////////////////////////////////////////////////////////////////////////////
1236 // Scalar Absolute Difference
1237 def SCALAR_ABD : IInst<"vabd", "sss", "SfSd">;
1239 ////////////////////////////////////////////////////////////////////////////////
1240 // Scalar Signed Saturating Absolute Value
1241 def SCALAR_SQABS : SInst<"vqabs", "ss", "ScSsSiSl">;
1243 ////////////////////////////////////////////////////////////////////////////////
1245 def SCALAR_NEG : SInst<"vneg", "ss", "Sl">;
1247 ////////////////////////////////////////////////////////////////////////////////
1248 // Scalar Signed Saturating Negate
1249 def SCALAR_SQNEG : SInst<"vqneg", "ss", "ScSsSiSl">;
1251 ////////////////////////////////////////////////////////////////////////////////
1252 // Scalar Signed Saturating Accumulated of Unsigned Value
1253 def SCALAR_SUQADD : SInst<"vuqadd", "sss", "ScSsSiSl">;
1255 ////////////////////////////////////////////////////////////////////////////////
1256 // Scalar Unsigned Saturating Accumulated of Signed Value
1257 def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">;
1259 ////////////////////////////////////////////////////////////////////////////////
1260 // Signed Saturating Doubling Multiply-Add Long
1261 def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">;
1263 ////////////////////////////////////////////////////////////////////////////////
1264 // Signed Saturating Doubling Multiply-Subtract Long
1265 def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">;
1267 ////////////////////////////////////////////////////////////////////////////////
1268 // Signed Saturating Doubling Multiply Long
1269 def SCALAR_SQDMULL : SInst<"vqdmull", "rss", "SsSi">;
1271 ////////////////////////////////////////////////////////////////////////////////
1272 // Scalar Signed Saturating Extract Unsigned Narrow
1273 def SCALAR_SQXTUN : SInst<"vqmovun", "zs", "SsSiSl">;
1275 ////////////////////////////////////////////////////////////////////////////////
1276 // Scalar Signed Saturating Extract Narrow
1277 def SCALAR_SQXTN : SInst<"vqmovn", "zs", "SsSiSl">;
1279 ////////////////////////////////////////////////////////////////////////////////
1280 // Scalar Unsigned Saturating Extract Narrow
1281 def SCALAR_UQXTN : SInst<"vqmovn", "zs", "SUsSUiSUl">;
1283 // Scalar Floating Point multiply (scalar, by element)
1284 def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "ssdi", "SfSd", OP_SCALAR_MUL_LN>;
1285 def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "ssji", "SfSd", OP_SCALAR_MUL_LNQ>;
1287 // Scalar Floating Point multiply extended (scalar, by element)
1288 def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "ssdi", "SfSd", OP_SCALAR_MULX_LN>;
1289 def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "ssji", "SfSd", OP_SCALAR_MULX_LNQ>;
1291 def SCALAR_VMUL_N : IInst<"vmul_n", "dds", "d">;
1293 // VMUL_LANE_A64 d type implemented using scalar mul lane
1294 def SCALAR_VMUL_LANE : IInst<"vmul_lane", "ddgi", "d">;
1296 // VMUL_LANEQ d type implemented using scalar mul lane
1297 def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "ddji", "d">;
1299 // VMULX_LANE d type implemented using scalar vmulx_lane
1300 def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "d", OP_SCALAR_VMULX_LN>;
1302 // VMULX_LANEQ d type implemented using scalar vmulx_laneq
1303 def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "d", OP_SCALAR_VMULX_LNQ>;
1305 // Scalar Floating Point fused multiply-add (scalar, by element)
1306 def SCALAR_FMLA_LANE : IInst<"vfma_lane", "sssdi", "SfSd">;
1307 def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "sssji", "SfSd">;
1309 // Scalar Floating Point fused multiply-subtract (scalar, by element)
1310 def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "sssdi", "SfSd", OP_FMS_LN>;
1311 def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "sssji", "SfSd", OP_FMS_LNQ>;
1313 // Signed Saturating Doubling Multiply Long (scalar by element)
1314 def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "rsdi", "SsSi", OP_SCALAR_QDMULL_LN>;
1315 def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "rsji", "SsSi", OP_SCALAR_QDMULL_LNQ>;
1317 // Signed Saturating Doubling Multiply-Add Long (scalar by element)
1318 def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "rrsdi", "SsSi">;
1319 def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "rrsji", "SsSi">;
1321 // Signed Saturating Doubling Multiply-Subtract Long (scalar by element)
1322 def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "rrsdi", "SsSi">;
1323 def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "rrsji", "SsSi">;
1325 // Scalar Integer Saturating Doubling Multiply Half High (scalar by element)
1326 def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QDMULH_LN>;
1327 def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QDMULH_LNQ>;
1329 // Scalar Integer Saturating Rounding Doubling Multiply Half High
1330 def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QRDMULH_LN>;
1331 def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QRDMULH_LNQ>;
1333 def SCALAR_VDUP_LANE : IInst<"vdup_lane", "sdi", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;
1334 def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "sji", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;
1336 def SCALAR_GET_LANE : IOpInst<"vget_lane", "sdi", "hQh", OP_SCALAR_GET_LN>;
1337 def SCALAR_SET_LANE : IOpInst<"vset_lane", "dsdi", "hQh", OP_SCALAR_SET_LN>;