1 //===--- Hexagon.h - Declare Hexagon target feature support -----*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares Hexagon TargetInfo objects.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
16 #include "clang/Basic/TargetInfo.h"
17 #include "clang/Basic/TargetOptions.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Support/Compiler.h"
24 // Hexagon abstract base class
25 class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
27 static const Builtin::Info BuiltinInfo[];
28 static const char *const GCCRegNames[];
29 static const TargetInfo::GCCRegAlias GCCRegAliases[];
31 std::string HVXVersion;
33 bool HasHVX64B = false;
34 bool HasHVX128B = false;
35 bool UseLongCalls = false;
38 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
39 : TargetInfo(Triple) {
40 // Specify the vector alignment explicitly. For v512x1, the calculated
41 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
42 // the required minimum of 64 bytes.
44 "e-m:e-p:32:32:32-a:0-n16:32-"
45 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
46 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
47 SizeType = UnsignedInt;
48 PtrDiffType = SignedInt;
49 IntPtrType = SignedInt;
51 // {} in inline assembly are packet specifiers, not assembly variant
55 LargeArrayMinWidth = 64;
57 UseBitFieldTypeAlignment = true;
58 ZeroLengthBitfieldBoundary = 32;
61 ArrayRef<Builtin::Info> getTargetBuiltins() const override;
63 bool validateAsmConstraint(const char *&Name,
64 TargetInfo::ConstraintInfo &Info) const override {
69 Info.setAllowsRegister();
73 case 'a': // Modifier register m0-m1.
74 Info.setAllowsRegister();
77 // Relocatable constant.
83 void getTargetDefines(const LangOptions &Opts,
84 MacroBuilder &Builder) const override;
86 bool isCLZForZeroUndef() const override { return false; }
88 bool hasFeature(StringRef Feature) const override;
91 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
93 const std::vector<std::string> &FeaturesVec) const override;
95 bool handleTargetFeatures(std::vector<std::string> &Features,
96 DiagnosticsEngine &Diags) override;
98 BuiltinVaListKind getBuiltinVaListKind() const override {
99 return TargetInfo::CharPtrBuiltinVaList;
102 ArrayRef<const char *> getGCCRegNames() const override;
104 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
106 const char *getClobbers() const override { return ""; }
108 static const char *getHexagonCPUSuffix(StringRef Name);
110 bool isValidCPUName(StringRef Name) const override {
111 return getHexagonCPUSuffix(Name);
114 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
116 bool setCPU(const std::string &Name) override {
117 if (!isValidCPUName(Name))
123 int getEHDataRegisterNumber(unsigned RegNo) const override {
124 return RegNo < 2 ? RegNo : -1;
127 } // namespace targets
129 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H