contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp

   1 //===--- Mips.cpp - Implement Mips target feature support -----------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements Mips TargetInfo objects.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "Targets.h"
  16 #include "clang/Basic/Diagnostic.h"
  17 #include "clang/Basic/MacroBuilder.h"
  18 #include "clang/Basic/TargetBuiltins.h"
  19 #include "llvm/ADT/StringSwitch.h"
  20
  21 using namespace clang;
  22 using namespace clang::targets;
  23
  24 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
  25 #define BUILTIN(ID, TYPE, ATTRS)                                               \
  26   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
  27 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
  28   {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
  29 #include "clang/Basic/BuiltinsMips.def"
  30 };
  31
  32 bool MipsTargetInfo::processorSupportsGPR64() const {
  33   return llvm::StringSwitch<bool>(CPU)
  34       .Case("mips3", true)
  35       .Case("mips4", true)
  36       .Case("mips5", true)
  37       .Case("mips64", true)
  38       .Case("mips64r2", true)
  39       .Case("mips64r3", true)
  40       .Case("mips64r5", true)
  41       .Case("mips64r6", true)
  42       .Case("octeon", true)
  43       .Default(false);
  44   return false;
  45 }
  46
  47 static constexpr llvm::StringLiteral ValidCPUNames[] = {
  48     {"mips1"},  {"mips2"},    {"mips3"},    {"mips4"},    {"mips5"},
  49     {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
  50     {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
  51     {"octeon"}, {"p5600"}};
  52
  53 bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
  54   return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames);
  55 }
  56
  57 void MipsTargetInfo::fillValidCPUList(
  58     SmallVectorImpl<StringRef> &Values) const {
  59   Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
  60 }
  61
  62 void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
  63                                       MacroBuilder &Builder) const {
  64   if (BigEndian) {
  65     DefineStd(Builder, "MIPSEB", Opts);
  66     Builder.defineMacro("_MIPSEB");
  67   } else {
  68     DefineStd(Builder, "MIPSEL", Opts);
  69     Builder.defineMacro("_MIPSEL");
  70   }
  71
  72   Builder.defineMacro("__mips__");
  73   Builder.defineMacro("_mips");
  74   if (Opts.GNUMode)
  75     Builder.defineMacro("mips");
  76
  77   if (ABI == "o32") {
  78     Builder.defineMacro("__mips", "32");
  79     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
  80   } else {
  81     Builder.defineMacro("__mips", "64");
  82     Builder.defineMacro("__mips64");
  83     Builder.defineMacro("__mips64__");
  84     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
  85   }
  86
  87   const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
  88                                  .Cases("mips32", "mips64", "1")
  89                                  .Cases("mips32r2", "mips64r2", "2")
  90                                  .Cases("mips32r3", "mips64r3", "3")
  91                                  .Cases("mips32r5", "mips64r5", "5")
  92                                  .Cases("mips32r6", "mips64r6", "6")
  93                                  .Default("");
  94   if (!ISARev.empty())
  95     Builder.defineMacro("__mips_isa_rev", ISARev);
  96
  97   if (ABI == "o32") {
  98     Builder.defineMacro("__mips_o32");
  99     Builder.defineMacro("_ABIO32", "1");
 100     Builder.defineMacro("_MIPS_SIM", "_ABIO32");
 101   } else if (ABI == "n32") {
 102     Builder.defineMacro("__mips_n32");
 103     Builder.defineMacro("_ABIN32", "2");
 104     Builder.defineMacro("_MIPS_SIM", "_ABIN32");
 105   } else if (ABI == "n64") {
 106     Builder.defineMacro("__mips_n64");
 107     Builder.defineMacro("_ABI64", "3");
 108     Builder.defineMacro("_MIPS_SIM", "_ABI64");
 109   } else
 110     llvm_unreachable("Invalid ABI.");
 111
 112   if (!IsNoABICalls) {
 113     Builder.defineMacro("__mips_abicalls");
 114     if (CanUseBSDABICalls)
 115       Builder.defineMacro("__ABICALLS__");
 116   }
 117
 118   Builder.defineMacro("__REGISTER_PREFIX__", "");
 119
 120   switch (FloatABI) {
 121   case HardFloat:
 122     Builder.defineMacro("__mips_hard_float", Twine(1));
 123     break;
 124   case SoftFloat:
 125     Builder.defineMacro("__mips_soft_float", Twine(1));
 126     break;
 127   }
 128
 129   if (IsSingleFloat)
 130     Builder.defineMacro("__mips_single_float", Twine(1));
 131
 132   Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
 133   Builder.defineMacro("_MIPS_FPSET",
 134                       Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
 135
 136   if (IsMips16)
 137     Builder.defineMacro("__mips16", Twine(1));
 138
 139   if (IsMicromips)
 140     Builder.defineMacro("__mips_micromips", Twine(1));
 141
 142   if (IsNan2008)
 143     Builder.defineMacro("__mips_nan2008", Twine(1));
 144
 145   if (IsAbs2008)
 146     Builder.defineMacro("__mips_abs2008", Twine(1));
 147
 148   switch (DspRev) {
 149   default:
 150     break;
 151   case DSP1:
 152     Builder.defineMacro("__mips_dsp_rev", Twine(1));
 153     Builder.defineMacro("__mips_dsp", Twine(1));
 154     break;
 155   case DSP2:
 156     Builder.defineMacro("__mips_dsp_rev", Twine(2));
 157     Builder.defineMacro("__mips_dspr2", Twine(1));
 158     Builder.defineMacro("__mips_dsp", Twine(1));
 159     break;
 160   }
 161
 162   if (HasMSA)
 163     Builder.defineMacro("__mips_msa", Twine(1));
 164
 165   if (DisableMadd4)
 166     Builder.defineMacro("__mips_no_madd4", Twine(1));
 167
 168   Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
 169   Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
 170   Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
 171
 172   Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
 173   Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
 174
 175   // These shouldn't be defined for MIPS-I but there's no need to check
 176   // for that since MIPS-I isn't supported.
 177   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
 178   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
 179   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
 180
 181   // 32-bit MIPS processors don't have the necessary lld/scd instructions
 182   // found in 64-bit processors. In the case of O32 on a 64-bit processor,
 183   // the instructions exist but using them violates the ABI since they
 184   // require 64-bit GPRs and O32 only supports 32-bit GPRs.
 185   if (ABI == "n32" || ABI == "n64")
 186     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
 187 }
 188
 189 bool MipsTargetInfo::hasFeature(StringRef Feature) const {
 190   return llvm::StringSwitch<bool>(Feature)
 191       .Case("mips", true)
 192       .Case("fp64", HasFP64)
 193       .Default(false);
 194 }
 195
 196 ArrayRef<Builtin::Info> MipsTargetInfo::getTargetBuiltins() const {
 197   return llvm::makeArrayRef(BuiltinInfo, clang::Mips::LastTSBuiltin -
 198                                              Builtin::FirstTSBuiltin);
 199 }
 200
 201 bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
 202   // microMIPS64R6 backend was removed.
 203   if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) {
 204     Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU;
 205     return false;
 206   }
 207   // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
 208   //        this yet. It's better to fail here than on the backend assertion.
 209   if (processorSupportsGPR64() && ABI == "o32") {
 210     Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
 211     return false;
 212   }
 213
 214   // 64-bit ABI's require 64-bit CPU's.
 215   if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
 216     Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
 217     return false;
 218   }
 219
 220   // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
 221   //        can't handle this yet. It's better to fail here than on the
 222   //        backend assertion.
 223   if (getTriple().isMIPS64() && ABI == "o32") {
 224     Diags.Report(diag::err_target_unsupported_abi_for_triple)
 225         << ABI << getTriple().str();
 226     return false;
 227   }
 228
 229   // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
 230   //        can't handle this yet. It's better to fail here than on the
 231   //        backend assertion.
 232   if (getTriple().isMIPS32() && (ABI == "n32" || ABI == "n64")) {
 233     Diags.Report(diag::err_target_unsupported_abi_for_triple)
 234         << ABI << getTriple().str();
 235     return false;
 236   }
 237
 238   return true;
 239 }