1 //===--- Mips.h - Declare Mips target feature support -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares Mips TargetInfo objects.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
15 #define LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
17 #include "clang/Basic/TargetInfo.h"
18 #include "clang/Basic/TargetOptions.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Support/Compiler.h"
25 class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
26 void setDataLayout() {
30 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
31 else if (ABI == "n32")
32 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
33 else if (ABI == "n64")
34 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
36 llvm_unreachable("Invalid ABI");
39 resetDataLayout(("E-" + Layout).str());
41 resetDataLayout(("e-" + Layout).str());
44 static const Builtin::Info BuiltinInfo[];
52 bool CanUseBSDABICalls;
53 enum MipsFloatABI { HardFloat, SoftFloat } FloatABI;
54 enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev;
57 bool UseIndirectJumpHazard;
64 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
65 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
66 IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
67 IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
68 DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
69 UseIndirectJumpHazard(false), HasFP64(false) {
70 TheCXXABI.set(TargetCXXABI::GenericMIPS);
72 setABI(getTriple().isMIPS32() ? "o32" : "n64");
74 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
76 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD ||
77 Triple.getOS() == llvm::Triple::OpenBSD;
80 bool isIEEE754_2008Default() const {
81 return CPU == "mips32r6" || CPU == "mips64r6";
84 bool isFP64Default() const {
85 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
88 bool isNan2008() const override { return IsNan2008; }
90 bool processorSupportsGPR64() const;
92 StringRef getABI() const override { return ABI; }
94 bool setABI(const std::string &Name) override {
114 void setO32ABITypes() {
115 Int64Type = SignedLongLong;
116 IntMaxType = Int64Type;
117 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
118 LongDoubleWidth = LongDoubleAlign = 64;
119 LongWidth = LongAlign = 32;
120 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
121 PointerWidth = PointerAlign = 32;
122 PtrDiffType = SignedInt;
123 SizeType = UnsignedInt;
127 void setN32N64ABITypes() {
128 LongDoubleWidth = LongDoubleAlign = 128;
129 LongDoubleFormat = &llvm::APFloat::IEEEquad();
130 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
131 LongDoubleWidth = LongDoubleAlign = 64;
132 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
134 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
138 void setN64ABITypes() {
140 if (getTriple().getOS() == llvm::Triple::OpenBSD) {
141 Int64Type = SignedLongLong;
143 Int64Type = SignedLong;
145 IntMaxType = Int64Type;
146 LongWidth = LongAlign = 64;
147 PointerWidth = PointerAlign = 64;
148 PtrDiffType = SignedLong;
149 SizeType = UnsignedLong;
152 void setN32ABITypes() {
154 Int64Type = SignedLongLong;
155 IntMaxType = Int64Type;
156 LongWidth = LongAlign = 32;
157 PointerWidth = PointerAlign = 32;
158 PtrDiffType = SignedInt;
159 SizeType = UnsignedInt;
162 bool isValidCPUName(StringRef Name) const override;
163 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
165 bool setCPU(const std::string &Name) override {
167 return isValidCPUName(Name);
170 const std::string &getCPU() const { return CPU; }
172 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
174 const std::vector<std::string> &FeaturesVec) const override {
178 Features["mips64r2"] = Features["cnmips"] = true;
180 Features[CPU] = true;
181 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
184 void getTargetDefines(const LangOptions &Opts,
185 MacroBuilder &Builder) const override;
187 ArrayRef<Builtin::Info> getTargetBuiltins() const override;
189 bool hasFeature(StringRef Feature) const override;
191 BuiltinVaListKind getBuiltinVaListKind() const override {
192 return TargetInfo::VoidPtrBuiltinVaList;
195 ArrayRef<const char *> getGCCRegNames() const override {
196 static const char *const GCCRegNames[] = {
197 // CPU register names
198 // Must match second column of GCCRegAliases
199 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",
200 "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20",
201 "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30",
203 // Floating point register names
204 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
205 "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
206 "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
207 "$f28", "$f29", "$f30", "$f31",
208 // Hi/lo and condition register names
209 "hi", "lo", "", "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5",
210 "$fcc6", "$fcc7", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi",
212 // MSA register names
213 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9",
214 "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", "$w16", "$w17", "$w18",
215 "$w19", "$w20", "$w21", "$w22", "$w23", "$w24", "$w25", "$w26", "$w27",
216 "$w28", "$w29", "$w30", "$w31",
217 // MSA control register names
218 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
219 "$msarequest", "$msamap", "$msaunmap"
221 return llvm::makeArrayRef(GCCRegNames);
224 bool validateAsmConstraint(const char *&Name,
225 TargetInfo::ConstraintInfo &Info) const override {
229 case 'r': // CPU registers.
230 case 'd': // Equivalent to "r" unless generating MIPS16 code.
231 case 'y': // Equivalent to "r", backward compatibility only.
232 case 'f': // floating-point registers.
233 case 'c': // $25 for indirect jumps
234 case 'l': // lo register
235 case 'x': // hilo register pair
236 Info.setAllowsRegister();
238 case 'I': // Signed 16-bit constant
239 case 'J': // Integer 0
240 case 'K': // Unsigned 16-bit constant
241 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
242 case 'M': // Constants not loadable via lui, addiu, or ori
243 case 'N': // Constant -1 to -65535
244 case 'O': // A signed 15-bit constant
245 case 'P': // A constant between 1 go 65535
247 case 'R': // An address that can be used in a non-macro load or store
248 Info.setAllowsMemory();
251 if (Name[1] == 'C') { // An address usable by ll, and sc.
252 Info.setAllowsMemory();
253 Name++; // Skip over 'Z'.
260 std::string convertConstraint(const char *&Constraint) const override {
262 switch (*Constraint) {
263 case 'Z': // Two-character constraint; add "^" hint for later parsing.
264 if (Constraint[1] == 'C') {
265 R = std::string("^") + std::string(Constraint, 2);
271 return TargetInfo::convertConstraint(Constraint);
274 const char *getClobbers() const override {
275 // In GCC, $1 is not widely used in generated code (it's used only in a few
276 // specific situations), so there is no real need for users to add it to
277 // the clobbers list if they want to use it in their inline assembly code.
279 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
280 // code generation, so using it in inline assembly without adding it to the
281 // clobbers list can cause conflicts between the inline assembly code and
282 // the surrounding generated code.
284 // Another problem is that LLVM is allowed to choose $1 for inline assembly
285 // operands, which will conflict with the ".set at" assembler option (which
286 // we use only for inline assembly, in order to maintain compatibility with
287 // GCC) and will also conflict with the user's usage of $1.
289 // The easiest way to avoid these conflicts and keep $1 as an allocatable
290 // register for generated code is to automatically clobber $1 for all inline
293 // FIXME: We should automatically clobber $1 only for inline assembly code
294 // which actually uses it. This would allow LLVM to use $1 for inline
295 // assembly operands if the user's assembly code doesn't use it.
299 bool handleTargetFeatures(std::vector<std::string> &Features,
300 DiagnosticsEngine &Diags) override {
303 IsNan2008 = isIEEE754_2008Default();
304 IsAbs2008 = isIEEE754_2008Default();
305 IsSingleFloat = false;
306 FloatABI = HardFloat;
308 HasFP64 = isFP64Default();
310 for (const auto &Feature : Features) {
311 if (Feature == "+single-float")
312 IsSingleFloat = true;
313 else if (Feature == "+soft-float")
314 FloatABI = SoftFloat;
315 else if (Feature == "+mips16")
317 else if (Feature == "+micromips")
319 else if (Feature == "+dsp")
320 DspRev = std::max(DspRev, DSP1);
321 else if (Feature == "+dspr2")
322 DspRev = std::max(DspRev, DSP2);
323 else if (Feature == "+msa")
325 else if (Feature == "+nomadd4")
327 else if (Feature == "+fp64")
329 else if (Feature == "-fp64")
331 else if (Feature == "+nan2008")
333 else if (Feature == "-nan2008")
335 else if (Feature == "+abs2008")
337 else if (Feature == "-abs2008")
339 else if (Feature == "+noabicalls")
341 else if (Feature == "+use-indirect-jump-hazard")
342 UseIndirectJumpHazard = true;
350 int getEHDataRegisterNumber(unsigned RegNo) const override {
358 bool isCLZForZeroUndef() const override { return false; }
360 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
361 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
362 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
363 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
364 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
365 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
366 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
367 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
368 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
369 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
370 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
371 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
374 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
375 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
376 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
377 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
378 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
379 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
380 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
381 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
382 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
383 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
384 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
388 return llvm::makeArrayRef(O32RegAliases);
389 return llvm::makeArrayRef(NewABIRegAliases);
392 bool hasInt128Type() const override {
393 return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
396 bool validateTarget(DiagnosticsEngine &Diags) const override;
398 } // namespace targets
401 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H