1 //===--- Mips.h - Declare Mips target feature support -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares Mips TargetInfo objects.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
15 #define LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
17 #include "clang/Basic/TargetInfo.h"
18 #include "clang/Basic/TargetOptions.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Support/Compiler.h"
25 class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
26 void setDataLayout() {
30 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
31 else if (ABI == "n32")
32 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
33 else if (ABI == "n64")
34 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
36 llvm_unreachable("Invalid ABI");
39 resetDataLayout(("E-" + Layout).str());
41 resetDataLayout(("e-" + Layout).str());
44 static const Builtin::Info BuiltinInfo[];
52 bool CanUseBSDABICalls;
53 enum MipsFloatABI { HardFloat, SoftFloat } FloatABI;
54 enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev;
57 bool UseIndirectJumpHazard;
64 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
65 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
66 IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
67 IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
68 DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
69 UseIndirectJumpHazard(false), HasFP64(false) {
70 TheCXXABI.set(TargetCXXABI::GenericMIPS);
72 setABI((getTriple().getArch() == llvm::Triple::mips ||
73 getTriple().getArch() == llvm::Triple::mipsel)
77 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
79 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD ||
80 Triple.getOS() == llvm::Triple::OpenBSD;
83 bool isIEEE754_2008Default() const {
84 return CPU == "mips32r6" || CPU == "mips64r6";
87 bool isFP64Default() const {
88 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
91 bool isNan2008() const override { return IsNan2008; }
93 bool processorSupportsGPR64() const;
95 StringRef getABI() const override { return ABI; }
97 bool setABI(const std::string &Name) override {
117 void setO32ABITypes() {
118 Int64Type = SignedLongLong;
119 IntMaxType = Int64Type;
120 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
121 LongDoubleWidth = LongDoubleAlign = 64;
122 LongWidth = LongAlign = 32;
123 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
124 PointerWidth = PointerAlign = 32;
125 PtrDiffType = SignedInt;
126 SizeType = UnsignedInt;
130 void setN32N64ABITypes() {
131 LongDoubleWidth = LongDoubleAlign = 128;
132 LongDoubleFormat = &llvm::APFloat::IEEEquad();
133 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
134 LongDoubleWidth = LongDoubleAlign = 64;
135 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
137 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
141 void setN64ABITypes() {
143 if (getTriple().getOS() == llvm::Triple::OpenBSD) {
144 Int64Type = SignedLongLong;
146 Int64Type = SignedLong;
148 IntMaxType = Int64Type;
149 LongWidth = LongAlign = 64;
150 PointerWidth = PointerAlign = 64;
151 PtrDiffType = SignedLong;
152 SizeType = UnsignedLong;
155 void setN32ABITypes() {
157 Int64Type = SignedLongLong;
158 IntMaxType = Int64Type;
159 LongWidth = LongAlign = 32;
160 PointerWidth = PointerAlign = 32;
161 PtrDiffType = SignedInt;
162 SizeType = UnsignedInt;
165 bool isValidCPUName(StringRef Name) const override;
167 bool setCPU(const std::string &Name) override {
169 return isValidCPUName(Name);
172 const std::string &getCPU() const { return CPU; }
174 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
176 const std::vector<std::string> &FeaturesVec) const override {
180 Features["mips64r2"] = Features["cnmips"] = true;
182 Features[CPU] = true;
183 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
186 void getTargetDefines(const LangOptions &Opts,
187 MacroBuilder &Builder) const override;
189 ArrayRef<Builtin::Info> getTargetBuiltins() const override;
191 bool hasFeature(StringRef Feature) const override;
193 BuiltinVaListKind getBuiltinVaListKind() const override {
194 return TargetInfo::VoidPtrBuiltinVaList;
197 ArrayRef<const char *> getGCCRegNames() const override {
198 static const char *const GCCRegNames[] = {
199 // CPU register names
200 // Must match second column of GCCRegAliases
201 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",
202 "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20",
203 "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30",
205 // Floating point register names
206 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
207 "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
208 "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
209 "$f28", "$f29", "$f30", "$f31",
210 // Hi/lo and condition register names
211 "hi", "lo", "", "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5",
212 "$fcc6", "$fcc7", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi",
214 // MSA register names
215 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9",
216 "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", "$w16", "$w17", "$w18",
217 "$w19", "$w20", "$w21", "$w22", "$w23", "$w24", "$w25", "$w26", "$w27",
218 "$w28", "$w29", "$w30", "$w31",
219 // MSA control register names
220 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
221 "$msarequest", "$msamap", "$msaunmap"
223 return llvm::makeArrayRef(GCCRegNames);
226 bool validateAsmConstraint(const char *&Name,
227 TargetInfo::ConstraintInfo &Info) const override {
231 case 'r': // CPU registers.
232 case 'd': // Equivalent to "r" unless generating MIPS16 code.
233 case 'y': // Equivalent to "r", backward compatibility only.
234 case 'f': // floating-point registers.
235 case 'c': // $25 for indirect jumps
236 case 'l': // lo register
237 case 'x': // hilo register pair
238 Info.setAllowsRegister();
240 case 'I': // Signed 16-bit constant
241 case 'J': // Integer 0
242 case 'K': // Unsigned 16-bit constant
243 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
244 case 'M': // Constants not loadable via lui, addiu, or ori
245 case 'N': // Constant -1 to -65535
246 case 'O': // A signed 15-bit constant
247 case 'P': // A constant between 1 go 65535
249 case 'R': // An address that can be used in a non-macro load or store
250 Info.setAllowsMemory();
253 if (Name[1] == 'C') { // An address usable by ll, and sc.
254 Info.setAllowsMemory();
255 Name++; // Skip over 'Z'.
262 std::string convertConstraint(const char *&Constraint) const override {
264 switch (*Constraint) {
265 case 'Z': // Two-character constraint; add "^" hint for later parsing.
266 if (Constraint[1] == 'C') {
267 R = std::string("^") + std::string(Constraint, 2);
273 return TargetInfo::convertConstraint(Constraint);
276 const char *getClobbers() const override {
277 // In GCC, $1 is not widely used in generated code (it's used only in a few
278 // specific situations), so there is no real need for users to add it to
279 // the clobbers list if they want to use it in their inline assembly code.
281 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
282 // code generation, so using it in inline assembly without adding it to the
283 // clobbers list can cause conflicts between the inline assembly code and
284 // the surrounding generated code.
286 // Another problem is that LLVM is allowed to choose $1 for inline assembly
287 // operands, which will conflict with the ".set at" assembler option (which
288 // we use only for inline assembly, in order to maintain compatibility with
289 // GCC) and will also conflict with the user's usage of $1.
291 // The easiest way to avoid these conflicts and keep $1 as an allocatable
292 // register for generated code is to automatically clobber $1 for all inline
295 // FIXME: We should automatically clobber $1 only for inline assembly code
296 // which actually uses it. This would allow LLVM to use $1 for inline
297 // assembly operands if the user's assembly code doesn't use it.
301 bool handleTargetFeatures(std::vector<std::string> &Features,
302 DiagnosticsEngine &Diags) override {
305 IsNan2008 = isIEEE754_2008Default();
306 IsAbs2008 = isIEEE754_2008Default();
307 IsSingleFloat = false;
308 FloatABI = HardFloat;
310 HasFP64 = isFP64Default();
312 for (const auto &Feature : Features) {
313 if (Feature == "+single-float")
314 IsSingleFloat = true;
315 else if (Feature == "+soft-float")
316 FloatABI = SoftFloat;
317 else if (Feature == "+mips16")
319 else if (Feature == "+micromips")
321 else if (Feature == "+dsp")
322 DspRev = std::max(DspRev, DSP1);
323 else if (Feature == "+dspr2")
324 DspRev = std::max(DspRev, DSP2);
325 else if (Feature == "+msa")
327 else if (Feature == "+nomadd4")
329 else if (Feature == "+fp64")
331 else if (Feature == "-fp64")
333 else if (Feature == "+nan2008")
335 else if (Feature == "-nan2008")
337 else if (Feature == "+abs2008")
339 else if (Feature == "-abs2008")
341 else if (Feature == "+noabicalls")
343 else if (Feature == "+use-indirect-jump-hazard")
344 UseIndirectJumpHazard = true;
352 int getEHDataRegisterNumber(unsigned RegNo) const override {
360 bool isCLZForZeroUndef() const override { return false; }
362 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
363 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
364 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
365 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
366 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
367 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
368 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
369 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
370 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
371 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
372 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
373 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
376 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
377 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
378 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
379 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
380 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
381 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
382 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
383 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
384 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
385 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
386 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
390 return llvm::makeArrayRef(O32RegAliases);
391 return llvm::makeArrayRef(NewABIRegAliases);
394 bool hasInt128Type() const override { return ABI == "n32" || ABI == "n64"; }
396 bool validateTarget(DiagnosticsEngine &Diags) const override;
398 } // namespace targets
401 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H