1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements X86 TargetInfo objects.
12 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Diagnostic.h"
17 #include "clang/Basic/TargetBuiltins.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
24 const Builtin::Info BuiltinInfoX86[] = {
25 #define BUILTIN(ID, TYPE, ATTRS) \
26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
30 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
31 #include "clang/Basic/BuiltinsX86.def"
33 #define BUILTIN(ID, TYPE, ATTRS) \
34 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
38 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
39 #include "clang/Basic/BuiltinsX86_64.def"
42 static const char *const GCCRegNames[] = {
43 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
44 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
45 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
46 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
47 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
48 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
49 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
50 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
51 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
52 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
53 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
54 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
55 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
56 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
57 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
58 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
59 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
60 "k2", "k3", "k4", "k5", "k6", "k7",
61 "cr0", "cr2", "cr3", "cr4", "cr8",
62 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
63 "bnd0", "bnd1", "bnd2", "bnd3",
66 const TargetInfo::AddlRegName AddlRegNames[] = {
67 {{"al", "ah", "eax", "rax"}, 0},
68 {{"bl", "bh", "ebx", "rbx"}, 3},
69 {{"cl", "ch", "ecx", "rcx"}, 2},
70 {{"dl", "dh", "edx", "rdx"}, 1},
75 {{"r8d", "r8w", "r8b"}, 38},
76 {{"r9d", "r9w", "r9b"}, 39},
77 {{"r10d", "r10w", "r10b"}, 40},
78 {{"r11d", "r11w", "r11b"}, 41},
79 {{"r12d", "r12w", "r12b"}, 42},
80 {{"r13d", "r13w", "r13b"}, 43},
81 {{"r14d", "r14w", "r14b"}, 44},
82 {{"r15d", "r15w", "r15b"}, 45},
85 } // namespace targets
88 using namespace clang;
89 using namespace clang::targets;
91 bool X86TargetInfo::setFPMath(StringRef Name) {
103 bool X86TargetInfo::initFeatureMap(
104 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
105 const std::vector<std::string> &FeaturesVec) const {
106 // FIXME: This *really* should not be here.
107 // X86_64 always has SSE2.
108 if (getTriple().getArch() == llvm::Triple::x86_64)
109 setFeatureEnabledImpl(Features, "sse2", true);
111 const CPUKind Kind = getCPUKind(CPU);
113 // Enable X87 for all X86 processors but Lakemont.
114 if (Kind != CK_Lakemont)
115 setFeatureEnabledImpl(Features, "x87", true);
131 setFeatureEnabledImpl(Features, "mmx", true);
135 setFeatureEnabledImpl(Features, "vaes", true);
136 setFeatureEnabledImpl(Features, "gfni", true);
137 setFeatureEnabledImpl(Features, "vpclmulqdq", true);
138 setFeatureEnabledImpl(Features, "avx512bitalg", true);
139 setFeatureEnabledImpl(Features, "avx512vnni", true);
140 setFeatureEnabledImpl(Features, "avx512vbmi2", true);
141 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
144 setFeatureEnabledImpl(Features, "avx512ifma", true);
145 setFeatureEnabledImpl(Features, "avx512vbmi", true);
146 setFeatureEnabledImpl(Features, "sha", true);
148 case CK_SkylakeServer:
149 setFeatureEnabledImpl(Features, "avx512f", true);
150 setFeatureEnabledImpl(Features, "avx512cd", true);
151 setFeatureEnabledImpl(Features, "avx512dq", true);
152 setFeatureEnabledImpl(Features, "avx512bw", true);
153 setFeatureEnabledImpl(Features, "avx512vl", true);
154 setFeatureEnabledImpl(Features, "pku", true);
155 setFeatureEnabledImpl(Features, "clwb", true);
157 case CK_SkylakeClient:
158 setFeatureEnabledImpl(Features, "xsavec", true);
159 setFeatureEnabledImpl(Features, "xsaves", true);
160 setFeatureEnabledImpl(Features, "mpx", true);
161 setFeatureEnabledImpl(Features, "sgx", true);
162 setFeatureEnabledImpl(Features, "clflushopt", true);
163 setFeatureEnabledImpl(Features, "rtm", true);
166 setFeatureEnabledImpl(Features, "rdseed", true);
167 setFeatureEnabledImpl(Features, "adx", true);
168 setFeatureEnabledImpl(Features, "prfchw", true);
171 setFeatureEnabledImpl(Features, "avx2", true);
172 setFeatureEnabledImpl(Features, "lzcnt", true);
173 setFeatureEnabledImpl(Features, "bmi", true);
174 setFeatureEnabledImpl(Features, "bmi2", true);
175 setFeatureEnabledImpl(Features, "fma", true);
176 setFeatureEnabledImpl(Features, "movbe", true);
179 setFeatureEnabledImpl(Features, "rdrnd", true);
180 setFeatureEnabledImpl(Features, "f16c", true);
181 setFeatureEnabledImpl(Features, "fsgsbase", true);
184 setFeatureEnabledImpl(Features, "avx", true);
185 setFeatureEnabledImpl(Features, "xsave", true);
186 setFeatureEnabledImpl(Features, "xsaveopt", true);
189 setFeatureEnabledImpl(Features, "aes", true);
190 setFeatureEnabledImpl(Features, "pclmul", true);
193 setFeatureEnabledImpl(Features, "sse4.2", true);
196 setFeatureEnabledImpl(Features, "sse4.1", true);
199 setFeatureEnabledImpl(Features, "ssse3", true);
204 setFeatureEnabledImpl(Features, "sse3", true);
205 setFeatureEnabledImpl(Features, "cx16", true);
210 setFeatureEnabledImpl(Features, "sse2", true);
214 setFeatureEnabledImpl(Features, "sse", true);
215 setFeatureEnabledImpl(Features, "fxsr", true);
219 setFeatureEnabledImpl(Features, "sha", true);
220 setFeatureEnabledImpl(Features, "rdrnd", true);
221 setFeatureEnabledImpl(Features, "rdseed", true);
222 setFeatureEnabledImpl(Features, "xsave", true);
223 setFeatureEnabledImpl(Features, "xsaveopt", true);
224 setFeatureEnabledImpl(Features, "xsavec", true);
225 setFeatureEnabledImpl(Features, "xsaves", true);
226 setFeatureEnabledImpl(Features, "clflushopt", true);
227 setFeatureEnabledImpl(Features, "mpx", true);
228 setFeatureEnabledImpl(Features, "fsgsbase", true);
231 setFeatureEnabledImpl(Features, "aes", true);
232 setFeatureEnabledImpl(Features, "pclmul", true);
233 setFeatureEnabledImpl(Features, "sse4.2", true);
234 setFeatureEnabledImpl(Features, "prfchw", true);
237 setFeatureEnabledImpl(Features, "movbe", true);
238 setFeatureEnabledImpl(Features, "ssse3", true);
239 setFeatureEnabledImpl(Features, "fxsr", true);
240 setFeatureEnabledImpl(Features, "cx16", true);
244 // TODO: Add avx5124fmaps/avx5124vnniw.
245 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
248 setFeatureEnabledImpl(Features, "avx512f", true);
249 setFeatureEnabledImpl(Features, "avx512cd", true);
250 setFeatureEnabledImpl(Features, "avx512er", true);
251 setFeatureEnabledImpl(Features, "avx512pf", true);
252 setFeatureEnabledImpl(Features, "prfchw", true);
253 setFeatureEnabledImpl(Features, "prefetchwt1", true);
254 setFeatureEnabledImpl(Features, "fxsr", true);
255 setFeatureEnabledImpl(Features, "rdseed", true);
256 setFeatureEnabledImpl(Features, "adx", true);
257 setFeatureEnabledImpl(Features, "lzcnt", true);
258 setFeatureEnabledImpl(Features, "bmi", true);
259 setFeatureEnabledImpl(Features, "bmi2", true);
260 setFeatureEnabledImpl(Features, "rtm", true);
261 setFeatureEnabledImpl(Features, "fma", true);
262 setFeatureEnabledImpl(Features, "rdrnd", true);
263 setFeatureEnabledImpl(Features, "f16c", true);
264 setFeatureEnabledImpl(Features, "fsgsbase", true);
265 setFeatureEnabledImpl(Features, "aes", true);
266 setFeatureEnabledImpl(Features, "pclmul", true);
267 setFeatureEnabledImpl(Features, "cx16", true);
268 setFeatureEnabledImpl(Features, "xsaveopt", true);
269 setFeatureEnabledImpl(Features, "xsave", true);
270 setFeatureEnabledImpl(Features, "movbe", true);
277 setFeatureEnabledImpl(Features, "3dnow", true);
281 setFeatureEnabledImpl(Features, "sse4a", true);
282 setFeatureEnabledImpl(Features, "lzcnt", true);
283 setFeatureEnabledImpl(Features, "popcnt", true);
286 setFeatureEnabledImpl(Features, "sse3", true);
289 setFeatureEnabledImpl(Features, "sse2", true);
292 setFeatureEnabledImpl(Features, "sse", true);
293 setFeatureEnabledImpl(Features, "fxsr", true);
297 setFeatureEnabledImpl(Features, "3dnowa", true);
301 setFeatureEnabledImpl(Features, "avx", true);
302 setFeatureEnabledImpl(Features, "aes", true);
303 setFeatureEnabledImpl(Features, "pclmul", true);
304 setFeatureEnabledImpl(Features, "bmi", true);
305 setFeatureEnabledImpl(Features, "f16c", true);
306 setFeatureEnabledImpl(Features, "xsaveopt", true);
307 setFeatureEnabledImpl(Features, "movbe", true);
310 setFeatureEnabledImpl(Features, "ssse3", true);
311 setFeatureEnabledImpl(Features, "sse4a", true);
312 setFeatureEnabledImpl(Features, "lzcnt", true);
313 setFeatureEnabledImpl(Features, "popcnt", true);
314 setFeatureEnabledImpl(Features, "prfchw", true);
315 setFeatureEnabledImpl(Features, "cx16", true);
316 setFeatureEnabledImpl(Features, "fxsr", true);
320 setFeatureEnabledImpl(Features, "adx", true);
321 setFeatureEnabledImpl(Features, "aes", true);
322 setFeatureEnabledImpl(Features, "avx2", true);
323 setFeatureEnabledImpl(Features, "bmi", true);
324 setFeatureEnabledImpl(Features, "bmi2", true);
325 setFeatureEnabledImpl(Features, "clflushopt", true);
326 setFeatureEnabledImpl(Features, "clzero", true);
327 setFeatureEnabledImpl(Features, "cx16", true);
328 setFeatureEnabledImpl(Features, "f16c", true);
329 setFeatureEnabledImpl(Features, "fma", true);
330 setFeatureEnabledImpl(Features, "fsgsbase", true);
331 setFeatureEnabledImpl(Features, "fxsr", true);
332 setFeatureEnabledImpl(Features, "lzcnt", true);
333 setFeatureEnabledImpl(Features, "mwaitx", true);
334 setFeatureEnabledImpl(Features, "movbe", true);
335 setFeatureEnabledImpl(Features, "pclmul", true);
336 setFeatureEnabledImpl(Features, "popcnt", true);
337 setFeatureEnabledImpl(Features, "prfchw", true);
338 setFeatureEnabledImpl(Features, "rdrnd", true);
339 setFeatureEnabledImpl(Features, "rdseed", true);
340 setFeatureEnabledImpl(Features, "sha", true);
341 setFeatureEnabledImpl(Features, "sse4a", true);
342 setFeatureEnabledImpl(Features, "xsave", true);
343 setFeatureEnabledImpl(Features, "xsavec", true);
344 setFeatureEnabledImpl(Features, "xsaveopt", true);
345 setFeatureEnabledImpl(Features, "xsaves", true);
349 setFeatureEnabledImpl(Features, "avx2", true);
350 setFeatureEnabledImpl(Features, "bmi2", true);
351 setFeatureEnabledImpl(Features, "mwaitx", true);
354 setFeatureEnabledImpl(Features, "fsgsbase", true);
355 setFeatureEnabledImpl(Features, "xsaveopt", true);
358 setFeatureEnabledImpl(Features, "bmi", true);
359 setFeatureEnabledImpl(Features, "fma", true);
360 setFeatureEnabledImpl(Features, "f16c", true);
361 setFeatureEnabledImpl(Features, "tbm", true);
364 // xop implies avx, sse4a and fma4.
365 setFeatureEnabledImpl(Features, "xop", true);
366 setFeatureEnabledImpl(Features, "lwp", true);
367 setFeatureEnabledImpl(Features, "lzcnt", true);
368 setFeatureEnabledImpl(Features, "aes", true);
369 setFeatureEnabledImpl(Features, "pclmul", true);
370 setFeatureEnabledImpl(Features, "prfchw", true);
371 setFeatureEnabledImpl(Features, "cx16", true);
372 setFeatureEnabledImpl(Features, "fxsr", true);
373 setFeatureEnabledImpl(Features, "xsave", true);
376 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
379 // Can't do this earlier because we need to be able to explicitly enable
380 // or disable these features and the things that they depend upon.
382 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
383 auto I = Features.find("sse4.2");
384 if (I != Features.end() && I->getValue() &&
385 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
387 Features["popcnt"] = true;
389 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
390 I = Features.find("3dnow");
391 if (I != Features.end() && I->getValue() &&
392 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
394 Features["prfchw"] = true;
396 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
398 I = Features.find("sse");
399 if (I != Features.end() && I->getValue() &&
400 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
402 Features["mmx"] = true;
407 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
408 X86SSEEnum Level, bool Enabled) {
412 Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
415 Features["avx2"] = true;
418 Features["avx"] = true;
419 Features["xsave"] = true;
422 Features["sse4.2"] = true;
425 Features["sse4.1"] = true;
428 Features["ssse3"] = true;
431 Features["sse3"] = true;
434 Features["sse2"] = true;
437 Features["sse"] = true;
448 Features["sse"] = false;
451 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
452 Features["gfni"] = false;
455 Features["sse3"] = false;
456 setXOPLevel(Features, NoXOP, false);
459 Features["ssse3"] = false;
462 Features["sse4.1"] = false;
465 Features["sse4.2"] = false;
468 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
469 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
470 setXOPLevel(Features, FMA4, false);
473 Features["avx2"] = false;
476 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
477 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
478 Features["avx512vl"] = Features["avx512vbmi"] =
479 Features["avx512ifma"] = Features["avx512vpopcntdq"] =
480 Features["avx512bitalg"] = Features["avx512vnni"] =
481 Features["avx512vbmi2"] = false;
486 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
487 MMX3DNowEnum Level, bool Enabled) {
491 Features["3dnowa"] = true;
494 Features["3dnow"] = true;
497 Features["mmx"] = true;
508 Features["mmx"] = false;
511 Features["3dnow"] = false;
514 Features["3dnowa"] = false;
519 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
524 Features["xop"] = true;
527 Features["fma4"] = true;
528 setSSELevel(Features, AVX, true);
531 Features["sse4a"] = true;
532 setSSELevel(Features, SSE3, true);
543 Features["sse4a"] = false;
546 Features["fma4"] = false;
549 Features["xop"] = false;
554 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
555 StringRef Name, bool Enabled) {
556 // This is a bit of a hack to deal with the sse4 target feature when used
557 // as part of the target attribute. We handle sse4 correctly everywhere
558 // else. See below for more information on how we handle the sse4 options.
560 Features[Name] = Enabled;
563 setMMXLevel(Features, MMX, Enabled);
564 } else if (Name == "sse") {
565 setSSELevel(Features, SSE1, Enabled);
566 } else if (Name == "sse2") {
567 setSSELevel(Features, SSE2, Enabled);
568 } else if (Name == "sse3") {
569 setSSELevel(Features, SSE3, Enabled);
570 } else if (Name == "ssse3") {
571 setSSELevel(Features, SSSE3, Enabled);
572 } else if (Name == "sse4.2") {
573 setSSELevel(Features, SSE42, Enabled);
574 } else if (Name == "sse4.1") {
575 setSSELevel(Features, SSE41, Enabled);
576 } else if (Name == "3dnow") {
577 setMMXLevel(Features, AMD3DNow, Enabled);
578 } else if (Name == "3dnowa") {
579 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
580 } else if (Name == "aes") {
582 setSSELevel(Features, SSE2, Enabled);
584 Features["vaes"] = false;
585 } else if (Name == "vaes") {
587 setSSELevel(Features, AVX, Enabled);
588 Features["aes"] = true;
590 } else if (Name == "pclmul") {
592 setSSELevel(Features, SSE2, Enabled);
594 Features["vpclmulqdq"] = false;
595 } else if (Name == "vpclmulqdq") {
597 setSSELevel(Features, AVX, Enabled);
598 Features["pclmul"] = true;
600 } else if (Name == "gfni") {
602 setSSELevel(Features, SSE2, Enabled);
603 } else if (Name == "avx") {
604 setSSELevel(Features, AVX, Enabled);
605 } else if (Name == "avx2") {
606 setSSELevel(Features, AVX2, Enabled);
607 } else if (Name == "avx512f") {
608 setSSELevel(Features, AVX512F, Enabled);
609 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
610 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
611 Name == "avx512vbmi" || Name == "avx512ifma" ||
612 Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
613 Name == "avx512vnni" || Name == "avx512vbmi2") {
615 setSSELevel(Features, AVX512F, Enabled);
616 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
617 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
618 Features["avx512bw"] = true;
619 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
620 if (Name == "avx512bw" && !Enabled)
621 Features["avx512vbmi"] = Features["avx512vbmi2"] =
622 Features["avx512bitalg"] = false;
623 } else if (Name == "fma") {
625 setSSELevel(Features, AVX, Enabled);
627 setSSELevel(Features, AVX512F, Enabled);
628 } else if (Name == "fma4") {
629 setXOPLevel(Features, FMA4, Enabled);
630 } else if (Name == "xop") {
631 setXOPLevel(Features, XOP, Enabled);
632 } else if (Name == "sse4a") {
633 setXOPLevel(Features, SSE4A, Enabled);
634 } else if (Name == "f16c") {
636 setSSELevel(Features, AVX, Enabled);
638 setSSELevel(Features, AVX512F, Enabled);
639 } else if (Name == "sha") {
641 setSSELevel(Features, SSE2, Enabled);
642 } else if (Name == "sse4") {
643 // We can get here via the __target__ attribute since that's not controlled
644 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
645 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
648 setSSELevel(Features, SSE42, Enabled);
650 setSSELevel(Features, SSE41, Enabled);
651 } else if (Name == "xsave") {
653 Features["xsaveopt"] = false;
654 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
656 Features["xsave"] = true;
660 /// handleTargetFeatures - Perform initialization based on the user
661 /// configured set of features.
662 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
663 DiagnosticsEngine &Diags) {
664 for (const auto &Feature : Features) {
665 if (Feature[0] != '+')
668 if (Feature == "+aes") {
670 } else if (Feature == "+vaes") {
672 } else if (Feature == "+pclmul") {
674 } else if (Feature == "+vpclmulqdq") {
675 HasVPCLMULQDQ = true;
676 } else if (Feature == "+lzcnt") {
678 } else if (Feature == "+rdrnd") {
680 } else if (Feature == "+fsgsbase") {
682 } else if (Feature == "+bmi") {
684 } else if (Feature == "+bmi2") {
686 } else if (Feature == "+popcnt") {
688 } else if (Feature == "+rtm") {
690 } else if (Feature == "+prfchw") {
692 } else if (Feature == "+rdseed") {
694 } else if (Feature == "+adx") {
696 } else if (Feature == "+tbm") {
698 } else if (Feature == "+lwp") {
700 } else if (Feature == "+fma") {
702 } else if (Feature == "+f16c") {
704 } else if (Feature == "+gfni") {
706 } else if (Feature == "+avx512cd") {
708 } else if (Feature == "+avx512vpopcntdq") {
709 HasAVX512VPOPCNTDQ = true;
710 } else if (Feature == "+avx512vnni") {
711 HasAVX512VNNI = true;
712 } else if (Feature == "+avx512er") {
714 } else if (Feature == "+avx512pf") {
716 } else if (Feature == "+avx512dq") {
718 } else if (Feature == "+avx512bitalg") {
719 HasAVX512BITALG = true;
720 } else if (Feature == "+avx512bw") {
722 } else if (Feature == "+avx512vl") {
724 } else if (Feature == "+avx512vbmi") {
725 HasAVX512VBMI = true;
726 } else if (Feature == "+avx512vbmi2") {
727 HasAVX512VBMI2 = true;
728 } else if (Feature == "+avx512ifma") {
729 HasAVX512IFMA = true;
730 } else if (Feature == "+sha") {
732 } else if (Feature == "+mpx") {
734 } else if (Feature == "+shstk") {
736 } else if (Feature == "+ibt") {
738 } else if (Feature == "+movbe") {
740 } else if (Feature == "+sgx") {
742 } else if (Feature == "+cx16") {
744 } else if (Feature == "+fxsr") {
746 } else if (Feature == "+xsave") {
748 } else if (Feature == "+xsaveopt") {
750 } else if (Feature == "+xsavec") {
752 } else if (Feature == "+xsaves") {
754 } else if (Feature == "+mwaitx") {
756 } else if (Feature == "+pku") {
758 } else if (Feature == "+clflushopt") {
759 HasCLFLUSHOPT = true;
760 } else if (Feature == "+clwb") {
762 } else if (Feature == "+prefetchwt1") {
763 HasPREFETCHWT1 = true;
764 } else if (Feature == "+clzero") {
766 } else if (Feature == "+retpoline") {
768 } else if (Feature == "+retpoline-external-thunk") {
769 HasRetpolineExternalThunk = true;
772 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
773 .Case("+avx512f", AVX512F)
776 .Case("+sse4.2", SSE42)
777 .Case("+sse4.1", SSE41)
778 .Case("+ssse3", SSSE3)
783 SSELevel = std::max(SSELevel, Level);
785 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
786 .Case("+3dnowa", AMD3DNowAthlon)
787 .Case("+3dnow", AMD3DNow)
789 .Default(NoMMX3DNow);
790 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
792 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
795 .Case("+sse4a", SSE4A)
797 XOPLevel = std::max(XOPLevel, XLevel);
800 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
801 // matches the selected sse level.
802 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
803 (FPMath == FP_387 && SSELevel >= SSE1)) {
804 Diags.Report(diag::err_target_unsupported_fpmath)
805 << (FPMath == FP_SSE ? "sse" : "387");
810 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
814 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
815 /// definitions for this particular subtarget.
816 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
817 MacroBuilder &Builder) const {
818 // Target identification.
819 if (getTriple().getArch() == llvm::Triple::x86_64) {
820 Builder.defineMacro("__amd64__");
821 Builder.defineMacro("__amd64");
822 Builder.defineMacro("__x86_64");
823 Builder.defineMacro("__x86_64__");
824 if (getTriple().getArchName() == "x86_64h") {
825 Builder.defineMacro("__x86_64h");
826 Builder.defineMacro("__x86_64h__");
829 DefineStd(Builder, "i386", Opts);
832 // Subtarget options.
833 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
834 // truly should be based on -mtune options.
839 // The rest are coming from the i386 define above.
840 Builder.defineMacro("__tune_i386__");
846 defineCPUMacros(Builder, "i486");
849 Builder.defineMacro("__pentium_mmx__");
850 Builder.defineMacro("__tune_pentium_mmx__");
854 defineCPUMacros(Builder, "i586");
855 defineCPUMacros(Builder, "pentium");
859 Builder.defineMacro("__tune_pentium3__");
863 Builder.defineMacro("__tune_pentium2__");
866 defineCPUMacros(Builder, "i686");
867 defineCPUMacros(Builder, "pentiumpro");
870 defineCPUMacros(Builder, "pentium4");
875 defineCPUMacros(Builder, "nocona");
879 defineCPUMacros(Builder, "core2");
882 defineCPUMacros(Builder, "atom");
885 defineCPUMacros(Builder, "slm");
888 defineCPUMacros(Builder, "goldmont");
896 case CK_SkylakeClient:
897 case CK_SkylakeServer:
900 // FIXME: Historically, we defined this legacy name, it would be nice to
901 // remove it at some point. We've never exposed fine-grained names for
902 // recent primary x86 CPUs, and we should keep it that way.
903 defineCPUMacros(Builder, "corei7");
906 defineCPUMacros(Builder, "knl");
911 defineCPUMacros(Builder, "i586", /*Tuning*/false);
912 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
913 Builder.defineMacro("__tune_lakemont__");
916 Builder.defineMacro("__k6_2__");
917 Builder.defineMacro("__tune_k6_2__");
920 if (CPU != CK_K6_2) { // In case of fallthrough
921 // FIXME: GCC may be enabling these in cases where some other k6
922 // architecture is specified but -m3dnow is explicitly provided. The
923 // exact semantics need to be determined and emulated here.
924 Builder.defineMacro("__k6_3__");
925 Builder.defineMacro("__tune_k6_3__");
929 defineCPUMacros(Builder, "k6");
933 defineCPUMacros(Builder, "athlon");
934 if (SSELevel != NoSSE) {
935 Builder.defineMacro("__athlon_sse__");
936 Builder.defineMacro("__tune_athlon_sse__");
942 defineCPUMacros(Builder, "k8");
945 defineCPUMacros(Builder, "amdfam10");
948 defineCPUMacros(Builder, "btver1");
951 defineCPUMacros(Builder, "btver2");
954 defineCPUMacros(Builder, "bdver1");
957 defineCPUMacros(Builder, "bdver2");
960 defineCPUMacros(Builder, "bdver3");
963 defineCPUMacros(Builder, "bdver4");
966 defineCPUMacros(Builder, "znver1");
969 defineCPUMacros(Builder, "geode");
973 // Target properties.
974 Builder.defineMacro("__REGISTER_PREFIX__", "");
976 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
977 // functions in glibc header files that use FP Stack inline asm which the
978 // backend can't deal with (PR879).
979 Builder.defineMacro("__NO_MATH_INLINES");
982 Builder.defineMacro("__AES__");
985 Builder.defineMacro("__VAES__");
988 Builder.defineMacro("__PCLMUL__");
991 Builder.defineMacro("__VPCLMULQDQ__");
994 Builder.defineMacro("__LZCNT__");
997 Builder.defineMacro("__RDRND__");
1000 Builder.defineMacro("__FSGSBASE__");
1003 Builder.defineMacro("__BMI__");
1006 Builder.defineMacro("__BMI2__");
1009 Builder.defineMacro("__POPCNT__");
1012 Builder.defineMacro("__RTM__");
1015 Builder.defineMacro("__PRFCHW__");
1018 Builder.defineMacro("__RDSEED__");
1021 Builder.defineMacro("__ADX__");
1024 Builder.defineMacro("__TBM__");
1027 Builder.defineMacro("__LWP__");
1030 Builder.defineMacro("__MWAITX__");
1034 Builder.defineMacro("__XOP__");
1037 Builder.defineMacro("__FMA4__");
1040 Builder.defineMacro("__SSE4A__");
1047 Builder.defineMacro("__FMA__");
1050 Builder.defineMacro("__F16C__");
1053 Builder.defineMacro("__GFNI__");
1056 Builder.defineMacro("__AVX512CD__");
1057 if (HasAVX512VPOPCNTDQ)
1058 Builder.defineMacro("__AVX512VPOPCNTDQ__");
1060 Builder.defineMacro("__AVX512VNNI__");
1062 Builder.defineMacro("__AVX512ER__");
1064 Builder.defineMacro("__AVX512PF__");
1066 Builder.defineMacro("__AVX512DQ__");
1067 if (HasAVX512BITALG)
1068 Builder.defineMacro("__AVX512BITALG__");
1070 Builder.defineMacro("__AVX512BW__");
1072 Builder.defineMacro("__AVX512VL__");
1074 Builder.defineMacro("__AVX512VBMI__");
1076 Builder.defineMacro("__AVX512VBMI2__");
1078 Builder.defineMacro("__AVX512IFMA__");
1081 Builder.defineMacro("__SHA__");
1084 Builder.defineMacro("__FXSR__");
1086 Builder.defineMacro("__XSAVE__");
1088 Builder.defineMacro("__XSAVEOPT__");
1090 Builder.defineMacro("__XSAVEC__");
1092 Builder.defineMacro("__XSAVES__");
1094 Builder.defineMacro("__PKU__");
1096 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1098 Builder.defineMacro("__CLFLUSHOPT__");
1100 Builder.defineMacro("__CLWB__");
1102 Builder.defineMacro("__MPX__");
1104 Builder.defineMacro("__SHSTK__");
1106 Builder.defineMacro("__SGX__");
1108 Builder.defineMacro("__PREFETCHWT1__");
1110 Builder.defineMacro("__CLZERO__");
1112 // Each case falls through to the previous one here.
1115 Builder.defineMacro("__AVX512F__");
1118 Builder.defineMacro("__AVX2__");
1121 Builder.defineMacro("__AVX__");
1124 Builder.defineMacro("__SSE4_2__");
1127 Builder.defineMacro("__SSE4_1__");
1130 Builder.defineMacro("__SSSE3__");
1133 Builder.defineMacro("__SSE3__");
1136 Builder.defineMacro("__SSE2__");
1137 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1140 Builder.defineMacro("__SSE__");
1141 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1147 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1157 Builder.defineMacro("_M_IX86_FP", Twine(2));
1160 Builder.defineMacro("_M_IX86_FP", Twine(1));
1163 Builder.defineMacro("_M_IX86_FP", Twine(0));
1168 // Each case falls through to the previous one here.
1169 switch (MMX3DNowLevel) {
1170 case AMD3DNowAthlon:
1171 Builder.defineMacro("__3dNOW_A__");
1174 Builder.defineMacro("__3dNOW__");
1177 Builder.defineMacro("__MMX__");
1183 if (CPU >= CK_i486) {
1184 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1185 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1186 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1189 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1192 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1195 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1196 return llvm::StringSwitch<bool>(Name)
1197 .Case("3dnow", true)
1198 .Case("3dnowa", true)
1203 .Case("avx512f", true)
1204 .Case("avx512cd", true)
1205 .Case("avx512vpopcntdq", true)
1206 .Case("avx512vnni", true)
1207 .Case("avx512er", true)
1208 .Case("avx512pf", true)
1209 .Case("avx512dq", true)
1210 .Case("avx512bitalg", true)
1211 .Case("avx512bw", true)
1212 .Case("avx512vl", true)
1213 .Case("avx512vbmi", true)
1214 .Case("avx512vbmi2", true)
1215 .Case("avx512ifma", true)
1218 .Case("clflushopt", true)
1220 .Case("clzero", true)
1225 .Case("fsgsbase", true)
1229 .Case("lzcnt", true)
1231 .Case("movbe", true)
1233 .Case("mwaitx", true)
1234 .Case("pclmul", true)
1236 .Case("popcnt", true)
1237 .Case("prefetchwt1", true)
1238 .Case("prfchw", true)
1239 .Case("rdrnd", true)
1240 .Case("rdseed", true)
1244 .Case("shstk", true)
1248 .Case("ssse3", true)
1250 .Case("sse4.1", true)
1251 .Case("sse4.2", true)
1252 .Case("sse4a", true)
1255 .Case("vpclmulqdq", true)
1258 .Case("xsave", true)
1259 .Case("xsavec", true)
1260 .Case("xsaves", true)
1261 .Case("xsaveopt", true)
1265 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1266 return llvm::StringSwitch<bool>(Feature)
1267 .Case("adx", HasADX)
1268 .Case("aes", HasAES)
1269 .Case("avx", SSELevel >= AVX)
1270 .Case("avx2", SSELevel >= AVX2)
1271 .Case("avx512f", SSELevel >= AVX512F)
1272 .Case("avx512cd", HasAVX512CD)
1273 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1274 .Case("avx512vnni", HasAVX512VNNI)
1275 .Case("avx512er", HasAVX512ER)
1276 .Case("avx512pf", HasAVX512PF)
1277 .Case("avx512dq", HasAVX512DQ)
1278 .Case("avx512bitalg", HasAVX512BITALG)
1279 .Case("avx512bw", HasAVX512BW)
1280 .Case("avx512vl", HasAVX512VL)
1281 .Case("avx512vbmi", HasAVX512VBMI)
1282 .Case("avx512vbmi2", HasAVX512VBMI2)
1283 .Case("avx512ifma", HasAVX512IFMA)
1284 .Case("bmi", HasBMI)
1285 .Case("bmi2", HasBMI2)
1286 .Case("clflushopt", HasCLFLUSHOPT)
1287 .Case("clwb", HasCLWB)
1288 .Case("clzero", HasCLZERO)
1289 .Case("cx16", HasCX16)
1290 .Case("f16c", HasF16C)
1291 .Case("fma", HasFMA)
1292 .Case("fma4", XOPLevel >= FMA4)
1293 .Case("fsgsbase", HasFSGSBASE)
1294 .Case("fxsr", HasFXSR)
1295 .Case("gfni", HasGFNI)
1296 .Case("ibt", HasIBT)
1297 .Case("lwp", HasLWP)
1298 .Case("lzcnt", HasLZCNT)
1299 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1300 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1301 .Case("mmx", MMX3DNowLevel >= MMX)
1302 .Case("movbe", HasMOVBE)
1303 .Case("mpx", HasMPX)
1304 .Case("mwaitx", HasMWAITX)
1305 .Case("pclmul", HasPCLMUL)
1306 .Case("pku", HasPKU)
1307 .Case("popcnt", HasPOPCNT)
1308 .Case("prefetchwt1", HasPREFETCHWT1)
1309 .Case("prfchw", HasPRFCHW)
1310 .Case("rdrnd", HasRDRND)
1311 .Case("rdseed", HasRDSEED)
1312 .Case("retpoline", HasRetpoline)
1313 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1314 .Case("rtm", HasRTM)
1315 .Case("sgx", HasSGX)
1316 .Case("sha", HasSHA)
1317 .Case("shstk", HasSHSTK)
1318 .Case("sse", SSELevel >= SSE1)
1319 .Case("sse2", SSELevel >= SSE2)
1320 .Case("sse3", SSELevel >= SSE3)
1321 .Case("ssse3", SSELevel >= SSSE3)
1322 .Case("sse4.1", SSELevel >= SSE41)
1323 .Case("sse4.2", SSELevel >= SSE42)
1324 .Case("sse4a", XOPLevel >= SSE4A)
1325 .Case("tbm", HasTBM)
1326 .Case("vaes", HasVAES)
1327 .Case("vpclmulqdq", HasVPCLMULQDQ)
1329 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1330 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1331 .Case("xop", XOPLevel >= XOP)
1332 .Case("xsave", HasXSAVE)
1333 .Case("xsavec", HasXSAVEC)
1334 .Case("xsaves", HasXSAVES)
1335 .Case("xsaveopt", HasXSAVEOPT)
1339 // We can't use a generic validation scheme for the features accepted here
1340 // versus subtarget features accepted in the target attribute because the
1341 // bitfield structure that's initialized in the runtime only supports the
1342 // below currently rather than the full range of subtarget features. (See
1343 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1344 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1345 return llvm::StringSwitch<bool>(FeatureStr)
1346 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1347 #include "llvm/Support/X86TargetParser.def"
1351 // We can't use a generic validation scheme for the cpus accepted here
1352 // versus subtarget cpus accepted in the target attribute because the
1353 // variables intitialized by the runtime only support the below currently
1354 // rather than the full range of cpus.
1355 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1356 return llvm::StringSwitch<bool>(FeatureStr)
1357 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1358 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1359 .Cases(STR, ALIAS, true)
1360 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1361 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1362 #include "llvm/Support/X86TargetParser.def"
1366 bool X86TargetInfo::validateAsmConstraint(
1367 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1371 // Constant constraints.
1372 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1374 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1375 // x86_64 instructions.
1377 Info.setRequiresImmediate();
1380 Info.setRequiresImmediate(0, 31);
1383 Info.setRequiresImmediate(0, 63);
1386 Info.setRequiresImmediate(-128, 127);
1389 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1392 Info.setRequiresImmediate(0, 3);
1395 Info.setRequiresImmediate(0, 255);
1398 Info.setRequiresImmediate(0, 127);
1400 // Register constraints.
1401 case 'Y': // 'Y' is the first character for several 2-character constraints.
1402 // Shift the pointer to the second character of the constraint.
1408 case '0': // First SSE register.
1410 case 't': // Any SSE register, when SSE2 is enabled.
1411 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1412 case 'm': // Any MMX register, when inter-unit moves enabled.
1413 case 'k': // AVX512 arch mask registers: k1-k7.
1414 Info.setAllowsRegister();
1417 case 'f': // Any x87 floating point stack register.
1418 // Constraint 'f' cannot be used for output operands.
1419 if (Info.ConstraintStr[0] == '=')
1421 Info.setAllowsRegister();
1429 case 'A': // edx:eax.
1430 case 't': // Top of floating point stack.
1431 case 'u': // Second from top of floating point stack.
1432 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1433 case 'y': // Any MMX register.
1434 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1435 case 'x': // Any SSE register.
1436 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
1437 // for intermideate k reg operations).
1438 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1439 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1440 case 'l': // "Index" registers: any general register that can be used as an
1441 // index in a base+index memory access.
1442 Info.setAllowsRegister();
1444 // Floating point constant constraints.
1445 case 'C': // SSE floating point constant.
1446 case 'G': // x87 floating point constant.
1451 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1452 unsigned Size) const {
1453 // Strip off constraint modifiers.
1454 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1455 Constraint = Constraint.substr(1);
1457 return validateOperandSize(Constraint, Size);
1460 bool X86TargetInfo::validateInputSize(StringRef Constraint,
1461 unsigned Size) const {
1462 return validateOperandSize(Constraint, Size);
1465 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1466 unsigned Size) const {
1467 switch (Constraint[0]) {
1471 // Registers k0-k7 (AVX512) size limit is 64 bit.
1479 // 'Y' is the first character for several 2-character constraints.
1480 switch (Constraint[1]) {
1484 // 'Ym' is synonymous with 'y'.
1490 if (SSELevel >= SSE1)
1491 return Size <= 128U;
1496 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1497 if (SSELevel < SSE2)
1503 if (SSELevel >= AVX512F)
1504 // 512-bit zmm registers can be used if target supports AVX512F.
1505 return Size <= 512U;
1506 else if (SSELevel >= AVX)
1507 // 256-bit ymm registers can be used if target supports AVX.
1508 return Size <= 256U;
1509 return Size <= 128U;
1516 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1517 switch (*Constraint) {
1519 return std::string("{ax}");
1521 return std::string("{bx}");
1523 return std::string("{cx}");
1525 return std::string("{dx}");
1527 return std::string("{si}");
1529 return std::string("{di}");
1530 case 'p': // address
1531 return std::string("im");
1532 case 't': // top of floating point stack.
1533 return std::string("{st}");
1534 case 'u': // second from top of floating point stack.
1535 return std::string("{st(1)}"); // second from top of floating point stack.
1537 switch (Constraint[1]) {
1539 // Break from inner switch and fall through (copy single char),
1540 // continue parsing after copying the current constraint into
1541 // the return string.
1550 // "^" hints llvm that this is a 2 letter constraint.
1551 // "Constraint++" is used to promote the string iterator
1552 // to the next constraint.
1553 return std::string("^") + std::string(Constraint++, 2);
1557 return std::string(1, *Constraint);
1561 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const {
1562 // Perform any per-CPU checks necessary to determine if this CPU is
1564 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1565 // invalid without explaining *why*.
1568 // No processor selected!
1570 #define PROC(ENUM, STRING, IS64BIT) \
1572 return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1573 #include "clang/Basic/X86Target.def"
1575 llvm_unreachable("Unhandled CPU kind");
1578 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
1579 return llvm::StringSwitch<CPUKind>(CPU)
1580 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1581 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1582 #include "clang/Basic/X86Target.def"
1583 .Default(CK_Generic);
1586 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1587 return llvm::makeArrayRef(GCCRegNames);
1590 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1591 return llvm::makeArrayRef(AddlRegNames);
1594 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1595 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1596 Builtin::FirstTSBuiltin + 1);
1599 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1600 return llvm::makeArrayRef(BuiltinInfoX86,
1601 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);