1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Cuda.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetInfo.h"
22 #include "clang/Basic/TargetOptions.h"
23 #include "clang/Basic/Version.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/TargetParser.h"
37 using namespace clang;
39 //===----------------------------------------------------------------------===//
40 // Common code shared among targets.
41 //===----------------------------------------------------------------------===//
43 /// DefineStd - Define a macro name and standard variants. For example if
44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
47 const LangOptions &Opts) {
48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
51 // in the user's namespace.
53 Builder.defineMacro(MacroName);
56 Builder.defineMacro("__" + MacroName);
59 Builder.defineMacro("__" + MacroName + "__");
62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
64 Builder.defineMacro("__" + CPUName);
65 Builder.defineMacro("__" + CPUName + "__");
67 Builder.defineMacro("__tune_" + CPUName + "__");
70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
71 const TargetOptions &Opts);
73 //===----------------------------------------------------------------------===//
74 // Defines specific to certain operating systems.
75 //===----------------------------------------------------------------------===//
78 template<typename TgtInfo>
79 class OSTargetInfo : public TgtInfo {
81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
82 MacroBuilder &Builder) const=0;
84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
85 : TgtInfo(Triple, Opts) {}
86 void getTargetDefines(const LangOptions &Opts,
87 MacroBuilder &Builder) const override {
88 TgtInfo::getTargetDefines(Opts, Builder);
89 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
95 template <typename Target>
96 class CloudABITargetInfo : public OSTargetInfo<Target> {
98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
99 MacroBuilder &Builder) const override {
100 Builder.defineMacro("__CloudABI__");
101 Builder.defineMacro("__ELF__");
103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
104 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
105 Builder.defineMacro("__STDC_UTF_16__");
106 Builder.defineMacro("__STDC_UTF_32__");
110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
111 : OSTargetInfo<Target>(Triple, Opts) {}
114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
115 const llvm::Triple &Triple,
116 StringRef &PlatformName,
117 VersionTuple &PlatformMinVersion) {
118 Builder.defineMacro("__APPLE_CC__", "6000");
119 Builder.defineMacro("__APPLE__");
120 Builder.defineMacro("__STDC_NO_THREADS__");
121 Builder.defineMacro("OBJC_NEW_PROPERTIES");
122 // AddressSanitizer doesn't play well with source fortification, which is on
123 // by default on Darwin.
124 if (Opts.Sanitize.has(SanitizerKind::Address))
125 Builder.defineMacro("_FORTIFY_SOURCE", "0");
127 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
129 // __weak is always defined, for use in blocks and with objc pointers.
130 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
131 Builder.defineMacro("__strong", "");
132 Builder.defineMacro("__unsafe_unretained", "");
136 Builder.defineMacro("__STATIC__");
138 Builder.defineMacro("__DYNAMIC__");
140 if (Opts.POSIXThreads)
141 Builder.defineMacro("_REENTRANT");
143 // Get the platform type and version number from the triple.
144 unsigned Maj, Min, Rev;
145 if (Triple.isMacOSX()) {
146 Triple.getMacOSXVersion(Maj, Min, Rev);
147 PlatformName = "macos";
149 Triple.getOSVersion(Maj, Min, Rev);
150 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
153 // If -target arch-pc-win32-macho option specified, we're
154 // generating code for Win32 ABI. No need to emit
155 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
156 if (PlatformName == "win32") {
157 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
161 // Set the appropriate OS version define.
162 if (Triple.isiOS()) {
163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
167 Str[1] = '0' + (Min / 10);
168 Str[2] = '0' + (Min % 10);
169 Str[3] = '0' + (Rev / 10);
170 Str[4] = '0' + (Rev % 10);
173 // Handle versions >= 10.
174 Str[0] = '0' + (Maj / 10);
175 Str[1] = '0' + (Maj % 10);
176 Str[2] = '0' + (Min / 10);
177 Str[3] = '0' + (Min % 10);
178 Str[4] = '0' + (Rev / 10);
179 Str[5] = '0' + (Rev % 10);
183 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
185 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
188 } else if (Triple.isWatchOS()) {
189 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
192 Str[1] = '0' + (Min / 10);
193 Str[2] = '0' + (Min % 10);
194 Str[3] = '0' + (Rev / 10);
195 Str[4] = '0' + (Rev % 10);
197 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
198 } else if (Triple.isMacOSX()) {
199 // Note that the Driver allows versions which aren't representable in the
200 // define (because we only get a single digit for the minor and micro
201 // revision numbers). So, we limit them to the maximum representable
203 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
205 if (Maj < 10 || (Maj == 10 && Min < 10)) {
206 Str[0] = '0' + (Maj / 10);
207 Str[1] = '0' + (Maj % 10);
208 Str[2] = '0' + std::min(Min, 9U);
209 Str[3] = '0' + std::min(Rev, 9U);
212 // Handle versions > 10.9.
213 Str[0] = '0' + (Maj / 10);
214 Str[1] = '0' + (Maj % 10);
215 Str[2] = '0' + (Min / 10);
216 Str[3] = '0' + (Min % 10);
217 Str[4] = '0' + (Rev / 10);
218 Str[5] = '0' + (Rev % 10);
221 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
224 // Tell users about the kernel if there is one.
225 if (Triple.isOSDarwin())
226 Builder.defineMacro("__MACH__");
228 // The Watch ABI uses Dwarf EH.
229 if(Triple.isWatchABI())
230 Builder.defineMacro("__ARM_DWARF_EH__");
232 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
235 template<typename Target>
236 class DarwinTargetInfo : public OSTargetInfo<Target> {
238 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
239 MacroBuilder &Builder) const override {
240 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
241 this->PlatformMinVersion);
245 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
246 : OSTargetInfo<Target>(Triple, Opts) {
247 // By default, no TLS, and we whitelist permitted architecture/OS
249 this->TLSSupported = false;
251 if (Triple.isMacOSX())
252 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
253 else if (Triple.isiOS()) {
254 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
255 if (Triple.getArch() == llvm::Triple::x86_64 ||
256 Triple.getArch() == llvm::Triple::aarch64)
257 this->TLSSupported = !Triple.isOSVersionLT(8);
258 else if (Triple.getArch() == llvm::Triple::x86 ||
259 Triple.getArch() == llvm::Triple::arm ||
260 Triple.getArch() == llvm::Triple::thumb)
261 this->TLSSupported = !Triple.isOSVersionLT(9);
262 } else if (Triple.isWatchOS())
263 this->TLSSupported = !Triple.isOSVersionLT(2);
265 this->MCountName = "\01mcount";
268 std::string isValidSectionSpecifier(StringRef SR) const override {
269 // Let MCSectionMachO validate this.
270 StringRef Segment, Section;
271 unsigned TAA, StubSize;
273 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
274 TAA, HasTAA, StubSize);
277 const char *getStaticInitSectionSpecifier() const override {
278 // FIXME: We should return 0 when building kexts.
279 return "__TEXT,__StaticInit,regular,pure_instructions";
282 /// Darwin does not support protected visibility. Darwin's "default"
283 /// is very similar to ELF's "protected"; Darwin requires a "weak"
284 /// attribute on declarations that can be dynamically replaced.
285 bool hasProtectedVisibility() const override {
289 unsigned getExnObjectAlignment() const override {
290 // The alignment of an exception object is 8-bytes for darwin since
291 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned))
292 // and therefore doesn't guarantee 16-byte alignment.
298 // DragonFlyBSD Target
299 template<typename Target>
300 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
302 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
303 MacroBuilder &Builder) const override {
304 // DragonFly defines; list based off of gcc output
305 Builder.defineMacro("__DragonFly__");
306 Builder.defineMacro("__DragonFly_cc_version", "100001");
307 Builder.defineMacro("__ELF__");
308 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
309 Builder.defineMacro("__tune_i386__");
310 DefineStd(Builder, "unix", Opts);
313 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
314 : OSTargetInfo<Target>(Triple, Opts) {
315 switch (Triple.getArch()) {
317 case llvm::Triple::x86:
318 case llvm::Triple::x86_64:
319 this->MCountName = ".mcount";
325 #ifndef FREEBSD_CC_VERSION
326 #define FREEBSD_CC_VERSION 0U
330 template<typename Target>
331 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
334 MacroBuilder &Builder) const override {
335 // FreeBSD defines; list based off of gcc output
337 unsigned Release = Triple.getOSMajorVersion();
340 unsigned CCVersion = FREEBSD_CC_VERSION;
342 CCVersion = Release * 100000U + 1U;
344 Builder.defineMacro("__FreeBSD__", Twine(Release));
345 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
346 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
347 DefineStd(Builder, "unix", Opts);
348 Builder.defineMacro("__ELF__");
350 // On FreeBSD, wchar_t contains the number of the code point as
351 // used by the character set of the locale. These character sets are
352 // not necessarily a superset of ASCII.
354 // FIXME: This is wrong; the macro refers to the numerical values
355 // of wchar_t *literals*, which are not locale-dependent. However,
356 // FreeBSD systems apparently depend on us getting this wrong, and
357 // setting this to 1 is conforming even if all the basic source
358 // character literals have the same encoding as char and wchar_t.
359 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
362 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
363 : OSTargetInfo<Target>(Triple, Opts) {
364 switch (Triple.getArch()) {
366 case llvm::Triple::x86:
367 case llvm::Triple::x86_64:
368 this->MCountName = ".mcount";
370 case llvm::Triple::mips:
371 case llvm::Triple::mipsel:
372 case llvm::Triple::ppc:
373 case llvm::Triple::ppc64:
374 case llvm::Triple::ppc64le:
375 this->MCountName = "_mcount";
377 case llvm::Triple::arm:
378 this->MCountName = "__mcount";
384 // GNU/kFreeBSD Target
385 template<typename Target>
386 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
388 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
389 MacroBuilder &Builder) const override {
390 // GNU/kFreeBSD defines; list based off of gcc output
392 DefineStd(Builder, "unix", Opts);
393 Builder.defineMacro("__FreeBSD_kernel__");
394 Builder.defineMacro("__GLIBC__");
395 Builder.defineMacro("__ELF__");
396 if (Opts.POSIXThreads)
397 Builder.defineMacro("_REENTRANT");
399 Builder.defineMacro("_GNU_SOURCE");
402 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
403 : OSTargetInfo<Target>(Triple, Opts) {}
407 template<typename Target>
408 class HaikuTargetInfo : public OSTargetInfo<Target> {
410 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
411 MacroBuilder &Builder) const override {
412 // Haiku defines; list based off of gcc output
413 Builder.defineMacro("__HAIKU__");
414 Builder.defineMacro("__ELF__");
415 DefineStd(Builder, "unix", Opts);
418 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
419 : OSTargetInfo<Target>(Triple, Opts) {
420 this->SizeType = TargetInfo::UnsignedLong;
421 this->IntPtrType = TargetInfo::SignedLong;
422 this->PtrDiffType = TargetInfo::SignedLong;
423 this->ProcessIDType = TargetInfo::SignedLong;
424 this->TLSSupported = false;
430 template<typename Target>
431 class MinixTargetInfo : public OSTargetInfo<Target> {
433 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
434 MacroBuilder &Builder) const override {
437 Builder.defineMacro("__minix", "3");
438 Builder.defineMacro("_EM_WSIZE", "4");
439 Builder.defineMacro("_EM_PSIZE", "4");
440 Builder.defineMacro("_EM_SSIZE", "2");
441 Builder.defineMacro("_EM_LSIZE", "4");
442 Builder.defineMacro("_EM_FSIZE", "4");
443 Builder.defineMacro("_EM_DSIZE", "8");
444 Builder.defineMacro("__ELF__");
445 DefineStd(Builder, "unix", Opts);
448 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
449 : OSTargetInfo<Target>(Triple, Opts) {}
453 template<typename Target>
454 class LinuxTargetInfo : public OSTargetInfo<Target> {
456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
457 MacroBuilder &Builder) const override {
458 // Linux defines; list based off of gcc output
459 DefineStd(Builder, "unix", Opts);
460 DefineStd(Builder, "linux", Opts);
461 Builder.defineMacro("__gnu_linux__");
462 Builder.defineMacro("__ELF__");
463 if (Triple.isAndroid()) {
464 Builder.defineMacro("__ANDROID__", "1");
465 unsigned Maj, Min, Rev;
466 Triple.getEnvironmentVersion(Maj, Min, Rev);
467 this->PlatformName = "android";
468 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
470 Builder.defineMacro("__ANDROID_API__", Twine(Maj));
472 if (Opts.POSIXThreads)
473 Builder.defineMacro("_REENTRANT");
475 Builder.defineMacro("_GNU_SOURCE");
476 if (this->HasFloat128)
477 Builder.defineMacro("__FLOAT128__");
480 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
481 : OSTargetInfo<Target>(Triple, Opts) {
482 this->WIntType = TargetInfo::UnsignedInt;
484 switch (Triple.getArch()) {
487 case llvm::Triple::ppc:
488 case llvm::Triple::ppc64:
489 case llvm::Triple::ppc64le:
490 this->MCountName = "_mcount";
492 case llvm::Triple::x86:
493 case llvm::Triple::x86_64:
494 case llvm::Triple::systemz:
495 this->HasFloat128 = true;
500 const char *getStaticInitSectionSpecifier() const override {
501 return ".text.startup";
506 template<typename Target>
507 class NetBSDTargetInfo : public OSTargetInfo<Target> {
509 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
510 MacroBuilder &Builder) const override {
511 // NetBSD defines; list based off of gcc output
512 Builder.defineMacro("__NetBSD__");
513 Builder.defineMacro("__unix__");
514 Builder.defineMacro("__ELF__");
515 if (Opts.POSIXThreads)
516 Builder.defineMacro("_REENTRANT");
518 switch (Triple.getArch()) {
521 case llvm::Triple::arm:
522 case llvm::Triple::armeb:
523 case llvm::Triple::thumb:
524 case llvm::Triple::thumbeb:
525 Builder.defineMacro("__ARM_DWARF_EH__");
530 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
531 : OSTargetInfo<Target>(Triple, Opts) {
532 this->MCountName = "_mcount";
537 template<typename Target>
538 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
540 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
541 MacroBuilder &Builder) const override {
542 // OpenBSD defines; list based off of gcc output
544 Builder.defineMacro("__OpenBSD__");
545 DefineStd(Builder, "unix", Opts);
546 Builder.defineMacro("__ELF__");
547 if (Opts.POSIXThreads)
548 Builder.defineMacro("_REENTRANT");
549 if (this->HasFloat128)
550 Builder.defineMacro("__FLOAT128__");
553 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
554 : OSTargetInfo<Target>(Triple, Opts) {
555 this->TLSSupported = false;
557 switch (Triple.getArch()) {
558 case llvm::Triple::x86:
559 case llvm::Triple::x86_64:
560 this->HasFloat128 = true;
563 this->MCountName = "__mcount";
565 case llvm::Triple::mips64:
566 case llvm::Triple::mips64el:
567 case llvm::Triple::ppc:
568 case llvm::Triple::sparcv9:
569 this->MCountName = "_mcount";
576 template<typename Target>
577 class BitrigTargetInfo : public OSTargetInfo<Target> {
579 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
580 MacroBuilder &Builder) const override {
581 // Bitrig defines; list based off of gcc output
583 Builder.defineMacro("__Bitrig__");
584 DefineStd(Builder, "unix", Opts);
585 Builder.defineMacro("__ELF__");
586 if (Opts.POSIXThreads)
587 Builder.defineMacro("_REENTRANT");
589 switch (Triple.getArch()) {
592 case llvm::Triple::arm:
593 case llvm::Triple::armeb:
594 case llvm::Triple::thumb:
595 case llvm::Triple::thumbeb:
596 Builder.defineMacro("__ARM_DWARF_EH__");
601 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
602 : OSTargetInfo<Target>(Triple, Opts) {
603 this->MCountName = "__mcount";
608 template<typename Target>
609 class PSPTargetInfo : public OSTargetInfo<Target> {
611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
612 MacroBuilder &Builder) const override {
613 // PSP defines; list based on the output of the pspdev gcc toolchain.
614 Builder.defineMacro("PSP");
615 Builder.defineMacro("_PSP");
616 Builder.defineMacro("__psp__");
617 Builder.defineMacro("__ELF__");
620 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {}
624 template<typename Target>
625 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
627 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
628 MacroBuilder &Builder) const override {
630 Builder.defineMacro("__PPC__");
631 Builder.defineMacro("__PPU__");
632 Builder.defineMacro("__CELLOS_LV2__");
633 Builder.defineMacro("__ELF__");
634 Builder.defineMacro("__LP32__");
635 Builder.defineMacro("_ARCH_PPC64");
636 Builder.defineMacro("__powerpc64__");
639 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
640 : OSTargetInfo<Target>(Triple, Opts) {
641 this->LongWidth = this->LongAlign = 32;
642 this->PointerWidth = this->PointerAlign = 32;
643 this->IntMaxType = TargetInfo::SignedLongLong;
644 this->Int64Type = TargetInfo::SignedLongLong;
645 this->SizeType = TargetInfo::UnsignedInt;
646 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64");
650 template <typename Target>
651 class PS4OSTargetInfo : public OSTargetInfo<Target> {
653 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
654 MacroBuilder &Builder) const override {
655 Builder.defineMacro("__FreeBSD__", "9");
656 Builder.defineMacro("__FreeBSD_cc_version", "900001");
657 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
658 DefineStd(Builder, "unix", Opts);
659 Builder.defineMacro("__ELF__");
660 Builder.defineMacro("__ORBIS__");
663 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
664 : OSTargetInfo<Target>(Triple, Opts) {
665 this->WCharType = this->UnsignedShort;
667 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
668 this->MaxTLSAlign = 256;
670 // On PS4, do not honor explicit bit field alignment,
671 // as in "__attribute__((aligned(2))) int b : 1;".
672 this->UseExplicitBitFieldAlignment = false;
674 switch (Triple.getArch()) {
676 case llvm::Triple::x86_64:
677 this->MCountName = ".mcount";
684 template<typename Target>
685 class SolarisTargetInfo : public OSTargetInfo<Target> {
687 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
688 MacroBuilder &Builder) const override {
689 DefineStd(Builder, "sun", Opts);
690 DefineStd(Builder, "unix", Opts);
691 Builder.defineMacro("__ELF__");
692 Builder.defineMacro("__svr4__");
693 Builder.defineMacro("__SVR4");
694 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
695 // newer, but to 500 for everything else. feature_test.h has a check to
696 // ensure that you are not using C99 with an old version of X/Open or C89
697 // with a new version.
699 Builder.defineMacro("_XOPEN_SOURCE", "600");
701 Builder.defineMacro("_XOPEN_SOURCE", "500");
703 Builder.defineMacro("__C99FEATURES__");
704 Builder.defineMacro("_LARGEFILE_SOURCE");
705 Builder.defineMacro("_LARGEFILE64_SOURCE");
706 Builder.defineMacro("__EXTENSIONS__");
707 Builder.defineMacro("_REENTRANT");
710 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
711 : OSTargetInfo<Target>(Triple, Opts) {
712 this->WCharType = this->SignedInt;
713 // FIXME: WIntType should be SignedLong
718 template<typename Target>
719 class WindowsTargetInfo : public OSTargetInfo<Target> {
721 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
722 MacroBuilder &Builder) const override {
723 Builder.defineMacro("_WIN32");
725 void getVisualStudioDefines(const LangOptions &Opts,
726 MacroBuilder &Builder) const {
727 if (Opts.CPlusPlus) {
729 Builder.defineMacro("_CPPRTTI");
731 if (Opts.CXXExceptions)
732 Builder.defineMacro("_CPPUNWIND");
736 Builder.defineMacro("__BOOL_DEFINED");
738 if (!Opts.CharIsSigned)
739 Builder.defineMacro("_CHAR_UNSIGNED");
741 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
742 // but it works for now.
743 if (Opts.POSIXThreads)
744 Builder.defineMacro("_MT");
746 if (Opts.MSCompatibilityVersion) {
747 Builder.defineMacro("_MSC_VER",
748 Twine(Opts.MSCompatibilityVersion / 100000));
749 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
750 // FIXME We cannot encode the revision information into 32-bits
751 Builder.defineMacro("_MSC_BUILD", Twine(1));
753 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
754 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
756 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
757 if (Opts.CPlusPlus1z)
758 Builder.defineMacro("_MSVC_LANG", "201403L");
759 else if (Opts.CPlusPlus14)
760 Builder.defineMacro("_MSVC_LANG", "201402L");
764 if (Opts.MicrosoftExt) {
765 Builder.defineMacro("_MSC_EXTENSIONS");
767 if (Opts.CPlusPlus11) {
768 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
769 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
770 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
774 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
778 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
779 : OSTargetInfo<Target>(Triple, Opts) {}
782 template <typename Target>
783 class NaClTargetInfo : public OSTargetInfo<Target> {
785 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
786 MacroBuilder &Builder) const override {
787 if (Opts.POSIXThreads)
788 Builder.defineMacro("_REENTRANT");
790 Builder.defineMacro("_GNU_SOURCE");
792 DefineStd(Builder, "unix", Opts);
793 Builder.defineMacro("__ELF__");
794 Builder.defineMacro("__native_client__");
798 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
799 : OSTargetInfo<Target>(Triple, Opts) {
800 this->LongAlign = 32;
801 this->LongWidth = 32;
802 this->PointerAlign = 32;
803 this->PointerWidth = 32;
804 this->IntMaxType = TargetInfo::SignedLongLong;
805 this->Int64Type = TargetInfo::SignedLongLong;
806 this->DoubleAlign = 64;
807 this->LongDoubleWidth = 64;
808 this->LongDoubleAlign = 64;
809 this->LongLongWidth = 64;
810 this->LongLongAlign = 64;
811 this->SizeType = TargetInfo::UnsignedInt;
812 this->PtrDiffType = TargetInfo::SignedInt;
813 this->IntPtrType = TargetInfo::SignedInt;
814 // RegParmMax is inherited from the underlying architecture.
815 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
816 if (Triple.getArch() == llvm::Triple::arm) {
817 // Handled in ARM's setABI().
818 } else if (Triple.getArch() == llvm::Triple::x86) {
819 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128");
820 } else if (Triple.getArch() == llvm::Triple::x86_64) {
821 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128");
822 } else if (Triple.getArch() == llvm::Triple::mipsel) {
823 // Handled on mips' setDataLayout.
825 assert(Triple.getArch() == llvm::Triple::le32);
826 this->resetDataLayout("e-p:32:32-i64:64");
832 template<typename Target>
833 class FuchsiaTargetInfo : public OSTargetInfo<Target> {
835 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
836 MacroBuilder &Builder) const override {
837 Builder.defineMacro("__Fuchsia__");
838 Builder.defineMacro("__ELF__");
839 if (Opts.POSIXThreads)
840 Builder.defineMacro("_REENTRANT");
841 // Required by the libc++ locale support.
843 Builder.defineMacro("_GNU_SOURCE");
846 FuchsiaTargetInfo(const llvm::Triple &Triple,
847 const TargetOptions &Opts)
848 : OSTargetInfo<Target>(Triple, Opts) {
849 this->MCountName = "__mcount";
853 // WebAssembly target
854 template <typename Target>
855 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
856 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
857 MacroBuilder &Builder) const final {
858 // A common platform macro.
859 if (Opts.POSIXThreads)
860 Builder.defineMacro("_REENTRANT");
861 // Follow g++ convention and predefine _GNU_SOURCE for C++.
863 Builder.defineMacro("_GNU_SOURCE");
866 // As an optimization, group static init code together in a section.
867 const char *getStaticInitSectionSpecifier() const final {
868 return ".text.__startup";
872 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple,
873 const TargetOptions &Opts)
874 : OSTargetInfo<Target>(Triple, Opts) {
875 this->MCountName = "__mcount";
876 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
880 //===----------------------------------------------------------------------===//
881 // Specific target implementations.
882 //===----------------------------------------------------------------------===//
884 // PPC abstract base class
885 class PPCTargetInfo : public TargetInfo {
886 static const Builtin::Info BuiltinInfo[];
887 static const char * const GCCRegNames[];
888 static const TargetInfo::GCCRegAlias GCCRegAliases[];
891 // Target cpu features.
907 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
908 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false),
909 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
910 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) {
912 SimdDefaultAlign = 128;
913 LongDoubleWidth = LongDoubleAlign = 128;
914 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
917 /// \brief Flags for architecture specific defines.
920 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
921 ArchDefinePpcgr = 1 << 1,
922 ArchDefinePpcsq = 1 << 2,
923 ArchDefine440 = 1 << 3,
924 ArchDefine603 = 1 << 4,
925 ArchDefine604 = 1 << 5,
926 ArchDefinePwr4 = 1 << 6,
927 ArchDefinePwr5 = 1 << 7,
928 ArchDefinePwr5x = 1 << 8,
929 ArchDefinePwr6 = 1 << 9,
930 ArchDefinePwr6x = 1 << 10,
931 ArchDefinePwr7 = 1 << 11,
932 ArchDefinePwr8 = 1 << 12,
933 ArchDefinePwr9 = 1 << 13,
934 ArchDefineA2 = 1 << 14,
935 ArchDefineA2q = 1 << 15
938 // Set the language option for altivec based on our value.
939 void adjust(LangOptions &Opts) override {
942 TargetInfo::adjust(Opts);
945 // Note: GCC recognizes the following additional cpus:
946 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
947 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
949 bool setCPU(const std::string &Name) override {
950 bool CPUKnown = llvm::StringSwitch<bool>(Name)
951 .Case("generic", true)
973 .Case("e500mc", true)
975 .Case("power3", true)
977 .Case("power4", true)
979 .Case("power5", true)
981 .Case("power5x", true)
983 .Case("power6", true)
985 .Case("power6x", true)
987 .Case("power7", true)
989 .Case("power8", true)
991 .Case("power9", true)
993 .Case("powerpc", true)
995 .Case("powerpc64", true)
997 .Case("powerpc64le", true)
998 .Case("ppc64le", true)
1008 StringRef getABI() const override { return ABI; }
1010 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1011 return llvm::makeArrayRef(BuiltinInfo,
1012 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
1015 bool isCLZForZeroUndef() const override { return false; }
1017 void getTargetDefines(const LangOptions &Opts,
1018 MacroBuilder &Builder) const override;
1021 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1023 const std::vector<std::string> &FeaturesVec) const override;
1025 bool handleTargetFeatures(std::vector<std::string> &Features,
1026 DiagnosticsEngine &Diags) override;
1027 bool hasFeature(StringRef Feature) const override;
1028 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
1029 bool Enabled) const override;
1031 ArrayRef<const char *> getGCCRegNames() const override;
1032 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
1033 bool validateAsmConstraint(const char *&Name,
1034 TargetInfo::ConstraintInfo &Info) const override {
1036 default: return false;
1039 case 'b': // Base register
1040 case 'f': // Floating point register
1041 Info.setAllowsRegister();
1043 // FIXME: The following are added to allow parsing.
1044 // I just took a guess at what the actions should be.
1045 // Also, is more specific checking needed? I.e. specific registers?
1046 case 'd': // Floating point register (containing 64-bit value)
1047 case 'v': // Altivec vector register
1048 Info.setAllowsRegister();
1052 case 'd':// VSX vector register to hold vector double data
1053 case 'f':// VSX vector register to hold vector float data
1054 case 's':// VSX vector register to hold scalar float data
1055 case 'a':// Any VSX register
1056 case 'c':// An individual CR bit
1061 Info.setAllowsRegister();
1062 Name++; // Skip over 'w'.
1064 case 'h': // `MQ', `CTR', or `LINK' register
1065 case 'q': // `MQ' register
1066 case 'c': // `CTR' register
1067 case 'l': // `LINK' register
1068 case 'x': // `CR' register (condition register) number 0
1069 case 'y': // `CR' register (condition register)
1070 case 'z': // `XER[CA]' carry bit (part of the XER register)
1071 Info.setAllowsRegister();
1073 case 'I': // Signed 16-bit constant
1074 case 'J': // Unsigned 16-bit constant shifted left 16 bits
1075 // (use `L' instead for SImode constants)
1076 case 'K': // Unsigned 16-bit constant
1077 case 'L': // Signed 16-bit constant shifted left 16 bits
1078 case 'M': // Constant larger than 31
1079 case 'N': // Exact power of 2
1080 case 'P': // Constant whose negation is a signed 16-bit constant
1081 case 'G': // Floating point constant that can be loaded into a
1082 // register with one instruction per word
1083 case 'H': // Integer/Floating point constant that can be loaded
1084 // into a register using three instructions
1086 case 'm': // Memory operand. Note that on PowerPC targets, m can
1087 // include addresses that update the base register. It
1088 // is therefore only safe to use `m' in an asm statement
1089 // if that asm statement accesses the operand exactly once.
1090 // The asm statement must also use `%U<opno>' as a
1091 // placeholder for the "update" flag in the corresponding
1092 // load or store instruction. For example:
1093 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1095 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
1096 // is not. Use es rather than m if you don't want the base
1097 // register to be updated.
1101 // es: A "stable" memory operand; that is, one which does not
1102 // include any automodification of the base register. Unlike
1103 // `m', this constraint can be used in asm statements that
1104 // might access the operand several times, or that might not
1105 // access it at all.
1106 Info.setAllowsMemory();
1107 Name++; // Skip over 'e'.
1109 case 'Q': // Memory operand that is an offset from a register (it is
1110 // usually better to use `m' or `es' in asm statements)
1111 case 'Z': // Memory operand that is an indexed or indirect from a
1112 // register (it is usually better to use `m' or `es' in
1114 Info.setAllowsMemory();
1115 Info.setAllowsRegister();
1117 case 'R': // AIX TOC entry
1118 case 'a': // Address operand that is an indexed or indirect from a
1119 // register (`p' is preferable for asm statements)
1120 case 'S': // Constant suitable as a 64-bit mask operand
1121 case 'T': // Constant suitable as a 32-bit mask operand
1122 case 'U': // System V Release 4 small data area reference
1123 case 't': // AND masks that can be performed by two rldic{l, r}
1125 case 'W': // Vector constant that does not require memory
1126 case 'j': // Vector constant that is all zeros.
1132 std::string convertConstraint(const char *&Constraint) const override {
1134 switch (*Constraint) {
1137 // Two-character constraint; add "^" hint for later parsing.
1138 R = std::string("^") + std::string(Constraint, 2);
1142 return TargetInfo::convertConstraint(Constraint);
1146 const char *getClobbers() const override {
1149 int getEHDataRegisterNumber(unsigned RegNo) const override {
1150 if (RegNo == 0) return 3;
1151 if (RegNo == 1) return 4;
1155 bool hasSjLjLowering() const override {
1159 bool useFloat128ManglingForLongDouble() const override {
1160 return LongDoubleWidth == 128 &&
1161 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
1162 getTriple().isOSBinFormatELF();
1166 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1167 #define BUILTIN(ID, TYPE, ATTRS) \
1168 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1169 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1170 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1171 #include "clang/Basic/BuiltinsPPC.def"
1174 /// handleTargetFeatures - Perform initialization based on the user
1175 /// configured set of features.
1176 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1177 DiagnosticsEngine &Diags) {
1178 for (const auto &Feature : Features) {
1179 if (Feature == "+altivec") {
1181 } else if (Feature == "+vsx") {
1183 } else if (Feature == "+bpermd") {
1185 } else if (Feature == "+extdiv") {
1187 } else if (Feature == "+power8-vector") {
1189 } else if (Feature == "+crypto") {
1191 } else if (Feature == "+direct-move") {
1192 HasDirectMove = true;
1193 } else if (Feature == "+qpx") {
1195 } else if (Feature == "+htm") {
1197 } else if (Feature == "+float128") {
1199 } else if (Feature == "+power9-vector") {
1202 // TODO: Finish this list and add an assert that we've handled them
1209 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1210 /// #defines that are not tied to a specific subtarget.
1211 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1212 MacroBuilder &Builder) const {
1213 // Target identification.
1214 Builder.defineMacro("__ppc__");
1215 Builder.defineMacro("__PPC__");
1216 Builder.defineMacro("_ARCH_PPC");
1217 Builder.defineMacro("__powerpc__");
1218 Builder.defineMacro("__POWERPC__");
1219 if (PointerWidth == 64) {
1220 Builder.defineMacro("_ARCH_PPC64");
1221 Builder.defineMacro("__powerpc64__");
1222 Builder.defineMacro("__ppc64__");
1223 Builder.defineMacro("__PPC64__");
1226 // Target properties.
1227 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1228 Builder.defineMacro("_LITTLE_ENDIAN");
1230 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1231 getTriple().getOS() != llvm::Triple::OpenBSD)
1232 Builder.defineMacro("_BIG_ENDIAN");
1236 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1237 Builder.defineMacro("_CALL_ELF", "1");
1239 Builder.defineMacro("_CALL_ELF", "2");
1241 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
1242 // our suppport post-dates this and it should work on all 64-bit ppc linux
1243 // platforms. It is guaranteed to work on all elfv2 platforms.
1244 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64)
1245 Builder.defineMacro("_CALL_LINUX", "1");
1247 // Subtarget options.
1248 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1249 Builder.defineMacro("__REGISTER_PREFIX__", "");
1251 // FIXME: Should be controlled by command line option.
1252 if (LongDoubleWidth == 128) {
1253 Builder.defineMacro("__LONG_DOUBLE_128__");
1254 Builder.defineMacro("__LONGDOUBLE128");
1257 // Define this for elfv2 (64-bit only) or 64-bit darwin.
1258 if (ABI == "elfv2" ||
1259 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64))
1260 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
1262 // CPU identification.
1263 ArchDefineTypes defs =
1264 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1265 .Case("440", ArchDefineName)
1266 .Case("450", ArchDefineName | ArchDefine440)
1267 .Case("601", ArchDefineName)
1268 .Case("602", ArchDefineName | ArchDefinePpcgr)
1269 .Case("603", ArchDefineName | ArchDefinePpcgr)
1270 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1271 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1272 .Case("604", ArchDefineName | ArchDefinePpcgr)
1273 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1274 .Case("620", ArchDefineName | ArchDefinePpcgr)
1275 .Case("630", ArchDefineName | ArchDefinePpcgr)
1276 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1277 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1278 .Case("750", ArchDefineName | ArchDefinePpcgr)
1279 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1281 .Case("a2", ArchDefineA2)
1282 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1283 .Case("pwr3", ArchDefinePpcgr)
1284 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1285 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1287 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 |
1288 ArchDefinePpcgr | ArchDefinePpcsq)
1289 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 |
1290 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1291 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x |
1292 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1294 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 |
1295 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1296 ArchDefinePpcgr | ArchDefinePpcsq)
1297 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x |
1298 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1299 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1300 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 |
1301 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1302 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1304 .Case("power3", ArchDefinePpcgr)
1305 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1306 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1308 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1309 ArchDefinePpcgr | ArchDefinePpcsq)
1310 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1311 ArchDefinePwr4 | ArchDefinePpcgr |
1313 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1314 ArchDefinePwr5 | ArchDefinePwr4 |
1315 ArchDefinePpcgr | ArchDefinePpcsq)
1316 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 |
1317 ArchDefinePwr5x | ArchDefinePwr5 |
1318 ArchDefinePwr4 | ArchDefinePpcgr |
1320 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1321 ArchDefinePwr6 | ArchDefinePwr5x |
1322 ArchDefinePwr5 | ArchDefinePwr4 |
1323 ArchDefinePpcgr | ArchDefinePpcsq)
1324 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
1325 ArchDefinePwr6x | ArchDefinePwr6 |
1326 ArchDefinePwr5x | ArchDefinePwr5 |
1327 ArchDefinePwr4 | ArchDefinePpcgr |
1329 // powerpc64le automatically defaults to at least power8.
1330 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1331 ArchDefinePwr6 | ArchDefinePwr5x |
1332 ArchDefinePwr5 | ArchDefinePwr4 |
1333 ArchDefinePpcgr | ArchDefinePpcsq)
1334 .Default(ArchDefineNone);
1336 if (defs & ArchDefineName)
1337 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1338 if (defs & ArchDefinePpcgr)
1339 Builder.defineMacro("_ARCH_PPCGR");
1340 if (defs & ArchDefinePpcsq)
1341 Builder.defineMacro("_ARCH_PPCSQ");
1342 if (defs & ArchDefine440)
1343 Builder.defineMacro("_ARCH_440");
1344 if (defs & ArchDefine603)
1345 Builder.defineMacro("_ARCH_603");
1346 if (defs & ArchDefine604)
1347 Builder.defineMacro("_ARCH_604");
1348 if (defs & ArchDefinePwr4)
1349 Builder.defineMacro("_ARCH_PWR4");
1350 if (defs & ArchDefinePwr5)
1351 Builder.defineMacro("_ARCH_PWR5");
1352 if (defs & ArchDefinePwr5x)
1353 Builder.defineMacro("_ARCH_PWR5X");
1354 if (defs & ArchDefinePwr6)
1355 Builder.defineMacro("_ARCH_PWR6");
1356 if (defs & ArchDefinePwr6x)
1357 Builder.defineMacro("_ARCH_PWR6X");
1358 if (defs & ArchDefinePwr7)
1359 Builder.defineMacro("_ARCH_PWR7");
1360 if (defs & ArchDefinePwr8)
1361 Builder.defineMacro("_ARCH_PWR8");
1362 if (defs & ArchDefinePwr9)
1363 Builder.defineMacro("_ARCH_PWR9");
1364 if (defs & ArchDefineA2)
1365 Builder.defineMacro("_ARCH_A2");
1366 if (defs & ArchDefineA2q) {
1367 Builder.defineMacro("_ARCH_A2Q");
1368 Builder.defineMacro("_ARCH_QP");
1371 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1372 Builder.defineMacro("__bg__");
1373 Builder.defineMacro("__THW_BLUEGENE__");
1374 Builder.defineMacro("__bgq__");
1375 Builder.defineMacro("__TOS_BGQ__");
1379 Builder.defineMacro("__VEC__", "10206");
1380 Builder.defineMacro("__ALTIVEC__");
1383 Builder.defineMacro("__VSX__");
1385 Builder.defineMacro("__POWER8_VECTOR__");
1387 Builder.defineMacro("__CRYPTO__");
1389 Builder.defineMacro("__HTM__");
1391 Builder.defineMacro("__FLOAT128__");
1393 Builder.defineMacro("__POWER9_VECTOR__");
1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1397 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1398 if (PointerWidth == 64)
1399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1401 // We have support for the bswap intrinsics so we can define this.
1402 Builder.defineMacro("__HAVE_BSWAP__", "1");
1404 // FIXME: The following are not yet generated here by Clang, but are
1405 // generated by GCC:
1408 // __RECIP_PRECISION__
1409 // __APPLE_ALTIVEC__
1416 // __CMODEL_MEDIUM__
1423 // Handle explicit options being passed to the compiler here: if we've
1424 // explicitly turned off vsx and turned on any of:
1429 // then go ahead and error since the customer has expressed an incompatible
1431 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1432 const std::vector<std::string> &FeaturesVec) {
1434 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1435 FeaturesVec.end()) {
1436 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1437 FeaturesVec.end()) {
1438 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1443 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1444 FeaturesVec.end()) {
1445 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1450 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
1451 FeaturesVec.end()) {
1452 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
1457 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") !=
1458 FeaturesVec.end()) {
1459 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
1468 bool PPCTargetInfo::initFeatureMap(
1469 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1470 const std::vector<std::string> &FeaturesVec) const {
1471 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1482 .Case("ppc64", true)
1483 .Case("ppc64le", true)
1486 Features["qpx"] = (CPU == "a2q");
1487 Features["power9-vector"] = (CPU == "pwr9");
1488 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1489 .Case("ppc64le", true)
1493 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1494 .Case("ppc64le", true)
1498 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1499 .Case("ppc64le", true)
1504 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1505 .Case("ppc64le", true)
1510 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1511 .Case("ppc64le", true)
1515 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1516 .Case("ppc64le", true)
1521 Features["htm"] = llvm::StringSwitch<bool>(CPU)
1522 .Case("ppc64le", true)
1527 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1530 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1533 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1534 return llvm::StringSwitch<bool>(Feature)
1535 .Case("powerpc", true)
1536 .Case("altivec", HasAltivec)
1537 .Case("vsx", HasVSX)
1538 .Case("power8-vector", HasP8Vector)
1539 .Case("crypto", HasP8Crypto)
1540 .Case("direct-move", HasDirectMove)
1541 .Case("qpx", HasQPX)
1542 .Case("htm", HasHTM)
1543 .Case("bpermd", HasBPERMD)
1544 .Case("extdiv", HasExtDiv)
1545 .Case("float128", HasFloat128)
1546 .Case("power9-vector", HasP9Vector)
1550 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1551 StringRef Name, bool Enabled) const {
1553 // If we're enabling any of the vsx based features then enable vsx and
1554 // altivec. We'll diagnose any problems later.
1555 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
1557 .Case("direct-move", true)
1558 .Case("power8-vector", true)
1559 .Case("power9-vector", true)
1560 .Case("float128", true)
1563 Features["vsx"] = Features["altivec"] = true;
1564 if (Name == "power9-vector")
1565 Features["power8-vector"] = true;
1566 Features[Name] = true;
1568 // If we're disabling altivec or vsx go ahead and disable all of the vsx
1570 if ((Name == "altivec") || (Name == "vsx"))
1571 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
1572 Features["float128"] = Features["power9-vector"] = false;
1573 if (Name == "power8-vector")
1574 Features["power9-vector"] = false;
1575 Features[Name] = false;
1579 const char * const PPCTargetInfo::GCCRegNames[] = {
1580 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1581 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1582 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1583 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1584 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1585 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1586 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1587 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1588 "mq", "lr", "ctr", "ap",
1589 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1591 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1592 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1593 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1594 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1596 "spe_acc", "spefscr",
1600 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1601 return llvm::makeArrayRef(GCCRegNames);
1604 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1605 // While some of these aliases do map to different registers
1606 // they still share the same register name.
1617 { { "10" }, "r10" },
1618 { { "11" }, "r11" },
1619 { { "12" }, "r12" },
1620 { { "13" }, "r13" },
1621 { { "14" }, "r14" },
1622 { { "15" }, "r15" },
1623 { { "16" }, "r16" },
1624 { { "17" }, "r17" },
1625 { { "18" }, "r18" },
1626 { { "19" }, "r19" },
1627 { { "20" }, "r20" },
1628 { { "21" }, "r21" },
1629 { { "22" }, "r22" },
1630 { { "23" }, "r23" },
1631 { { "24" }, "r24" },
1632 { { "25" }, "r25" },
1633 { { "26" }, "r26" },
1634 { { "27" }, "r27" },
1635 { { "28" }, "r28" },
1636 { { "29" }, "r29" },
1637 { { "30" }, "r30" },
1638 { { "31" }, "r31" },
1639 { { "fr0" }, "f0" },
1640 { { "fr1" }, "f1" },
1641 { { "fr2" }, "f2" },
1642 { { "fr3" }, "f3" },
1643 { { "fr4" }, "f4" },
1644 { { "fr5" }, "f5" },
1645 { { "fr6" }, "f6" },
1646 { { "fr7" }, "f7" },
1647 { { "fr8" }, "f8" },
1648 { { "fr9" }, "f9" },
1649 { { "fr10" }, "f10" },
1650 { { "fr11" }, "f11" },
1651 { { "fr12" }, "f12" },
1652 { { "fr13" }, "f13" },
1653 { { "fr14" }, "f14" },
1654 { { "fr15" }, "f15" },
1655 { { "fr16" }, "f16" },
1656 { { "fr17" }, "f17" },
1657 { { "fr18" }, "f18" },
1658 { { "fr19" }, "f19" },
1659 { { "fr20" }, "f20" },
1660 { { "fr21" }, "f21" },
1661 { { "fr22" }, "f22" },
1662 { { "fr23" }, "f23" },
1663 { { "fr24" }, "f24" },
1664 { { "fr25" }, "f25" },
1665 { { "fr26" }, "f26" },
1666 { { "fr27" }, "f27" },
1667 { { "fr28" }, "f28" },
1668 { { "fr29" }, "f29" },
1669 { { "fr30" }, "f30" },
1670 { { "fr31" }, "f31" },
1671 { { "cc" }, "cr0" },
1674 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1675 return llvm::makeArrayRef(GCCRegAliases);
1678 class PPC32TargetInfo : public PPCTargetInfo {
1680 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1681 : PPCTargetInfo(Triple, Opts) {
1682 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
1684 switch (getTriple().getOS()) {
1685 case llvm::Triple::Linux:
1686 case llvm::Triple::FreeBSD:
1687 case llvm::Triple::NetBSD:
1688 SizeType = UnsignedInt;
1689 PtrDiffType = SignedInt;
1690 IntPtrType = SignedInt;
1696 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1697 LongDoubleWidth = LongDoubleAlign = 64;
1698 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1701 // PPC32 supports atomics up to 4 bytes.
1702 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1705 BuiltinVaListKind getBuiltinVaListKind() const override {
1706 // This is the ELF definition, and is overridden by the Darwin sub-target
1707 return TargetInfo::PowerABIBuiltinVaList;
1711 // Note: ABI differences may eventually require us to have a separate
1712 // TargetInfo for little endian.
1713 class PPC64TargetInfo : public PPCTargetInfo {
1715 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1716 : PPCTargetInfo(Triple, Opts) {
1717 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1718 IntMaxType = SignedLong;
1719 Int64Type = SignedLong;
1721 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1722 resetDataLayout("e-m:e-i64:64-n32:64");
1725 resetDataLayout("E-m:e-i64:64-n32:64");
1729 switch (getTriple().getOS()) {
1730 case llvm::Triple::FreeBSD:
1731 LongDoubleWidth = LongDoubleAlign = 64;
1732 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1734 case llvm::Triple::NetBSD:
1735 IntMaxType = SignedLongLong;
1736 Int64Type = SignedLongLong;
1742 // PPC64 supports atomics up to 8 bytes.
1743 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1745 BuiltinVaListKind getBuiltinVaListKind() const override {
1746 return TargetInfo::CharPtrBuiltinVaList;
1748 // PPC64 Linux-specific ABI options.
1749 bool setABI(const std::string &Name) override {
1750 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1758 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> {
1760 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1761 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
1762 HasAlignMac68kSupport = true;
1763 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1764 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1766 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
1768 BuiltinVaListKind getBuiltinVaListKind() const override {
1769 return TargetInfo::CharPtrBuiltinVaList;
1773 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> {
1775 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1776 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
1777 HasAlignMac68kSupport = true;
1778 resetDataLayout("E-m:o-i64:64-n32:64");
1782 static const unsigned NVPTXAddrSpaceMap[] = {
1786 4, // opencl_constant
1787 // FIXME: generic has to be added to the target
1788 0, // opencl_generic
1794 class NVPTXTargetInfo : public TargetInfo {
1795 static const char *const GCCRegNames[];
1796 static const Builtin::Info BuiltinInfo[];
1798 std::unique_ptr<TargetInfo> HostTarget;
1801 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
1802 unsigned TargetPointerWidth)
1803 : TargetInfo(Triple) {
1804 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
1805 "NVPTX only supports 32- and 64-bit modes.");
1807 TLSSupported = false;
1808 AddrSpaceMap = &NVPTXAddrSpaceMap;
1809 UseAddrSpaceMapMangling = true;
1811 // Define available target features
1812 // These must be defined in sorted order!
1813 NoAsmVariants = true;
1814 GPU = CudaArch::SM_20;
1816 if (TargetPointerWidth == 32)
1817 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64");
1819 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64");
1821 // If possible, get a TargetInfo for our host triple, so we can match its
1823 llvm::Triple HostTriple(Opts.HostTriple);
1824 if (!HostTriple.isNVPTX())
1825 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
1827 // If no host target, make some guesses about the data layout and return.
1829 LongWidth = LongAlign = TargetPointerWidth;
1830 PointerWidth = PointerAlign = TargetPointerWidth;
1831 switch (TargetPointerWidth) {
1833 SizeType = TargetInfo::UnsignedInt;
1834 PtrDiffType = TargetInfo::SignedInt;
1835 IntPtrType = TargetInfo::SignedInt;
1838 SizeType = TargetInfo::UnsignedLong;
1839 PtrDiffType = TargetInfo::SignedLong;
1840 IntPtrType = TargetInfo::SignedLong;
1843 llvm_unreachable("TargetPointerWidth must be 32 or 64");
1848 // Copy properties from host target.
1849 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
1850 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
1851 BoolWidth = HostTarget->getBoolWidth();
1852 BoolAlign = HostTarget->getBoolAlign();
1853 IntWidth = HostTarget->getIntWidth();
1854 IntAlign = HostTarget->getIntAlign();
1855 HalfWidth = HostTarget->getHalfWidth();
1856 HalfAlign = HostTarget->getHalfAlign();
1857 FloatWidth = HostTarget->getFloatWidth();
1858 FloatAlign = HostTarget->getFloatAlign();
1859 DoubleWidth = HostTarget->getDoubleWidth();
1860 DoubleAlign = HostTarget->getDoubleAlign();
1861 LongWidth = HostTarget->getLongWidth();
1862 LongAlign = HostTarget->getLongAlign();
1863 LongLongWidth = HostTarget->getLongLongWidth();
1864 LongLongAlign = HostTarget->getLongLongAlign();
1865 MinGlobalAlign = HostTarget->getMinGlobalAlign();
1866 NewAlign = HostTarget->getNewAlign();
1867 DefaultAlignForAttributeAligned =
1868 HostTarget->getDefaultAlignForAttributeAligned();
1869 SizeType = HostTarget->getSizeType();
1870 IntMaxType = HostTarget->getIntMaxType();
1871 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
1872 IntPtrType = HostTarget->getIntPtrType();
1873 WCharType = HostTarget->getWCharType();
1874 WIntType = HostTarget->getWIntType();
1875 Char16Type = HostTarget->getChar16Type();
1876 Char32Type = HostTarget->getChar32Type();
1877 Int64Type = HostTarget->getInt64Type();
1878 SigAtomicType = HostTarget->getSigAtomicType();
1879 ProcessIDType = HostTarget->getProcessIDType();
1881 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
1882 UseZeroLengthBitfieldAlignment =
1883 HostTarget->useZeroLengthBitfieldAlignment();
1884 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
1885 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
1887 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
1888 // we need those macros to be identical on host and device, because (among
1889 // other things) they affect which standard library classes are defined, and
1890 // we need all classes to be defined on both the host and device.
1891 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
1893 // Properties intentionally not copied from host:
1894 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
1895 // host/device boundary.
1896 // - SuitableAlign: Not visible across the host/device boundary, and may
1897 // correctly be different on host/device, e.g. if host has wider vector
1898 // types than device.
1899 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
1900 // as its double type, but that's not necessarily true on the host.
1901 // TODO: nvcc emits a warning when using long double on device; we should
1904 void getTargetDefines(const LangOptions &Opts,
1905 MacroBuilder &Builder) const override {
1906 Builder.defineMacro("__PTX__");
1907 Builder.defineMacro("__NVPTX__");
1908 if (Opts.CUDAIsDevice) {
1909 // Set __CUDA_ARCH__ for the GPU specified.
1910 std::string CUDAArchCode = [this] {
1912 case CudaArch::UNKNOWN:
1913 assert(false && "No GPU arch when compiling CUDA device code.");
1915 case CudaArch::SM_20:
1917 case CudaArch::SM_21:
1919 case CudaArch::SM_30:
1921 case CudaArch::SM_32:
1923 case CudaArch::SM_35:
1925 case CudaArch::SM_37:
1927 case CudaArch::SM_50:
1929 case CudaArch::SM_52:
1931 case CudaArch::SM_53:
1933 case CudaArch::SM_60:
1935 case CudaArch::SM_61:
1937 case CudaArch::SM_62:
1940 llvm_unreachable("unhandled CudaArch");
1942 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1945 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1946 return llvm::makeArrayRef(BuiltinInfo,
1947 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1950 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1952 const std::vector<std::string> &FeaturesVec) const override {
1953 Features["satom"] = GPU >= CudaArch::SM_60;
1954 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1957 bool hasFeature(StringRef Feature) const override {
1958 return llvm::StringSwitch<bool>(Feature)
1959 .Cases("ptx", "nvptx", true)
1960 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope.
1964 ArrayRef<const char *> getGCCRegNames() const override;
1965 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1969 bool validateAsmConstraint(const char *&Name,
1970 TargetInfo::ConstraintInfo &Info) const override {
1980 Info.setAllowsRegister();
1984 const char *getClobbers() const override {
1985 // FIXME: Is this really right?
1988 BuiltinVaListKind getBuiltinVaListKind() const override {
1990 return TargetInfo::CharPtrBuiltinVaList;
1992 bool setCPU(const std::string &Name) override {
1993 GPU = StringToCudaArch(Name);
1994 return GPU != CudaArch::UNKNOWN;
1996 void setSupportedOpenCLOpts() override {
1997 auto &Opts = getSupportedOpenCLOpts();
1998 Opts.support("cl_clang_storage_class_specifiers");
1999 Opts.support("cl_khr_gl_sharing");
2000 Opts.support("cl_khr_icd");
2002 Opts.support("cl_khr_fp64");
2003 Opts.support("cl_khr_byte_addressable_store");
2004 Opts.support("cl_khr_global_int32_base_atomics");
2005 Opts.support("cl_khr_global_int32_extended_atomics");
2006 Opts.support("cl_khr_local_int32_base_atomics");
2007 Opts.support("cl_khr_local_int32_extended_atomics");
2010 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2011 // CUDA compilations support all of the host's calling conventions.
2013 // TODO: We should warn if you apply a non-default CC to anything other than
2016 return HostTarget->checkCallingConvention(CC);
2017 return CCCR_Warning;
2021 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
2022 #define BUILTIN(ID, TYPE, ATTRS) \
2023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2024 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2025 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2026 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2027 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2028 #include "clang/Basic/BuiltinsNVPTX.def"
2031 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
2033 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
2034 return llvm::makeArrayRef(GCCRegNames);
2037 static const LangAS::Map AMDGPUNonOpenCLPrivateIsZeroMap = {
2041 2, // opencl_constant
2042 4, // opencl_generic
2047 static const LangAS::Map AMDGPUNonOpenCLGenericIsZeroMap = {
2051 2, // opencl_constant
2052 0, // opencl_generic
2057 static const LangAS::Map AMDGPUOpenCLPrivateIsZeroMap = {
2061 2, // opencl_constant
2062 4, // opencl_generic
2067 static const LangAS::Map AMDGPUOpenCLGenericIsZeroMap = {
2071 2, // opencl_constant
2072 0, // opencl_generic
2078 // If you edit the description strings, make sure you update
2079 // getPointerWidthV().
2081 static const char *const DataLayoutStringR600 =
2082 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2083 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2085 static const char *const DataLayoutStringSIPrivateIsZero =
2086 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
2087 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2088 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2090 static const char *const DataLayoutStringSIGenericIsZero =
2091 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
2092 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2093 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
2095 class AMDGPUTargetInfo final : public TargetInfo {
2096 static const Builtin::Info BuiltinInfo[];
2097 static const char * const GCCRegNames[];
2100 unsigned Generic, Global, Local, Constant, Private;
2101 AddrSpace(bool IsGenericZero_ = false){
2102 if (IsGenericZero_) {
2118 /// \brief The GPU profiles supported by the AMDGPU target.
2126 GK_EVERGREEN_DOUBLE_OPS,
2127 GK_NORTHERN_ISLANDS,
2140 static bool hasFullSpeedFMAF32(StringRef GPUName) {
2141 return parseAMDGCNName(GPUName) >= GK_GFX9;
2144 static bool isAMDGCN(const llvm::Triple &TT) {
2145 return TT.getArch() == llvm::Triple::amdgcn;
2148 static bool isGenericZero(const llvm::Triple &TT) {
2149 return TT.getEnvironmentName() == "amdgiz" ||
2150 TT.getEnvironmentName() == "amdgizcl";
2153 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
2154 : TargetInfo(Triple) ,
2155 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600),
2159 AS(isGenericZero(Triple)){
2160 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2165 auto IsGenericZero = isGenericZero(Triple);
2166 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
2167 (IsGenericZero ? DataLayoutStringSIGenericIsZero :
2168 DataLayoutStringSIPrivateIsZero)
2169 : DataLayoutStringR600);
2170 assert(DataLayout->getAllocaAddrSpace() == AS.Private);
2173 llvm::StringSwitch<const LangAS::Map *>(Triple.getEnvironmentName())
2174 .Case("opencl", &AMDGPUOpenCLPrivateIsZeroMap)
2175 .Case("amdgiz", &AMDGPUNonOpenCLGenericIsZeroMap)
2176 .Case("amdgizcl", &AMDGPUOpenCLGenericIsZeroMap)
2177 .Default(&AMDGPUNonOpenCLPrivateIsZeroMap);
2178 UseAddrSpaceMapMangling = true;
2181 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
2182 if (GPU <= GK_CAYMAN)
2185 if (AddrSpace == AS.Private || AddrSpace == AS.Local) {
2191 uint64_t getMaxPointerWidth() const override {
2192 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
2195 const char * getClobbers() const override {
2199 ArrayRef<const char *> getGCCRegNames() const override;
2201 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2205 bool validateAsmConstraint(const char *&Name,
2206 TargetInfo::ConstraintInfo &Info) const override {
2211 Info.setAllowsRegister();
2217 bool initFeatureMap(llvm::StringMap<bool> &Features,
2218 DiagnosticsEngine &Diags, StringRef CPU,
2219 const std::vector<std::string> &FeatureVec) const override;
2221 void adjustTargetOptions(const CodeGenOptions &CGOpts,
2222 TargetOptions &TargetOpts) const override {
2223 bool hasFP32Denormals = false;
2224 bool hasFP64Denormals = false;
2225 for (auto &I : TargetOpts.FeaturesAsWritten) {
2226 if (I == "+fp32-denormals" || I == "-fp32-denormals")
2227 hasFP32Denormals = true;
2228 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals")
2229 hasFP64Denormals = true;
2231 if (!hasFP32Denormals)
2232 TargetOpts.Features.push_back(
2233 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) &&
2234 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str());
2235 // Always do not flush fp64 or fp16 denorms.
2236 if (!hasFP64Denormals && hasFP64)
2237 TargetOpts.Features.push_back("+fp64-fp16-denormals");
2240 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2241 return llvm::makeArrayRef(BuiltinInfo,
2242 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
2245 void getTargetDefines(const LangOptions &Opts,
2246 MacroBuilder &Builder) const override {
2247 if (getTriple().getArch() == llvm::Triple::amdgcn)
2248 Builder.defineMacro("__AMDGCN__");
2250 Builder.defineMacro("__R600__");
2253 Builder.defineMacro("__HAS_FMAF__");
2255 Builder.defineMacro("__HAS_LDEXPF__");
2257 Builder.defineMacro("__HAS_FP64__");
2260 BuiltinVaListKind getBuiltinVaListKind() const override {
2261 return TargetInfo::CharPtrBuiltinVaList;
2264 static GPUKind parseR600Name(StringRef Name) {
2265 return llvm::StringSwitch<GPUKind>(Name)
2266 .Case("r600" , GK_R600)
2267 .Case("rv610", GK_R600)
2268 .Case("rv620", GK_R600)
2269 .Case("rv630", GK_R600)
2270 .Case("rv635", GK_R600)
2271 .Case("rs780", GK_R600)
2272 .Case("rs880", GK_R600)
2273 .Case("rv670", GK_R600_DOUBLE_OPS)
2274 .Case("rv710", GK_R700)
2275 .Case("rv730", GK_R700)
2276 .Case("rv740", GK_R700_DOUBLE_OPS)
2277 .Case("rv770", GK_R700_DOUBLE_OPS)
2278 .Case("palm", GK_EVERGREEN)
2279 .Case("cedar", GK_EVERGREEN)
2280 .Case("sumo", GK_EVERGREEN)
2281 .Case("sumo2", GK_EVERGREEN)
2282 .Case("redwood", GK_EVERGREEN)
2283 .Case("juniper", GK_EVERGREEN)
2284 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
2285 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
2286 .Case("barts", GK_NORTHERN_ISLANDS)
2287 .Case("turks", GK_NORTHERN_ISLANDS)
2288 .Case("caicos", GK_NORTHERN_ISLANDS)
2289 .Case("cayman", GK_CAYMAN)
2290 .Case("aruba", GK_CAYMAN)
2294 static GPUKind parseAMDGCNName(StringRef Name) {
2295 return llvm::StringSwitch<GPUKind>(Name)
2296 .Case("tahiti", GK_GFX6)
2297 .Case("pitcairn", GK_GFX6)
2298 .Case("verde", GK_GFX6)
2299 .Case("oland", GK_GFX6)
2300 .Case("hainan", GK_GFX6)
2301 .Case("bonaire", GK_GFX7)
2302 .Case("kabini", GK_GFX7)
2303 .Case("kaveri", GK_GFX7)
2304 .Case("hawaii", GK_GFX7)
2305 .Case("mullins", GK_GFX7)
2306 .Case("gfx700", GK_GFX7)
2307 .Case("gfx701", GK_GFX7)
2308 .Case("gfx702", GK_GFX7)
2309 .Case("tonga", GK_GFX8)
2310 .Case("iceland", GK_GFX8)
2311 .Case("carrizo", GK_GFX8)
2312 .Case("fiji", GK_GFX8)
2313 .Case("stoney", GK_GFX8)
2314 .Case("polaris10", GK_GFX8)
2315 .Case("polaris11", GK_GFX8)
2316 .Case("gfx800", GK_GFX8)
2317 .Case("gfx801", GK_GFX8)
2318 .Case("gfx802", GK_GFX8)
2319 .Case("gfx803", GK_GFX8)
2320 .Case("gfx804", GK_GFX8)
2321 .Case("gfx810", GK_GFX8)
2322 .Case("gfx900", GK_GFX9)
2323 .Case("gfx901", GK_GFX9)
2327 bool setCPU(const std::string &Name) override {
2328 if (getTriple().getArch() == llvm::Triple::amdgcn)
2329 GPU = parseAMDGCNName(Name);
2331 GPU = parseR600Name(Name);
2333 return GPU != GK_NONE;
2336 void setSupportedOpenCLOpts() override {
2337 auto &Opts = getSupportedOpenCLOpts();
2338 Opts.support("cl_clang_storage_class_specifiers");
2339 Opts.support("cl_khr_icd");
2342 Opts.support("cl_khr_fp64");
2343 if (GPU >= GK_EVERGREEN) {
2344 Opts.support("cl_khr_byte_addressable_store");
2345 Opts.support("cl_khr_global_int32_base_atomics");
2346 Opts.support("cl_khr_global_int32_extended_atomics");
2347 Opts.support("cl_khr_local_int32_base_atomics");
2348 Opts.support("cl_khr_local_int32_extended_atomics");
2350 if (GPU >= GK_GFX6) {
2351 Opts.support("cl_khr_fp16");
2352 Opts.support("cl_khr_int64_base_atomics");
2353 Opts.support("cl_khr_int64_extended_atomics");
2354 Opts.support("cl_khr_mipmap_image");
2355 Opts.support("cl_khr_subgroups");
2356 Opts.support("cl_khr_3d_image_writes");
2357 Opts.support("cl_amd_media_ops");
2358 Opts.support("cl_amd_media_ops2");
2362 LangAS::ID getOpenCLImageAddrSpace() const override {
2363 return LangAS::opencl_constant;
2366 /// \returns Target specific vtbl ptr address space.
2367 unsigned getVtblPtrAddressSpace() const override {
2368 // \todo: We currently have address spaces defined in AMDGPU Backend. It
2369 // would be nice if we could use it here instead of using bare numbers (same
2370 // applies to getDWARFAddressSpace).
2371 return 2; // constant.
2374 /// \returns If a target requires an address within a target specific address
2375 /// space \p AddressSpace to be converted in order to be used, then return the
2376 /// corresponding target specific DWARF address space.
2378 /// \returns Otherwise return None and no conversion will be emitted in the
2380 Optional<unsigned> getDWARFAddressSpace(
2381 unsigned AddressSpace) const override {
2382 const unsigned DWARF_Private = 1;
2383 const unsigned DWARF_Local = 2;
2384 if (AddressSpace == AS.Private) {
2385 return DWARF_Private;
2386 } else if (AddressSpace == AS.Local) {
2393 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2396 return CCCR_Warning;
2398 case CC_OpenCLKernel:
2403 // In amdgcn target the null pointer in global, constant, and generic
2404 // address space has value 0 but in private and local address space has
2406 uint64_t getNullPointerValue(unsigned AS) const override {
2407 return AS == LangAS::opencl_local ? ~0 : 0;
2411 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
2412 #define BUILTIN(ID, TYPE, ATTRS) \
2413 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2414 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2415 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2416 #include "clang/Basic/BuiltinsAMDGPU.def"
2418 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
2419 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2420 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2421 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2422 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
2423 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
2424 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
2425 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
2426 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
2427 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
2428 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
2429 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
2430 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
2431 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
2432 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
2433 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
2434 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
2435 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
2436 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
2437 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
2438 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2439 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2440 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2441 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2442 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2443 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2444 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2445 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2446 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2447 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2448 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2449 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2450 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2451 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2452 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2453 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2454 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2455 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2456 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2457 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2458 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2459 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2460 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2461 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2462 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2463 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2464 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2465 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2466 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2467 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi",
2468 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi"
2471 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2472 return llvm::makeArrayRef(GCCRegNames);
2475 bool AMDGPUTargetInfo::initFeatureMap(
2476 llvm::StringMap<bool> &Features,
2477 DiagnosticsEngine &Diags, StringRef CPU,
2478 const std::vector<std::string> &FeatureVec) const {
2480 // XXX - What does the member GPU mean if device name string passed here?
2481 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2485 switch (parseAMDGCNName(CPU)) {
2491 Features["gfx9-insts"] = true;
2494 Features["s-memrealtime"] = true;
2495 Features["16-bit-insts"] = true;
2496 Features["dpp"] = true;
2502 llvm_unreachable("unhandled subtarget");
2508 switch (parseR600Name(CPU)) {
2512 case GK_NORTHERN_ISLANDS:
2514 case GK_R600_DOUBLE_OPS:
2515 case GK_R700_DOUBLE_OPS:
2516 case GK_EVERGREEN_DOUBLE_OPS:
2518 Features["fp64"] = true;
2523 llvm_unreachable("unhandled subtarget");
2527 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
2530 const Builtin::Info BuiltinInfoX86[] = {
2531 #define BUILTIN(ID, TYPE, ATTRS) \
2532 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2533 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2534 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2535 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2536 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2537 #include "clang/Basic/BuiltinsX86.def"
2539 #define BUILTIN(ID, TYPE, ATTRS) \
2540 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2541 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2542 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2543 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2544 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2545 #include "clang/Basic/BuiltinsX86_64.def"
2549 static const char* const GCCRegNames[] = {
2550 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2551 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2552 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2553 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2554 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2555 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2556 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2557 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2558 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2559 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23",
2560 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31",
2561 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23",
2562 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31",
2563 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7",
2564 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
2565 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
2566 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
2567 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
2570 const TargetInfo::AddlRegName AddlRegNames[] = {
2571 { { "al", "ah", "eax", "rax" }, 0 },
2572 { { "bl", "bh", "ebx", "rbx" }, 3 },
2573 { { "cl", "ch", "ecx", "rcx" }, 2 },
2574 { { "dl", "dh", "edx", "rdx" }, 1 },
2575 { { "esi", "rsi" }, 4 },
2576 { { "edi", "rdi" }, 5 },
2577 { { "esp", "rsp" }, 7 },
2578 { { "ebp", "rbp" }, 6 },
2579 { { "r8d", "r8w", "r8b" }, 38 },
2580 { { "r9d", "r9w", "r9b" }, 39 },
2581 { { "r10d", "r10w", "r10b" }, 40 },
2582 { { "r11d", "r11w", "r11b" }, 41 },
2583 { { "r12d", "r12w", "r12b" }, 42 },
2584 { { "r13d", "r13w", "r13b" }, 43 },
2585 { { "r14d", "r14w", "r14b" }, 44 },
2586 { { "r15d", "r15w", "r15b" }, 45 },
2589 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2590 // most of the implementation can be shared.
2591 class X86TargetInfo : public TargetInfo {
2593 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2596 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2597 } MMX3DNowLevel = NoMMX3DNow;
2605 bool HasAES = false;
2606 bool HasPCLMUL = false;
2607 bool HasLZCNT = false;
2608 bool HasRDRND = false;
2609 bool HasFSGSBASE = false;
2610 bool HasBMI = false;
2611 bool HasBMI2 = false;
2612 bool HasPOPCNT = false;
2613 bool HasRTM = false;
2614 bool HasPRFCHW = false;
2615 bool HasRDSEED = false;
2616 bool HasADX = false;
2617 bool HasTBM = false;
2618 bool HasLWP = false;
2619 bool HasFMA = false;
2620 bool HasF16C = false;
2621 bool HasAVX512CD = false;
2622 bool HasAVX512ER = false;
2623 bool HasAVX512PF = false;
2624 bool HasAVX512DQ = false;
2625 bool HasAVX512BW = false;
2626 bool HasAVX512VL = false;
2627 bool HasAVX512VBMI = false;
2628 bool HasAVX512IFMA = false;
2629 bool HasSHA = false;
2630 bool HasMPX = false;
2631 bool HasSGX = false;
2632 bool HasCX16 = false;
2633 bool HasFXSR = false;
2634 bool HasXSAVE = false;
2635 bool HasXSAVEOPT = false;
2636 bool HasXSAVEC = false;
2637 bool HasXSAVES = false;
2638 bool HasMWAITX = false;
2639 bool HasCLZERO = false;
2640 bool HasPKU = false;
2641 bool HasCLFLUSHOPT = false;
2642 bool HasCLWB = false;
2643 bool HasMOVBE = false;
2644 bool HasPREFETCHWT1 = false;
2646 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2648 /// Each enumeration represents a particular CPU supported by Clang. These
2649 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2654 /// i386-generation processors.
2660 /// i486-generation processors.
2669 /// i586-generation processors, P5 microarchitecture based.
2677 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2687 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2688 /// Clang however has some logic to suport this.
2689 // FIXME: Warn, deprecate, and potentially remove this.
2694 /// Netburst microarchitecture based processors.
2703 /// Core microarchitecture based processors.
2707 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2708 /// codename which GCC no longer accepts as an option to -march, but Clang
2709 /// has some logic for recognizing it.
2710 // FIXME: Warn, deprecate, and potentially remove this.
2722 /// Nehalem microarchitecture based processors.
2726 /// Westmere microarchitecture based processors.
2729 /// \name Sandy Bridge
2730 /// Sandy Bridge microarchitecture based processors.
2733 /// \name Ivy Bridge
2734 /// Ivy Bridge microarchitecture based processors.
2738 /// Haswell microarchitecture based processors.
2742 /// Broadwell microarchitecture based processors.
2745 /// \name Skylake Client
2746 /// Skylake client microarchitecture based processors.
2749 /// \name Skylake Server
2750 /// Skylake server microarchitecture based processors.
2753 /// \name Cannonlake Client
2754 /// Cannonlake client microarchitecture based processors.
2757 /// \name Knights Landing
2758 /// Knights Landing processor.
2762 /// Lakemont microarchitecture based processors.
2766 /// K6 architecture processors.
2774 /// K7 architecture processors.
2777 CK_AthlonThunderbird,
2784 /// K8 architecture processors.
2797 /// Bobcat architecture processors.
2804 /// Bulldozer architecture processors.
2813 /// Zen architecture processors.
2818 /// This specification is deprecated and will be removed in the future.
2819 /// Users should prefer \see CK_K8.
2820 // FIXME: Warn on this when the CPU is set to it.
2826 /// Geode processors.
2832 CPUKind getCPUKind(StringRef CPU) const {
2833 return llvm::StringSwitch<CPUKind>(CPU)
2834 .Case("i386", CK_i386)
2835 .Case("i486", CK_i486)
2836 .Case("winchip-c6", CK_WinChipC6)
2837 .Case("winchip2", CK_WinChip2)
2839 .Case("i586", CK_i586)
2840 .Case("pentium", CK_Pentium)
2841 .Case("pentium-mmx", CK_PentiumMMX)
2842 .Case("i686", CK_i686)
2843 .Case("pentiumpro", CK_PentiumPro)
2844 .Case("pentium2", CK_Pentium2)
2845 .Case("pentium3", CK_Pentium3)
2846 .Case("pentium3m", CK_Pentium3M)
2847 .Case("pentium-m", CK_PentiumM)
2848 .Case("c3-2", CK_C3_2)
2849 .Case("yonah", CK_Yonah)
2850 .Case("pentium4", CK_Pentium4)
2851 .Case("pentium4m", CK_Pentium4M)
2852 .Case("prescott", CK_Prescott)
2853 .Case("nocona", CK_Nocona)
2854 .Case("core2", CK_Core2)
2855 .Case("penryn", CK_Penryn)
2856 .Case("bonnell", CK_Bonnell)
2857 .Case("atom", CK_Bonnell) // Legacy name.
2858 .Case("silvermont", CK_Silvermont)
2859 .Case("slm", CK_Silvermont) // Legacy name.
2860 .Case("nehalem", CK_Nehalem)
2861 .Case("corei7", CK_Nehalem) // Legacy name.
2862 .Case("westmere", CK_Westmere)
2863 .Case("sandybridge", CK_SandyBridge)
2864 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2865 .Case("ivybridge", CK_IvyBridge)
2866 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2867 .Case("haswell", CK_Haswell)
2868 .Case("core-avx2", CK_Haswell) // Legacy name.
2869 .Case("broadwell", CK_Broadwell)
2870 .Case("skylake", CK_SkylakeClient)
2871 .Case("skylake-avx512", CK_SkylakeServer)
2872 .Case("skx", CK_SkylakeServer) // Legacy name.
2873 .Case("cannonlake", CK_Cannonlake)
2874 .Case("knl", CK_KNL)
2875 .Case("lakemont", CK_Lakemont)
2877 .Case("k6-2", CK_K6_2)
2878 .Case("k6-3", CK_K6_3)
2879 .Case("athlon", CK_Athlon)
2880 .Case("athlon-tbird", CK_AthlonThunderbird)
2881 .Case("athlon-4", CK_Athlon4)
2882 .Case("athlon-xp", CK_AthlonXP)
2883 .Case("athlon-mp", CK_AthlonMP)
2884 .Case("athlon64", CK_Athlon64)
2885 .Case("athlon64-sse3", CK_Athlon64SSE3)
2886 .Case("athlon-fx", CK_AthlonFX)
2888 .Case("k8-sse3", CK_K8SSE3)
2889 .Case("opteron", CK_Opteron)
2890 .Case("opteron-sse3", CK_OpteronSSE3)
2891 .Case("barcelona", CK_AMDFAM10)
2892 .Case("amdfam10", CK_AMDFAM10)
2893 .Case("btver1", CK_BTVER1)
2894 .Case("btver2", CK_BTVER2)
2895 .Case("bdver1", CK_BDVER1)
2896 .Case("bdver2", CK_BDVER2)
2897 .Case("bdver3", CK_BDVER3)
2898 .Case("bdver4", CK_BDVER4)
2899 .Case("znver1", CK_ZNVER1)
2900 .Case("x86-64", CK_x86_64)
2901 .Case("geode", CK_Geode)
2902 .Default(CK_Generic);
2909 } FPMath = FP_Default;
2912 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
2913 : TargetInfo(Triple) {
2914 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
2916 unsigned getFloatEvalMethod() const override {
2917 // X87 evaluates with 80 bits "long double" precision.
2918 return SSELevel == NoSSE ? 2 : 0;
2920 ArrayRef<const char *> getGCCRegNames() const override {
2921 return llvm::makeArrayRef(GCCRegNames);
2923 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2926 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2927 return llvm::makeArrayRef(AddlRegNames);
2929 bool validateCpuSupports(StringRef Name) const override;
2930 bool validateAsmConstraint(const char *&Name,
2931 TargetInfo::ConstraintInfo &info) const override;
2933 bool validateGlobalRegisterVariable(StringRef RegName,
2935 bool &HasSizeMismatch) const override {
2936 // esp and ebp are the only 32-bit registers the x86 backend can currently
2938 if (RegName.equals("esp") || RegName.equals("ebp")) {
2939 // Check that the register size is 32-bit.
2940 HasSizeMismatch = RegSize != 32;
2947 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2949 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2951 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2953 std::string convertConstraint(const char *&Constraint) const override;
2954 const char *getClobbers() const override {
2955 return "~{dirflag},~{fpsr},~{flags}";
2958 StringRef getConstraintRegister(const StringRef &Constraint,
2959 const StringRef &Expression) const override {
2960 StringRef::iterator I, E;
2961 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
2968 // For the register constraints, return the matching register name
2981 // In case the constraint is 'r' we need to return Expression
2985 // Default value if there is no constraint for the register
2991 void getTargetDefines(const LangOptions &Opts,
2992 MacroBuilder &Builder) const override;
2993 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2995 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2997 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2999 void setFeatureEnabled(llvm::StringMap<bool> &Features,
3000 StringRef Name, bool Enabled) const override {
3001 setFeatureEnabledImpl(Features, Name, Enabled);
3003 // This exists purely to cut down on the number of virtual calls in
3004 // initFeatureMap which calls this repeatedly.
3005 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3006 StringRef Name, bool Enabled);
3008 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
3010 const std::vector<std::string> &FeaturesVec) const override;
3011 bool hasFeature(StringRef Feature) const override;
3012 bool handleTargetFeatures(std::vector<std::string> &Features,
3013 DiagnosticsEngine &Diags) override;
3014 StringRef getABI() const override {
3015 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
3017 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
3019 if (getTriple().getArch() == llvm::Triple::x86 &&
3020 MMX3DNowLevel == NoMMX3DNow)
3024 bool setCPU(const std::string &Name) override {
3025 CPU = getCPUKind(Name);
3027 // Perform any per-CPU checks necessary to determine if this CPU is
3029 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
3030 // invalid without explaining *why*.
3033 // No processor selected!
3060 case CK_AthlonThunderbird:
3065 // Only accept certain architectures when compiling in 32-bit mode.
3066 if (getTriple().getArch() != llvm::Triple::x86)
3077 case CK_SandyBridge:
3081 case CK_SkylakeClient:
3082 case CK_SkylakeServer:
3086 case CK_Athlon64SSE3:
3091 case CK_OpteronSSE3:
3103 llvm_unreachable("Unhandled CPU kind");
3106 bool setFPMath(StringRef Name) override;
3108 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3109 // Most of the non-ARM calling conventions are i386 conventions.
3111 case CC_X86ThisCall:
3112 case CC_X86FastCall:
3114 case CC_X86VectorCall:
3119 case CC_IntelOclBicc:
3122 return CCCR_Warning;
3126 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3127 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
3130 bool hasSjLjLowering() const override {
3134 void setSupportedOpenCLOpts() override {
3135 getSupportedOpenCLOpts().supportAll();
3139 bool X86TargetInfo::setFPMath(StringRef Name) {
3140 if (Name == "387") {
3144 if (Name == "sse") {
3151 bool X86TargetInfo::initFeatureMap(
3152 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
3153 const std::vector<std::string> &FeaturesVec) const {
3154 // FIXME: This *really* should not be here.
3155 // X86_64 always has SSE2.
3156 if (getTriple().getArch() == llvm::Triple::x86_64)
3157 setFeatureEnabledImpl(Features, "sse2", true);
3159 const CPUKind Kind = getCPUKind(CPU);
3161 // Enable X87 for all X86 processors but Lakemont.
3162 if (Kind != CK_Lakemont)
3163 setFeatureEnabledImpl(Features, "x87", true);
3179 setFeatureEnabledImpl(Features, "mmx", true);
3184 setFeatureEnabledImpl(Features, "sse", true);
3185 setFeatureEnabledImpl(Features, "fxsr", true);
3191 setFeatureEnabledImpl(Features, "sse2", true);
3192 setFeatureEnabledImpl(Features, "fxsr", true);
3197 setFeatureEnabledImpl(Features, "sse3", true);
3198 setFeatureEnabledImpl(Features, "fxsr", true);
3199 setFeatureEnabledImpl(Features, "cx16", true);
3203 setFeatureEnabledImpl(Features, "ssse3", true);
3204 setFeatureEnabledImpl(Features, "fxsr", true);
3205 setFeatureEnabledImpl(Features, "cx16", true);
3208 setFeatureEnabledImpl(Features, "sse4.1", true);
3209 setFeatureEnabledImpl(Features, "fxsr", true);
3210 setFeatureEnabledImpl(Features, "cx16", true);
3213 setFeatureEnabledImpl(Features, "avx512ifma", true);
3214 setFeatureEnabledImpl(Features, "avx512vbmi", true);
3215 setFeatureEnabledImpl(Features, "sha", true);
3217 case CK_SkylakeServer:
3218 setFeatureEnabledImpl(Features, "avx512f", true);
3219 setFeatureEnabledImpl(Features, "avx512cd", true);
3220 setFeatureEnabledImpl(Features, "avx512dq", true);
3221 setFeatureEnabledImpl(Features, "avx512bw", true);
3222 setFeatureEnabledImpl(Features, "avx512vl", true);
3223 setFeatureEnabledImpl(Features, "pku", true);
3224 setFeatureEnabledImpl(Features, "clwb", true);
3226 case CK_SkylakeClient:
3227 setFeatureEnabledImpl(Features, "xsavec", true);
3228 setFeatureEnabledImpl(Features, "xsaves", true);
3229 setFeatureEnabledImpl(Features, "mpx", true);
3230 setFeatureEnabledImpl(Features, "sgx", true);
3231 setFeatureEnabledImpl(Features, "clflushopt", true);
3232 setFeatureEnabledImpl(Features, "rtm", true);
3235 setFeatureEnabledImpl(Features, "rdseed", true);
3236 setFeatureEnabledImpl(Features, "adx", true);
3239 setFeatureEnabledImpl(Features, "avx2", true);
3240 setFeatureEnabledImpl(Features, "lzcnt", true);
3241 setFeatureEnabledImpl(Features, "bmi", true);
3242 setFeatureEnabledImpl(Features, "bmi2", true);
3243 setFeatureEnabledImpl(Features, "fma", true);
3244 setFeatureEnabledImpl(Features, "movbe", true);
3247 setFeatureEnabledImpl(Features, "rdrnd", true);
3248 setFeatureEnabledImpl(Features, "f16c", true);
3249 setFeatureEnabledImpl(Features, "fsgsbase", true);
3251 case CK_SandyBridge:
3252 setFeatureEnabledImpl(Features, "avx", true);
3253 setFeatureEnabledImpl(Features, "xsave", true);
3254 setFeatureEnabledImpl(Features, "xsaveopt", true);
3258 setFeatureEnabledImpl(Features, "aes", true);
3259 setFeatureEnabledImpl(Features, "pclmul", true);
3262 setFeatureEnabledImpl(Features, "sse4.2", true);
3263 setFeatureEnabledImpl(Features, "fxsr", true);
3264 setFeatureEnabledImpl(Features, "cx16", true);
3267 setFeatureEnabledImpl(Features, "avx512f", true);
3268 setFeatureEnabledImpl(Features, "avx512cd", true);
3269 setFeatureEnabledImpl(Features, "avx512er", true);
3270 setFeatureEnabledImpl(Features, "avx512pf", true);
3271 setFeatureEnabledImpl(Features, "prefetchwt1", true);
3272 setFeatureEnabledImpl(Features, "fxsr", true);
3273 setFeatureEnabledImpl(Features, "rdseed", true);
3274 setFeatureEnabledImpl(Features, "adx", true);
3275 setFeatureEnabledImpl(Features, "lzcnt", true);
3276 setFeatureEnabledImpl(Features, "bmi", true);
3277 setFeatureEnabledImpl(Features, "bmi2", true);
3278 setFeatureEnabledImpl(Features, "rtm", true);
3279 setFeatureEnabledImpl(Features, "fma", true);
3280 setFeatureEnabledImpl(Features, "rdrnd", true);
3281 setFeatureEnabledImpl(Features, "f16c", true);
3282 setFeatureEnabledImpl(Features, "fsgsbase", true);
3283 setFeatureEnabledImpl(Features, "aes", true);
3284 setFeatureEnabledImpl(Features, "pclmul", true);
3285 setFeatureEnabledImpl(Features, "cx16", true);
3286 setFeatureEnabledImpl(Features, "xsaveopt", true);
3287 setFeatureEnabledImpl(Features, "xsave", true);
3288 setFeatureEnabledImpl(Features, "movbe", true);
3294 setFeatureEnabledImpl(Features, "3dnow", true);
3297 case CK_AthlonThunderbird:
3299 setFeatureEnabledImpl(Features, "3dnowa", true);
3304 setFeatureEnabledImpl(Features, "sse", true);
3305 setFeatureEnabledImpl(Features, "3dnowa", true);
3306 setFeatureEnabledImpl(Features, "fxsr", true);
3312 setFeatureEnabledImpl(Features, "sse2", true);
3313 setFeatureEnabledImpl(Features, "3dnowa", true);
3314 setFeatureEnabledImpl(Features, "fxsr", true);
3317 setFeatureEnabledImpl(Features, "sse4a", true);
3318 setFeatureEnabledImpl(Features, "lzcnt", true);
3319 setFeatureEnabledImpl(Features, "popcnt", true);
3322 case CK_OpteronSSE3:
3323 case CK_Athlon64SSE3:
3324 setFeatureEnabledImpl(Features, "sse3", true);
3325 setFeatureEnabledImpl(Features, "3dnowa", true);
3326 setFeatureEnabledImpl(Features, "fxsr", true);
3329 setFeatureEnabledImpl(Features, "avx", true);
3330 setFeatureEnabledImpl(Features, "aes", true);
3331 setFeatureEnabledImpl(Features, "pclmul", true);
3332 setFeatureEnabledImpl(Features, "bmi", true);
3333 setFeatureEnabledImpl(Features, "f16c", true);
3334 setFeatureEnabledImpl(Features, "xsaveopt", true);
3337 setFeatureEnabledImpl(Features, "ssse3", true);
3338 setFeatureEnabledImpl(Features, "sse4a", true);
3339 setFeatureEnabledImpl(Features, "lzcnt", true);
3340 setFeatureEnabledImpl(Features, "popcnt", true);
3341 setFeatureEnabledImpl(Features, "prfchw", true);
3342 setFeatureEnabledImpl(Features, "cx16", true);
3343 setFeatureEnabledImpl(Features, "fxsr", true);
3346 setFeatureEnabledImpl(Features, "adx", true);
3347 setFeatureEnabledImpl(Features, "aes", true);
3348 setFeatureEnabledImpl(Features, "avx2", true);
3349 setFeatureEnabledImpl(Features, "bmi", true);
3350 setFeatureEnabledImpl(Features, "bmi2", true);
3351 setFeatureEnabledImpl(Features, "clflushopt", true);
3352 setFeatureEnabledImpl(Features, "clzero", true);
3353 setFeatureEnabledImpl(Features, "cx16", true);
3354 setFeatureEnabledImpl(Features, "f16c", true);
3355 setFeatureEnabledImpl(Features, "fma", true);
3356 setFeatureEnabledImpl(Features, "fsgsbase", true);
3357 setFeatureEnabledImpl(Features, "fxsr", true);
3358 setFeatureEnabledImpl(Features, "lzcnt", true);
3359 setFeatureEnabledImpl(Features, "mwaitx", true);
3360 setFeatureEnabledImpl(Features, "movbe", true);
3361 setFeatureEnabledImpl(Features, "pclmul", true);
3362 setFeatureEnabledImpl(Features, "popcnt", true);
3363 setFeatureEnabledImpl(Features, "prfchw", true);
3364 setFeatureEnabledImpl(Features, "rdrnd", true);
3365 setFeatureEnabledImpl(Features, "rdseed", true);
3366 setFeatureEnabledImpl(Features, "sha", true);
3367 setFeatureEnabledImpl(Features, "sse4a", true);
3368 setFeatureEnabledImpl(Features, "xsave", true);
3369 setFeatureEnabledImpl(Features, "xsavec", true);
3370 setFeatureEnabledImpl(Features, "xsaveopt", true);
3371 setFeatureEnabledImpl(Features, "xsaves", true);
3374 setFeatureEnabledImpl(Features, "avx2", true);
3375 setFeatureEnabledImpl(Features, "bmi2", true);
3376 setFeatureEnabledImpl(Features, "mwaitx", true);
3379 setFeatureEnabledImpl(Features, "fsgsbase", true);
3380 setFeatureEnabledImpl(Features, "xsaveopt", true);
3383 setFeatureEnabledImpl(Features, "bmi", true);
3384 setFeatureEnabledImpl(Features, "fma", true);
3385 setFeatureEnabledImpl(Features, "f16c", true);
3386 setFeatureEnabledImpl(Features, "tbm", true);
3389 // xop implies avx, sse4a and fma4.
3390 setFeatureEnabledImpl(Features, "xop", true);
3391 setFeatureEnabledImpl(Features, "lwp", true);
3392 setFeatureEnabledImpl(Features, "lzcnt", true);
3393 setFeatureEnabledImpl(Features, "aes", true);
3394 setFeatureEnabledImpl(Features, "pclmul", true);
3395 setFeatureEnabledImpl(Features, "prfchw", true);
3396 setFeatureEnabledImpl(Features, "cx16", true);
3397 setFeatureEnabledImpl(Features, "fxsr", true);
3398 setFeatureEnabledImpl(Features, "xsave", true);
3401 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
3404 // Can't do this earlier because we need to be able to explicitly enable
3405 // or disable these features and the things that they depend upon.
3407 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3408 auto I = Features.find("sse4.2");
3409 if (I != Features.end() && I->getValue() &&
3410 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
3412 Features["popcnt"] = true;
3414 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3415 I = Features.find("3dnow");
3416 if (I != Features.end() && I->getValue() &&
3417 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
3419 Features["prfchw"] = true;
3421 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3423 I = Features.find("sse");
3424 if (I != Features.end() && I->getValue() &&
3425 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
3427 Features["mmx"] = true;
3432 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
3433 X86SSEEnum Level, bool Enabled) {
3437 Features["avx512f"] = true;
3439 Features["avx2"] = true;
3441 Features["avx"] = true;
3442 Features["xsave"] = true;
3444 Features["sse4.2"] = true;
3446 Features["sse4.1"] = true;
3448 Features["ssse3"] = true;
3450 Features["sse3"] = true;
3452 Features["sse2"] = true;
3454 Features["sse"] = true;
3464 Features["sse"] = false;
3466 Features["sse2"] = Features["pclmul"] = Features["aes"] =
3467 Features["sha"] = false;
3469 Features["sse3"] = false;
3470 setXOPLevel(Features, NoXOP, false);
3472 Features["ssse3"] = false;
3474 Features["sse4.1"] = false;
3476 Features["sse4.2"] = false;
3478 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
3479 Features["xsaveopt"] = false;
3480 setXOPLevel(Features, FMA4, false);
3482 Features["avx2"] = false;
3484 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
3485 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
3486 Features["avx512vl"] = Features["avx512vbmi"] =
3487 Features["avx512ifma"] = false;
3491 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
3492 MMX3DNowEnum Level, bool Enabled) {
3495 case AMD3DNowAthlon:
3496 Features["3dnowa"] = true;
3498 Features["3dnow"] = true;
3500 Features["mmx"] = true;
3510 Features["mmx"] = false;
3512 Features["3dnow"] = false;
3513 case AMD3DNowAthlon:
3514 Features["3dnowa"] = false;
3518 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3523 Features["xop"] = true;
3525 Features["fma4"] = true;
3526 setSSELevel(Features, AVX, true);
3528 Features["sse4a"] = true;
3529 setSSELevel(Features, SSE3, true);
3539 Features["sse4a"] = false;
3541 Features["fma4"] = false;
3543 Features["xop"] = false;
3547 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3548 StringRef Name, bool Enabled) {
3549 // This is a bit of a hack to deal with the sse4 target feature when used
3550 // as part of the target attribute. We handle sse4 correctly everywhere
3551 // else. See below for more information on how we handle the sse4 options.
3553 Features[Name] = Enabled;
3555 if (Name == "mmx") {
3556 setMMXLevel(Features, MMX, Enabled);
3557 } else if (Name == "sse") {
3558 setSSELevel(Features, SSE1, Enabled);
3559 } else if (Name == "sse2") {
3560 setSSELevel(Features, SSE2, Enabled);
3561 } else if (Name == "sse3") {
3562 setSSELevel(Features, SSE3, Enabled);
3563 } else if (Name == "ssse3") {
3564 setSSELevel(Features, SSSE3, Enabled);
3565 } else if (Name == "sse4.2") {
3566 setSSELevel(Features, SSE42, Enabled);
3567 } else if (Name == "sse4.1") {
3568 setSSELevel(Features, SSE41, Enabled);
3569 } else if (Name == "3dnow") {
3570 setMMXLevel(Features, AMD3DNow, Enabled);
3571 } else if (Name == "3dnowa") {
3572 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
3573 } else if (Name == "aes") {
3575 setSSELevel(Features, SSE2, Enabled);
3576 } else if (Name == "pclmul") {
3578 setSSELevel(Features, SSE2, Enabled);
3579 } else if (Name == "avx") {
3580 setSSELevel(Features, AVX, Enabled);
3581 } else if (Name == "avx2") {
3582 setSSELevel(Features, AVX2, Enabled);
3583 } else if (Name == "avx512f") {
3584 setSSELevel(Features, AVX512F, Enabled);
3585 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
3586 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
3587 Name == "avx512vbmi" || Name == "avx512ifma") {
3589 setSSELevel(Features, AVX512F, Enabled);
3590 // Enable BWI instruction if VBMI is being enabled.
3591 if (Name == "avx512vbmi" && Enabled)
3592 Features["avx512bw"] = true;
3593 // Also disable VBMI if BWI is being disabled.
3594 if (Name == "avx512bw" && !Enabled)
3595 Features["avx512vbmi"] = false;
3596 } else if (Name == "fma") {
3598 setSSELevel(Features, AVX, Enabled);
3599 } else if (Name == "fma4") {
3600 setXOPLevel(Features, FMA4, Enabled);
3601 } else if (Name == "xop") {
3602 setXOPLevel(Features, XOP, Enabled);
3603 } else if (Name == "sse4a") {
3604 setXOPLevel(Features, SSE4A, Enabled);
3605 } else if (Name == "f16c") {
3607 setSSELevel(Features, AVX, Enabled);
3608 } else if (Name == "sha") {
3610 setSSELevel(Features, SSE2, Enabled);
3611 } else if (Name == "sse4") {
3612 // We can get here via the __target__ attribute since that's not controlled
3613 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
3614 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
3617 setSSELevel(Features, SSE42, Enabled);
3619 setSSELevel(Features, SSE41, Enabled);
3620 } else if (Name == "xsave") {
3622 Features["xsaveopt"] = false;
3623 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
3625 Features["xsave"] = true;
3629 /// handleTargetFeatures - Perform initialization based on the user
3630 /// configured set of features.
3631 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
3632 DiagnosticsEngine &Diags) {
3633 for (const auto &Feature : Features) {
3634 if (Feature[0] != '+')
3637 if (Feature == "+aes") {
3639 } else if (Feature == "+pclmul") {
3641 } else if (Feature == "+lzcnt") {
3643 } else if (Feature == "+rdrnd") {
3645 } else if (Feature == "+fsgsbase") {
3647 } else if (Feature == "+bmi") {
3649 } else if (Feature == "+bmi2") {
3651 } else if (Feature == "+popcnt") {
3653 } else if (Feature == "+rtm") {
3655 } else if (Feature == "+prfchw") {
3657 } else if (Feature == "+rdseed") {
3659 } else if (Feature == "+adx") {
3661 } else if (Feature == "+tbm") {
3663 } else if (Feature == "+lwp") {
3665 } else if (Feature == "+fma") {
3667 } else if (Feature == "+f16c") {
3669 } else if (Feature == "+avx512cd") {
3671 } else if (Feature == "+avx512er") {
3673 } else if (Feature == "+avx512pf") {
3675 } else if (Feature == "+avx512dq") {
3677 } else if (Feature == "+avx512bw") {
3679 } else if (Feature == "+avx512vl") {
3681 } else if (Feature == "+avx512vbmi") {
3682 HasAVX512VBMI = true;
3683 } else if (Feature == "+avx512ifma") {
3684 HasAVX512IFMA = true;
3685 } else if (Feature == "+sha") {
3687 } else if (Feature == "+mpx") {
3689 } else if (Feature == "+movbe") {
3691 } else if (Feature == "+sgx") {
3693 } else if (Feature == "+cx16") {
3695 } else if (Feature == "+fxsr") {
3697 } else if (Feature == "+xsave") {
3699 } else if (Feature == "+xsaveopt") {
3701 } else if (Feature == "+xsavec") {
3703 } else if (Feature == "+xsaves") {
3705 } else if (Feature == "+mwaitx") {
3707 } else if (Feature == "+pku") {
3709 } else if (Feature == "+clflushopt") {
3710 HasCLFLUSHOPT = true;
3711 } else if (Feature == "+clwb") {
3713 } else if (Feature == "+prefetchwt1") {
3714 HasPREFETCHWT1 = true;
3715 } else if (Feature == "+clzero") {
3719 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3720 .Case("+avx512f", AVX512F)
3721 .Case("+avx2", AVX2)
3723 .Case("+sse4.2", SSE42)
3724 .Case("+sse4.1", SSE41)
3725 .Case("+ssse3", SSSE3)
3726 .Case("+sse3", SSE3)
3727 .Case("+sse2", SSE2)
3730 SSELevel = std::max(SSELevel, Level);
3732 MMX3DNowEnum ThreeDNowLevel =
3733 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3734 .Case("+3dnowa", AMD3DNowAthlon)
3735 .Case("+3dnow", AMD3DNow)
3737 .Default(NoMMX3DNow);
3738 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3740 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3742 .Case("+fma4", FMA4)
3743 .Case("+sse4a", SSE4A)
3745 XOPLevel = std::max(XOPLevel, XLevel);
3748 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3749 // matches the selected sse level.
3750 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3751 (FPMath == FP_387 && SSELevel >= SSE1)) {
3752 Diags.Report(diag::err_target_unsupported_fpmath) <<
3753 (FPMath == FP_SSE ? "sse" : "387");
3758 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3762 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3763 /// definitions for this particular subtarget.
3764 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3765 MacroBuilder &Builder) const {
3766 // Target identification.
3767 if (getTriple().getArch() == llvm::Triple::x86_64) {
3768 Builder.defineMacro("__amd64__");
3769 Builder.defineMacro("__amd64");
3770 Builder.defineMacro("__x86_64");
3771 Builder.defineMacro("__x86_64__");
3772 if (getTriple().getArchName() == "x86_64h") {
3773 Builder.defineMacro("__x86_64h");
3774 Builder.defineMacro("__x86_64h__");
3777 DefineStd(Builder, "i386", Opts);
3780 // Subtarget options.
3781 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3782 // truly should be based on -mtune options.
3787 // The rest are coming from the i386 define above.
3788 Builder.defineMacro("__tune_i386__");
3794 defineCPUMacros(Builder, "i486");
3797 Builder.defineMacro("__pentium_mmx__");
3798 Builder.defineMacro("__tune_pentium_mmx__");
3802 defineCPUMacros(Builder, "i586");
3803 defineCPUMacros(Builder, "pentium");
3808 Builder.defineMacro("__tune_pentium3__");
3812 Builder.defineMacro("__tune_pentium2__");
3815 Builder.defineMacro("__tune_i686__");
3816 Builder.defineMacro("__tune_pentiumpro__");
3819 Builder.defineMacro("__i686");
3820 Builder.defineMacro("__i686__");
3821 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3822 Builder.defineMacro("__pentiumpro");
3823 Builder.defineMacro("__pentiumpro__");
3827 defineCPUMacros(Builder, "pentium4");
3832 defineCPUMacros(Builder, "nocona");
3836 defineCPUMacros(Builder, "core2");
3839 defineCPUMacros(Builder, "atom");
3842 defineCPUMacros(Builder, "slm");
3846 case CK_SandyBridge:
3850 case CK_SkylakeClient:
3851 // FIXME: Historically, we defined this legacy name, it would be nice to
3852 // remove it at some point. We've never exposed fine-grained names for
3853 // recent primary x86 CPUs, and we should keep it that way.
3854 defineCPUMacros(Builder, "corei7");
3856 case CK_SkylakeServer:
3857 defineCPUMacros(Builder, "skx");
3862 defineCPUMacros(Builder, "knl");
3865 Builder.defineMacro("__tune_lakemont__");
3868 Builder.defineMacro("__k6_2__");
3869 Builder.defineMacro("__tune_k6_2__");
3872 if (CPU != CK_K6_2) { // In case of fallthrough
3873 // FIXME: GCC may be enabling these in cases where some other k6
3874 // architecture is specified but -m3dnow is explicitly provided. The
3875 // exact semantics need to be determined and emulated here.
3876 Builder.defineMacro("__k6_3__");
3877 Builder.defineMacro("__tune_k6_3__");
3881 defineCPUMacros(Builder, "k6");
3884 case CK_AthlonThunderbird:
3888 defineCPUMacros(Builder, "athlon");
3889 if (SSELevel != NoSSE) {
3890 Builder.defineMacro("__athlon_sse__");
3891 Builder.defineMacro("__tune_athlon_sse__");
3898 case CK_OpteronSSE3:
3900 case CK_Athlon64SSE3:
3902 defineCPUMacros(Builder, "k8");
3905 defineCPUMacros(Builder, "amdfam10");
3908 defineCPUMacros(Builder, "btver1");
3911 defineCPUMacros(Builder, "btver2");
3914 defineCPUMacros(Builder, "bdver1");
3917 defineCPUMacros(Builder, "bdver2");
3920 defineCPUMacros(Builder, "bdver3");
3923 defineCPUMacros(Builder, "bdver4");
3926 defineCPUMacros(Builder, "znver1");
3929 defineCPUMacros(Builder, "geode");
3933 // Target properties.
3934 Builder.defineMacro("__REGISTER_PREFIX__", "");
3936 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3937 // functions in glibc header files that use FP Stack inline asm which the
3938 // backend can't deal with (PR879).
3939 Builder.defineMacro("__NO_MATH_INLINES");
3942 Builder.defineMacro("__AES__");
3945 Builder.defineMacro("__PCLMUL__");
3948 Builder.defineMacro("__LZCNT__");
3951 Builder.defineMacro("__RDRND__");
3954 Builder.defineMacro("__FSGSBASE__");
3957 Builder.defineMacro("__BMI__");
3960 Builder.defineMacro("__BMI2__");
3963 Builder.defineMacro("__POPCNT__");
3966 Builder.defineMacro("__RTM__");
3969 Builder.defineMacro("__PRFCHW__");
3972 Builder.defineMacro("__RDSEED__");
3975 Builder.defineMacro("__ADX__");
3978 Builder.defineMacro("__TBM__");
3981 Builder.defineMacro("__LWP__");
3984 Builder.defineMacro("__MWAITX__");
3988 Builder.defineMacro("__XOP__");
3990 Builder.defineMacro("__FMA4__");
3992 Builder.defineMacro("__SSE4A__");
3998 Builder.defineMacro("__FMA__");
4001 Builder.defineMacro("__F16C__");
4004 Builder.defineMacro("__AVX512CD__");
4006 Builder.defineMacro("__AVX512ER__");
4008 Builder.defineMacro("__AVX512PF__");
4010 Builder.defineMacro("__AVX512DQ__");
4012 Builder.defineMacro("__AVX512BW__");
4014 Builder.defineMacro("__AVX512VL__");
4016 Builder.defineMacro("__AVX512VBMI__");
4018 Builder.defineMacro("__AVX512IFMA__");
4021 Builder.defineMacro("__SHA__");
4024 Builder.defineMacro("__FXSR__");
4026 Builder.defineMacro("__XSAVE__");
4028 Builder.defineMacro("__XSAVEOPT__");
4030 Builder.defineMacro("__XSAVEC__");
4032 Builder.defineMacro("__XSAVES__");
4034 Builder.defineMacro("__PKU__");
4036 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
4038 Builder.defineMacro("__CLFLUSHOPT__");
4040 Builder.defineMacro("__CLWB__");
4042 Builder.defineMacro("__MPX__");
4044 Builder.defineMacro("__SGX__");
4046 Builder.defineMacro("__PREFETCHWT1__");
4048 Builder.defineMacro("__CLZERO__");
4050 // Each case falls through to the previous one here.
4053 Builder.defineMacro("__AVX512F__");
4055 Builder.defineMacro("__AVX2__");
4057 Builder.defineMacro("__AVX__");
4059 Builder.defineMacro("__SSE4_2__");
4061 Builder.defineMacro("__SSE4_1__");
4063 Builder.defineMacro("__SSSE3__");
4065 Builder.defineMacro("__SSE3__");
4067 Builder.defineMacro("__SSE2__");
4068 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
4070 Builder.defineMacro("__SSE__");
4071 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
4076 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
4086 Builder.defineMacro("_M_IX86_FP", Twine(2));
4089 Builder.defineMacro("_M_IX86_FP", Twine(1));
4092 Builder.defineMacro("_M_IX86_FP", Twine(0));
4096 // Each case falls through to the previous one here.
4097 switch (MMX3DNowLevel) {
4098 case AMD3DNowAthlon:
4099 Builder.defineMacro("__3dNOW_A__");
4101 Builder.defineMacro("__3dNOW__");
4103 Builder.defineMacro("__MMX__");
4108 if (CPU >= CK_i486) {
4109 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4110 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4111 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4114 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4117 bool X86TargetInfo::hasFeature(StringRef Feature) const {
4118 return llvm::StringSwitch<bool>(Feature)
4119 .Case("aes", HasAES)
4120 .Case("avx", SSELevel >= AVX)
4121 .Case("avx2", SSELevel >= AVX2)
4122 .Case("avx512f", SSELevel >= AVX512F)
4123 .Case("avx512cd", HasAVX512CD)
4124 .Case("avx512er", HasAVX512ER)
4125 .Case("avx512pf", HasAVX512PF)
4126 .Case("avx512dq", HasAVX512DQ)
4127 .Case("avx512bw", HasAVX512BW)
4128 .Case("avx512vl", HasAVX512VL)
4129 .Case("avx512vbmi", HasAVX512VBMI)
4130 .Case("avx512ifma", HasAVX512IFMA)
4131 .Case("bmi", HasBMI)
4132 .Case("bmi2", HasBMI2)
4133 .Case("clflushopt", HasCLFLUSHOPT)
4134 .Case("clwb", HasCLWB)
4135 .Case("clzero", HasCLZERO)
4136 .Case("cx16", HasCX16)
4137 .Case("f16c", HasF16C)
4138 .Case("fma", HasFMA)
4139 .Case("fma4", XOPLevel >= FMA4)
4140 .Case("fsgsbase", HasFSGSBASE)
4141 .Case("fxsr", HasFXSR)
4142 .Case("lzcnt", HasLZCNT)
4143 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
4144 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
4145 .Case("mmx", MMX3DNowLevel >= MMX)
4146 .Case("movbe", HasMOVBE)
4147 .Case("mpx", HasMPX)
4148 .Case("pclmul", HasPCLMUL)
4149 .Case("pku", HasPKU)
4150 .Case("popcnt", HasPOPCNT)
4151 .Case("prefetchwt1", HasPREFETCHWT1)
4152 .Case("prfchw", HasPRFCHW)
4153 .Case("rdrnd", HasRDRND)
4154 .Case("rdseed", HasRDSEED)
4155 .Case("rtm", HasRTM)
4156 .Case("sgx", HasSGX)
4157 .Case("sha", HasSHA)
4158 .Case("sse", SSELevel >= SSE1)
4159 .Case("sse2", SSELevel >= SSE2)
4160 .Case("sse3", SSELevel >= SSE3)
4161 .Case("ssse3", SSELevel >= SSSE3)
4162 .Case("sse4.1", SSELevel >= SSE41)
4163 .Case("sse4.2", SSELevel >= SSE42)
4164 .Case("sse4a", XOPLevel >= SSE4A)
4165 .Case("tbm", HasTBM)
4166 .Case("lwp", HasLWP)
4168 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
4169 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
4170 .Case("xop", XOPLevel >= XOP)
4171 .Case("xsave", HasXSAVE)
4172 .Case("xsavec", HasXSAVEC)
4173 .Case("xsaves", HasXSAVES)
4174 .Case("xsaveopt", HasXSAVEOPT)
4178 // We can't use a generic validation scheme for the features accepted here
4179 // versus subtarget features accepted in the target attribute because the
4180 // bitfield structure that's initialized in the runtime only supports the
4181 // below currently rather than the full range of subtarget features. (See
4182 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
4183 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
4184 return llvm::StringSwitch<bool>(FeatureStr)
4187 .Case("popcnt", true)
4191 .Case("ssse3", true)
4192 .Case("sse4.1", true)
4193 .Case("sse4.2", true)
4196 .Case("sse4a", true)
4200 .Case("avx512f", true)
4204 .Case("pclmul", true)
4205 .Case("avx512vl", true)
4206 .Case("avx512bw", true)
4207 .Case("avx512dq", true)
4208 .Case("avx512cd", true)
4209 .Case("avx512er", true)
4210 .Case("avx512pf", true)
4211 .Case("avx512vbmi", true)
4212 .Case("avx512ifma", true)
4217 X86TargetInfo::validateAsmConstraint(const char *&Name,
4218 TargetInfo::ConstraintInfo &Info) const {
4220 default: return false;
4221 // Constant constraints.
4222 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
4224 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
4225 // x86_64 instructions.
4227 Info.setRequiresImmediate();
4230 Info.setRequiresImmediate(0, 31);
4233 Info.setRequiresImmediate(0, 63);
4236 Info.setRequiresImmediate(-128, 127);
4239 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
4242 Info.setRequiresImmediate(0, 3);
4245 Info.setRequiresImmediate(0, 255);
4248 Info.setRequiresImmediate(0, 127);
4250 // Register constraints.
4251 case 'Y': // 'Y' is the first character for several 2-character constraints.
4252 // Shift the pointer to the second character of the constraint.
4257 case '0': // First SSE register.
4258 case 't': // Any SSE register, when SSE2 is enabled.
4259 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
4260 case 'm': // Any MMX register, when inter-unit moves enabled.
4261 case 'k': // AVX512 arch mask registers: k1-k7.
4262 Info.setAllowsRegister();
4265 case 'f': // Any x87 floating point stack register.
4266 // Constraint 'f' cannot be used for output operands.
4267 if (Info.ConstraintStr[0] == '=')
4269 Info.setAllowsRegister();
4277 case 'A': // edx:eax.
4278 case 't': // Top of floating point stack.
4279 case 'u': // Second from top of floating point stack.
4280 case 'q': // Any register accessible as [r]l: a, b, c, and d.
4281 case 'y': // Any MMX register.
4282 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
4283 case 'x': // Any SSE register.
4284 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
4285 // for intermideate k reg operations).
4286 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
4287 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
4288 case 'l': // "Index" registers: any general register that can be used as an
4289 // index in a base+index memory access.
4290 Info.setAllowsRegister();
4292 // Floating point constant constraints.
4293 case 'C': // SSE floating point constant.
4294 case 'G': // x87 floating point constant.
4299 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
4300 unsigned Size) const {
4301 // Strip off constraint modifiers.
4302 while (Constraint[0] == '=' ||
4303 Constraint[0] == '+' ||
4304 Constraint[0] == '&')
4305 Constraint = Constraint.substr(1);
4307 return validateOperandSize(Constraint, Size);
4310 bool X86TargetInfo::validateInputSize(StringRef Constraint,
4311 unsigned Size) const {
4312 return validateOperandSize(Constraint, Size);
4315 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
4316 unsigned Size) const {
4317 switch (Constraint[0]) {
4320 // Registers k0-k7 (AVX512) size limit is 64 bit.
4329 if (SSELevel >= AVX512F)
4330 // 512-bit zmm registers can be used if target supports AVX512F.
4331 return Size <= 512U;
4332 else if (SSELevel >= AVX)
4333 // 256-bit ymm registers can be used if target supports AVX.
4334 return Size <= 256U;
4335 return Size <= 128U;
4337 // 'Y' is the first character for several 2-character constraints.
4338 switch (Constraint[1]) {
4341 // 'Ym' is synonymous with 'y'.
4346 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
4347 if (SSELevel >= AVX512F)
4348 return Size <= 512U;
4349 else if (SSELevel >= AVX)
4350 return Size <= 256U;
4351 return SSELevel >= SSE2 && Size <= 128U;
4360 X86TargetInfo::convertConstraint(const char *&Constraint) const {
4361 switch (*Constraint) {
4362 case 'a': return std::string("{ax}");
4363 case 'b': return std::string("{bx}");
4364 case 'c': return std::string("{cx}");
4365 case 'd': return std::string("{dx}");
4366 case 'S': return std::string("{si}");
4367 case 'D': return std::string("{di}");
4368 case 'p': // address
4369 return std::string("im");
4370 case 't': // top of floating point stack.
4371 return std::string("{st}");
4372 case 'u': // second from top of floating point stack.
4373 return std::string("{st(1)}"); // second from top of floating point stack.
4375 switch (Constraint[1]) {
4377 // Break from inner switch and fall through (copy single char),
4378 // continue parsing after copying the current constraint into
4379 // the return string.
4382 // "^" hints llvm that this is a 2 letter constraint.
4383 // "Constraint++" is used to promote the string iterator
4384 // to the next constraint.
4385 return std::string("^") + std::string(Constraint++, 2);
4389 return std::string(1, *Constraint);
4393 // X86-32 generic target
4394 class X86_32TargetInfo : public X86TargetInfo {
4396 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4397 : X86TargetInfo(Triple, Opts) {
4398 DoubleAlign = LongLongAlign = 32;
4399 LongDoubleWidth = 96;
4400 LongDoubleAlign = 32;
4401 SuitableAlign = 128;
4402 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
4403 SizeType = UnsignedInt;
4404 PtrDiffType = SignedInt;
4405 IntPtrType = SignedInt;
4408 // Use fpret for all types.
4409 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
4410 (1 << TargetInfo::Double) |
4411 (1 << TargetInfo::LongDouble));
4413 // x86-32 has atomics up to 8 bytes
4414 // FIXME: Check that we actually have cmpxchg8b before setting
4415 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
4416 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4418 BuiltinVaListKind getBuiltinVaListKind() const override {
4419 return TargetInfo::CharPtrBuiltinVaList;
4422 int getEHDataRegisterNumber(unsigned RegNo) const override {
4423 if (RegNo == 0) return 0;
4424 if (RegNo == 1) return 2;
4427 bool validateOperandSize(StringRef Constraint,
4428 unsigned Size) const override {
4429 switch (Constraint[0]) {
4445 return X86TargetInfo::validateOperandSize(Constraint, Size);
4447 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4448 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
4449 Builtin::FirstTSBuiltin + 1);
4453 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
4455 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4456 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
4458 unsigned getFloatEvalMethod() const override {
4459 unsigned Major, Minor, Micro;
4460 getTriple().getOSVersion(Major, Minor, Micro);
4461 // New NetBSD uses the default rounding mode.
4462 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
4463 return X86_32TargetInfo::getFloatEvalMethod();
4464 // NetBSD before 6.99.26 defaults to "double" rounding.
4469 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
4471 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4472 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4473 SizeType = UnsignedLong;
4474 IntPtrType = SignedLong;
4475 PtrDiffType = SignedLong;
4479 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
4481 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4482 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4483 SizeType = UnsignedLong;
4484 IntPtrType = SignedLong;
4485 PtrDiffType = SignedLong;
4489 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
4491 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4492 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4493 LongDoubleWidth = 128;
4494 LongDoubleAlign = 128;
4495 SuitableAlign = 128;
4496 MaxVectorAlign = 256;
4497 // The watchOS simulator uses the builtin bool type for Objective-C.
4498 llvm::Triple T = llvm::Triple(Triple);
4500 UseSignedCharForObjCBool = false;
4501 SizeType = UnsignedLong;
4502 IntPtrType = SignedLong;
4503 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
4504 HasAlignMac68kSupport = true;
4507 bool handleTargetFeatures(std::vector<std::string> &Features,
4508 DiagnosticsEngine &Diags) override {
4509 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
4512 // We now know the features we have: we can decide how to align vectors.
4514 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4519 // x86-32 Windows target
4520 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
4522 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4523 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4524 WCharType = UnsignedShort;
4525 DoubleAlign = LongLongAlign = 64;
4527 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4528 resetDataLayout(IsWinCOFF
4529 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
4530 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4532 void getTargetDefines(const LangOptions &Opts,
4533 MacroBuilder &Builder) const override {
4534 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4538 // x86-32 Windows Visual Studio target
4539 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
4541 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
4542 const TargetOptions &Opts)
4543 : WindowsX86_32TargetInfo(Triple, Opts) {
4544 LongDoubleWidth = LongDoubleAlign = 64;
4545 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4547 void getTargetDefines(const LangOptions &Opts,
4548 MacroBuilder &Builder) const override {
4549 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4550 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
4551 // The value of the following reflects processor type.
4552 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
4553 // We lost the original triple, so we use the default.
4554 Builder.defineMacro("_M_IX86", "600");
4558 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4559 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
4560 // supports __declspec natively under -fms-extensions, but we define a no-op
4561 // __declspec macro anyway for pre-processor compatibility.
4562 if (Opts.MicrosoftExt)
4563 Builder.defineMacro("__declspec", "__declspec");
4565 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
4567 if (!Opts.MicrosoftExt) {
4568 // Provide macros for all the calling convention keywords. Provide both
4569 // single and double underscore prefixed variants. These are available on
4570 // x64 as well as x86, even though they have no effect.
4571 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
4572 for (const char *CC : CCs) {
4573 std::string GCCSpelling = "__attribute__((__";
4575 GCCSpelling += "__))";
4576 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
4577 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
4582 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4583 Builder.defineMacro("__MSVCRT__");
4584 Builder.defineMacro("__MINGW32__");
4585 addCygMingDefines(Opts, Builder);
4588 // x86-32 MinGW target
4589 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
4591 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4592 : WindowsX86_32TargetInfo(Triple, Opts) {}
4593 void getTargetDefines(const LangOptions &Opts,
4594 MacroBuilder &Builder) const override {
4595 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4596 DefineStd(Builder, "WIN32", Opts);
4597 DefineStd(Builder, "WINNT", Opts);
4598 Builder.defineMacro("_X86_");
4599 addMinGWDefines(Opts, Builder);
4603 // x86-32 Cygwin target
4604 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
4606 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4607 : X86_32TargetInfo(Triple, Opts) {
4608 WCharType = UnsignedShort;
4609 DoubleAlign = LongLongAlign = 64;
4610 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4612 void getTargetDefines(const LangOptions &Opts,
4613 MacroBuilder &Builder) const override {
4614 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4615 Builder.defineMacro("_X86_");
4616 Builder.defineMacro("__CYGWIN__");
4617 Builder.defineMacro("__CYGWIN32__");
4618 addCygMingDefines(Opts, Builder);
4619 DefineStd(Builder, "unix", Opts);
4621 Builder.defineMacro("_GNU_SOURCE");
4625 // x86-32 Haiku target
4626 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> {
4628 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4629 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4631 void getTargetDefines(const LangOptions &Opts,
4632 MacroBuilder &Builder) const override {
4633 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4634 Builder.defineMacro("__INTEL__");
4638 // X86-32 MCU target
4639 class MCUX86_32TargetInfo : public X86_32TargetInfo {
4641 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4642 : X86_32TargetInfo(Triple, Opts) {
4643 LongDoubleWidth = 64;
4644 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4645 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
4646 WIntType = UnsignedInt;
4649 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4650 // On MCU we support only C calling convention.
4651 return CC == CC_C ? CCCR_OK : CCCR_Warning;
4654 void getTargetDefines(const LangOptions &Opts,
4655 MacroBuilder &Builder) const override {
4656 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4657 Builder.defineMacro("__iamcu");
4658 Builder.defineMacro("__iamcu__");
4661 bool allowsLargerPreferedTypeAlignment() const override {
4667 template<typename Target>
4668 class RTEMSTargetInfo : public OSTargetInfo<Target> {
4670 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4671 MacroBuilder &Builder) const override {
4672 // RTEMS defines; list based off of gcc output
4674 Builder.defineMacro("__rtems__");
4675 Builder.defineMacro("__ELF__");
4679 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4680 : OSTargetInfo<Target>(Triple, Opts) {
4681 switch (Triple.getArch()) {
4683 case llvm::Triple::x86:
4684 // this->MCountName = ".mcount";
4686 case llvm::Triple::mips:
4687 case llvm::Triple::mipsel:
4688 case llvm::Triple::ppc:
4689 case llvm::Triple::ppc64:
4690 case llvm::Triple::ppc64le:
4691 // this->MCountName = "_mcount";
4693 case llvm::Triple::arm:
4694 // this->MCountName = "__mcount";
4700 // x86-32 RTEMS target
4701 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
4703 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4704 : X86_32TargetInfo(Triple, Opts) {
4705 SizeType = UnsignedLong;
4706 IntPtrType = SignedLong;
4707 PtrDiffType = SignedLong;
4709 void getTargetDefines(const LangOptions &Opts,
4710 MacroBuilder &Builder) const override {
4711 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4712 Builder.defineMacro("__INTEL__");
4713 Builder.defineMacro("__rtems__");
4717 // x86-64 generic target
4718 class X86_64TargetInfo : public X86TargetInfo {
4720 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4721 : X86TargetInfo(Triple, Opts) {
4722 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
4724 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4725 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
4726 LongDoubleWidth = 128;
4727 LongDoubleAlign = 128;
4728 LargeArrayMinWidth = 128;
4729 LargeArrayAlign = 128;
4730 SuitableAlign = 128;
4731 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
4732 PtrDiffType = IsX32 ? SignedInt : SignedLong;
4733 IntPtrType = IsX32 ? SignedInt : SignedLong;
4734 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
4735 Int64Type = IsX32 ? SignedLongLong : SignedLong;
4738 // Pointers are 32-bit in x32.
4739 resetDataLayout(IsX32
4740 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
4741 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4742 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
4744 // Use fpret only for long double.
4745 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4747 // Use fp2ret for _Complex long double.
4748 ComplexLongDoubleUsesFP2Ret = true;
4750 // Make __builtin_ms_va_list available.
4751 HasBuiltinMSVaList = true;
4753 // x86-64 has atomics up to 16 bytes.
4754 MaxAtomicPromoteWidth = 128;
4755 MaxAtomicInlineWidth = 128;
4757 BuiltinVaListKind getBuiltinVaListKind() const override {
4758 return TargetInfo::X86_64ABIBuiltinVaList;
4761 int getEHDataRegisterNumber(unsigned RegNo) const override {
4762 if (RegNo == 0) return 0;
4763 if (RegNo == 1) return 1;
4767 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4771 case CC_X86VectorCall:
4772 case CC_IntelOclBicc:
4773 case CC_X86_64Win64:
4774 case CC_PreserveMost:
4775 case CC_PreserveAll:
4779 return CCCR_Warning;
4783 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4787 // for x32 we need it here explicitly
4788 bool hasInt128Type() const override { return true; }
4789 unsigned getUnwindWordWidth() const override { return 64; }
4790 unsigned getRegisterWidth() const override { return 64; }
4792 bool validateGlobalRegisterVariable(StringRef RegName,
4794 bool &HasSizeMismatch) const override {
4795 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4797 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4798 // Check that the register size is 64-bit.
4799 HasSizeMismatch = RegSize != 64;
4803 // Check if the register is a 32-bit register the backend can handle.
4804 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4807 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4808 return llvm::makeArrayRef(BuiltinInfoX86,
4809 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
4813 // x86-64 Windows target
4814 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4816 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4817 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4818 WCharType = UnsignedShort;
4819 LongWidth = LongAlign = 32;
4820 DoubleAlign = LongLongAlign = 64;
4821 IntMaxType = SignedLongLong;
4822 Int64Type = SignedLongLong;
4823 SizeType = UnsignedLongLong;
4824 PtrDiffType = SignedLongLong;
4825 IntPtrType = SignedLongLong;
4828 void getTargetDefines(const LangOptions &Opts,
4829 MacroBuilder &Builder) const override {
4830 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4831 Builder.defineMacro("_WIN64");
4834 BuiltinVaListKind getBuiltinVaListKind() const override {
4835 return TargetInfo::CharPtrBuiltinVaList;
4838 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4841 case CC_X86ThisCall:
4842 case CC_X86FastCall:
4845 case CC_X86VectorCall:
4846 case CC_IntelOclBicc:
4852 return CCCR_Warning;
4857 // x86-64 Windows Visual Studio target
4858 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4860 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
4861 const TargetOptions &Opts)
4862 : WindowsX86_64TargetInfo(Triple, Opts) {
4863 LongDoubleWidth = LongDoubleAlign = 64;
4864 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4866 void getTargetDefines(const LangOptions &Opts,
4867 MacroBuilder &Builder) const override {
4868 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4869 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4870 Builder.defineMacro("_M_X64", "100");
4871 Builder.defineMacro("_M_AMD64", "100");
4875 // x86-64 MinGW target
4876 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4878 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4879 : WindowsX86_64TargetInfo(Triple, Opts) {
4880 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4881 // with x86 FP ops. Weird.
4882 LongDoubleWidth = LongDoubleAlign = 128;
4883 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
4886 void getTargetDefines(const LangOptions &Opts,
4887 MacroBuilder &Builder) const override {
4888 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4889 DefineStd(Builder, "WIN64", Opts);
4890 Builder.defineMacro("__MINGW64__");
4891 addMinGWDefines(Opts, Builder);
4893 // GCC defines this macro when it is using __gxx_personality_seh0.
4894 if (!Opts.SjLjExceptions)
4895 Builder.defineMacro("__SEH__");
4899 // x86-64 Cygwin target
4900 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4902 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4903 : X86_64TargetInfo(Triple, Opts) {
4904 TLSSupported = false;
4905 WCharType = UnsignedShort;
4907 void getTargetDefines(const LangOptions &Opts,
4908 MacroBuilder &Builder) const override {
4909 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4910 Builder.defineMacro("__x86_64__");
4911 Builder.defineMacro("__CYGWIN__");
4912 Builder.defineMacro("__CYGWIN64__");
4913 addCygMingDefines(Opts, Builder);
4914 DefineStd(Builder, "unix", Opts);
4916 Builder.defineMacro("_GNU_SOURCE");
4918 // GCC defines this macro when it is using __gxx_personality_seh0.
4919 if (!Opts.SjLjExceptions)
4920 Builder.defineMacro("__SEH__");
4924 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4926 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4927 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4928 Int64Type = SignedLongLong;
4929 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4930 llvm::Triple T = llvm::Triple(Triple);
4932 UseSignedCharForObjCBool = false;
4933 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
4936 bool handleTargetFeatures(std::vector<std::string> &Features,
4937 DiagnosticsEngine &Diags) override {
4938 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4941 // We now know the features we have: we can decide how to align vectors.
4943 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4948 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4950 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4951 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4952 IntMaxType = SignedLongLong;
4953 Int64Type = SignedLongLong;
4957 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4959 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4960 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4961 IntMaxType = SignedLongLong;
4962 Int64Type = SignedLongLong;
4966 class ARMTargetInfo : public TargetInfo {
4967 // Possible FPU choices.
4976 // Possible HWDiv features.
4978 HWDivThumb = (1 << 0),
4982 static bool FPUModeIsVFP(FPUMode Mode) {
4983 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4986 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4987 static const char * const GCCRegNames[];
4989 std::string ABI, CPU;
4991 StringRef CPUProfile;
5001 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
5002 unsigned ArchProfile;
5003 unsigned ArchVersion;
5007 unsigned IsAAPCS : 1;
5010 // Initialized via features.
5011 unsigned SoftFloat : 1;
5012 unsigned SoftFloatABI : 1;
5015 unsigned Crypto : 1;
5017 unsigned Unaligned : 1;
5020 LDREX_B = (1 << 0), /// byte (8-bit)
5021 LDREX_H = (1 << 1), /// half (16-bit)
5022 LDREX_W = (1 << 2), /// word (32-bit)
5023 LDREX_D = (1 << 3), /// double (64-bit)
5028 // ACLE 6.5.1 Hardware floating point
5030 HW_FP_HP = (1 << 1), /// half (16-bit)
5031 HW_FP_SP = (1 << 2), /// single (32-bit)
5032 HW_FP_DP = (1 << 3), /// double (64-bit)
5036 static const Builtin::Info BuiltinInfo[];
5038 void setABIAAPCS() {
5041 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5042 const llvm::Triple &T = getTriple();
5044 // size_t is unsigned long on MachO-derived environments, NetBSD,
5045 // OpenBSD and Bitrig.
5046 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
5047 T.getOS() == llvm::Triple::OpenBSD ||
5048 T.getOS() == llvm::Triple::Bitrig)
5049 SizeType = UnsignedLong;
5051 SizeType = UnsignedInt;
5053 switch (T.getOS()) {
5054 case llvm::Triple::NetBSD:
5055 case llvm::Triple::OpenBSD:
5056 WCharType = SignedInt;
5058 case llvm::Triple::Win32:
5059 WCharType = UnsignedShort;
5061 case llvm::Triple::Linux:
5063 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
5064 WCharType = UnsignedInt;
5068 UseBitFieldTypeAlignment = true;
5070 ZeroLengthBitfieldBoundary = 0;
5072 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
5073 // so set preferred for small types to 32.
5074 if (T.isOSBinFormatMachO()) {
5075 resetDataLayout(BigEndian
5076 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5077 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5078 } else if (T.isOSWindows()) {
5079 assert(!BigEndian && "Windows on ARM does not support big endian");
5088 } else if (T.isOSNaCl()) {
5089 assert(!BigEndian && "NaCl on ARM does not support big endian");
5090 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
5092 resetDataLayout(BigEndian
5093 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5094 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5097 // FIXME: Enumerated types are variable width in straight AAPCS.
5100 void setABIAPCS(bool IsAAPCS16) {
5101 const llvm::Triple &T = getTriple();
5106 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5108 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
5110 // size_t is unsigned int on FreeBSD.
5111 if (T.getOS() == llvm::Triple::FreeBSD)
5112 SizeType = UnsignedInt;
5114 SizeType = UnsignedLong;
5116 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
5117 WCharType = SignedInt;
5119 // Do not respect the alignment of bit-field types when laying out
5120 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
5121 UseBitFieldTypeAlignment = false;
5123 /// gcc forces the alignment to 4 bytes, regardless of the type of the
5124 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
5126 ZeroLengthBitfieldBoundary = 32;
5128 if (T.isOSBinFormatMachO() && IsAAPCS16) {
5129 assert(!BigEndian && "AAPCS16 does not support big-endian");
5130 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
5131 } else if (T.isOSBinFormatMachO())
5134 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5135 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5139 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5140 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5142 // FIXME: Override "preferred align" for double and long long.
5145 void setArchInfo() {
5146 StringRef ArchName = getTriple().getArchName();
5148 ArchISA = llvm::ARM::parseArchISA(ArchName);
5149 CPU = llvm::ARM::getDefaultCPU(ArchName);
5150 unsigned AK = llvm::ARM::parseArch(ArchName);
5151 if (AK != llvm::ARM::AK_INVALID)
5153 setArchInfo(ArchKind);
5156 void setArchInfo(unsigned Kind) {
5159 // cache TargetParser info
5161 SubArch = llvm::ARM::getSubArch(ArchKind);
5162 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
5163 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
5165 // cache CPU related strings
5166 CPUAttr = getCPUAttr();
5167 CPUProfile = getCPUProfile();
5171 // when triple does not specify a sub arch,
5172 // then we are not using inline atomics
5173 bool ShouldUseInlineAtomic =
5174 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
5175 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
5176 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
5177 if (ArchProfile == llvm::ARM::PK_M) {
5178 MaxAtomicPromoteWidth = 32;
5179 if (ShouldUseInlineAtomic)
5180 MaxAtomicInlineWidth = 32;
5183 MaxAtomicPromoteWidth = 64;
5184 if (ShouldUseInlineAtomic)
5185 MaxAtomicInlineWidth = 64;
5189 bool isThumb() const {
5190 return (ArchISA == llvm::ARM::IK_THUMB);
5193 bool supportsThumb() const {
5194 return CPUAttr.count('T') || ArchVersion >= 6;
5197 bool supportsThumb2() const {
5198 return CPUAttr.equals("6T2") ||
5199 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
5202 StringRef getCPUAttr() const {
5203 // For most sub-arches, the build attribute CPU name is enough.
5204 // For Cortex variants, it's slightly different.
5207 return llvm::ARM::getCPUAttr(ArchKind);
5208 case llvm::ARM::AK_ARMV6M:
5210 case llvm::ARM::AK_ARMV7S:
5212 case llvm::ARM::AK_ARMV7A:
5214 case llvm::ARM::AK_ARMV7R:
5216 case llvm::ARM::AK_ARMV7M:
5218 case llvm::ARM::AK_ARMV7EM:
5220 case llvm::ARM::AK_ARMV7VE:
5222 case llvm::ARM::AK_ARMV8A:
5224 case llvm::ARM::AK_ARMV8_1A:
5226 case llvm::ARM::AK_ARMV8_2A:
5228 case llvm::ARM::AK_ARMV8MBaseline:
5230 case llvm::ARM::AK_ARMV8MMainline:
5232 case llvm::ARM::AK_ARMV8R:
5237 StringRef getCPUProfile() const {
5238 switch(ArchProfile) {
5239 case llvm::ARM::PK_A:
5241 case llvm::ARM::PK_R:
5243 case llvm::ARM::PK_M:
5251 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5252 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
5255 switch (getTriple().getOS()) {
5256 case llvm::Triple::NetBSD:
5257 case llvm::Triple::OpenBSD:
5258 PtrDiffType = SignedLong;
5261 PtrDiffType = SignedInt;
5265 // Cache arch related info.
5268 // {} in inline assembly are neon specifiers, not assembly variant
5270 NoAsmVariants = true;
5272 // FIXME: This duplicates code from the driver that sets the -target-abi
5273 // option - this code is used if -target-abi isn't passed and should
5274 // be unified in some way.
5275 if (Triple.isOSBinFormatMachO()) {
5276 // The backend is hardwired to assume AAPCS for M-class processors, ensure
5277 // the frontend matches that.
5278 if (Triple.getEnvironment() == llvm::Triple::EABI ||
5279 Triple.getOS() == llvm::Triple::UnknownOS ||
5280 ArchProfile == llvm::ARM::PK_M) {
5282 } else if (Triple.isWatchABI()) {
5287 } else if (Triple.isOSWindows()) {
5288 // FIXME: this is invalid for WindowsCE
5291 // Select the default based on the platform.
5292 switch (Triple.getEnvironment()) {
5293 case llvm::Triple::Android:
5294 case llvm::Triple::GNUEABI:
5295 case llvm::Triple::GNUEABIHF:
5296 case llvm::Triple::MuslEABI:
5297 case llvm::Triple::MuslEABIHF:
5298 setABI("aapcs-linux");
5300 case llvm::Triple::EABIHF:
5301 case llvm::Triple::EABI:
5304 case llvm::Triple::GNU:
5308 if (Triple.getOS() == llvm::Triple::NetBSD)
5310 else if (Triple.getOS() == llvm::Triple::OpenBSD)
5311 setABI("aapcs-linux");
5318 // ARM targets default to using the ARM C++ ABI.
5319 TheCXXABI.set(TargetCXXABI::GenericARM);
5321 // ARM has atomics up to 8 bytes
5324 // Do force alignment of members that follow zero length bitfields. If
5325 // the alignment of the zero-length bitfield is greater than the member
5326 // that follows it, `bar', `bar' will be aligned as the type of the
5327 // zero length bitfield.
5328 UseZeroLengthBitfieldAlignment = true;
5330 if (Triple.getOS() == llvm::Triple::Linux ||
5331 Triple.getOS() == llvm::Triple::UnknownOS)
5333 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount";
5336 StringRef getABI() const override { return ABI; }
5338 bool setABI(const std::string &Name) override {
5341 // The defaults (above) are for AAPCS, check if we need to change them.
5343 // FIXME: We need support for -meabi... we could just mangle it into the
5345 if (Name == "apcs-gnu" || Name == "aapcs16") {
5346 setABIAPCS(Name == "aapcs16");
5349 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
5356 // FIXME: This should be based on Arch attributes, not CPU names.
5358 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5360 const std::vector<std::string> &FeaturesVec) const override {
5362 std::vector<StringRef> TargetFeatures;
5363 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
5365 // get default FPU features
5366 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
5367 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
5369 // get default Extension features
5370 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
5371 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
5373 for (auto Feature : TargetFeatures)
5374 if (Feature[0] == '+')
5375 Features[Feature.drop_front(1)] = true;
5377 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
5380 bool handleTargetFeatures(std::vector<std::string> &Features,
5381 DiagnosticsEngine &Diags) override {
5387 SoftFloat = SoftFloatABI = false;
5390 // This does not diagnose illegal cases like having both
5391 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
5392 uint32_t HW_FP_remove = 0;
5393 for (const auto &Feature : Features) {
5394 if (Feature == "+soft-float") {
5396 } else if (Feature == "+soft-float-abi") {
5397 SoftFloatABI = true;
5398 } else if (Feature == "+vfp2") {
5400 HW_FP |= HW_FP_SP | HW_FP_DP;
5401 } else if (Feature == "+vfp3") {
5403 HW_FP |= HW_FP_SP | HW_FP_DP;
5404 } else if (Feature == "+vfp4") {
5406 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5407 } else if (Feature == "+fp-armv8") {
5409 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5410 } else if (Feature == "+neon") {
5412 HW_FP |= HW_FP_SP | HW_FP_DP;
5413 } else if (Feature == "+hwdiv") {
5414 HWDiv |= HWDivThumb;
5415 } else if (Feature == "+hwdiv-arm") {
5417 } else if (Feature == "+crc") {
5419 } else if (Feature == "+crypto") {
5421 } else if (Feature == "+dsp") {
5423 } else if (Feature == "+fp-only-sp") {
5424 HW_FP_remove |= HW_FP_DP;
5425 } else if (Feature == "+strict-align") {
5427 } else if (Feature == "+fp16") {
5431 HW_FP &= ~HW_FP_remove;
5433 switch (ArchVersion) {
5435 if (ArchProfile == llvm::ARM::PK_M)
5437 else if (ArchKind == llvm::ARM::AK_ARMV6K)
5438 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5443 if (ArchProfile == llvm::ARM::PK_M)
5444 LDREX = LDREX_W | LDREX_H | LDREX_B ;
5446 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5449 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5452 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
5453 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
5457 if (FPMath == FP_Neon)
5458 Features.push_back("+neonfp");
5459 else if (FPMath == FP_VFP)
5460 Features.push_back("-neonfp");
5462 // Remove front-end specific options which the backend handles differently.
5464 std::find(Features.begin(), Features.end(), "+soft-float-abi");
5465 if (Feature != Features.end())
5466 Features.erase(Feature);
5471 bool hasFeature(StringRef Feature) const override {
5472 return llvm::StringSwitch<bool>(Feature)
5474 .Case("aarch32", true)
5475 .Case("softfloat", SoftFloat)
5476 .Case("thumb", isThumb())
5477 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
5478 .Case("vfp", FPU && !SoftFloat)
5479 .Case("hwdiv", HWDiv & HWDivThumb)
5480 .Case("hwdiv-arm", HWDiv & HWDivARM)
5484 bool setCPU(const std::string &Name) override {
5485 if (Name != "generic")
5486 setArchInfo(llvm::ARM::parseCPUArch(Name));
5488 if (ArchKind == llvm::ARM::AK_INVALID)
5495 bool setFPMath(StringRef Name) override;
5497 void getTargetDefines(const LangOptions &Opts,
5498 MacroBuilder &Builder) const override {
5499 // Target identification.
5500 Builder.defineMacro("__arm");
5501 Builder.defineMacro("__arm__");
5502 // For bare-metal none-eabi.
5503 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
5504 (getTriple().getEnvironment() == llvm::Triple::EABI ||
5505 getTriple().getEnvironment() == llvm::Triple::EABIHF))
5506 Builder.defineMacro("__ELF__");
5509 // Target properties.
5510 Builder.defineMacro("__REGISTER_PREFIX__", "");
5512 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
5513 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
5514 if (getTriple().isWatchABI())
5515 Builder.defineMacro("__ARM_ARCH_7K__", "2");
5517 if (!CPUAttr.empty())
5518 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
5520 // ACLE 6.4.1 ARM/Thumb instruction set architecture
5521 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
5522 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
5524 if (ArchVersion >= 8) {
5525 // ACLE 6.5.7 Crypto Extension
5527 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5528 // ACLE 6.5.8 CRC32 Extension
5530 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5531 // ACLE 6.5.10 Numeric Maximum and Minimum
5532 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5533 // ACLE 6.5.9 Directed Rounding
5534 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5537 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
5538 // is not defined for the M-profile.
5539 // NOTE that the default profile is assumed to be 'A'
5540 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
5541 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
5543 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
5544 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
5545 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
5546 // v7 and v8 architectures excluding v8-M Baseline.
5547 if (supportsThumb2())
5548 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
5549 else if (supportsThumb())
5550 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
5552 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
5553 // instruction set such as ARM or Thumb.
5554 Builder.defineMacro("__ARM_32BIT_STATE", "1");
5556 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
5558 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
5559 if (!CPUProfile.empty())
5560 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
5562 // ACLE 6.4.3 Unaligned access supported in hardware
5564 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5566 // ACLE 6.4.4 LDREX/STREX
5568 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
5571 if (ArchVersion == 5 ||
5572 (ArchVersion == 6 && CPUProfile != "M") ||
5574 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5576 // ACLE 6.5.1 Hardware Floating Point
5578 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
5581 Builder.defineMacro("__ARM_ACLE", "200");
5583 // FP16 support (we currently only support IEEE format).
5584 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5585 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5587 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
5588 if (ArchVersion >= 7 && (FPU & VFP4FPU))
5589 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5591 // Subtarget options.
5593 // FIXME: It's more complicated than this and we don't really support
5595 // Windows on ARM does not "support" interworking
5596 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
5597 Builder.defineMacro("__THUMB_INTERWORK__");
5599 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
5600 // Embedded targets on Darwin follow AAPCS, but not EABI.
5601 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
5602 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows())
5603 Builder.defineMacro("__ARM_EABI__");
5604 Builder.defineMacro("__ARM_PCS", "1");
5607 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" ||
5609 Builder.defineMacro("__ARM_PCS_VFP", "1");
5612 Builder.defineMacro("__SOFTFP__");
5614 if (ArchKind == llvm::ARM::AK_XSCALE)
5615 Builder.defineMacro("__XSCALE__");
5618 Builder.defineMacro("__THUMBEL__");
5619 Builder.defineMacro("__thumb__");
5620 if (supportsThumb2())
5621 Builder.defineMacro("__thumb2__");
5624 // ACLE 6.4.9 32-bit SIMD instructions
5625 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
5626 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
5628 // ACLE 6.4.10 Hardware Integer Divide
5629 if (((HWDiv & HWDivThumb) && isThumb()) ||
5630 ((HWDiv & HWDivARM) && !isThumb())) {
5631 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
5632 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
5635 // Note, this is always on in gcc, even though it doesn't make sense.
5636 Builder.defineMacro("__APCS_32__");
5638 if (FPUModeIsVFP((FPUMode) FPU)) {
5639 Builder.defineMacro("__VFP_FP__");
5641 Builder.defineMacro("__ARM_VFPV2__");
5643 Builder.defineMacro("__ARM_VFPV3__");
5645 Builder.defineMacro("__ARM_VFPV4__");
5647 Builder.defineMacro("__ARM_FPV5__");
5650 // This only gets set when Neon instructions are actually available, unlike
5651 // the VFP define, hence the soft float and arch check. This is subtly
5652 // different from gcc, we follow the intent which was that it should be set
5653 // when Neon instructions are actually available.
5654 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
5655 Builder.defineMacro("__ARM_NEON", "1");
5656 Builder.defineMacro("__ARM_NEON__");
5657 // current AArch32 NEON implementations do not support double-precision
5658 // floating-point even when it is present in VFP.
5659 Builder.defineMacro("__ARM_NEON_FP",
5660 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
5663 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
5664 Opts.ShortWChar ? "2" : "4");
5666 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5667 Opts.ShortEnums ? "1" : "4");
5669 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
5670 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5671 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5672 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5673 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5676 // ACLE 6.4.7 DSP instructions
5678 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
5681 // ACLE 6.4.8 Saturation instructions
5683 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
5684 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
5688 // ACLE 6.4.6 Q (saturation) flag
5690 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
5692 if (Opts.UnsafeFPMath)
5693 Builder.defineMacro("__ARM_FP_FAST", "1");
5695 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
5696 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5699 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5700 return llvm::makeArrayRef(BuiltinInfo,
5701 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
5703 bool isCLZForZeroUndef() const override { return false; }
5704 BuiltinVaListKind getBuiltinVaListKind() const override {
5706 ? AAPCSABIBuiltinVaList
5707 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList
5708 : TargetInfo::VoidPtrBuiltinVaList);
5710 ArrayRef<const char *> getGCCRegNames() const override;
5711 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5712 bool validateAsmConstraint(const char *&Name,
5713 TargetInfo::ConstraintInfo &Info) const override {
5718 case 't': // VFP Floating point register single precision
5719 case 'w': // VFP Floating point register double precision
5720 Info.setAllowsRegister();
5729 case 'Q': // A memory address that is a single base register.
5730 Info.setAllowsMemory();
5732 case 'U': // a memory reference...
5734 case 'q': // ...ARMV4 ldrsb
5735 case 'v': // ...VFP load/store (reg+constant offset)
5736 case 'y': // ...iWMMXt load/store
5737 case 't': // address valid for load/store opaque types wider
5739 case 'n': // valid address for Neon doubleword vector load/store
5740 case 'm': // valid address for Neon element and structure load/store
5741 case 's': // valid address for non-offset loads/stores of quad-word
5742 // values in four ARM registers
5743 Info.setAllowsMemory();
5750 std::string convertConstraint(const char *&Constraint) const override {
5752 switch (*Constraint) {
5753 case 'U': // Two-character constraint; add "^" hint for later parsing.
5754 R = std::string("^") + std::string(Constraint, 2);
5757 case 'p': // 'p' should be translated to 'r' by default.
5758 R = std::string("r");
5761 return std::string(1, *Constraint);
5766 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5767 std::string &SuggestedModifier) const override {
5768 bool isOutput = (Constraint[0] == '=');
5769 bool isInOut = (Constraint[0] == '+');
5771 // Strip off constraint modifiers.
5772 while (Constraint[0] == '=' ||
5773 Constraint[0] == '+' ||
5774 Constraint[0] == '&')
5775 Constraint = Constraint.substr(1);
5777 switch (Constraint[0]) {
5782 return (isInOut || isOutput || Size <= 64);
5784 // A register of size 32 cannot fit a vector type.
5792 const char *getClobbers() const override {
5793 // FIXME: Is this really right?
5797 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5804 return CCCR_Warning;
5808 int getEHDataRegisterNumber(unsigned RegNo) const override {
5809 if (RegNo == 0) return 0;
5810 if (RegNo == 1) return 1;
5814 bool hasSjLjLowering() const override {
5819 bool ARMTargetInfo::setFPMath(StringRef Name) {
5820 if (Name == "neon") {
5823 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5831 const char * const ARMTargetInfo::GCCRegNames[] = {
5832 // Integer registers
5833 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5834 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5837 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5838 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5839 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5840 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5843 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5844 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5845 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5846 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5849 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5850 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5853 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5854 return llvm::makeArrayRef(GCCRegNames);
5857 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5867 { { "v6", "rfp" }, "r9" },
5868 { { "sl" }, "r10" },
5869 { { "fp" }, "r11" },
5870 { { "ip" }, "r12" },
5871 { { "r13" }, "sp" },
5872 { { "r14" }, "lr" },
5873 { { "r15" }, "pc" },
5874 // The S, D and Q registers overlap, but aren't really aliases; we
5875 // don't want to substitute one of these for a different-sized one.
5878 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5879 return llvm::makeArrayRef(GCCRegAliases);
5882 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5883 #define BUILTIN(ID, TYPE, ATTRS) \
5884 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5885 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5886 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5887 #include "clang/Basic/BuiltinsNEON.def"
5889 #define BUILTIN(ID, TYPE, ATTRS) \
5890 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5891 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5892 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5893 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5894 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5895 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
5896 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
5897 #include "clang/Basic/BuiltinsARM.def"
5900 class ARMleTargetInfo : public ARMTargetInfo {
5902 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5903 : ARMTargetInfo(Triple, Opts) {}
5904 void getTargetDefines(const LangOptions &Opts,
5905 MacroBuilder &Builder) const override {
5906 Builder.defineMacro("__ARMEL__");
5907 ARMTargetInfo::getTargetDefines(Opts, Builder);
5911 class ARMbeTargetInfo : public ARMTargetInfo {
5913 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5914 : ARMTargetInfo(Triple, Opts) {}
5915 void getTargetDefines(const LangOptions &Opts,
5916 MacroBuilder &Builder) const override {
5917 Builder.defineMacro("__ARMEB__");
5918 Builder.defineMacro("__ARM_BIG_ENDIAN");
5919 ARMTargetInfo::getTargetDefines(Opts, Builder);
5923 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5924 const llvm::Triple Triple;
5926 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5927 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
5928 WCharType = UnsignedShort;
5929 SizeType = UnsignedInt;
5931 void getVisualStudioDefines(const LangOptions &Opts,
5932 MacroBuilder &Builder) const {
5933 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5935 // FIXME: this is invalid for WindowsCE
5936 Builder.defineMacro("_M_ARM_NT", "1");
5937 Builder.defineMacro("_M_ARMT", "_M_ARM");
5938 Builder.defineMacro("_M_THUMB", "_M_ARM");
5940 assert((Triple.getArch() == llvm::Triple::arm ||
5941 Triple.getArch() == llvm::Triple::thumb) &&
5942 "invalid architecture for Windows ARM target info");
5943 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5944 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5946 // TODO map the complete set of values
5947 // 31: VFPv3 40: VFPv4
5948 Builder.defineMacro("_M_ARM_FP", "31");
5950 BuiltinVaListKind getBuiltinVaListKind() const override {
5951 return TargetInfo::CharPtrBuiltinVaList;
5953 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5956 case CC_X86ThisCall:
5957 case CC_X86FastCall:
5958 case CC_X86VectorCall:
5963 return CCCR_Warning;
5968 // Windows ARM + Itanium C++ ABI Target
5969 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5971 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
5972 const TargetOptions &Opts)
5973 : WindowsARMTargetInfo(Triple, Opts) {
5974 TheCXXABI.set(TargetCXXABI::GenericARM);
5977 void getTargetDefines(const LangOptions &Opts,
5978 MacroBuilder &Builder) const override {
5979 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5981 if (Opts.MSVCCompat)
5982 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5986 // Windows ARM, MS (C++) ABI
5987 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5989 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
5990 const TargetOptions &Opts)
5991 : WindowsARMTargetInfo(Triple, Opts) {
5992 TheCXXABI.set(TargetCXXABI::Microsoft);
5995 void getTargetDefines(const LangOptions &Opts,
5996 MacroBuilder &Builder) const override {
5997 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5998 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
6003 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
6005 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6006 : WindowsARMTargetInfo(Triple, Opts) {
6007 TheCXXABI.set(TargetCXXABI::GenericARM);
6010 void getTargetDefines(const LangOptions &Opts,
6011 MacroBuilder &Builder) const override {
6012 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
6013 DefineStd(Builder, "WIN32", Opts);
6014 DefineStd(Builder, "WINNT", Opts);
6015 Builder.defineMacro("_ARM_");
6016 addMinGWDefines(Opts, Builder);
6020 // ARM Cygwin target
6021 class CygwinARMTargetInfo : public ARMleTargetInfo {
6023 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6024 : ARMleTargetInfo(Triple, Opts) {
6025 TLSSupported = false;
6026 WCharType = UnsignedShort;
6027 DoubleAlign = LongLongAlign = 64;
6028 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
6030 void getTargetDefines(const LangOptions &Opts,
6031 MacroBuilder &Builder) const override {
6032 ARMleTargetInfo::getTargetDefines(Opts, Builder);
6033 Builder.defineMacro("_ARM_");
6034 Builder.defineMacro("__CYGWIN__");
6035 Builder.defineMacro("__CYGWIN32__");
6036 DefineStd(Builder, "unix", Opts);
6038 Builder.defineMacro("_GNU_SOURCE");
6042 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> {
6044 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6045 MacroBuilder &Builder) const override {
6046 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6050 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6051 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
6052 HasAlignMac68kSupport = true;
6053 // iOS always has 64-bit atomic instructions.
6054 // FIXME: This should be based off of the target features in
6056 MaxAtomicInlineWidth = 64;
6058 if (Triple.isWatchABI()) {
6059 // Darwin on iOS uses a variant of the ARM C++ ABI.
6060 TheCXXABI.set(TargetCXXABI::WatchOS);
6062 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
6063 // size_t is long, it's a bit weird for it to be int.
6064 PtrDiffType = SignedLong;
6066 // BOOL should be a real boolean on the new ABI
6067 UseSignedCharForObjCBool = false;
6069 TheCXXABI.set(TargetCXXABI::iOS);
6073 class AArch64TargetInfo : public TargetInfo {
6074 virtual void setDataLayout() = 0;
6075 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6076 static const char *const GCCRegNames[];
6089 static const Builtin::Info BuiltinInfo[];
6094 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6095 : TargetInfo(Triple), ABI("aapcs") {
6096 if (getTriple().getOS() == llvm::Triple::NetBSD ||
6097 getTriple().getOS() == llvm::Triple::OpenBSD) {
6098 WCharType = SignedInt;
6100 // NetBSD apparently prefers consistency across ARM targets to consistency
6101 // across 64-bit targets.
6102 Int64Type = SignedLongLong;
6103 IntMaxType = SignedLongLong;
6105 WCharType = UnsignedInt;
6106 Int64Type = SignedLong;
6107 IntMaxType = SignedLong;
6110 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6111 MaxVectorAlign = 128;
6112 MaxAtomicInlineWidth = 128;
6113 MaxAtomicPromoteWidth = 128;
6115 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
6116 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6118 // {} in inline assembly are neon specifiers, not assembly variant
6120 NoAsmVariants = true;
6122 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
6123 // contributes to the alignment of the containing aggregate in the same way
6124 // a plain (non bit-field) member of that type would, without exception for
6125 // zero-sized or anonymous bit-fields."
6126 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
6127 UseZeroLengthBitfieldAlignment = true;
6129 // AArch64 targets default to using the ARM C++ ABI.
6130 TheCXXABI.set(TargetCXXABI::GenericAArch64);
6132 if (Triple.getOS() == llvm::Triple::Linux)
6133 this->MCountName = "\01_mcount";
6134 else if (Triple.getOS() == llvm::Triple::UnknownOS)
6135 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount";
6138 StringRef getABI() const override { return ABI; }
6139 bool setABI(const std::string &Name) override {
6140 if (Name != "aapcs" && Name != "darwinpcs")
6147 bool setCPU(const std::string &Name) override {
6148 return Name == "generic" ||
6149 llvm::AArch64::parseCPUArch(Name) !=
6150 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID);
6153 void getTargetDefines(const LangOptions &Opts,
6154 MacroBuilder &Builder) const override {
6155 // Target identification.
6156 Builder.defineMacro("__aarch64__");
6157 // For bare-metal none-eabi.
6158 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
6159 (getTriple().getEnvironment() == llvm::Triple::EABI ||
6160 getTriple().getEnvironment() == llvm::Triple::EABIHF))
6161 Builder.defineMacro("__ELF__");
6163 // Target properties.
6164 Builder.defineMacro("_LP64");
6165 Builder.defineMacro("__LP64__");
6167 // ACLE predefines. Many can only have one possible value on v8 AArch64.
6168 Builder.defineMacro("__ARM_ACLE", "200");
6169 Builder.defineMacro("__ARM_ARCH", "8");
6170 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
6172 Builder.defineMacro("__ARM_64BIT_STATE", "1");
6173 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
6174 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
6176 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
6177 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
6178 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
6179 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
6180 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
6181 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
6182 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
6184 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
6186 // 0xe implies support for half, single and double precision operations.
6187 Builder.defineMacro("__ARM_FP", "0xE");
6189 // PCS specifies this for SysV variants, which is all we support. Other ABIs
6190 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
6191 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
6192 Builder.defineMacro("__ARM_FP16_ARGS", "1");
6194 if (Opts.UnsafeFPMath)
6195 Builder.defineMacro("__ARM_FP_FAST", "1");
6197 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
6199 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
6200 Opts.ShortEnums ? "1" : "4");
6202 if (FPU == NeonMode) {
6203 Builder.defineMacro("__ARM_NEON", "1");
6204 // 64-bit NEON supports half, single and double precision operations.
6205 Builder.defineMacro("__ARM_NEON_FP", "0xE");
6209 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
6212 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
6215 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
6218 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
6220 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
6221 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6222 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6223 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6224 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6227 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6228 return llvm::makeArrayRef(BuiltinInfo,
6229 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
6232 bool hasFeature(StringRef Feature) const override {
6233 return Feature == "aarch64" ||
6234 Feature == "arm64" ||
6236 (Feature == "neon" && FPU == NeonMode);
6239 bool handleTargetFeatures(std::vector<std::string> &Features,
6240 DiagnosticsEngine &Diags) override {
6247 for (const auto &Feature : Features) {
6248 if (Feature == "+neon")
6250 if (Feature == "+crc")
6252 if (Feature == "+crypto")
6254 if (Feature == "+strict-align")
6256 if (Feature == "+v8.1a")
6265 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6269 case CC_PreserveMost:
6270 case CC_PreserveAll:
6273 return CCCR_Warning;
6277 bool isCLZForZeroUndef() const override { return false; }
6279 BuiltinVaListKind getBuiltinVaListKind() const override {
6280 return TargetInfo::AArch64ABIBuiltinVaList;
6283 ArrayRef<const char *> getGCCRegNames() const override;
6284 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6286 bool validateAsmConstraint(const char *&Name,
6287 TargetInfo::ConstraintInfo &Info) const override {
6291 case 'w': // Floating point and SIMD registers (V0-V31)
6292 Info.setAllowsRegister();
6294 case 'I': // Constant that can be used with an ADD instruction
6295 case 'J': // Constant that can be used with a SUB instruction
6296 case 'K': // Constant that can be used with a 32-bit logical instruction
6297 case 'L': // Constant that can be used with a 64-bit logical instruction
6298 case 'M': // Constant that can be used as a 32-bit MOV immediate
6299 case 'N': // Constant that can be used as a 64-bit MOV immediate
6300 case 'Y': // Floating point constant zero
6301 case 'Z': // Integer constant zero
6303 case 'Q': // A memory reference with base register and no offset
6304 Info.setAllowsMemory();
6306 case 'S': // A symbolic address
6307 Info.setAllowsRegister();
6310 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
6311 // Utf: A memory address suitable for ldp/stp in TF mode.
6312 // Usa: An absolute symbolic address.
6313 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
6314 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
6315 case 'z': // Zero register, wzr or xzr
6316 Info.setAllowsRegister();
6318 case 'x': // Floating point and SIMD registers (V0-V15)
6319 Info.setAllowsRegister();
6326 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
6327 std::string &SuggestedModifier) const override {
6328 // Strip off constraint modifiers.
6329 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
6330 Constraint = Constraint.substr(1);
6332 switch (Constraint[0]) {
6340 // For now assume that the person knows what they're
6341 // doing with the modifier.
6344 // By default an 'r' constraint will be in the 'x'
6349 SuggestedModifier = "w";
6356 const char *getClobbers() const override { return ""; }
6358 int getEHDataRegisterNumber(unsigned RegNo) const override {
6367 const char *const AArch64TargetInfo::GCCRegNames[] = {
6368 // 32-bit Integer registers
6369 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
6370 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
6371 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
6373 // 64-bit Integer registers
6374 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
6375 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
6376 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
6378 // 32-bit floating point regsisters
6379 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
6380 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
6381 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6383 // 64-bit floating point regsisters
6384 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
6385 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
6386 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6389 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
6390 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
6391 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
6394 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
6395 return llvm::makeArrayRef(GCCRegNames);
6398 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
6399 { { "w31" }, "wsp" },
6400 { { "x29" }, "fp" },
6401 { { "x30" }, "lr" },
6402 { { "x31" }, "sp" },
6403 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
6404 // don't want to substitute one of these for a different-sized one.
6407 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
6408 return llvm::makeArrayRef(GCCRegAliases);
6411 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
6412 #define BUILTIN(ID, TYPE, ATTRS) \
6413 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6414 #include "clang/Basic/BuiltinsNEON.def"
6416 #define BUILTIN(ID, TYPE, ATTRS) \
6417 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6418 #include "clang/Basic/BuiltinsAArch64.def"
6421 class AArch64leTargetInfo : public AArch64TargetInfo {
6422 void setDataLayout() override {
6423 if (getTriple().isOSBinFormatMachO())
6424 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
6426 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6430 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6431 : AArch64TargetInfo(Triple, Opts) {
6433 void getTargetDefines(const LangOptions &Opts,
6434 MacroBuilder &Builder) const override {
6435 Builder.defineMacro("__AARCH64EL__");
6436 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6440 class AArch64beTargetInfo : public AArch64TargetInfo {
6441 void setDataLayout() override {
6442 assert(!getTriple().isOSBinFormatMachO());
6443 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6447 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6448 : AArch64TargetInfo(Triple, Opts) {}
6449 void getTargetDefines(const LangOptions &Opts,
6450 MacroBuilder &Builder) const override {
6451 Builder.defineMacro("__AARCH64EB__");
6452 Builder.defineMacro("__AARCH_BIG_ENDIAN");
6453 Builder.defineMacro("__ARM_BIG_ENDIAN");
6454 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6458 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
6460 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6461 MacroBuilder &Builder) const override {
6462 Builder.defineMacro("__AARCH64_SIMD__");
6463 Builder.defineMacro("__ARM64_ARCH_8__");
6464 Builder.defineMacro("__ARM_NEON__");
6465 Builder.defineMacro("__LITTLE_ENDIAN__");
6466 Builder.defineMacro("__REGISTER_PREFIX__", "");
6467 Builder.defineMacro("__arm64", "1");
6468 Builder.defineMacro("__arm64__", "1");
6470 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6474 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6475 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
6476 Int64Type = SignedLongLong;
6477 WCharType = SignedInt;
6478 UseSignedCharForObjCBool = false;
6480 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
6481 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
6483 TheCXXABI.set(TargetCXXABI::iOS64);
6486 BuiltinVaListKind getBuiltinVaListKind() const override {
6487 return TargetInfo::CharPtrBuiltinVaList;
6491 // Hexagon abstract base class
6492 class HexagonTargetInfo : public TargetInfo {
6493 static const Builtin::Info BuiltinInfo[];
6494 static const char * const GCCRegNames[];
6495 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6497 bool HasHVX, HasHVXDouble;
6501 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6502 : TargetInfo(Triple) {
6503 // Specify the vector alignment explicitly. For v512x1, the calculated
6504 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
6505 // the required minimum of 64 bytes.
6506 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-"
6507 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
6508 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
6509 SizeType = UnsignedInt;
6510 PtrDiffType = SignedInt;
6511 IntPtrType = SignedInt;
6513 // {} in inline assembly are packet specifiers, not assembly variant
6515 NoAsmVariants = true;
6517 LargeArrayMinWidth = 64;
6518 LargeArrayAlign = 64;
6519 UseBitFieldTypeAlignment = true;
6520 ZeroLengthBitfieldBoundary = 32;
6521 HasHVX = HasHVXDouble = false;
6522 UseLongCalls = false;
6525 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6526 return llvm::makeArrayRef(BuiltinInfo,
6527 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
6530 bool validateAsmConstraint(const char *&Name,
6531 TargetInfo::ConstraintInfo &Info) const override {
6536 Info.setAllowsRegister();
6541 // Relocatable constant.
6547 void getTargetDefines(const LangOptions &Opts,
6548 MacroBuilder &Builder) const override;
6550 bool isCLZForZeroUndef() const override { return false; }
6552 bool hasFeature(StringRef Feature) const override {
6553 return llvm::StringSwitch<bool>(Feature)
6554 .Case("hexagon", true)
6555 .Case("hvx", HasHVX)
6556 .Case("hvx-double", HasHVXDouble)
6557 .Case("long-calls", UseLongCalls)
6561 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6562 StringRef CPU, const std::vector<std::string> &FeaturesVec)
6565 bool handleTargetFeatures(std::vector<std::string> &Features,
6566 DiagnosticsEngine &Diags) override;
6568 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
6569 bool Enabled) const override;
6571 BuiltinVaListKind getBuiltinVaListKind() const override {
6572 return TargetInfo::CharPtrBuiltinVaList;
6574 ArrayRef<const char *> getGCCRegNames() const override;
6575 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6576 const char *getClobbers() const override {
6580 static const char *getHexagonCPUSuffix(StringRef Name) {
6581 return llvm::StringSwitch<const char*>(Name)
6582 .Case("hexagonv4", "4")
6583 .Case("hexagonv5", "5")
6584 .Case("hexagonv55", "55")
6585 .Case("hexagonv60", "60")
6586 .Case("hexagonv62", "62")
6590 bool setCPU(const std::string &Name) override {
6591 if (!getHexagonCPUSuffix(Name))
6597 int getEHDataRegisterNumber(unsigned RegNo) const override {
6598 return RegNo < 2 ? RegNo : -1;
6602 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
6603 MacroBuilder &Builder) const {
6604 Builder.defineMacro("__qdsp6__", "1");
6605 Builder.defineMacro("__hexagon__", "1");
6607 if (CPU == "hexagonv4") {
6608 Builder.defineMacro("__HEXAGON_V4__");
6609 Builder.defineMacro("__HEXAGON_ARCH__", "4");
6610 if (Opts.HexagonQdsp6Compat) {
6611 Builder.defineMacro("__QDSP6_V4__");
6612 Builder.defineMacro("__QDSP6_ARCH__", "4");
6614 } else if (CPU == "hexagonv5") {
6615 Builder.defineMacro("__HEXAGON_V5__");
6616 Builder.defineMacro("__HEXAGON_ARCH__", "5");
6617 if(Opts.HexagonQdsp6Compat) {
6618 Builder.defineMacro("__QDSP6_V5__");
6619 Builder.defineMacro("__QDSP6_ARCH__", "5");
6621 } else if (CPU == "hexagonv55") {
6622 Builder.defineMacro("__HEXAGON_V55__");
6623 Builder.defineMacro("__HEXAGON_ARCH__", "55");
6624 Builder.defineMacro("__QDSP6_V55__");
6625 Builder.defineMacro("__QDSP6_ARCH__", "55");
6626 } else if (CPU == "hexagonv60") {
6627 Builder.defineMacro("__HEXAGON_V60__");
6628 Builder.defineMacro("__HEXAGON_ARCH__", "60");
6629 Builder.defineMacro("__QDSP6_V60__");
6630 Builder.defineMacro("__QDSP6_ARCH__", "60");
6631 } else if (CPU == "hexagonv62") {
6632 Builder.defineMacro("__HEXAGON_V62__");
6633 Builder.defineMacro("__HEXAGON_ARCH__", "62");
6636 if (hasFeature("hvx")) {
6637 Builder.defineMacro("__HVX__");
6638 if (hasFeature("hvx-double"))
6639 Builder.defineMacro("__HVXDBL__");
6643 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
6644 DiagnosticsEngine &Diags, StringRef CPU,
6645 const std::vector<std::string> &FeaturesVec) const {
6646 // Default for v60: -hvx, -hvx-double.
6647 Features["hvx"] = false;
6648 Features["hvx-double"] = false;
6649 Features["long-calls"] = false;
6651 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6654 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
6655 DiagnosticsEngine &Diags) {
6656 for (auto &F : Features) {
6659 else if (F == "-hvx")
6660 HasHVX = HasHVXDouble = false;
6661 else if (F == "+hvx-double")
6662 HasHVX = HasHVXDouble = true;
6663 else if (F == "-hvx-double")
6664 HasHVXDouble = false;
6666 if (F == "+long-calls")
6667 UseLongCalls = true;
6668 else if (F == "-long-calls")
6669 UseLongCalls = false;
6674 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
6675 StringRef Name, bool Enabled) const {
6677 if (Name == "hvx-double")
6678 Features["hvx"] = true;
6681 Features["hvx-double"] = false;
6683 Features[Name] = Enabled;
6686 const char *const HexagonTargetInfo::GCCRegNames[] = {
6687 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6688 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6689 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6690 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
6691 "p0", "p1", "p2", "p3",
6692 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
6695 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
6696 return llvm::makeArrayRef(GCCRegNames);
6699 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
6700 { { "sp" }, "r29" },
6701 { { "fp" }, "r30" },
6702 { { "lr" }, "r31" },
6705 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
6706 return llvm::makeArrayRef(GCCRegAliases);
6710 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
6711 #define BUILTIN(ID, TYPE, ATTRS) \
6712 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6713 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6714 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6715 #include "clang/Basic/BuiltinsHexagon.def"
6718 class LanaiTargetInfo : public TargetInfo {
6719 // Class for Lanai (32-bit).
6720 // The CPU profiles supported by the Lanai backend
6726 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6727 static const char *const GCCRegNames[];
6730 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6731 : TargetInfo(Triple) {
6732 // Description string has to be kept in sync with backend.
6733 resetDataLayout("E" // Big endian
6734 "-m:e" // ELF name manging
6735 "-p:32:32" // 32 bit pointers, 32 bit aligned
6736 "-i64:64" // 64 bit integers, 64 bit aligned
6737 "-a:0:32" // 32 bit alignment of objects of aggregate type
6738 "-n32" // 32 bit native integer width
6739 "-S64" // 64 bit natural stack alignment
6742 // Setting RegParmMax equal to what mregparm was set to in the old
6746 // Set the default CPU to V11
6749 // Temporary approach to make everything at least word-aligned and allow for
6750 // safely casting between pointers with different alignment requirements.
6751 // TODO: Remove this when there are no more cast align warnings on the
6753 MinGlobalAlign = 32;
6756 void getTargetDefines(const LangOptions &Opts,
6757 MacroBuilder &Builder) const override {
6758 // Define __lanai__ when building for target lanai.
6759 Builder.defineMacro("__lanai__");
6761 // Set define for the CPU specified.
6764 Builder.defineMacro("__LANAI_V11__");
6767 llvm_unreachable("Unhandled target CPU");
6771 bool setCPU(const std::string &Name) override {
6772 CPU = llvm::StringSwitch<CPUKind>(Name)
6773 .Case("v11", CK_V11)
6776 return CPU != CK_NONE;
6779 bool hasFeature(StringRef Feature) const override {
6780 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
6783 ArrayRef<const char *> getGCCRegNames() const override;
6785 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6787 BuiltinVaListKind getBuiltinVaListKind() const override {
6788 return TargetInfo::VoidPtrBuiltinVaList;
6791 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6793 bool validateAsmConstraint(const char *&Name,
6794 TargetInfo::ConstraintInfo &info) const override {
6798 const char *getClobbers() const override { return ""; }
6801 const char *const LanaiTargetInfo::GCCRegNames[] = {
6802 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
6803 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
6804 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
6806 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
6807 return llvm::makeArrayRef(GCCRegNames);
6810 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
6820 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
6821 return llvm::makeArrayRef(GCCRegAliases);
6824 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
6825 class SparcTargetInfo : public TargetInfo {
6826 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6827 static const char * const GCCRegNames[];
6830 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6831 : TargetInfo(Triple), SoftFloat(false) {}
6833 int getEHDataRegisterNumber(unsigned RegNo) const override {
6834 if (RegNo == 0) return 24;
6835 if (RegNo == 1) return 25;
6839 bool handleTargetFeatures(std::vector<std::string> &Features,
6840 DiagnosticsEngine &Diags) override {
6841 // Check if software floating point is enabled
6842 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
6843 if (Feature != Features.end()) {
6848 void getTargetDefines(const LangOptions &Opts,
6849 MacroBuilder &Builder) const override {
6850 DefineStd(Builder, "sparc", Opts);
6851 Builder.defineMacro("__REGISTER_PREFIX__", "");
6854 Builder.defineMacro("SOFT_FLOAT", "1");
6857 bool hasFeature(StringRef Feature) const override {
6858 return llvm::StringSwitch<bool>(Feature)
6859 .Case("softfloat", SoftFloat)
6860 .Case("sparc", true)
6864 bool hasSjLjLowering() const override {
6868 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6869 // FIXME: Implement!
6872 BuiltinVaListKind getBuiltinVaListKind() const override {
6873 return TargetInfo::VoidPtrBuiltinVaList;
6875 ArrayRef<const char *> getGCCRegNames() const override;
6876 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6877 bool validateAsmConstraint(const char *&Name,
6878 TargetInfo::ConstraintInfo &info) const override {
6879 // FIXME: Implement!
6881 case 'I': // Signed 13-bit constant
6883 case 'K': // 32-bit constant with the low 12 bits clear
6884 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
6885 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
6886 case 'N': // Same as 'K' but zext (required for SIMode)
6887 case 'O': // The constant 4096
6892 info.setAllowsRegister();
6897 const char *getClobbers() const override {
6898 // FIXME: Implement!
6902 // No Sparc V7 for now, the backend doesn't support it anyway.
6933 enum CPUGeneration {
6938 CPUGeneration getCPUGeneration(CPUKind Kind) const {
6946 case CK_SPARCLITE86X:
6953 case CK_LEON2_AT697E:
6954 case CK_LEON2_AT697F:
6956 case CK_LEON3_UT699:
6957 case CK_LEON3_GR712RC:
6959 case CK_LEON4_GR740:
6963 case CK_ULTRASPARC3:
6970 llvm_unreachable("Unexpected CPU kind");
6973 CPUKind getCPUKind(StringRef Name) const {
6974 return llvm::StringSwitch<CPUKind>(Name)
6976 .Case("supersparc", CK_SUPERSPARC)
6977 .Case("sparclite", CK_SPARCLITE)
6978 .Case("f934", CK_F934)
6979 .Case("hypersparc", CK_HYPERSPARC)
6980 .Case("sparclite86x", CK_SPARCLITE86X)
6981 .Case("sparclet", CK_SPARCLET)
6982 .Case("tsc701", CK_TSC701)
6984 .Case("ultrasparc", CK_ULTRASPARC)
6985 .Case("ultrasparc3", CK_ULTRASPARC3)
6986 .Case("niagara", CK_NIAGARA)
6987 .Case("niagara2", CK_NIAGARA2)
6988 .Case("niagara3", CK_NIAGARA3)
6989 .Case("niagara4", CK_NIAGARA4)
6990 .Case("ma2100", CK_MYRIAD2100)
6991 .Case("ma2150", CK_MYRIAD2150)
6992 .Case("ma2450", CK_MYRIAD2450)
6993 // FIXME: the myriad2[.n] spellings are obsolete,
6994 // but a grace period is needed to allow updating dependent builds.
6995 .Case("myriad2", CK_MYRIAD2100)
6996 .Case("myriad2.1", CK_MYRIAD2100)
6997 .Case("myriad2.2", CK_MYRIAD2150)
6998 .Case("leon2", CK_LEON2)
6999 .Case("at697e", CK_LEON2_AT697E)
7000 .Case("at697f", CK_LEON2_AT697F)
7001 .Case("leon3", CK_LEON3)
7002 .Case("ut699", CK_LEON3_UT699)
7003 .Case("gr712rc", CK_LEON3_GR712RC)
7004 .Case("leon4", CK_LEON4)
7005 .Case("gr740", CK_LEON4_GR740)
7006 .Default(CK_GENERIC);
7009 bool setCPU(const std::string &Name) override {
7010 CPU = getCPUKind(Name);
7011 return CPU != CK_GENERIC;
7015 const char * const SparcTargetInfo::GCCRegNames[] = {
7016 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7017 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7018 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7019 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7022 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
7023 return llvm::makeArrayRef(GCCRegNames);
7026 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
7037 { { "o2" }, "r10" },
7038 { { "o3" }, "r11" },
7039 { { "o4" }, "r12" },
7040 { { "o5" }, "r13" },
7041 { { "o6", "sp" }, "r14" },
7042 { { "o7" }, "r15" },
7043 { { "l0" }, "r16" },
7044 { { "l1" }, "r17" },
7045 { { "l2" }, "r18" },
7046 { { "l3" }, "r19" },
7047 { { "l4" }, "r20" },
7048 { { "l5" }, "r21" },
7049 { { "l6" }, "r22" },
7050 { { "l7" }, "r23" },
7051 { { "i0" }, "r24" },
7052 { { "i1" }, "r25" },
7053 { { "i2" }, "r26" },
7054 { { "i3" }, "r27" },
7055 { { "i4" }, "r28" },
7056 { { "i5" }, "r29" },
7057 { { "i6", "fp" }, "r30" },
7058 { { "i7" }, "r31" },
7061 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
7062 return llvm::makeArrayRef(GCCRegAliases);
7065 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
7066 class SparcV8TargetInfo : public SparcTargetInfo {
7068 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7069 : SparcTargetInfo(Triple, Opts) {
7070 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
7071 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
7072 switch (getTriple().getOS()) {
7074 SizeType = UnsignedInt;
7075 IntPtrType = SignedInt;
7076 PtrDiffType = SignedInt;
7078 case llvm::Triple::NetBSD:
7079 case llvm::Triple::OpenBSD:
7080 SizeType = UnsignedLong;
7081 IntPtrType = SignedLong;
7082 PtrDiffType = SignedLong;
7085 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
7086 // on up to 64 bits.
7087 MaxAtomicPromoteWidth = 64;
7088 MaxAtomicInlineWidth = 32;
7091 void getTargetDefines(const LangOptions &Opts,
7092 MacroBuilder &Builder) const override {
7093 SparcTargetInfo::getTargetDefines(Opts, Builder);
7094 switch (getCPUGeneration(CPU)) {
7096 Builder.defineMacro("__sparcv8");
7097 if (getTriple().getOS() != llvm::Triple::Solaris)
7098 Builder.defineMacro("__sparcv8__");
7101 Builder.defineMacro("__sparcv9");
7102 if (getTriple().getOS() != llvm::Triple::Solaris) {
7103 Builder.defineMacro("__sparcv9__");
7104 Builder.defineMacro("__sparc_v9__");
7108 if (getTriple().getVendor() == llvm::Triple::Myriad) {
7109 std::string MyriadArchValue, Myriad2Value;
7110 Builder.defineMacro("__sparc_v8__");
7111 Builder.defineMacro("__leon__");
7114 MyriadArchValue = "__ma2150";
7118 MyriadArchValue = "__ma2450";
7122 MyriadArchValue = "__ma2100";
7126 Builder.defineMacro(MyriadArchValue, "1");
7127 Builder.defineMacro(MyriadArchValue+"__", "1");
7128 Builder.defineMacro("__myriad2__", Myriad2Value);
7129 Builder.defineMacro("__myriad2", Myriad2Value);
7133 bool hasSjLjLowering() const override {
7138 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
7139 class SparcV8elTargetInfo : public SparcV8TargetInfo {
7141 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7142 : SparcV8TargetInfo(Triple, Opts) {
7143 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
7147 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
7148 class SparcV9TargetInfo : public SparcTargetInfo {
7150 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7151 : SparcTargetInfo(Triple, Opts) {
7152 // FIXME: Support Sparc quad-precision long double?
7153 resetDataLayout("E-m:e-i64:64-n32:64-S128");
7154 // This is an LP64 platform.
7155 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7157 // OpenBSD uses long long for int64_t and intmax_t.
7158 if (getTriple().getOS() == llvm::Triple::OpenBSD)
7159 IntMaxType = SignedLongLong;
7161 IntMaxType = SignedLong;
7162 Int64Type = IntMaxType;
7164 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
7165 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
7166 LongDoubleWidth = 128;
7167 LongDoubleAlign = 128;
7168 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7169 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7172 void getTargetDefines(const LangOptions &Opts,
7173 MacroBuilder &Builder) const override {
7174 SparcTargetInfo::getTargetDefines(Opts, Builder);
7175 Builder.defineMacro("__sparcv9");
7176 Builder.defineMacro("__arch64__");
7177 // Solaris doesn't need these variants, but the BSDs do.
7178 if (getTriple().getOS() != llvm::Triple::Solaris) {
7179 Builder.defineMacro("__sparc64__");
7180 Builder.defineMacro("__sparc_v9__");
7181 Builder.defineMacro("__sparcv9__");
7185 bool setCPU(const std::string &Name) override {
7186 if (!SparcTargetInfo::setCPU(Name))
7188 return getCPUGeneration(CPU) == CG_V9;
7192 class SystemZTargetInfo : public TargetInfo {
7193 static const Builtin::Info BuiltinInfo[];
7194 static const char *const GCCRegNames[];
7196 bool HasTransactionalExecution;
7200 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7201 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
7203 IntMaxType = SignedLong;
7204 Int64Type = SignedLong;
7205 TLSSupported = true;
7206 IntWidth = IntAlign = 32;
7207 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
7208 PointerWidth = PointerAlign = 64;
7209 LongDoubleWidth = 128;
7210 LongDoubleAlign = 64;
7211 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7212 DefaultAlignForAttributeAligned = 64;
7213 MinGlobalAlign = 16;
7214 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
7215 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7217 void getTargetDefines(const LangOptions &Opts,
7218 MacroBuilder &Builder) const override {
7219 Builder.defineMacro("__s390__");
7220 Builder.defineMacro("__s390x__");
7221 Builder.defineMacro("__zarch__");
7222 Builder.defineMacro("__LONG_DOUBLE_128__");
7224 const std::string ISARev = llvm::StringSwitch<std::string>(CPU)
7225 .Cases("arch8", "z10", "8")
7226 .Cases("arch9", "z196", "9")
7227 .Cases("arch10", "zEC12", "10")
7228 .Cases("arch11", "z13", "11")
7230 if (!ISARev.empty())
7231 Builder.defineMacro("__ARCH__", ISARev);
7233 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7235 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7236 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7238 if (HasTransactionalExecution)
7239 Builder.defineMacro("__HTM__");
7241 Builder.defineMacro("__VX__");
7243 Builder.defineMacro("__VEC__", "10301");
7245 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7246 return llvm::makeArrayRef(BuiltinInfo,
7247 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
7250 ArrayRef<const char *> getGCCRegNames() const override;
7251 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7255 bool validateAsmConstraint(const char *&Name,
7256 TargetInfo::ConstraintInfo &info) const override;
7257 const char *getClobbers() const override {
7258 // FIXME: Is this really right?
7261 BuiltinVaListKind getBuiltinVaListKind() const override {
7262 return TargetInfo::SystemZBuiltinVaList;
7264 bool setCPU(const std::string &Name) override {
7266 bool CPUKnown = llvm::StringSwitch<bool>(Name)
7268 .Case("arch8", true)
7270 .Case("arch9", true)
7271 .Case("zEC12", true)
7272 .Case("arch10", true)
7274 .Case("arch11", true)
7280 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7282 const std::vector<std::string> &FeaturesVec) const override {
7283 if (CPU == "zEC12" || CPU == "arch10")
7284 Features["transactional-execution"] = true;
7285 if (CPU == "z13" || CPU == "arch11") {
7286 Features["transactional-execution"] = true;
7287 Features["vector"] = true;
7289 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7292 bool handleTargetFeatures(std::vector<std::string> &Features,
7293 DiagnosticsEngine &Diags) override {
7294 HasTransactionalExecution = false;
7295 for (const auto &Feature : Features) {
7296 if (Feature == "+transactional-execution")
7297 HasTransactionalExecution = true;
7298 else if (Feature == "+vector")
7301 // If we use the vector ABI, vector types are 64-bit aligned.
7303 MaxVectorAlign = 64;
7304 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
7305 "-v128:64-a:8:16-n32:64");
7310 bool hasFeature(StringRef Feature) const override {
7311 return llvm::StringSwitch<bool>(Feature)
7312 .Case("systemz", true)
7313 .Case("htm", HasTransactionalExecution)
7314 .Case("vx", HasVector)
7318 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7324 return CCCR_Warning;
7328 StringRef getABI() const override {
7334 bool useFloat128ManglingForLongDouble() const override {
7339 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
7340 #define BUILTIN(ID, TYPE, ATTRS) \
7341 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7342 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7343 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
7344 #include "clang/Basic/BuiltinsSystemZ.def"
7347 const char *const SystemZTargetInfo::GCCRegNames[] = {
7348 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7349 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7350 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
7351 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
7354 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
7355 return llvm::makeArrayRef(GCCRegNames);
7358 bool SystemZTargetInfo::
7359 validateAsmConstraint(const char *&Name,
7360 TargetInfo::ConstraintInfo &Info) const {
7365 case 'a': // Address register
7366 case 'd': // Data register (equivalent to 'r')
7367 case 'f': // Floating-point register
7368 Info.setAllowsRegister();
7371 case 'I': // Unsigned 8-bit constant
7372 case 'J': // Unsigned 12-bit constant
7373 case 'K': // Signed 16-bit constant
7374 case 'L': // Signed 20-bit displacement (on all targets we support)
7375 case 'M': // 0x7fffffff
7378 case 'Q': // Memory with base and unsigned 12-bit displacement
7379 case 'R': // Likewise, plus an index
7380 case 'S': // Memory with base and signed 20-bit displacement
7381 case 'T': // Likewise, plus an index
7382 Info.setAllowsMemory();
7387 class MSP430TargetInfo : public TargetInfo {
7388 static const char *const GCCRegNames[];
7391 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7392 : TargetInfo(Triple) {
7393 TLSSupported = false;
7398 LongAlign = LongLongAlign = 16;
7402 SizeType = UnsignedInt;
7403 IntMaxType = SignedLongLong;
7404 IntPtrType = SignedInt;
7405 PtrDiffType = SignedInt;
7406 SigAtomicType = SignedLong;
7407 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16");
7409 void getTargetDefines(const LangOptions &Opts,
7410 MacroBuilder &Builder) const override {
7411 Builder.defineMacro("MSP430");
7412 Builder.defineMacro("__MSP430__");
7413 // FIXME: defines for different 'flavours' of MCU
7415 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7416 // FIXME: Implement.
7419 bool hasFeature(StringRef Feature) const override {
7420 return Feature == "msp430";
7422 ArrayRef<const char *> getGCCRegNames() const override;
7423 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7427 bool validateAsmConstraint(const char *&Name,
7428 TargetInfo::ConstraintInfo &info) const override {
7431 case 'K': // the constant 1
7432 case 'L': // constant -1^20 .. 1^19
7433 case 'M': // constant 1-4:
7436 // No target constraints for now.
7439 const char *getClobbers() const override {
7440 // FIXME: Is this really right?
7443 BuiltinVaListKind getBuiltinVaListKind() const override {
7445 return TargetInfo::CharPtrBuiltinVaList;
7449 const char *const MSP430TargetInfo::GCCRegNames[] = {
7450 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7451 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
7453 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
7454 return llvm::makeArrayRef(GCCRegNames);
7457 // LLVM and Clang cannot be used directly to output native binaries for
7458 // target, but is used to compile C code to llvm bitcode with correct
7459 // type and alignment information.
7461 // TCE uses the llvm bitcode as input and uses it for generating customized
7462 // target processor and program binary. TCE co-design environment is
7463 // publicly available in http://tce.cs.tut.fi
7465 static const unsigned TCEOpenCLAddrSpaceMap[] = {
7469 5, // opencl_constant
7470 // FIXME: generic has to be added to the target
7471 0, // opencl_generic
7477 class TCETargetInfo : public TargetInfo {
7479 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7480 : TargetInfo(Triple) {
7481 TLSSupported = false;
7483 LongWidth = LongLongWidth = 32;
7486 LongAlign = LongLongAlign = 32;
7489 SizeType = UnsignedInt;
7490 IntMaxType = SignedLong;
7491 IntPtrType = SignedInt;
7492 PtrDiffType = SignedInt;
7497 LongDoubleWidth = 32;
7498 LongDoubleAlign = 32;
7499 FloatFormat = &llvm::APFloat::IEEEsingle();
7500 DoubleFormat = &llvm::APFloat::IEEEsingle();
7501 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
7502 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-"
7503 "i16:16:32-i32:32:32-i64:32:32-"
7504 "f32:32:32-f64:32:32-v64:32:32-"
7505 "v128:32:32-v256:32:32-v512:32:32-"
7506 "v1024:32:32-a0:0:32-n32");
7507 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
7508 UseAddrSpaceMapMangling = true;
7511 void getTargetDefines(const LangOptions &Opts,
7512 MacroBuilder &Builder) const override {
7513 DefineStd(Builder, "tce", Opts);
7514 Builder.defineMacro("__TCE__");
7515 Builder.defineMacro("__TCE_V1__");
7517 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
7519 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7520 const char *getClobbers() const override { return ""; }
7521 BuiltinVaListKind getBuiltinVaListKind() const override {
7522 return TargetInfo::VoidPtrBuiltinVaList;
7524 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7525 bool validateAsmConstraint(const char *&Name,
7526 TargetInfo::ConstraintInfo &info) const override {
7529 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7534 class TCELETargetInfo : public TCETargetInfo {
7536 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7537 : TCETargetInfo(Triple, Opts) {
7540 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-"
7541 "i16:16:32-i32:32:32-i64:32:32-"
7542 "f32:32:32-f64:32:32-v64:32:32-"
7543 "v128:32:32-v256:32:32-v512:32:32-"
7544 "v1024:32:32-a0:0:32-n32");
7548 virtual void getTargetDefines(const LangOptions &Opts,
7549 MacroBuilder &Builder) const {
7550 DefineStd(Builder, "tcele", Opts);
7551 Builder.defineMacro("__TCE__");
7552 Builder.defineMacro("__TCE_V1__");
7553 Builder.defineMacro("__TCELE__");
7554 Builder.defineMacro("__TCELE_V1__");
7559 class BPFTargetInfo : public TargetInfo {
7561 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7562 : TargetInfo(Triple) {
7563 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7564 SizeType = UnsignedLong;
7565 PtrDiffType = SignedLong;
7566 IntPtrType = SignedLong;
7567 IntMaxType = SignedLong;
7568 Int64Type = SignedLong;
7570 if (Triple.getArch() == llvm::Triple::bpfeb) {
7571 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
7573 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7575 MaxAtomicPromoteWidth = 64;
7576 MaxAtomicInlineWidth = 64;
7577 TLSSupported = false;
7579 void getTargetDefines(const LangOptions &Opts,
7580 MacroBuilder &Builder) const override {
7581 DefineStd(Builder, "bpf", Opts);
7582 Builder.defineMacro("__BPF__");
7584 bool hasFeature(StringRef Feature) const override {
7585 return Feature == "bpf";
7588 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7589 const char *getClobbers() const override {
7592 BuiltinVaListKind getBuiltinVaListKind() const override {
7593 return TargetInfo::VoidPtrBuiltinVaList;
7595 ArrayRef<const char *> getGCCRegNames() const override {
7598 bool validateAsmConstraint(const char *&Name,
7599 TargetInfo::ConstraintInfo &info) const override {
7602 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7607 class MipsTargetInfo : public TargetInfo {
7608 void setDataLayout() {
7612 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
7613 else if (ABI == "n32")
7614 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7615 else if (ABI == "n64")
7616 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7618 llvm_unreachable("Invalid ABI");
7621 resetDataLayout(("E-" + Layout).str());
7623 resetDataLayout(("e-" + Layout).str());
7627 static const Builtin::Info BuiltinInfo[];
7634 bool CanUseBSDABICalls;
7636 HardFloat, SoftFloat
7648 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7649 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
7650 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
7651 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
7652 HasMSA(false), HasFP64(false) {
7653 TheCXXABI.set(TargetCXXABI::GenericMIPS);
7655 setABI((getTriple().getArch() == llvm::Triple::mips ||
7656 getTriple().getArch() == llvm::Triple::mipsel)
7660 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
7662 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD ||
7663 Triple.getOS() == llvm::Triple::OpenBSD;
7666 bool isNaN2008Default() const {
7667 return CPU == "mips32r6" || CPU == "mips64r6";
7670 bool isFP64Default() const {
7671 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
7674 bool isNan2008() const override {
7678 bool processorSupportsGPR64() const {
7679 return llvm::StringSwitch<bool>(CPU)
7680 .Case("mips3", true)
7681 .Case("mips4", true)
7682 .Case("mips5", true)
7683 .Case("mips64", true)
7684 .Case("mips64r2", true)
7685 .Case("mips64r3", true)
7686 .Case("mips64r5", true)
7687 .Case("mips64r6", true)
7688 .Case("octeon", true)
7693 StringRef getABI() const override { return ABI; }
7694 bool setABI(const std::string &Name) override {
7695 if (Name == "o32") {
7701 if (Name == "n32") {
7706 if (Name == "n64") {
7714 void setO32ABITypes() {
7715 Int64Type = SignedLongLong;
7716 IntMaxType = Int64Type;
7717 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7718 LongDoubleWidth = LongDoubleAlign = 64;
7719 LongWidth = LongAlign = 32;
7720 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7721 PointerWidth = PointerAlign = 32;
7722 PtrDiffType = SignedInt;
7723 SizeType = UnsignedInt;
7727 void setN32N64ABITypes() {
7728 LongDoubleWidth = LongDoubleAlign = 128;
7729 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7730 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
7731 LongDoubleWidth = LongDoubleAlign = 64;
7732 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
7734 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7735 SuitableAlign = 128;
7738 void setN64ABITypes() {
7739 setN32N64ABITypes();
7740 if (getTriple().getOS() == llvm::Triple::OpenBSD) {
7741 Int64Type = SignedLongLong;
7743 Int64Type = SignedLong;
7745 IntMaxType = Int64Type;
7746 LongWidth = LongAlign = 64;
7747 PointerWidth = PointerAlign = 64;
7748 PtrDiffType = SignedLong;
7749 SizeType = UnsignedLong;
7752 void setN32ABITypes() {
7753 setN32N64ABITypes();
7754 Int64Type = SignedLongLong;
7755 IntMaxType = Int64Type;
7756 LongWidth = LongAlign = 32;
7757 PointerWidth = PointerAlign = 32;
7758 PtrDiffType = SignedInt;
7759 SizeType = UnsignedInt;
7762 bool setCPU(const std::string &Name) override {
7764 return llvm::StringSwitch<bool>(Name)
7765 .Case("mips1", true)
7766 .Case("mips2", true)
7767 .Case("mips3", true)
7768 .Case("mips4", true)
7769 .Case("mips5", true)
7770 .Case("mips32", true)
7771 .Case("mips32r2", true)
7772 .Case("mips32r3", true)
7773 .Case("mips32r5", true)
7774 .Case("mips32r6", true)
7775 .Case("mips64", true)
7776 .Case("mips64r2", true)
7777 .Case("mips64r3", true)
7778 .Case("mips64r5", true)
7779 .Case("mips64r6", true)
7780 .Case("octeon", true)
7781 .Case("p5600", true)
7784 const std::string& getCPU() const { return CPU; }
7786 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7788 const std::vector<std::string> &FeaturesVec) const override {
7791 if (CPU == "octeon")
7792 Features["mips64r2"] = Features["cnmips"] = true;
7794 Features[CPU] = true;
7795 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7798 void getTargetDefines(const LangOptions &Opts,
7799 MacroBuilder &Builder) const override {
7801 DefineStd(Builder, "MIPSEB", Opts);
7802 Builder.defineMacro("_MIPSEB");
7804 DefineStd(Builder, "MIPSEL", Opts);
7805 Builder.defineMacro("_MIPSEL");
7808 Builder.defineMacro("__mips__");
7809 Builder.defineMacro("_mips");
7811 Builder.defineMacro("mips");
7814 Builder.defineMacro("__mips", "32");
7815 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
7817 Builder.defineMacro("__mips", "64");
7818 Builder.defineMacro("__mips64");
7819 Builder.defineMacro("__mips64__");
7820 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
7823 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
7824 .Cases("mips32", "mips64", "1")
7825 .Cases("mips32r2", "mips64r2", "2")
7826 .Cases("mips32r3", "mips64r3", "3")
7827 .Cases("mips32r5", "mips64r5", "5")
7828 .Cases("mips32r6", "mips64r6", "6")
7830 if (!ISARev.empty())
7831 Builder.defineMacro("__mips_isa_rev", ISARev);
7834 Builder.defineMacro("__mips_o32");
7835 Builder.defineMacro("_ABIO32", "1");
7836 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
7837 } else if (ABI == "n32") {
7838 Builder.defineMacro("__mips_n32");
7839 Builder.defineMacro("_ABIN32", "2");
7840 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
7841 } else if (ABI == "n64") {
7842 Builder.defineMacro("__mips_n64");
7843 Builder.defineMacro("_ABI64", "3");
7844 Builder.defineMacro("_MIPS_SIM", "_ABI64");
7846 llvm_unreachable("Invalid ABI.");
7848 if (!IsNoABICalls) {
7849 Builder.defineMacro("__mips_abicalls");
7850 if (CanUseBSDABICalls)
7851 Builder.defineMacro("__ABICALLS__");
7854 Builder.defineMacro("__REGISTER_PREFIX__", "");
7858 Builder.defineMacro("__mips_hard_float", Twine(1));
7861 Builder.defineMacro("__mips_soft_float", Twine(1));
7866 Builder.defineMacro("__mips_single_float", Twine(1));
7868 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
7869 Builder.defineMacro("_MIPS_FPSET",
7870 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
7873 Builder.defineMacro("__mips16", Twine(1));
7876 Builder.defineMacro("__mips_micromips", Twine(1));
7879 Builder.defineMacro("__mips_nan2008", Twine(1));
7885 Builder.defineMacro("__mips_dsp_rev", Twine(1));
7886 Builder.defineMacro("__mips_dsp", Twine(1));
7889 Builder.defineMacro("__mips_dsp_rev", Twine(2));
7890 Builder.defineMacro("__mips_dspr2", Twine(1));
7891 Builder.defineMacro("__mips_dsp", Twine(1));
7896 Builder.defineMacro("__mips_msa", Twine(1));
7898 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
7899 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
7900 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
7902 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
7903 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
7905 // These shouldn't be defined for MIPS-I but there's no need to check
7906 // for that since MIPS-I isn't supported.
7907 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7908 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7909 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7911 // 32-bit MIPS processors don't have the necessary lld/scd instructions
7912 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
7913 // the instructions exist but using them violates the ABI since they
7914 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
7915 if (ABI == "n32" || ABI == "n64")
7916 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7919 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7920 return llvm::makeArrayRef(BuiltinInfo,
7921 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
7923 bool hasFeature(StringRef Feature) const override {
7924 return llvm::StringSwitch<bool>(Feature)
7926 .Case("fp64", HasFP64)
7929 BuiltinVaListKind getBuiltinVaListKind() const override {
7930 return TargetInfo::VoidPtrBuiltinVaList;
7932 ArrayRef<const char *> getGCCRegNames() const override {
7933 static const char *const GCCRegNames[] = {
7934 // CPU register names
7935 // Must match second column of GCCRegAliases
7936 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
7937 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
7938 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
7939 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
7940 // Floating point register names
7941 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
7942 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
7943 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
7944 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
7945 // Hi/lo and condition register names
7946 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
7947 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
7949 // MSA register names
7950 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
7951 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
7952 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
7953 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
7954 // MSA control register names
7955 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
7956 "$msarequest", "$msamap", "$msaunmap"
7958 return llvm::makeArrayRef(GCCRegNames);
7960 bool validateAsmConstraint(const char *&Name,
7961 TargetInfo::ConstraintInfo &Info) const override {
7965 case 'r': // CPU registers.
7966 case 'd': // Equivalent to "r" unless generating MIPS16 code.
7967 case 'y': // Equivalent to "r", backward compatibility only.
7968 case 'f': // floating-point registers.
7969 case 'c': // $25 for indirect jumps
7970 case 'l': // lo register
7971 case 'x': // hilo register pair
7972 Info.setAllowsRegister();
7974 case 'I': // Signed 16-bit constant
7975 case 'J': // Integer 0
7976 case 'K': // Unsigned 16-bit constant
7977 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
7978 case 'M': // Constants not loadable via lui, addiu, or ori
7979 case 'N': // Constant -1 to -65535
7980 case 'O': // A signed 15-bit constant
7981 case 'P': // A constant between 1 go 65535
7983 case 'R': // An address that can be used in a non-macro load or store
7984 Info.setAllowsMemory();
7987 if (Name[1] == 'C') { // An address usable by ll, and sc.
7988 Info.setAllowsMemory();
7989 Name++; // Skip over 'Z'.
7996 std::string convertConstraint(const char *&Constraint) const override {
7998 switch (*Constraint) {
7999 case 'Z': // Two-character constraint; add "^" hint for later parsing.
8000 if (Constraint[1] == 'C') {
8001 R = std::string("^") + std::string(Constraint, 2);
8007 return TargetInfo::convertConstraint(Constraint);
8010 const char *getClobbers() const override {
8011 // In GCC, $1 is not widely used in generated code (it's used only in a few
8012 // specific situations), so there is no real need for users to add it to
8013 // the clobbers list if they want to use it in their inline assembly code.
8015 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
8016 // code generation, so using it in inline assembly without adding it to the
8017 // clobbers list can cause conflicts between the inline assembly code and
8018 // the surrounding generated code.
8020 // Another problem is that LLVM is allowed to choose $1 for inline assembly
8021 // operands, which will conflict with the ".set at" assembler option (which
8022 // we use only for inline assembly, in order to maintain compatibility with
8023 // GCC) and will also conflict with the user's usage of $1.
8025 // The easiest way to avoid these conflicts and keep $1 as an allocatable
8026 // register for generated code is to automatically clobber $1 for all inline
8029 // FIXME: We should automatically clobber $1 only for inline assembly code
8030 // which actually uses it. This would allow LLVM to use $1 for inline
8031 // assembly operands if the user's assembly code doesn't use it.
8035 bool handleTargetFeatures(std::vector<std::string> &Features,
8036 DiagnosticsEngine &Diags) override {
8038 IsMicromips = false;
8039 IsNan2008 = isNaN2008Default();
8040 IsSingleFloat = false;
8041 FloatABI = HardFloat;
8043 HasFP64 = isFP64Default();
8045 for (const auto &Feature : Features) {
8046 if (Feature == "+single-float")
8047 IsSingleFloat = true;
8048 else if (Feature == "+soft-float")
8049 FloatABI = SoftFloat;
8050 else if (Feature == "+mips16")
8052 else if (Feature == "+micromips")
8054 else if (Feature == "+dsp")
8055 DspRev = std::max(DspRev, DSP1);
8056 else if (Feature == "+dspr2")
8057 DspRev = std::max(DspRev, DSP2);
8058 else if (Feature == "+msa")
8060 else if (Feature == "+fp64")
8062 else if (Feature == "-fp64")
8064 else if (Feature == "+nan2008")
8066 else if (Feature == "-nan2008")
8068 else if (Feature == "+noabicalls")
8069 IsNoABICalls = true;
8077 int getEHDataRegisterNumber(unsigned RegNo) const override {
8078 if (RegNo == 0) return 4;
8079 if (RegNo == 1) return 5;
8083 bool isCLZForZeroUndef() const override { return false; }
8085 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8086 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
8087 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8088 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8089 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
8090 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
8091 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
8092 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8093 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8094 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8095 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8096 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8098 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
8099 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8100 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8101 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
8102 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
8103 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
8104 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8105 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8106 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8107 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8108 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8111 return llvm::makeArrayRef(O32RegAliases);
8112 return llvm::makeArrayRef(NewABIRegAliases);
8115 bool hasInt128Type() const override {
8116 return ABI == "n32" || ABI == "n64";
8119 bool validateTarget(DiagnosticsEngine &Diags) const override {
8120 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
8121 // this yet. It's better to fail here than on the backend assertion.
8122 if (processorSupportsGPR64() && ABI == "o32") {
8123 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8127 // 64-bit ABI's require 64-bit CPU's.
8128 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
8129 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8133 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
8134 // can't handle this yet. It's better to fail here than on the
8135 // backend assertion.
8136 if ((getTriple().getArch() == llvm::Triple::mips64 ||
8137 getTriple().getArch() == llvm::Triple::mips64el) &&
8139 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8140 << ABI << getTriple().str();
8144 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
8145 // can't handle this yet. It's better to fail here than on the
8146 // backend assertion.
8147 if ((getTriple().getArch() == llvm::Triple::mips ||
8148 getTriple().getArch() == llvm::Triple::mipsel) &&
8149 (ABI == "n32" || ABI == "n64")) {
8150 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8151 << ABI << getTriple().str();
8159 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
8160 #define BUILTIN(ID, TYPE, ATTRS) \
8161 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8162 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8163 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8164 #include "clang/Basic/BuiltinsMips.def"
8167 class PNaClTargetInfo : public TargetInfo {
8169 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8170 : TargetInfo(Triple) {
8171 this->LongAlign = 32;
8172 this->LongWidth = 32;
8173 this->PointerAlign = 32;
8174 this->PointerWidth = 32;
8175 this->IntMaxType = TargetInfo::SignedLongLong;
8176 this->Int64Type = TargetInfo::SignedLongLong;
8177 this->DoubleAlign = 64;
8178 this->LongDoubleWidth = 64;
8179 this->LongDoubleAlign = 64;
8180 this->SizeType = TargetInfo::UnsignedInt;
8181 this->PtrDiffType = TargetInfo::SignedInt;
8182 this->IntPtrType = TargetInfo::SignedInt;
8183 this->RegParmMax = 0; // Disallow regparm
8186 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
8187 Builder.defineMacro("__le32__");
8188 Builder.defineMacro("__pnacl__");
8190 void getTargetDefines(const LangOptions &Opts,
8191 MacroBuilder &Builder) const override {
8192 getArchDefines(Opts, Builder);
8194 bool hasFeature(StringRef Feature) const override {
8195 return Feature == "pnacl";
8197 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8198 BuiltinVaListKind getBuiltinVaListKind() const override {
8199 return TargetInfo::PNaClABIBuiltinVaList;
8201 ArrayRef<const char *> getGCCRegNames() const override;
8202 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
8203 bool validateAsmConstraint(const char *&Name,
8204 TargetInfo::ConstraintInfo &Info) const override {
8208 const char *getClobbers() const override {
8213 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
8217 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
8221 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
8222 class NaClMips32TargetInfo : public MipsTargetInfo {
8224 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8225 : MipsTargetInfo(Triple, Opts) {}
8227 BuiltinVaListKind getBuiltinVaListKind() const override {
8228 return TargetInfo::PNaClABIBuiltinVaList;
8232 class Le64TargetInfo : public TargetInfo {
8233 static const Builtin::Info BuiltinInfo[];
8236 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8237 : TargetInfo(Triple) {
8238 NoAsmVariants = true;
8239 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
8240 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8241 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
8244 void getTargetDefines(const LangOptions &Opts,
8245 MacroBuilder &Builder) const override {
8246 DefineStd(Builder, "unix", Opts);
8247 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
8248 Builder.defineMacro("__ELF__");
8250 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8251 return llvm::makeArrayRef(BuiltinInfo,
8252 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
8254 BuiltinVaListKind getBuiltinVaListKind() const override {
8255 return TargetInfo::PNaClABIBuiltinVaList;
8257 const char *getClobbers() const override { return ""; }
8258 ArrayRef<const char *> getGCCRegNames() const override {
8261 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8264 bool validateAsmConstraint(const char *&Name,
8265 TargetInfo::ConstraintInfo &Info) const override {
8269 bool hasProtectedVisibility() const override { return false; }
8272 class WebAssemblyTargetInfo : public TargetInfo {
8273 static const Builtin::Info BuiltinInfo[];
8281 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
8282 : TargetInfo(T), SIMDLevel(NoSIMD) {
8283 NoAsmVariants = true;
8284 SuitableAlign = 128;
8285 LargeArrayMinWidth = 128;
8286 LargeArrayAlign = 128;
8287 SimdDefaultAlign = 128;
8288 SigAtomicType = SignedLong;
8289 LongDoubleWidth = LongDoubleAlign = 128;
8290 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8291 SizeType = UnsignedInt;
8292 PtrDiffType = SignedInt;
8293 IntPtrType = SignedInt;
8297 void getTargetDefines(const LangOptions &Opts,
8298 MacroBuilder &Builder) const override {
8299 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
8300 if (SIMDLevel >= SIMD128)
8301 Builder.defineMacro("__wasm_simd128__");
8306 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8308 const std::vector<std::string> &FeaturesVec) const override {
8309 if (CPU == "bleeding-edge")
8310 Features["simd128"] = true;
8311 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8313 bool hasFeature(StringRef Feature) const final {
8314 return llvm::StringSwitch<bool>(Feature)
8315 .Case("simd128", SIMDLevel >= SIMD128)
8318 bool handleTargetFeatures(std::vector<std::string> &Features,
8319 DiagnosticsEngine &Diags) final {
8320 for (const auto &Feature : Features) {
8321 if (Feature == "+simd128") {
8322 SIMDLevel = std::max(SIMDLevel, SIMD128);
8325 if (Feature == "-simd128") {
8326 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
8330 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
8331 << "-target-feature";
8336 bool setCPU(const std::string &Name) final {
8337 return llvm::StringSwitch<bool>(Name)
8339 .Case("bleeding-edge", true)
8340 .Case("generic", true)
8343 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
8344 return llvm::makeArrayRef(BuiltinInfo,
8345 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
8347 BuiltinVaListKind getBuiltinVaListKind() const final {
8348 return VoidPtrBuiltinVaList;
8350 ArrayRef<const char *> getGCCRegNames() const final {
8353 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
8357 validateAsmConstraint(const char *&Name,
8358 TargetInfo::ConstraintInfo &Info) const final {
8361 const char *getClobbers() const final { return ""; }
8362 bool isCLZForZeroUndef() const final { return false; }
8363 bool hasInt128Type() const final { return true; }
8364 IntType getIntTypeByWidth(unsigned BitWidth,
8365 bool IsSigned) const final {
8366 // WebAssembly prefers long long for explicitly 64-bit integers.
8367 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8368 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8370 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8371 bool IsSigned) const final {
8372 // WebAssembly uses long long for int_least64_t and int_fast64_t.
8373 return BitWidth == 64
8374 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8375 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8379 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
8380 #define BUILTIN(ID, TYPE, ATTRS) \
8381 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8382 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8383 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8384 #include "clang/Basic/BuiltinsWebAssembly.def"
8387 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
8389 explicit WebAssembly32TargetInfo(const llvm::Triple &T,
8390 const TargetOptions &Opts)
8391 : WebAssemblyTargetInfo(T, Opts) {
8392 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
8393 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
8397 void getTargetDefines(const LangOptions &Opts,
8398 MacroBuilder &Builder) const override {
8399 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8400 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
8404 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
8406 explicit WebAssembly64TargetInfo(const llvm::Triple &T,
8407 const TargetOptions &Opts)
8408 : WebAssemblyTargetInfo(T, Opts) {
8409 LongAlign = LongWidth = 64;
8410 PointerAlign = PointerWidth = 64;
8411 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8412 SizeType = UnsignedLong;
8413 PtrDiffType = SignedLong;
8414 IntPtrType = SignedLong;
8415 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
8419 void getTargetDefines(const LangOptions &Opts,
8420 MacroBuilder &Builder) const override {
8421 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8422 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
8426 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
8427 #define BUILTIN(ID, TYPE, ATTRS) \
8428 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8429 #include "clang/Basic/BuiltinsLe64.def"
8432 static const unsigned SPIRAddrSpaceMap[] = {
8436 2, // opencl_constant
8437 4, // opencl_generic
8442 class SPIRTargetInfo : public TargetInfo {
8444 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8445 : TargetInfo(Triple) {
8446 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
8447 "SPIR target must use unknown OS");
8448 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
8449 "SPIR target must use unknown environment type");
8450 TLSSupported = false;
8451 LongWidth = LongAlign = 64;
8452 AddrSpaceMap = &SPIRAddrSpaceMap;
8453 UseAddrSpaceMapMangling = true;
8454 // Define available target features
8455 // These must be defined in sorted order!
8456 NoAsmVariants = true;
8458 void getTargetDefines(const LangOptions &Opts,
8459 MacroBuilder &Builder) const override {
8460 DefineStd(Builder, "SPIR", Opts);
8462 bool hasFeature(StringRef Feature) const override {
8463 return Feature == "spir";
8466 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8467 const char *getClobbers() const override { return ""; }
8468 ArrayRef<const char *> getGCCRegNames() const override { return None; }
8469 bool validateAsmConstraint(const char *&Name,
8470 TargetInfo::ConstraintInfo &info) const override {
8473 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8476 BuiltinVaListKind getBuiltinVaListKind() const override {
8477 return TargetInfo::VoidPtrBuiltinVaList;
8480 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
8481 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
8485 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
8486 return CC_SpirFunction;
8489 void setSupportedOpenCLOpts() override {
8490 // Assume all OpenCL extensions and optional core features are supported
8491 // for SPIR since it is a generic target.
8492 getSupportedOpenCLOpts().supportAll();
8496 class SPIR32TargetInfo : public SPIRTargetInfo {
8498 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8499 : SPIRTargetInfo(Triple, Opts) {
8500 PointerWidth = PointerAlign = 32;
8501 SizeType = TargetInfo::UnsignedInt;
8502 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
8503 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
8504 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8506 void getTargetDefines(const LangOptions &Opts,
8507 MacroBuilder &Builder) const override {
8508 DefineStd(Builder, "SPIR32", Opts);
8512 class SPIR64TargetInfo : public SPIRTargetInfo {
8514 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8515 : SPIRTargetInfo(Triple, Opts) {
8516 PointerWidth = PointerAlign = 64;
8517 SizeType = TargetInfo::UnsignedLong;
8518 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
8519 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
8520 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8522 void getTargetDefines(const LangOptions &Opts,
8523 MacroBuilder &Builder) const override {
8524 DefineStd(Builder, "SPIR64", Opts);
8528 class XCoreTargetInfo : public TargetInfo {
8529 static const Builtin::Info BuiltinInfo[];
8531 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8532 : TargetInfo(Triple) {
8533 NoAsmVariants = true;
8536 DoubleAlign = LongDoubleAlign = 32;
8537 SizeType = UnsignedInt;
8538 PtrDiffType = SignedInt;
8539 IntPtrType = SignedInt;
8540 WCharType = UnsignedChar;
8541 WIntType = UnsignedInt;
8542 UseZeroLengthBitfieldAlignment = true;
8543 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
8544 "-f64:32-a:0:32-n32");
8546 void getTargetDefines(const LangOptions &Opts,
8547 MacroBuilder &Builder) const override {
8548 Builder.defineMacro("__XS1B__");
8550 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8551 return llvm::makeArrayRef(BuiltinInfo,
8552 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
8554 BuiltinVaListKind getBuiltinVaListKind() const override {
8555 return TargetInfo::VoidPtrBuiltinVaList;
8557 const char *getClobbers() const override {
8560 ArrayRef<const char *> getGCCRegNames() const override {
8561 static const char * const GCCRegNames[] = {
8562 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8563 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
8565 return llvm::makeArrayRef(GCCRegNames);
8567 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8570 bool validateAsmConstraint(const char *&Name,
8571 TargetInfo::ConstraintInfo &Info) const override {
8574 int getEHDataRegisterNumber(unsigned RegNo) const override {
8575 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
8576 return (RegNo < 2)? RegNo : -1;
8578 bool allowsLargerPreferedTypeAlignment() const override {
8583 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
8584 #define BUILTIN(ID, TYPE, ATTRS) \
8585 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8586 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8587 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8588 #include "clang/Basic/BuiltinsXCore.def"
8591 // x86_32 Android target
8592 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
8594 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8595 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
8597 LongDoubleWidth = 64;
8598 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8602 // x86_64 Android target
8603 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
8605 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8606 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
8607 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8610 bool useFloat128ManglingForLongDouble() const override {
8615 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
8616 class RenderScript32TargetInfo : public ARMleTargetInfo {
8618 RenderScript32TargetInfo(const llvm::Triple &Triple,
8619 const TargetOptions &Opts)
8620 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
8622 Triple.getEnvironmentName()),
8624 IsRenderScriptTarget = true;
8625 LongWidth = LongAlign = 64;
8627 void getTargetDefines(const LangOptions &Opts,
8628 MacroBuilder &Builder) const override {
8629 Builder.defineMacro("__RENDERSCRIPT__");
8630 ARMleTargetInfo::getTargetDefines(Opts, Builder);
8634 // 64-bit RenderScript is aarch64
8635 class RenderScript64TargetInfo : public AArch64leTargetInfo {
8637 RenderScript64TargetInfo(const llvm::Triple &Triple,
8638 const TargetOptions &Opts)
8639 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
8641 Triple.getEnvironmentName()),
8643 IsRenderScriptTarget = true;
8646 void getTargetDefines(const LangOptions &Opts,
8647 MacroBuilder &Builder) const override {
8648 Builder.defineMacro("__RENDERSCRIPT__");
8649 AArch64leTargetInfo::getTargetDefines(Opts, Builder);
8653 /// Information about a specific microcontroller.
8656 const char *DefineName;
8659 // This list should be kept up-to-date with AVRDevices.td in LLVM.
8660 static ArrayRef<MCUInfo> AVRMcus = {
8661 { "at90s1200", "__AVR_AT90S1200__" },
8662 { "attiny11", "__AVR_ATtiny11__" },
8663 { "attiny12", "__AVR_ATtiny12__" },
8664 { "attiny15", "__AVR_ATtiny15__" },
8665 { "attiny28", "__AVR_ATtiny28__" },
8666 { "at90s2313", "__AVR_AT90S2313__" },
8667 { "at90s2323", "__AVR_AT90S2323__" },
8668 { "at90s2333", "__AVR_AT90S2333__" },
8669 { "at90s2343", "__AVR_AT90S2343__" },
8670 { "attiny22", "__AVR_ATtiny22__" },
8671 { "attiny26", "__AVR_ATtiny26__" },
8672 { "at86rf401", "__AVR_AT86RF401__" },
8673 { "at90s4414", "__AVR_AT90S4414__" },
8674 { "at90s4433", "__AVR_AT90S4433__" },
8675 { "at90s4434", "__AVR_AT90S4434__" },
8676 { "at90s8515", "__AVR_AT90S8515__" },
8677 { "at90c8534", "__AVR_AT90c8534__" },
8678 { "at90s8535", "__AVR_AT90S8535__" },
8679 { "ata5272", "__AVR_ATA5272__" },
8680 { "attiny13", "__AVR_ATtiny13__" },
8681 { "attiny13a", "__AVR_ATtiny13A__" },
8682 { "attiny2313", "__AVR_ATtiny2313__" },
8683 { "attiny2313a", "__AVR_ATtiny2313A__" },
8684 { "attiny24", "__AVR_ATtiny24__" },
8685 { "attiny24a", "__AVR_ATtiny24A__" },
8686 { "attiny4313", "__AVR_ATtiny4313__" },
8687 { "attiny44", "__AVR_ATtiny44__" },
8688 { "attiny44a", "__AVR_ATtiny44A__" },
8689 { "attiny84", "__AVR_ATtiny84__" },
8690 { "attiny84a", "__AVR_ATtiny84A__" },
8691 { "attiny25", "__AVR_ATtiny25__" },
8692 { "attiny45", "__AVR_ATtiny45__" },
8693 { "attiny85", "__AVR_ATtiny85__" },
8694 { "attiny261", "__AVR_ATtiny261__" },
8695 { "attiny261a", "__AVR_ATtiny261A__" },
8696 { "attiny461", "__AVR_ATtiny461__" },
8697 { "attiny461a", "__AVR_ATtiny461A__" },
8698 { "attiny861", "__AVR_ATtiny861__" },
8699 { "attiny861a", "__AVR_ATtiny861A__" },
8700 { "attiny87", "__AVR_ATtiny87__" },
8701 { "attiny43u", "__AVR_ATtiny43U__" },
8702 { "attiny48", "__AVR_ATtiny48__" },
8703 { "attiny88", "__AVR_ATtiny88__" },
8704 { "attiny828", "__AVR_ATtiny828__" },
8705 { "at43usb355", "__AVR_AT43USB355__" },
8706 { "at76c711", "__AVR_AT76C711__" },
8707 { "atmega103", "__AVR_ATmega103__" },
8708 { "at43usb320", "__AVR_AT43USB320__" },
8709 { "attiny167", "__AVR_ATtiny167__" },
8710 { "at90usb82", "__AVR_AT90USB82__" },
8711 { "at90usb162", "__AVR_AT90USB162__" },
8712 { "ata5505", "__AVR_ATA5505__" },
8713 { "atmega8u2", "__AVR_ATmega8U2__" },
8714 { "atmega16u2", "__AVR_ATmega16U2__" },
8715 { "atmega32u2", "__AVR_ATmega32U2__" },
8716 { "attiny1634", "__AVR_ATtiny1634__" },
8717 { "atmega8", "__AVR_ATmega8__" },
8718 { "ata6289", "__AVR_ATA6289__" },
8719 { "atmega8a", "__AVR_ATmega8A__" },
8720 { "ata6285", "__AVR_ATA6285__" },
8721 { "ata6286", "__AVR_ATA6286__" },
8722 { "atmega48", "__AVR_ATmega48__" },
8723 { "atmega48a", "__AVR_ATmega48A__" },
8724 { "atmega48pa", "__AVR_ATmega48PA__" },
8725 { "atmega48p", "__AVR_ATmega48P__" },
8726 { "atmega88", "__AVR_ATmega88__" },
8727 { "atmega88a", "__AVR_ATmega88A__" },
8728 { "atmega88p", "__AVR_ATmega88P__" },
8729 { "atmega88pa", "__AVR_ATmega88PA__" },
8730 { "atmega8515", "__AVR_ATmega8515__" },
8731 { "atmega8535", "__AVR_ATmega8535__" },
8732 { "atmega8hva", "__AVR_ATmega8HVA__" },
8733 { "at90pwm1", "__AVR_AT90PWM1__" },
8734 { "at90pwm2", "__AVR_AT90PWM2__" },
8735 { "at90pwm2b", "__AVR_AT90PWM2B__" },
8736 { "at90pwm3", "__AVR_AT90PWM3__" },
8737 { "at90pwm3b", "__AVR_AT90PWM3B__" },
8738 { "at90pwm81", "__AVR_AT90PWM81__" },
8739 { "ata5790", "__AVR_ATA5790__" },
8740 { "ata5795", "__AVR_ATA5795__" },
8741 { "atmega16", "__AVR_ATmega16__" },
8742 { "atmega16a", "__AVR_ATmega16A__" },
8743 { "atmega161", "__AVR_ATmega161__" },
8744 { "atmega162", "__AVR_ATmega162__" },
8745 { "atmega163", "__AVR_ATmega163__" },
8746 { "atmega164a", "__AVR_ATmega164A__" },
8747 { "atmega164p", "__AVR_ATmega164P__" },
8748 { "atmega164pa", "__AVR_ATmega164PA__" },
8749 { "atmega165", "__AVR_ATmega165__" },
8750 { "atmega165a", "__AVR_ATmega165A__" },
8751 { "atmega165p", "__AVR_ATmega165P__" },
8752 { "atmega165pa", "__AVR_ATmega165PA__" },
8753 { "atmega168", "__AVR_ATmega168__" },
8754 { "atmega168a", "__AVR_ATmega168A__" },
8755 { "atmega168p", "__AVR_ATmega168P__" },
8756 { "atmega168pa", "__AVR_ATmega168PA__" },
8757 { "atmega169", "__AVR_ATmega169__" },
8758 { "atmega169a", "__AVR_ATmega169A__" },
8759 { "atmega169p", "__AVR_ATmega169P__" },
8760 { "atmega169pa", "__AVR_ATmega169PA__" },
8761 { "atmega32", "__AVR_ATmega32__" },
8762 { "atmega32a", "__AVR_ATmega32A__" },
8763 { "atmega323", "__AVR_ATmega323__" },
8764 { "atmega324a", "__AVR_ATmega324A__" },
8765 { "atmega324p", "__AVR_ATmega324P__" },
8766 { "atmega324pa", "__AVR_ATmega324PA__" },
8767 { "atmega325", "__AVR_ATmega325__" },
8768 { "atmega325a", "__AVR_ATmega325A__" },
8769 { "atmega325p", "__AVR_ATmega325P__" },
8770 { "atmega325pa", "__AVR_ATmega325PA__" },
8771 { "atmega3250", "__AVR_ATmega3250__" },
8772 { "atmega3250a", "__AVR_ATmega3250A__" },
8773 { "atmega3250p", "__AVR_ATmega3250P__" },
8774 { "atmega3250pa", "__AVR_ATmega3250PA__" },
8775 { "atmega328", "__AVR_ATmega328__" },
8776 { "atmega328p", "__AVR_ATmega328P__" },
8777 { "atmega329", "__AVR_ATmega329__" },
8778 { "atmega329a", "__AVR_ATmega329A__" },
8779 { "atmega329p", "__AVR_ATmega329P__" },
8780 { "atmega329pa", "__AVR_ATmega329PA__" },
8781 { "atmega3290", "__AVR_ATmega3290__" },
8782 { "atmega3290a", "__AVR_ATmega3290A__" },
8783 { "atmega3290p", "__AVR_ATmega3290P__" },
8784 { "atmega3290pa", "__AVR_ATmega3290PA__" },
8785 { "atmega406", "__AVR_ATmega406__" },
8786 { "atmega64", "__AVR_ATmega64__" },
8787 { "atmega64a", "__AVR_ATmega64A__" },
8788 { "atmega640", "__AVR_ATmega640__" },
8789 { "atmega644", "__AVR_ATmega644__" },
8790 { "atmega644a", "__AVR_ATmega644A__" },
8791 { "atmega644p", "__AVR_ATmega644P__" },
8792 { "atmega644pa", "__AVR_ATmega644PA__" },
8793 { "atmega645", "__AVR_ATmega645__" },
8794 { "atmega645a", "__AVR_ATmega645A__" },
8795 { "atmega645p", "__AVR_ATmega645P__" },
8796 { "atmega649", "__AVR_ATmega649__" },
8797 { "atmega649a", "__AVR_ATmega649A__" },
8798 { "atmega649p", "__AVR_ATmega649P__" },
8799 { "atmega6450", "__AVR_ATmega6450__" },
8800 { "atmega6450a", "__AVR_ATmega6450A__" },
8801 { "atmega6450p", "__AVR_ATmega6450P__" },
8802 { "atmega6490", "__AVR_ATmega6490__" },
8803 { "atmega6490a", "__AVR_ATmega6490A__" },
8804 { "atmega6490p", "__AVR_ATmega6490P__" },
8805 { "atmega64rfr2", "__AVR_ATmega64RFR2__" },
8806 { "atmega644rfr2", "__AVR_ATmega644RFR2__" },
8807 { "atmega16hva", "__AVR_ATmega16HVA__" },
8808 { "atmega16hva2", "__AVR_ATmega16HVA2__" },
8809 { "atmega16hvb", "__AVR_ATmega16HVB__" },
8810 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" },
8811 { "atmega32hvb", "__AVR_ATmega32HVB__" },
8812 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" },
8813 { "atmega64hve", "__AVR_ATmega64HVE__" },
8814 { "at90can32", "__AVR_AT90CAN32__" },
8815 { "at90can64", "__AVR_AT90CAN64__" },
8816 { "at90pwm161", "__AVR_AT90PWM161__" },
8817 { "at90pwm216", "__AVR_AT90PWM216__" },
8818 { "at90pwm316", "__AVR_AT90PWM316__" },
8819 { "atmega32c1", "__AVR_ATmega32C1__" },
8820 { "atmega64c1", "__AVR_ATmega64C1__" },
8821 { "atmega16m1", "__AVR_ATmega16M1__" },
8822 { "atmega32m1", "__AVR_ATmega32M1__" },
8823 { "atmega64m1", "__AVR_ATmega64M1__" },
8824 { "atmega16u4", "__AVR_ATmega16U4__" },
8825 { "atmega32u4", "__AVR_ATmega32U4__" },
8826 { "atmega32u6", "__AVR_ATmega32U6__" },
8827 { "at90usb646", "__AVR_AT90USB646__" },
8828 { "at90usb647", "__AVR_AT90USB647__" },
8829 { "at90scr100", "__AVR_AT90SCR100__" },
8830 { "at94k", "__AVR_AT94K__" },
8831 { "m3000", "__AVR_AT000__" },
8832 { "atmega128", "__AVR_ATmega128__" },
8833 { "atmega128a", "__AVR_ATmega128A__" },
8834 { "atmega1280", "__AVR_ATmega1280__" },
8835 { "atmega1281", "__AVR_ATmega1281__" },
8836 { "atmega1284", "__AVR_ATmega1284__" },
8837 { "atmega1284p", "__AVR_ATmega1284P__" },
8838 { "atmega128rfa1", "__AVR_ATmega128RFA1__" },
8839 { "atmega128rfr2", "__AVR_ATmega128RFR2__" },
8840 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" },
8841 { "at90can128", "__AVR_AT90CAN128__" },
8842 { "at90usb1286", "__AVR_AT90USB1286__" },
8843 { "at90usb1287", "__AVR_AT90USB1287__" },
8844 { "atmega2560", "__AVR_ATmega2560__" },
8845 { "atmega2561", "__AVR_ATmega2561__" },
8846 { "atmega256rfr2", "__AVR_ATmega256RFR2__" },
8847 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" },
8848 { "atxmega16a4", "__AVR_ATxmega16A4__" },
8849 { "atxmega16a4u", "__AVR_ATxmega16a4U__" },
8850 { "atxmega16c4", "__AVR_ATxmega16C4__" },
8851 { "atxmega16d4", "__AVR_ATxmega16D4__" },
8852 { "atxmega32a4", "__AVR_ATxmega32A4__" },
8853 { "atxmega32a4u", "__AVR_ATxmega32A4U__" },
8854 { "atxmega32c4", "__AVR_ATxmega32C4__" },
8855 { "atxmega32d4", "__AVR_ATxmega32D4__" },
8856 { "atxmega32e5", "__AVR_ATxmega32E5__" },
8857 { "atxmega16e5", "__AVR_ATxmega16E5__" },
8858 { "atxmega8e5", "__AVR_ATxmega8E5__" },
8859 { "atxmega32x1", "__AVR_ATxmega32X1__" },
8860 { "atxmega64a3", "__AVR_ATxmega64A3__" },
8861 { "atxmega64a3u", "__AVR_ATxmega64A3U__" },
8862 { "atxmega64a4u", "__AVR_ATxmega64A4U__" },
8863 { "atxmega64b1", "__AVR_ATxmega64B1__" },
8864 { "atxmega64b3", "__AVR_ATxmega64B3__" },
8865 { "atxmega64c3", "__AVR_ATxmega64C3__" },
8866 { "atxmega64d3", "__AVR_ATxmega64D3__" },
8867 { "atxmega64d4", "__AVR_ATxmega64D4__" },
8868 { "atxmega64a1", "__AVR_ATxmega64A1__" },
8869 { "atxmega64a1u", "__AVR_ATxmega64A1U__" },
8870 { "atxmega128a3", "__AVR_ATxmega128A3__" },
8871 { "atxmega128a3u", "__AVR_ATxmega128A3U__" },
8872 { "atxmega128b1", "__AVR_ATxmega128B1__" },
8873 { "atxmega128b3", "__AVR_ATxmega128B3__" },
8874 { "atxmega128c3", "__AVR_ATxmega128C3__" },
8875 { "atxmega128d3", "__AVR_ATxmega128D3__" },
8876 { "atxmega128d4", "__AVR_ATxmega128D4__" },
8877 { "atxmega192a3", "__AVR_ATxmega192A3__" },
8878 { "atxmega192a3u", "__AVR_ATxmega192A3U__" },
8879 { "atxmega192c3", "__AVR_ATxmega192C3__" },
8880 { "atxmega192d3", "__AVR_ATxmega192D3__" },
8881 { "atxmega256a3", "__AVR_ATxmega256A3__" },
8882 { "atxmega256a3u", "__AVR_ATxmega256A3U__" },
8883 { "atxmega256a3b", "__AVR_ATxmega256A3B__" },
8884 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" },
8885 { "atxmega256c3", "__AVR_ATxmega256C3__" },
8886 { "atxmega256d3", "__AVR_ATxmega256D3__" },
8887 { "atxmega384c3", "__AVR_ATxmega384C3__" },
8888 { "atxmega384d3", "__AVR_ATxmega384D3__" },
8889 { "atxmega128a1", "__AVR_ATxmega128A1__" },
8890 { "atxmega128a1u", "__AVR_ATxmega128A1U__" },
8891 { "atxmega128a4u", "__AVR_ATxmega128a4U__" },
8892 { "attiny4", "__AVR_ATtiny4__" },
8893 { "attiny5", "__AVR_ATtiny5__" },
8894 { "attiny9", "__AVR_ATtiny9__" },
8895 { "attiny10", "__AVR_ATtiny10__" },
8896 { "attiny20", "__AVR_ATtiny20__" },
8897 { "attiny40", "__AVR_ATtiny40__" },
8898 { "attiny102", "__AVR_ATtiny102__" },
8899 { "attiny104", "__AVR_ATtiny104__" },
8903 class AVRTargetInfo : public TargetInfo {
8905 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8906 : TargetInfo(Triple) {
8907 TLSSupported = false;
8917 DefaultAlignForAttributeAligned = 8;
8924 DoubleFormat = &llvm::APFloat::IEEEsingle();
8925 LongDoubleWidth = 32;
8926 LongDoubleAlign = 8;
8927 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
8928 SizeType = UnsignedInt;
8929 PtrDiffType = SignedInt;
8930 IntPtrType = SignedInt;
8931 Char16Type = UnsignedInt;
8932 WCharType = SignedInt;
8933 WIntType = SignedInt;
8934 Char32Type = UnsignedLong;
8935 SigAtomicType = SignedChar;
8936 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
8937 "-f32:32:32-f64:64:64-n8");
8940 void getTargetDefines(const LangOptions &Opts,
8941 MacroBuilder &Builder) const override {
8942 Builder.defineMacro("AVR");
8943 Builder.defineMacro("__AVR");
8944 Builder.defineMacro("__AVR__");
8946 if (!this->CPU.empty()) {
8947 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(),
8948 [&](const MCUInfo &Info) { return Info.Name == this->CPU; });
8950 if (It != AVRMcus.end())
8951 Builder.defineMacro(It->DefineName);
8955 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8959 BuiltinVaListKind getBuiltinVaListKind() const override {
8960 return TargetInfo::VoidPtrBuiltinVaList;
8963 const char *getClobbers() const override {
8967 ArrayRef<const char *> getGCCRegNames() const override {
8968 static const char * const GCCRegNames[] = {
8969 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8970 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8971 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8972 "r24", "r25", "X", "Y", "Z", "SP"
8974 return llvm::makeArrayRef(GCCRegNames);
8977 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8981 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
8982 static const TargetInfo::AddlRegName AddlRegNames[] = {
8983 { { "r26", "r27"}, 26 },
8984 { { "r28", "r29"}, 27 },
8985 { { "r30", "r31"}, 28 },
8986 { { "SPL", "SPH"}, 29 },
8988 return llvm::makeArrayRef(AddlRegNames);
8991 bool validateAsmConstraint(const char *&Name,
8992 TargetInfo::ConstraintInfo &Info) const override {
8993 // There aren't any multi-character AVR specific constraints.
8994 if (StringRef(Name).size() > 1) return false;
8997 default: return false;
8998 case 'a': // Simple upper registers
8999 case 'b': // Base pointer registers pairs
9000 case 'd': // Upper register
9001 case 'l': // Lower registers
9002 case 'e': // Pointer register pairs
9003 case 'q': // Stack pointer register
9004 case 'r': // Any register
9005 case 'w': // Special upper register pairs
9006 case 't': // Temporary register
9007 case 'x': case 'X': // Pointer register pair X
9008 case 'y': case 'Y': // Pointer register pair Y
9009 case 'z': case 'Z': // Pointer register pair Z
9010 Info.setAllowsRegister();
9012 case 'I': // 6-bit positive integer constant
9013 Info.setRequiresImmediate(0, 63);
9015 case 'J': // 6-bit negative integer constant
9016 Info.setRequiresImmediate(-63, 0);
9018 case 'K': // Integer constant (Range: 2)
9019 Info.setRequiresImmediate(2);
9021 case 'L': // Integer constant (Range: 0)
9022 Info.setRequiresImmediate(0);
9024 case 'M': // 8-bit integer constant
9025 Info.setRequiresImmediate(0, 0xff);
9027 case 'N': // Integer constant (Range: -1)
9028 Info.setRequiresImmediate(-1);
9030 case 'O': // Integer constant (Range: 8, 16, 24)
9031 Info.setRequiresImmediate({8, 16, 24});
9033 case 'P': // Integer constant (Range: 1)
9034 Info.setRequiresImmediate(1);
9036 case 'R': // Integer constant (Range: -6 to 5)
9037 Info.setRequiresImmediate(-6, 5);
9039 case 'G': // Floating point constant
9040 case 'Q': // A memory address based on Y or Z pointer with displacement.
9047 IntType getIntTypeByWidth(unsigned BitWidth,
9048 bool IsSigned) const final {
9049 // AVR prefers int for 16-bit integers.
9050 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt)
9051 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
9054 IntType getLeastIntTypeByWidth(unsigned BitWidth,
9055 bool IsSigned) const final {
9056 // AVR uses int for int_least16_t and int_fast16_t.
9057 return BitWidth == 16
9058 ? (IsSigned ? SignedInt : UnsignedInt)
9059 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
9062 bool setCPU(const std::string &Name) override {
9063 bool IsFamily = llvm::StringSwitch<bool>(Name)
9066 .Case("avr25", true)
9068 .Case("avr31", true)
9069 .Case("avr35", true)
9072 .Case("avr51", true)
9074 .Case("avrxmega1", true)
9075 .Case("avrxmega2", true)
9076 .Case("avrxmega3", true)
9077 .Case("avrxmega4", true)
9078 .Case("avrxmega5", true)
9079 .Case("avrxmega6", true)
9080 .Case("avrxmega7", true)
9081 .Case("avrtiny", true)
9084 if (IsFamily) this->CPU = Name;
9086 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(),
9087 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end();
9089 if (IsMCU) this->CPU = Name;
9091 return IsFamily || IsMCU;
9098 } // end anonymous namespace
9100 //===----------------------------------------------------------------------===//
9102 //===----------------------------------------------------------------------===//
9104 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
9105 const TargetOptions &Opts) {
9106 llvm::Triple::OSType os = Triple.getOS();
9108 switch (Triple.getArch()) {
9112 case llvm::Triple::xcore:
9113 return new XCoreTargetInfo(Triple, Opts);
9115 case llvm::Triple::hexagon:
9116 return new HexagonTargetInfo(Triple, Opts);
9118 case llvm::Triple::lanai:
9119 return new LanaiTargetInfo(Triple, Opts);
9121 case llvm::Triple::aarch64:
9122 if (Triple.isOSDarwin())
9123 return new DarwinAArch64TargetInfo(Triple, Opts);
9126 case llvm::Triple::CloudABI:
9127 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts);
9128 case llvm::Triple::FreeBSD:
9129 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9130 case llvm::Triple::Fuchsia:
9131 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9132 case llvm::Triple::Linux:
9133 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9134 case llvm::Triple::NetBSD:
9135 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9136 case llvm::Triple::OpenBSD:
9137 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9139 return new AArch64leTargetInfo(Triple, Opts);
9142 case llvm::Triple::aarch64_be:
9144 case llvm::Triple::FreeBSD:
9145 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9146 case llvm::Triple::Fuchsia:
9147 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9148 case llvm::Triple::Linux:
9149 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9150 case llvm::Triple::NetBSD:
9151 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9153 return new AArch64beTargetInfo(Triple, Opts);
9156 case llvm::Triple::arm:
9157 case llvm::Triple::thumb:
9158 if (Triple.isOSBinFormatMachO())
9159 return new DarwinARMTargetInfo(Triple, Opts);
9162 case llvm::Triple::CloudABI:
9163 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts);
9164 case llvm::Triple::Linux:
9165 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts);
9166 case llvm::Triple::FreeBSD:
9167 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9168 case llvm::Triple::NetBSD:
9169 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9170 case llvm::Triple::OpenBSD:
9171 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9172 case llvm::Triple::Bitrig:
9173 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts);
9174 case llvm::Triple::RTEMS:
9175 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
9176 case llvm::Triple::NaCl:
9177 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
9178 case llvm::Triple::Win32:
9179 switch (Triple.getEnvironment()) {
9180 case llvm::Triple::Cygnus:
9181 return new CygwinARMTargetInfo(Triple, Opts);
9182 case llvm::Triple::GNU:
9183 return new MinGWARMTargetInfo(Triple, Opts);
9184 case llvm::Triple::Itanium:
9185 return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
9186 case llvm::Triple::MSVC:
9187 default: // Assume MSVC for unknown environments
9188 return new MicrosoftARMleTargetInfo(Triple, Opts);
9191 return new ARMleTargetInfo(Triple, Opts);
9194 case llvm::Triple::armeb:
9195 case llvm::Triple::thumbeb:
9196 if (Triple.isOSDarwin())
9197 return new DarwinARMTargetInfo(Triple, Opts);
9200 case llvm::Triple::Linux:
9201 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9202 case llvm::Triple::FreeBSD:
9203 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9204 case llvm::Triple::NetBSD:
9205 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9206 case llvm::Triple::OpenBSD:
9207 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9208 case llvm::Triple::Bitrig:
9209 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9210 case llvm::Triple::RTEMS:
9211 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9212 case llvm::Triple::NaCl:
9213 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9215 return new ARMbeTargetInfo(Triple, Opts);
9218 case llvm::Triple::avr:
9219 return new AVRTargetInfo(Triple, Opts);
9220 case llvm::Triple::bpfeb:
9221 case llvm::Triple::bpfel:
9222 return new BPFTargetInfo(Triple, Opts);
9224 case llvm::Triple::msp430:
9225 return new MSP430TargetInfo(Triple, Opts);
9227 case llvm::Triple::mips:
9229 case llvm::Triple::Linux:
9230 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9231 case llvm::Triple::RTEMS:
9232 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9233 case llvm::Triple::FreeBSD:
9234 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9235 case llvm::Triple::NetBSD:
9236 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9238 return new MipsTargetInfo(Triple, Opts);
9241 case llvm::Triple::mipsel:
9243 case llvm::Triple::Linux:
9244 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9245 case llvm::Triple::RTEMS:
9246 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9247 case llvm::Triple::FreeBSD:
9248 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9249 case llvm::Triple::NetBSD:
9250 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9251 case llvm::Triple::NaCl:
9252 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
9254 return new MipsTargetInfo(Triple, Opts);
9257 case llvm::Triple::mips64:
9259 case llvm::Triple::Linux:
9260 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9261 case llvm::Triple::RTEMS:
9262 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9263 case llvm::Triple::FreeBSD:
9264 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9265 case llvm::Triple::NetBSD:
9266 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9267 case llvm::Triple::OpenBSD:
9268 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9270 return new MipsTargetInfo(Triple, Opts);
9273 case llvm::Triple::mips64el:
9275 case llvm::Triple::Linux:
9276 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9277 case llvm::Triple::RTEMS:
9278 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9279 case llvm::Triple::FreeBSD:
9280 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9281 case llvm::Triple::NetBSD:
9282 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9283 case llvm::Triple::OpenBSD:
9284 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9286 return new MipsTargetInfo(Triple, Opts);
9289 case llvm::Triple::le32:
9291 case llvm::Triple::NaCl:
9292 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
9297 case llvm::Triple::le64:
9298 return new Le64TargetInfo(Triple, Opts);
9300 case llvm::Triple::ppc:
9301 if (Triple.isOSDarwin())
9302 return new DarwinPPC32TargetInfo(Triple, Opts);
9304 case llvm::Triple::Linux:
9305 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
9306 case llvm::Triple::FreeBSD:
9307 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9308 case llvm::Triple::NetBSD:
9309 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9310 case llvm::Triple::OpenBSD:
9311 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9312 case llvm::Triple::RTEMS:
9313 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts);
9315 return new PPC32TargetInfo(Triple, Opts);
9318 case llvm::Triple::ppc64:
9319 if (Triple.isOSDarwin())
9320 return new DarwinPPC64TargetInfo(Triple, Opts);
9322 case llvm::Triple::Linux:
9323 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9324 case llvm::Triple::Lv2:
9325 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts);
9326 case llvm::Triple::FreeBSD:
9327 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9328 case llvm::Triple::NetBSD:
9329 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9331 return new PPC64TargetInfo(Triple, Opts);
9334 case llvm::Triple::ppc64le:
9336 case llvm::Triple::Linux:
9337 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9338 case llvm::Triple::NetBSD:
9339 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9341 return new PPC64TargetInfo(Triple, Opts);
9344 case llvm::Triple::nvptx:
9345 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32);
9346 case llvm::Triple::nvptx64:
9347 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64);
9349 case llvm::Triple::amdgcn:
9350 case llvm::Triple::r600:
9351 return new AMDGPUTargetInfo(Triple, Opts);
9353 case llvm::Triple::sparc:
9355 case llvm::Triple::Linux:
9356 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9357 case llvm::Triple::Solaris:
9358 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9359 case llvm::Triple::NetBSD:
9360 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9361 case llvm::Triple::OpenBSD:
9362 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9363 case llvm::Triple::RTEMS:
9364 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9366 return new SparcV8TargetInfo(Triple, Opts);
9369 // The 'sparcel' architecture copies all the above cases except for Solaris.
9370 case llvm::Triple::sparcel:
9372 case llvm::Triple::Linux:
9373 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9374 case llvm::Triple::NetBSD:
9375 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9376 case llvm::Triple::OpenBSD:
9377 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9378 case llvm::Triple::RTEMS:
9379 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9381 return new SparcV8elTargetInfo(Triple, Opts);
9384 case llvm::Triple::sparcv9:
9386 case llvm::Triple::Linux:
9387 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9388 case llvm::Triple::Solaris:
9389 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9390 case llvm::Triple::NetBSD:
9391 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9392 case llvm::Triple::OpenBSD:
9393 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9394 case llvm::Triple::FreeBSD:
9395 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9397 return new SparcV9TargetInfo(Triple, Opts);
9400 case llvm::Triple::systemz:
9402 case llvm::Triple::Linux:
9403 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts);
9405 return new SystemZTargetInfo(Triple, Opts);
9408 case llvm::Triple::tce:
9409 return new TCETargetInfo(Triple, Opts);
9411 case llvm::Triple::tcele:
9412 return new TCELETargetInfo(Triple, Opts);
9414 case llvm::Triple::x86:
9415 if (Triple.isOSDarwin())
9416 return new DarwinI386TargetInfo(Triple, Opts);
9419 case llvm::Triple::CloudABI:
9420 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts);
9421 case llvm::Triple::Linux: {
9422 switch (Triple.getEnvironment()) {
9424 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts);
9425 case llvm::Triple::Android:
9426 return new AndroidX86_32TargetInfo(Triple, Opts);
9429 case llvm::Triple::DragonFly:
9430 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9431 case llvm::Triple::NetBSD:
9432 return new NetBSDI386TargetInfo(Triple, Opts);
9433 case llvm::Triple::OpenBSD:
9434 return new OpenBSDI386TargetInfo(Triple, Opts);
9435 case llvm::Triple::Bitrig:
9436 return new BitrigI386TargetInfo(Triple, Opts);
9437 case llvm::Triple::FreeBSD:
9438 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9439 case llvm::Triple::KFreeBSD:
9440 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9441 case llvm::Triple::Minix:
9442 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts);
9443 case llvm::Triple::Solaris:
9444 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts);
9445 case llvm::Triple::Win32: {
9446 switch (Triple.getEnvironment()) {
9447 case llvm::Triple::Cygnus:
9448 return new CygwinX86_32TargetInfo(Triple, Opts);
9449 case llvm::Triple::GNU:
9450 return new MinGWX86_32TargetInfo(Triple, Opts);
9451 case llvm::Triple::Itanium:
9452 case llvm::Triple::MSVC:
9453 default: // Assume MSVC for unknown environments
9454 return new MicrosoftX86_32TargetInfo(Triple, Opts);
9457 case llvm::Triple::Haiku:
9458 return new HaikuX86_32TargetInfo(Triple, Opts);
9459 case llvm::Triple::RTEMS:
9460 return new RTEMSX86_32TargetInfo(Triple, Opts);
9461 case llvm::Triple::NaCl:
9462 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
9463 case llvm::Triple::ELFIAMCU:
9464 return new MCUX86_32TargetInfo(Triple, Opts);
9466 return new X86_32TargetInfo(Triple, Opts);
9469 case llvm::Triple::x86_64:
9470 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
9471 return new DarwinX86_64TargetInfo(Triple, Opts);
9474 case llvm::Triple::CloudABI:
9475 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts);
9476 case llvm::Triple::Linux: {
9477 switch (Triple.getEnvironment()) {
9479 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts);
9480 case llvm::Triple::Android:
9481 return new AndroidX86_64TargetInfo(Triple, Opts);
9484 case llvm::Triple::DragonFly:
9485 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9486 case llvm::Triple::NetBSD:
9487 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9488 case llvm::Triple::OpenBSD:
9489 return new OpenBSDX86_64TargetInfo(Triple, Opts);
9490 case llvm::Triple::Bitrig:
9491 return new BitrigX86_64TargetInfo(Triple, Opts);
9492 case llvm::Triple::FreeBSD:
9493 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9494 case llvm::Triple::Fuchsia:
9495 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts);
9496 case llvm::Triple::KFreeBSD:
9497 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9498 case llvm::Triple::Solaris:
9499 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts);
9500 case llvm::Triple::Win32: {
9501 switch (Triple.getEnvironment()) {
9502 case llvm::Triple::Cygnus:
9503 return new CygwinX86_64TargetInfo(Triple, Opts);
9504 case llvm::Triple::GNU:
9505 return new MinGWX86_64TargetInfo(Triple, Opts);
9506 case llvm::Triple::MSVC:
9507 default: // Assume MSVC for unknown environments
9508 return new MicrosoftX86_64TargetInfo(Triple, Opts);
9511 case llvm::Triple::Haiku:
9512 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
9513 case llvm::Triple::NaCl:
9514 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
9515 case llvm::Triple::PS4:
9516 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
9518 return new X86_64TargetInfo(Triple, Opts);
9521 case llvm::Triple::spir: {
9522 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9523 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9525 return new SPIR32TargetInfo(Triple, Opts);
9527 case llvm::Triple::spir64: {
9528 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9529 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9531 return new SPIR64TargetInfo(Triple, Opts);
9533 case llvm::Triple::wasm32:
9534 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9535 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9536 Triple.getOS() != llvm::Triple::UnknownOS ||
9537 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9538 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9540 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts);
9541 case llvm::Triple::wasm64:
9542 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9543 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9544 Triple.getOS() != llvm::Triple::UnknownOS ||
9545 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9546 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9548 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts);
9550 case llvm::Triple::renderscript32:
9551 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts);
9552 case llvm::Triple::renderscript64:
9553 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts);
9557 /// CreateTargetInfo - Return the target info object for the specified target
9560 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
9561 const std::shared_ptr<TargetOptions> &Opts) {
9562 llvm::Triple Triple(Opts->Triple);
9564 // Construct the target
9565 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts));
9567 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
9570 Target->TargetOpts = Opts;
9572 // Set the target CPU if specified.
9573 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
9574 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
9578 // Set the target ABI if specified.
9579 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
9580 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
9584 // Set the fp math unit.
9585 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
9586 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
9590 // Compute the default target features, we need the target to handle this
9591 // because features may have dependencies on one another.
9592 llvm::StringMap<bool> Features;
9593 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
9594 Opts->FeaturesAsWritten))
9597 // Add the features to the compile options.
9598 Opts->Features.clear();
9599 for (const auto &F : Features)
9600 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
9602 if (!Target->handleTargetFeatures(Opts->Features, Diags))
9605 Target->setSupportedOpenCLOpts();
9606 Target->setOpenCLExtensionOpts();
9608 if (!Target->validateTarget(Diags))
9611 return Target.release();